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Restructure handling of CA1, CA2, CB1, CB2 lines on MOS 652x chips #42

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@breqdev breqdev commented Apr 14, 2024

Previously, the Port interface only provided a poll method to get whether the IRQ line should be set high. Ultimately, this glosses over a lot of complexity in how the control lines are handled in the PIA, VIA, and CIA. For instance, CX2 can be used as an output, and there are details regarding rising/falling edge directions and which flags should be set in the VIA and CIA.

The existing Commodore machines worked fine with the simplified model, but @nkizz's work with the Apple I ran across some limitations of this representation. Additionally, existing emulators can now be enhanced with more features (e.g. this allows the PET emulator to blank the screen when CA2 is written to).

Most importantly, this migrates the Port interface into the mos652x module and modifies it as follows:

  • read() and write() are now read_data() and write_data()
  • poll() now returns a 2-tuple with the value of CX1 and CX2 (high or low)
  • write_cx2() writes a value to CX2 (currently blanks the screen in the PET emulator)

Test with the following BASIC in the PET emulator: (should blank the screen)

POKE 59409,PEEK(59409) OR 48
POKE 59409,PEEK(59409) AND 247

Detection of rising and falling edges is handled higher in the abstraction (within the mos652x module).

@breqdev breqdev requested review from miakizz and ava-silver April 14, 2024 06:53
@breqdev breqdev self-assigned this Apr 14, 2024
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codecov bot commented Apr 14, 2024

Codecov Report

Attention: Patch coverage is 55.02959% with 152 lines in your changes are missing coverage. Please review.

Project coverage is 27.27%. Comparing base (e8dcd25) to head (7b42716).

Files Patch % Lines
src/memory/mos652x/pia.rs 19.60% 41 Missing ⚠️
src/memory/mos652x/via.rs 70.47% 31 Missing ⚠️
src/systems/pet/mod.rs 0.00% 30 Missing ⚠️
src/systems/vic/mod.rs 0.00% 17 Missing ⚠️
src/memory/mos652x/port.rs 61.76% 13 Missing ⚠️
src/systems/c64/mod.rs 0.00% 12 Missing ⚠️
src/memory/mos652x/mod.rs 86.11% 5 Missing ⚠️
src/memory/mos6510.rs 0.00% 3 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main      #42      +/-   ##
==========================================
- Coverage   27.31%   27.27%   -0.04%     
==========================================
  Files          44       42       -2     
  Lines        9055     9112      +57     
==========================================
+ Hits         2473     2485      +12     
- Misses       6582     6627      +45     

☔ View full report in Codecov by Sentry.
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miakizz commented Apr 18, 2024

This looks good to me, my only question I have is to double check if the CA/CB lines can change state without triggering the IRQ line as the Apple I straight up doesn't have that connected

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breqdev commented Apr 27, 2024

This looks good to me, my only question I have is to double check if the CA/CB lines can change state without triggering the IRQ line as the Apple I straight up doesn't have that connected

Should be supported in ce03a82! Appreciate you pointing this out

@breqdev breqdev marked this pull request as ready for review April 27, 2024 03:14
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lgtm

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2 participants