Changelog.md: update to 4.1a

bucaps · Dec 8, 2020 · 965827c · 965827c
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+# Version 4.1a
+
+ - Added
+	 - Model a arbitrary fixed latency between LLC cache and Memory controller
+ - Changed
+	 - For Ramulator and DRAMSim3, memory access request is split into MEM_BUS_WIDTH sized parts and latency for each part is queried
+ - Fixed
+	 - Rounding mode (rm) must be calculated again before executing FP instruction during simulation
+
 # Version 4.0a
 
  - Added