From 965827c80ec6f293904744adebae428328b5e473 Mon Sep 17 00:00:00 2001
From: gkothar1 <gkothar1@binghamton.edu>
Date: Tue, 8 Dec 2020 15:16:27 -0500
Subject: [PATCH] Changelog.md: update to 4.1a

---
 Changelog.md | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Changelog.md b/Changelog.md
index 3c1d971..814342e 100644
--- a/Changelog.md
+++ b/Changelog.md
@@ -1,3 +1,12 @@
+# Version 4.1a
+
+ - Added
+	 - Model a arbitrary fixed latency between LLC cache and Memory controller
+ - Changed
+	 - For Ramulator and DRAMSim3, memory access request is split into MEM_BUS_WIDTH sized parts and latency for each part is queried
+ - Fixed
+	 - Rounding mode (rm) must be calculated again before executing FP instruction during simulation
+
 # Version 4.0a
 
  - Added