Is the delay from the output of the cell to the output port of the chip specified by INTERCONNECT ?

[takanie1967]

I use OSS_CVC_7.00b-x86_64-rhel6x of 07/07/14 (Linux-elf).

When I simulate a delay simulation by CVC in which SDF is annotated,
the change timing of the output port of the chip is incorrect. There are two cases.
(1) The IOPATH delay of the cell that drives the output port of the chip becomes zero.
(2) The INTERCONNECT delay from the output of the cell to the output port of the chip becomes zero.

I use INTERCONNECT to specify the delay of (2), but I guess this is wrong.
If anyone knows the correct way to specify it, please let me know.

For example, in the case of below module,
the delay of (1) is from BUFX2_01.A to BUFX2_01.Y , and,
the delay of (2) is from BUFX2_01.Y to out1 .

module test0105 ( clk , nrst , in1 , out1 );
input clk, nrst, in1 ;
output out1;
wire tmp1;
DFFSR FF01 ( .CLK (clk), .R(nrst), .S(1'b1), .D(in1), .Q(tmp1) );
BUFX2 BUFX2_01 ( .A (tmp1), .Y (out1) );
endmodule
(* I use osu018_stdcells.{lib,v} for the library. *)