chisel decoder.

[sequencer]

switch to decoder, recode InstructionType uop to OneHot, improve dispatch timing by removing useless Mux.
(just a prototype, not guarantee the correctness ;p)

[sequencer]

From the RTL designer's review, your usage in decoder module needs a OH encoding which saves the extract comparing logic: (not (or (xor a b)))

[carlosedp]

This is great... with chipsalliance/chisel#2261 it will be even better :)

[sequencer]

Actually these padding are useless, in your future design, my suggestion is splitting instruction error out of this type and remove INST_R here.

[carlosedp]

I tried it out but got the error:

[info] - should Decode an ADD instruction (type R) *** FAILED ***
[info]   java.util.NoSuchElementException: None.get
[info]   at ... ()
[info]   at chiselv.Decoder.$anonfun$signals$2(Decoder.scala:46)
[info]   at chisel3.internal.prefix$.apply(prefix.scala:49)
[info]   at chiselv.Decoder.$anonfun$signals$1(Decoder.scala:108)
[info]   at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
[info]   at chiselv.Decoder.<init>(Decoder.scala:38)
[info]   at chiselv.DecoderSpec.$anonfun$new$2(DecoderSpec.scala:15)
[info]   at ... ()
[info]   at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
[info]   ...

Any idea what cou be wrong?

[sequencer]

I tried it out but got the error:

[info] - should Decode an ADD instruction (type R) *** FAILED ***
[info]   java.util.NoSuchElementException: None.get
[info]   at ... ()
[info]   at chiselv.Decoder.$anonfun$signals$2(Decoder.scala:46)
[info]   at chisel3.internal.prefix$.apply(prefix.scala:49)
[info]   at chiselv.Decoder.$anonfun$signals$1(Decoder.scala:108)
[info]   at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
[info]   at chiselv.Decoder.<init>(Decoder.scala:38)
[info]   at chiselv.DecoderSpec.$anonfun$new$2(DecoderSpec.scala:15)
[info]   at ... ()
[info]   at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
[info]   ...

Any idea what cou be wrong?

This is a strange bug:
chipsalliance/chisel#2268
I will try to fix this in Chisel

[carlosedp]

Hey @sequencer ... just a reminder to catch-up on this whenever we can :)
Would be awesome then to have it as a recipe in the Chisel cookbook :)

[sequencer]

Sorry for the delay again!
I did some fix ups, but seems there is a bug in your decode table which was figured by Decoder.

[carlosedp]

Hey Jiuyang, I've rebased and fixed my decode pattern but now I'm getting:

[info] - should Decode an ADD instruction (type R) *** FAILED ***
[info]   chisel3.internal.ChiselException: Connection between sink (Decoder.io.DecoderPort.inst: IO[Instruction]) and source (Decoder.signals.inst: Wire[UInt<6>]) failed @: Sink (Instruction) and Source (UInt<6>) have different types.
[info]   at ... ()
[info]   at chiselv.Decoder.<init>(Decoder.scala:127)
[info]   at chiselv.DecoderSpec.$anonfun$new$2(DecoderSpec.scala:15)
[info]   at ... ()
[info]   at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
[info]   ...

I expect the Instruction type in the output but currently it's a UInt.

Also I'm seeing lots of debug messages looking for "espresso" in my path.

[sequencer]

I expect the Instruction type in the output but currently it's a UInt.

Just cast it(I know it's dirty, we should have a better name in the future)

Also I'm seeing lots of debug messages looking for "espresso" in my path.

It's available from https://github.com/chipsalliance/espresso

[carlosedp]

Thanks Jiuyang! It worked perfectly :D

I've cast like: io.DecoderPort.inst := signals.inst.asTypeOf(new Instruction.Type)

But I'm getting:

[warn] Decoder.scala:127: Casting non-literal UInt to chiselv.Instruction. You can use chiselv.Instruction.safe to cast without this warning. in class chiselv.Decoder

What's the right way to do without the warning?

Other than that... I think we need some nicer way to avoid all casts and etc... :) It's a kinda complex and hard to remember pattern :)

[carlosedp]

This is pretty neat, as an example I synthesized for ECP5 FPGA:

Without decoder (switch/is and MuxLookup)

Info: Device utilisation:
Info: 	       TRELLIS_SLICE:  3939/41820     9%
Info: 	          TRELLIS_IO:    13/  365     3%
Info: Max frequency for clock '$glbnet$SOC_clock': 16.02 MHz (PASS at 9.00 MHz)

With decoder/mux1H:

Info: 	       TRELLIS_SLICE:  3684/41820     8%
Info: 	          TRELLIS_IO:    13/  365     3%
Info: Max frequency for clock '$glbnet$SOC_clock': 19.43 MHz (PASS at 9.00 MHz)

Saved about 300 LEs and gained about 3.5Mhz!

[sequencer]

Would you mind benchmark QMC vs espresso. I'm also curious to this.
I thought PPA of QMC should be better, while slower than espresso.
But for this case, I think it will as fast as espresso.

[carlosedp]

You mean by having espresso or not right?
In terms of execution time for my core, the difference is not noticeable... all runs around 32-38 seconds... there is a difference tho in synthesis... without using the espresso compiler I get:

Info: Device utilisation:
Info: 	       TRELLIS_SLICE:  3762/41820     8%
Info: 	          TRELLIS_IO:    13/  365     3%

Info: Max frequency for clock '$glbnet$SOC_clock': 20.34 MHz (PASS at 9.00 MHz)

A bit more LEs but faster clock.