forked from SumoLogic/telegraf
-
Notifications
You must be signed in to change notification settings - Fork 0
/
ras_test.go
255 lines (237 loc) · 6.88 KB
/
ras_test.go
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
// +build linux
// +build 386 amd64 arm arm64
package ras
import (
"fmt"
"testing"
"github.com/influxdata/telegraf/testutil"
"github.com/stretchr/testify/assert"
)
func TestUpdateCounters(t *testing.T) {
ras := newRas()
for _, mce := range testData {
ras.updateCounters(&mce)
}
assert.Equal(t, 1, len(ras.cpuSocketCounters), "Should contain counters only for single socket")
for metric, value := range ras.cpuSocketCounters[0] {
if metric == processorBase {
// processor_base_errors is sum of other seven errors: internal_timer_errors, smm_handler_code_access_violation_errors,
// internal_parity_errors, frc_errors, external_mce_errors, microcode_rom_parity_errors and unclassified_mce_errors
assert.Equal(t, int64(7), value, fmt.Sprintf("%s should have value of 7", processorBase))
} else {
assert.Equal(t, int64(1), value, fmt.Sprintf("%s should have value of 1", metric))
}
}
for metric, value := range ras.serverCounters {
assert.Equal(t, int64(1), value, fmt.Sprintf("%s should have value of 1", metric))
}
}
func TestUpdateLatestTimestamp(t *testing.T) {
ras := newRas()
ts := "2020-08-01 15:13:27 +0200"
testData = append(testData, []machineCheckError{
{
Timestamp: "2019-05-20 08:25:55 +0200",
SocketID: 0,
ErrorMsg: "",
MciStatusMsg: "",
},
{
Timestamp: "2018-02-21 12:27:22 +0200",
SocketID: 0,
ErrorMsg: "",
MciStatusMsg: "",
},
{
Timestamp: ts,
SocketID: 0,
ErrorMsg: "",
MciStatusMsg: "",
},
}...)
for _, mce := range testData {
err := ras.updateLatestTimestamp(mce.Timestamp)
assert.NoError(t, err)
}
assert.Equal(t, ts, ras.latestTimestamp.Format(dateLayout))
}
func TestMultipleSockets(t *testing.T) {
ras := newRas()
cacheL2 := "Instruction CACHE Level-2 Generic Error"
overflow := "Error_overflow Corrected_error"
testData = []machineCheckError{
{
Timestamp: "2019-05-20 08:25:55 +0200",
SocketID: 0,
ErrorMsg: cacheL2,
MciStatusMsg: overflow,
},
{
Timestamp: "2018-02-21 12:27:22 +0200",
SocketID: 1,
ErrorMsg: cacheL2,
MciStatusMsg: overflow,
},
{
Timestamp: "2020-03-21 14:17:28 +0200",
SocketID: 2,
ErrorMsg: cacheL2,
MciStatusMsg: overflow,
},
{
Timestamp: "2020-03-21 17:24:18 +0200",
SocketID: 3,
ErrorMsg: cacheL2,
MciStatusMsg: overflow,
},
}
for _, mce := range testData {
ras.updateCounters(&mce)
}
assert.Equal(t, 4, len(ras.cpuSocketCounters), "Should contain counters for four sockets")
for _, metricData := range ras.cpuSocketCounters {
for metric, value := range metricData {
if metric == levelTwoCache {
assert.Equal(t, int64(1), value, fmt.Sprintf("%s should have value of 1", levelTwoCache))
} else {
assert.Equal(t, int64(0), value, fmt.Sprintf("%s should have value of 0", metric))
}
}
}
}
func TestMissingDatabase(t *testing.T) {
var acc testutil.Accumulator
ras := newRas()
ras.DBPath = "/tmp/test.db"
err := ras.Start(&acc)
assert.Error(t, err)
}
func TestEmptyDatabase(t *testing.T) {
ras := newRas()
assert.Equal(t, 1, len(ras.cpuSocketCounters), "Should contain default counters for one socket")
assert.Equal(t, 2, len(ras.serverCounters), "Should contain default counters for server")
for metric, value := range ras.cpuSocketCounters[0] {
assert.Equal(t, int64(0), value, fmt.Sprintf("%s should have value of 0", metric))
}
for metric, value := range ras.serverCounters {
assert.Equal(t, int64(0), value, fmt.Sprintf("%s should have value of 0", metric))
}
}
func newRas() *Ras {
defaultTimestamp, _ := parseDate("1970-01-01 00:00:01 -0700")
return &Ras{
DBPath: defaultDbPath,
latestTimestamp: defaultTimestamp,
cpuSocketCounters: map[int]metricCounters{
0: *newMetricCounters(),
},
serverCounters: map[string]int64{
levelTwoCache: 0,
upi: 0,
},
}
}
var testData = []machineCheckError{
{
Timestamp: "2020-05-20 07:34:53 +0200",
SocketID: 0,
ErrorMsg: "MEMORY CONTROLLER RD_CHANNEL0_ERR Transaction: Memory read error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 07:35:11 +0200",
SocketID: 0,
ErrorMsg: "MEMORY CONTROLLER RD_CHANNEL0_ERR Transaction: Memory read error",
MciStatusMsg: "Uncorrected_error",
},
{
Timestamp: "2020-05-20 07:37:50 +0200",
SocketID: 0,
ErrorMsg: "MEMORY CONTROLLER RD_CHANNEL2_ERR Transaction: Memory write error",
MciStatusMsg: "Uncorrected_error",
},
{
Timestamp: "2020-05-20 08:14:51 +0200",
SocketID: 0,
ErrorMsg: "MEMORY CONTROLLER WR_CHANNEL2_ERR Transaction: Memory write error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:15:31 +0200",
SocketID: 0,
ErrorMsg: "corrected filtering (some unreported errors in same region) Instruction CACHE Level-0 Read Error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:16:32 +0200",
SocketID: 0,
ErrorMsg: "Instruction TLB Level-0 Error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:16:56 +0200",
SocketID: 0,
ErrorMsg: "No Error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:17:24 +0200",
SocketID: 0,
ErrorMsg: "Unclassified",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:17:41 +0200",
SocketID: 0,
ErrorMsg: "Microcode ROM parity error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:17:48 +0200",
SocketID: 0,
ErrorMsg: "FRC error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:18:18 +0200",
SocketID: 0,
ErrorMsg: "Internal parity error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:18:34 +0200",
SocketID: 0,
ErrorMsg: "SMM Handler Code Access Violation",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:18:54 +0200",
SocketID: 0,
ErrorMsg: "Internal Timer error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:21:23 +0200",
SocketID: 0,
ErrorMsg: "BUS Level-3 Generic Generic IO Request-did-not-timeout Error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:23:23 +0200",
SocketID: 0,
ErrorMsg: "External error",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:25:31 +0200",
SocketID: 0,
ErrorMsg: "UPI: COR LL Rx detected CRC error - successful LLR without Phy Reinit",
MciStatusMsg: "Error_overflow Corrected_error",
},
{
Timestamp: "2020-05-20 08:25:55 +0200",
SocketID: 0,
ErrorMsg: "Instruction CACHE Level-2 Generic Error",
MciStatusMsg: "Error_overflow Corrected_error",
},
}