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@tmichalak
tmichalak committed Sep 25, 2024
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# Sphinx build info version 1
# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
config: 58eccbd399e0dc34fb00129a1ff696c6
tags: 645f666f9bcd5a90fca523b33c5a78b7
2 changes: 1 addition & 1 deletion html/dev.html
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Expand Up @@ -250,7 +250,7 @@ <h1 id="cores-veer-el2">Cores VeeR EL2<a class="headerlink" href="#cores-veer-el
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<td class="headerInfo">Test Date:</td>
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<span id="L28"><span class="lineNum"> 28</span> : )</span>
<span id="L29"><span class="lineNum"> 29</span> : // ,TAG = 1)</span>
<span id="L30"><span class="lineNum"> 30</span> : (</span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC tlaBgGNC"> 27232830 : input clk,</span></span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC tlaBgGNC"> 26640341 : input clk,</span></span>
<span id="L32"><span class="lineNum"> 32</span> <span class="tlaGNC"> 32 : input rst_l,</span></span>
<span id="L33"><span class="lineNum"> 33</span> <span class="tlaUNC tlaBgUNC"> 0 : input scan_mode,</span></span>
<span id="L34"><span class="lineNum"> 34</span> <span class="tlaGNC tlaBgGNC"> 20 : input bus_clk_en,</span></span>
Expand Down Expand Up @@ -242,9 +242,9 @@
<span id="L138"><span class="lineNum"> 138</span> <span class="tlaGNC"> 20 : buf_read_error_in = 1'b0; // signal indicating that an error came back with the read from the core</span></span>
<span id="L139"><span class="lineNum"> 139</span> <span class="tlaGNC"> 20 : cmdbuf_wr_en = 1'b0; // all clear from the gasket to load the buffer with the command for reads, command/dat for writes</span></span>
<span id="L140"><span class="lineNum"> 140</span> <span class="tlaGNC"> 20 : case (buf_state)</span></span>
<span id="L141"><span class="lineNum"> 141</span> <span class="tlaGNC"> 6964055 : IDLE: begin // No commands recieved</span></span>
<span id="L142"><span class="lineNum"> 142</span> <span class="tlaGNC"> 6964055 : buf_nxtstate = ahb_hwrite ? WR : RD;</span></span>
<span id="L143"><span class="lineNum"> 143</span> <span class="tlaGNC"> 6964055 : buf_state_en = ahb_hready &amp; ahb_htrans[1] &amp; ahb_hsel; // only transition on a valid hrtans</span></span>
<span id="L141"><span class="lineNum"> 141</span> <span class="tlaGNC"> 6895287 : IDLE: begin // No commands recieved</span></span>
<span id="L142"><span class="lineNum"> 142</span> <span class="tlaGNC"> 6895287 : buf_nxtstate = ahb_hwrite ? WR : RD;</span></span>
<span id="L143"><span class="lineNum"> 143</span> <span class="tlaGNC"> 6895287 : buf_state_en = ahb_hready &amp; ahb_htrans[1] &amp; ahb_hsel; // only transition on a valid hrtans</span></span>
<span id="L144"><span class="lineNum"> 144</span> : end</span>
<span id="L145"><span class="lineNum"> 145</span> <span class="tlaGNC"> 2210 : WR: begin // Write command recieved last cycle</span></span>
<span id="L146"><span class="lineNum"> 146</span> <span class="tlaGNC"> 2210 : buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite ? WR : RD;</span></span>
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<tr>
<td class="headerInfo">Test Date:</td>
<td class="headerInfoValue">
19-09-2024
25-09-2024
</td>
<td></td>

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<span id="L27"><span class="lineNum"> 27</span> : `include "el2_param.vh"</span>
<span id="L28"><span class="lineNum"> 28</span> : ,parameter TAG = 1) (</span>
<span id="L29"><span class="lineNum"> 29</span> : </span>
<span id="L30"><span class="lineNum"> 30</span> <span class="tlaGNC tlaBgGNC"> 24551185 : input clk,</span></span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC"> 24551185 : input free_clk,</span></span>
<span id="L30"><span class="lineNum"> 30</span> <span class="tlaGNC tlaBgGNC"> 24004573 : input clk,</span></span>
<span id="L31"><span class="lineNum"> 31</span> <span class="tlaGNC"> 24004573 : input free_clk,</span></span>
<span id="L32"><span class="lineNum"> 32</span> <span class="tlaGNC"> 21 : input rst_l,</span></span>
<span id="L33"><span class="lineNum"> 33</span> <span class="tlaUNC tlaBgUNC"> 0 : input scan_mode,</span></span>
<span id="L34"><span class="lineNum"> 34</span> <span class="tlaGNC tlaBgGNC"> 21 : input bus_clk_en,</span></span>
Expand Down Expand Up @@ -389,18 +389,18 @@
<span id="L285"><span class="lineNum"> 285</span> <span class="tlaGNC"> 21 : rd_bypass_idle = 1'b0;</span></span>
<span id="L286"><span class="lineNum"> 286</span> : </span>
<span id="L287"><span class="lineNum"> 287</span> <span class="tlaGNC"> 21 : case (buf_state)</span></span>
<span id="L288"><span class="lineNum"> 288</span> <span class="tlaGNC"> 6946569 : IDLE: begin</span></span>
<span id="L289"><span class="lineNum"> 289</span> <span class="tlaGNC"> 6946569 : master_ready = 1'b1;</span></span>
<span id="L290"><span class="lineNum"> 290</span> <span class="tlaGNC"> 6946569 : buf_write_in = (master_opc[2:1] == 2'b01);</span></span>
<span id="L291"><span class="lineNum"> 291</span> <span class="tlaGNC"> 6946569 : buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;</span></span>
<span id="L292"><span class="lineNum"> 292</span> <span class="tlaGNC"> 6946569 : buf_state_en = master_valid &amp; master_ready;</span></span>
<span id="L293"><span class="lineNum"> 293</span> <span class="tlaGNC"> 6946569 : buf_wr_en = buf_state_en;</span></span>
<span id="L294"><span class="lineNum"> 294</span> <span class="tlaGNC"> 6946569 : buf_data_wr_en = buf_state_en &amp; (buf_nxtstate == CMD_WR);</span></span>
<span id="L295"><span class="lineNum"> 295</span> <span class="tlaGNC"> 6946569 : buf_cmd_byte_ptr_en = buf_state_en;</span></span>
<span id="L296"><span class="lineNum"> 296</span> <span class="tlaGNC"> 6946569 : buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];</span></span>
<span id="L297"><span class="lineNum"> 297</span> <span class="tlaGNC"> 6946569 : bypass_en = buf_state_en;</span></span>
<span id="L298"><span class="lineNum"> 298</span> <span class="tlaGNC"> 6946569 : rd_bypass_idle = bypass_en &amp; (buf_nxtstate == CMD_RD);</span></span>
<span id="L299"><span class="lineNum"> 299</span> <span class="tlaGNC"> 6946569 : ahb_htrans[1:0] = {2{bypass_en}} &amp; 2'b10;</span></span>
<span id="L288"><span class="lineNum"> 288</span> <span class="tlaGNC"> 6877801 : IDLE: begin</span></span>
<span id="L289"><span class="lineNum"> 289</span> <span class="tlaGNC"> 6877801 : master_ready = 1'b1;</span></span>
<span id="L290"><span class="lineNum"> 290</span> <span class="tlaGNC"> 6877801 : buf_write_in = (master_opc[2:1] == 2'b01);</span></span>
<span id="L291"><span class="lineNum"> 291</span> <span class="tlaGNC"> 6877801 : buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;</span></span>
<span id="L292"><span class="lineNum"> 292</span> <span class="tlaGNC"> 6877801 : buf_state_en = master_valid &amp; master_ready;</span></span>
<span id="L293"><span class="lineNum"> 293</span> <span class="tlaGNC"> 6877801 : buf_wr_en = buf_state_en;</span></span>
<span id="L294"><span class="lineNum"> 294</span> <span class="tlaGNC"> 6877801 : buf_data_wr_en = buf_state_en &amp; (buf_nxtstate == CMD_WR);</span></span>
<span id="L295"><span class="lineNum"> 295</span> <span class="tlaGNC"> 6877801 : buf_cmd_byte_ptr_en = buf_state_en;</span></span>
<span id="L296"><span class="lineNum"> 296</span> <span class="tlaGNC"> 6877801 : buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];</span></span>
<span id="L297"><span class="lineNum"> 297</span> <span class="tlaGNC"> 6877801 : bypass_en = buf_state_en;</span></span>
<span id="L298"><span class="lineNum"> 298</span> <span class="tlaGNC"> 6877801 : rd_bypass_idle = bypass_en &amp; (buf_nxtstate == CMD_RD);</span></span>
<span id="L299"><span class="lineNum"> 299</span> <span class="tlaGNC"> 6877801 : ahb_htrans[1:0] = {2{bypass_en}} &amp; 2'b10;</span></span>
<span id="L300"><span class="lineNum"> 300</span> : end</span>
<span id="L301"><span class="lineNum"> 301</span> <span class="tlaGNC"> 1894 : CMD_RD: begin</span></span>
<span id="L302"><span class="lineNum"> 302</span> <span class="tlaGNC"> 1894 : buf_nxtstate = (master_valid &amp; (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;</span></span>
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