diff --git a/doctrees/environment.pickle b/doctrees/environment.pickle index bdf6046b7bf..9f294e59dee 100644 Binary files a/doctrees/environment.pickle and b/doctrees/environment.pickle differ diff --git a/html/.buildinfo b/html/.buildinfo new file mode 100644 index 00000000000..60ad2d5ce1f --- /dev/null +++ b/html/.buildinfo @@ -0,0 +1,4 @@ +# Sphinx build info version 1 +# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done. +config: 58eccbd399e0dc34fb00129a1ff696c6 +tags: 645f666f9bcd5a90fca523b33c5a78b7 diff --git a/html/dev.html b/html/dev.html index ac96d72d3ed..4d51f15a15e 100644 --- a/html/dev.html +++ b/html/dev.html @@ -296,7 +296,7 @@

Active pull requestsIndividual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/dev/196/coverage_dashboard.html b/html/dev/196/coverage_dashboard.html index e0f34bff88e..04cb94f79bd 100644 --- a/html/dev/196/coverage_dashboard.html +++ b/html/dev/196/coverage_dashboard.html @@ -318,7 +318,7 @@

Individual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/dev/223/coverage_dashboard.html b/html/dev/223/coverage_dashboard.html index 6999b6bdaf8..b95f250a3dd 100644 --- a/html/dev/223/coverage_dashboard.html +++ b/html/dev/223/coverage_dashboard.html @@ -372,7 +372,7 @@

Individual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/dev/230/coverage_dashboard.html b/html/dev/230/coverage_dashboard.html index 53f2443d42e..68b1d7330b6 100644 --- a/html/dev/230/coverage_dashboard.html +++ b/html/dev/230/coverage_dashboard.html @@ -366,7 +366,7 @@

Individual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/dev/236/coverage_dashboard.html b/html/dev/236/coverage_dashboard.html index 6999b6bdaf8..b95f250a3dd 100644 --- a/html/dev/236/coverage_dashboard.html +++ b/html/dev/236/coverage_dashboard.html @@ -372,7 +372,7 @@

Individual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/dev/75/coverage_dashboard.html b/html/dev/75/coverage_dashboard.html index 7af443f712f..11a42c13187 100644 --- a/html/dev/75/coverage_dashboard.html +++ b/html/dev/75/coverage_dashboard.html @@ -277,7 +277,7 @@

Individual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/genindex.html b/html/genindex.html index 2458a1ac26f..658a9f5bbcb 100644 --- a/html/genindex.html +++ b/html/genindex.html @@ -243,7 +243,7 @@ Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/index.html b/html/index.html index b31c318e2ed..4eb4e9efe14 100644 --- a/html/index.html +++ b/html/index.html @@ -250,7 +250,7 @@

Cores VeeR EL2Main branch Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/main/coverage_dashboard.html b/html/main/coverage_dashboard.html index be18b02deb6..9262a644f31 100644 --- a/html/main/coverage_dashboard.html +++ b/html/main/coverage_dashboard.html @@ -372,7 +372,7 @@

Individual test reports Last update: - 2024-09-24 + 2024-09-25 diff --git a/html/main/coverage_dashboard/all/index.html b/html/main/coverage_dashboard/all/index.html index b63e6f487c0..018fec517b8 100644 --- a/html/main/coverage_dashboard/all/index.html +++ b/html/main/coverage_dashboard/all/index.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design.html index 43a4dabf3f5..da8b89b9a66 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dbg.html index 4c5e9570540..89f8e4f8ca3 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dbg.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dbg.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dec.html index 2dc3885df0d..e6a3840bf95 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dec.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dec.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dmi.html index a694e564ae3..aa1a7de7016 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dmi.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_dmi.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_exu.html index 8856ef2d1f2..85efaa76043 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_exu.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_exu.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_ifu.html index 258ac9463e2..31382d2c0c4 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_ifu.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_ifu.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_include.html index 6def3522ea3..6f5b7dc5e58 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_include.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_include.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lib.html index 335a538161e..0261c0f6bb6 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lib.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lib.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lsu.html index 57444da142d..b54c66fc117 100644 --- a/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lsu.html +++ b/html/main/coverage_dashboard/all/index_Cores-VeeR-EL2_design_lsu.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all/index_ahb_to_axi4.sv.html index 3ef1d60483e..18e66a67762 100644 --- a/html/main/coverage_dashboard/all/index_ahb_to_axi4.sv.html +++ b/html/main/coverage_dashboard/all/index_ahb_to_axi4.sv.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -132,7 +132,7 @@ 28 : ) 29 : // ,TAG = 1) 30 : ( - 31 27232830 : input clk, + 31 26640341 : input clk, 32 32 : input rst_l, 33 0 : input scan_mode, 34 20 : input bus_clk_en, @@ -242,9 +242,9 @@ 138 20 : buf_read_error_in = 1'b0; // signal indicating that an error came back with the read from the core 139 20 : cmdbuf_wr_en = 1'b0; // all clear from the gasket to load the buffer with the command for reads, command/dat for writes 140 20 : case (buf_state) - 141 6964055 : IDLE: begin // No commands recieved - 142 6964055 : buf_nxtstate = ahb_hwrite ? WR : RD; - 143 6964055 : buf_state_en = ahb_hready & ahb_htrans[1] & ahb_hsel; // only transition on a valid hrtans + 141 6895287 : IDLE: begin // No commands recieved + 142 6895287 : buf_nxtstate = ahb_hwrite ? WR : RD; + 143 6895287 : buf_state_en = ahb_hready & ahb_htrans[1] & ahb_hsel; // only transition on a valid hrtans 144 : end 145 2210 : WR: begin // Write command recieved last cycle 146 2210 : buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite ? WR : RD; diff --git a/html/main/coverage_dashboard/all/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all/index_axi4_to_ahb.sv.html index 4594cc35ee7..48ded90c874 100644 --- a/html/main/coverage_dashboard/all/index_axi4_to_ahb.sv.html +++ b/html/main/coverage_dashboard/all/index_axi4_to_ahb.sv.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -131,8 +131,8 @@ 27 : `include "el2_param.vh" 28 : ,parameter TAG = 1) ( 29 : - 30 24551185 : input clk, - 31 24551185 : input free_clk, + 30 24004573 : input clk, + 31 24004573 : input free_clk, 32 21 : input rst_l, 33 0 : input scan_mode, 34 21 : input bus_clk_en, @@ -389,18 +389,18 @@ 285 21 : rd_bypass_idle = 1'b0; 286 : 287 21 : case (buf_state) - 288 6946569 : IDLE: begin - 289 6946569 : master_ready = 1'b1; - 290 6946569 : buf_write_in = (master_opc[2:1] == 2'b01); - 291 6946569 : buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD; - 292 6946569 : buf_state_en = master_valid & master_ready; - 293 6946569 : buf_wr_en = buf_state_en; - 294 6946569 : buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR); - 295 6946569 : buf_cmd_byte_ptr_en = buf_state_en; - 296 6946569 : buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0]; - 297 6946569 : bypass_en = buf_state_en; - 298 6946569 : rd_bypass_idle = bypass_en & (buf_nxtstate == CMD_RD); - 299 6946569 : ahb_htrans[1:0] = {2{bypass_en}} & 2'b10; + 288 6877801 : IDLE: begin + 289 6877801 : master_ready = 1'b1; + 290 6877801 : buf_write_in = (master_opc[2:1] == 2'b01); + 291 6877801 : buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD; + 292 6877801 : buf_state_en = master_valid & master_ready; + 293 6877801 : buf_wr_en = buf_state_en; + 294 6877801 : buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR); + 295 6877801 : buf_cmd_byte_ptr_en = buf_state_en; + 296 6877801 : buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0]; + 297 6877801 : bypass_en = buf_state_en; + 298 6877801 : rd_bypass_idle = bypass_en & (buf_nxtstate == CMD_RD); + 299 6877801 : ahb_htrans[1:0] = {2{bypass_en}} & 2'b10; 300 : end 301 1894 : CMD_RD: begin 302 1894 : buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD; diff --git a/html/main/coverage_dashboard/all/index_beh_lib.sv.html b/html/main/coverage_dashboard/all/index_beh_lib.sv.html index 5dcdd06fa7f..6b9b12f9459 100644 --- a/html/main/coverage_dashboard/all/index_beh_lib.sv.html +++ b/html/main/coverage_dashboard/all/index_beh_lib.sv.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -123,7 +123,7 @@ 19 : module rvdff #( parameter WIDTH=1, SHORT=0 ) 20 : ( 21 742 : input logic [WIDTH-1:0] din, - 22 59264685 : input logic clk, + 22 58718061 : input logic clk, 23 542 : input logic rst_l, 24 : 25 745 : output logic [WIDTH-1:0] dout @@ -139,11 +139,11 @@ 35 : end 36 : `endif 37 : - 38 24308894 : always_ff @(posedge clk or negedge rst_l) begin + 38 24180477 : always_ff @(posedge clk or negedge rst_l) begin 39 3466 : if (rst_l == 0) 40 1740 : dout[WIDTH-1:0] <= 0; 41 : else - 42 24308533 : dout[WIDTH-1:0] <= din[WIDTH-1:0]; + 42 24180116 : dout[WIDTH-1:0] <= din[WIDTH-1:0]; 43 : end 44 : 45 : end @@ -154,7 +154,7 @@ 50 : ( 51 87916 : input logic [WIDTH-1:0] din, 52 14508 : input logic en, - 53 59635290 : input logic clk, + 53 59088666 : input logic clk, 54 609 : input logic rst_l, 55 834 : output logic [WIDTH-1:0] dout 56 : ); @@ -171,10 +171,10 @@ 67 : // rvdff with en and clear 68 : module rvdffsc #( parameter WIDTH=1, SHORT=0 ) 69 : ( - 70 778501 : input logic [WIDTH-1:0] din, + 70 777153 : input logic [WIDTH-1:0] din, 71 343374 : input logic en, 72 343558 : input logic clear, - 73 247548826 : input logic clk, + 73 245178822 : input logic clk, 74 1401 : input logic rst_l, 75 295188 : output logic [WIDTH-1:0] dout 76 : ); @@ -192,13 +192,13 @@ 88 : // _fpga versions 89 : module rvdff_fpga #( parameter WIDTH=1, SHORT=0 ) 90 : ( - 91 3729097 : input logic [WIDTH-1:0] din, + 91 3705942 : input logic [WIDTH-1:0] din, 92 9473980 : input logic clk, 93 1360 : input logic clken, - 94 106036643 : input logic rawclk, + 94 105444130 : input logic rawclk, 95 1171 : input logic rst_l, 96 : - 97 3729026 : output logic [WIDTH-1:0] dout + 97 3705870 : output logic [WIDTH-1:0] dout 98 : ); 99 : 100 : if (SHORT == 1) begin : genblock @@ -220,7 +220,7 @@ 116 2374 : input logic en, 117 57008 : input logic clk, 118 662 : input logic clken, - 119 124009391 : input logic rawclk, + 119 122870266 : input logic rawclk, 120 691 : input logic rst_l, 121 : 122 31 : output logic [WIDTH-1:0] dout @@ -243,14 +243,14 @@ 139 : module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 ) 140 : ( 141 1221 : input logic [WIDTH-1:0] din, - 142 3543250 : input logic en, + 142 3451669 : input logic en, 143 3024 : input logic clear, - 144 3411859 : input logic clk, + 144 3317907 : input logic clk, 145 977 : input logic clken, - 146 158721159 : input logic rawclk, + 146 157582022 : input logic rawclk, 147 1037 : input logic rst_l, 148 : - 149 177398 : output logic [WIDTH-1:0] dout + 149 171210 : output logic [WIDTH-1:0] dout 150 : ); 151 : 152 0 : logic [WIDTH-1:0] din_new; @@ -269,9 +269,9 @@ 165 : 166 : module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 ) 167 : ( - 168 3121522 : input logic [WIDTH-1:0] din, + 168 3111078 : input logic [WIDTH-1:0] din, 169 347562 : input logic en, - 170 59466018 : input logic clk, + 170 58919394 : input logic clk, 171 534 : input logic rst_l, 172 0 : input logic scan_mode, 173 6731 : output logic [WIDTH-1:0] dout @@ -309,12 +309,12 @@ 205 : 206 : module rvdffpcie #( parameter WIDTH=31 ) 207 : ( - 208 140094 : input logic [WIDTH-1:0] din, - 209 580374798 : input logic clk, + 208 139028 : input logic [WIDTH-1:0] din, + 209 577094982 : input logic clk, 210 3840 : input logic rst_l, - 211 47050225 : input logic en, + 211 46776297 : input logic en, 212 0 : input logic scan_mode, - 213 139867 : output logic [WIDTH-1:0] dout + 213 138801 : output logic [WIDTH-1:0] dout 214 : ); 215 : 216 : @@ -343,7 +343,7 @@ 239 : module rvdfflie #( parameter WIDTH=16, LEFT=8 ) 240 : ( 241 300 : input logic [WIDTH-1:0] din, - 242 59176340 : input logic clk, + 242 58629716 : input logic clk, 243 364 : input logic rst_l, 244 322 : input logic en, 245 0 : input logic scan_mode, @@ -397,12 +397,12 @@ 293 : // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en 294 : module rvdffppe #( parameter integer WIDTH = 39 ) 295 : ( - 296 219944 : input logic [WIDTH-1:0] din, - 297 61843746 : input logic clk, + 296 218996 : input logic [WIDTH-1:0] din, + 297 61251245 : input logic clk, 298 316 : input logic rst_l, - 299 5991939 : input logic en, + 299 5955435 : input logic en, 300 0 : input logic scan_mode, - 301 219944 : output logic [WIDTH-1:0] dout + 301 218996 : output logic [WIDTH-1:0] dout 302 : ); 303 : 304 : localparam integer RIGHT = 31; @@ -440,16 +440,16 @@ 336 : 337 : module rvdffie #( parameter WIDTH=1, OVERRIDE=0 ) 338 : ( - 339 149724 : input logic [WIDTH-1:0] din, + 339 149530 : input logic [WIDTH-1:0] din, 340 : - 341 61843746 : input logic clk, + 341 61251245 : input logic clk, 342 316 : input logic rst_l, 343 0 : input logic scan_mode, - 344 149724 : output logic [WIDTH-1:0] dout + 344 149530 : output logic [WIDTH-1:0] dout 345 : ); 346 : 347 0 : logic l1clk; - 348 78293 : logic en; + 348 78318 : logic en; 349 : 350 : 351 : @@ -519,13 +519,13 @@ 415 : 416 : module rvsyncss #(parameter WIDTH = 251) 417 : ( - 418 61843746 : input logic clk, + 418 61251245 : input logic clk, 419 316 : input logic rst_l, - 420 17 : input logic [WIDTH-1:0] din, - 421 12 : output logic [WIDTH-1:0] dout + 420 13 : input logic [WIDTH-1:0] din, + 421 10 : output logic [WIDTH-1:0] dout 422 : ); 423 : - 424 12 : logic [WIDTH-1:0] din_ff1; + 424 10 : logic [WIDTH-1:0] din_ff1; 425 : 426 : rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); 427 : rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); @@ -535,10 +535,10 @@ 431 : module rvsyncss_fpga #(parameter WIDTH = 251) 432 : ( 433 3127890 : input logic gw_clk, - 434 1502440592 : input logic rawclk, + 434 1493967734 : input logic rawclk, 435 10063 : input logic clken, 436 9960 : input logic rst_l, - 437 3421 : input logic [WIDTH-1:0] din, + 437 3423 : input logic [WIDTH-1:0] din, 438 3420 : output logic [WIDTH-1:0] dout 439 : ); 440 : @@ -551,17 +551,17 @@ 447 : 448 : module rvlsadder 449 : ( - 450 476238 : input logic [31:0] rs1, - 451 270136 : input logic [11:0] offset, + 450 474296 : input logic [31:0] rs1, + 451 269562 : input logic [11:0] offset, 452 : - 453 594111 : output logic [31:0] dout + 453 592373 : output logic [31:0] dout 454 : ); 455 : - 456 281606 : logic cout; - 457 368726 : logic sign; + 456 281032 : logic cout; + 457 368072 : logic sign; 458 : - 459 1464889 : logic [31:12] rs1_inc; - 460 17884 : logic [31:12] rs1_dec; + 459 1461019 : logic [31:12] rs1_inc; + 460 14626 : logic [31:12] rs1_dec; 461 : 462 : assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]}; 463 : @@ -582,13 +582,13 @@ 478 : module rvbradder 479 : ( 480 2210 : input [31:1] pc, - 481 3642214 : input [12:1] offset, + 481 3630007 : input [12:1] offset, 482 : - 483 139780 : output [31:1] dout + 483 138714 : output [31:1] dout 484 : ); 485 : - 486 4180298 : logic cout; - 487 3834276 : logic sign; + 486 4168177 : logic cout; + 487 3821249 : logic sign; 488 : 489 2280 : logic [31:13] pc_inc; 490 106032 : logic [31:13] pc_dec; @@ -615,10 +615,10 @@ 511 : ( 512 16813 : input logic [WIDTH-1:0] din, 513 : - 514 26587 : output logic [WIDTH-1:0] dout + 514 26555 : output logic [WIDTH-1:0] dout 515 : ); 516 : - 517 27432 : logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din + 517 27400 : logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din 518 : 519 : genvar i; 520 : @@ -700,7 +700,7 @@ 596 : // Check if the S_ADDR <= addr < E_ADDR 597 : module rvrangecheck #(CCM_SADR = 32'h0, 598 : CCM_SIZE = 128) ( - 599 1188555 : input logic [31:0] addr, // Address to be checked for range + 599 1185079 : input logic [31:0] addr, // Address to be checked for range 600 0 : output logic in_range, // S_ADDR <= start_addr < E_ADDR 601 828482 : output logic in_region 602 : ); @@ -744,7 +744,7 @@ 640 : 641 : module rvecc_encode ( 642 7578 : input [31:0] din, - 643 67266 : output [6:0] ecc_out + 643 67262 : output [6:0] ecc_out 644 : ); 645 50887 : logic [5:0] ecc_out_temp; 646 : @@ -760,12 +760,12 @@ 656 : endmodule // rvecc_encode 657 : 658 : module rvecc_decode ( - 659 2127952 : input en, - 660 505562 : input [31:0] din, - 661 839208 : input [6:0] ecc_in, + 659 2127910 : input en, + 660 505506 : input [31:0] din, + 661 839200 : input [6:0] ecc_in, 662 634 : input sed_ded, // only do detection and no correction. Used for the I$ - 663 505562 : output [31:0] dout, - 664 839208 : output [6:0] ecc_out, + 663 505506 : output [31:0] dout, + 664 839200 : output [6:0] ecc_out, 665 12 : output single_ecc_error, 666 8 : output double_ecc_error 667 : @@ -773,7 +773,7 @@ 669 : 670 1140 : logic [6:0] ecc_check; 671 0 : logic [38:0] error_mask; - 672 1009341 : logic [38:0] din_plus_parity, dout_plus_parity; + 672 1009261 : logic [38:0] din_plus_parity, dout_plus_parity; 673 : 674 : // Generate the ecc bits 675 : assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; @@ -804,8 +804,8 @@ 700 : endmodule // rvecc_decode 701 : 702 : module rvecc_encode_64 ( - 703 2037611 : input [63:0] din, - 704 4245520 : output [6:0] ecc_out + 703 2030380 : input [63:0] din, + 704 4223474 : output [6:0] ecc_out 705 : ); 706 : assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; 707 : @@ -825,7 +825,7 @@ 721 : 722 : 723 : module rvecc_decode_64 ( - 724 2629384 : input en, + 724 2629378 : input en, 725 446297 : input [63:0] din, 726 1164725 : input [6:0] ecc_in, 727 0 : output ecc_error @@ -896,10 +896,10 @@ 792 : 793 : module rvoclkhdr 794 : ( - 795 26675376 : input logic en, - 796 1670378587 : input logic clk, + 795 26514856 : input logic en, + 796 1654381060 : input logic clk, 797 0 : input logic scan_mode, - 798 1669902276 : output logic l1clk + 798 1653904749 : output logic l1clk 799 : ); 800 : 801 0 : logic SE; diff --git a/html/main/coverage_dashboard/all/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all/index_dmi_jtag_to_core_sync.v.html index cdab7d496da..18854fa2d56 100644 --- a/html/main/coverage_dashboard/all/index_dmi_jtag_to_core_sync.v.html +++ b/html/main/coverage_dashboard/all/index_dmi_jtag_to_core_sync.v.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -133,7 +133,7 @@ 29 : 30 : // Processor Signals 31 328 : input rst_n, // Core reset - 32 61850958 : input clk, // Core clock + 32 61258457 : input clk, // Core clock 33 : 34 270 : output reg_en, // 1 bit Write interface bit to Processor 35 128 : output reg_wr_en // 1 bit Write enable to Processor @@ -150,14 +150,14 @@ 46 : 47 : 48 : // synchronizers - 49 24266515 : always @ ( posedge clk or negedge rst_n) begin + 49 24138098 : always @ ( posedge clk or negedge rst_n) begin 50 1337 : if(!rst_n) begin 51 1349 : rden <= '0; 52 1349 : wren <= '0; 53 : end - 54 24265166 : else begin - 55 24265166 : rden <= {rden[1:0], rd_en}; - 56 24265166 : wren <= {wren[1:0], wr_en}; + 54 24136749 : else begin + 55 24136749 : rden <= {rden[1:0], rd_en}; + 56 24136749 : wren <= {wren[1:0], wr_en}; 57 : end 58 : end 59 : diff --git a/html/main/coverage_dashboard/all/index_dmi_mux.v.html b/html/main/coverage_dashboard/all/index_dmi_mux.v.html index e8b4d402dd4..01fa639f313 100644 --- a/html/main/coverage_dashboard/all/index_dmi_mux.v.html +++ b/html/main/coverage_dashboard/all/index_dmi_mux.v.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 diff --git a/html/main/coverage_dashboard/all/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all/index_dmi_wrapper.v.html index a1e53e7c7e2..b5747e1b60c 100644 --- a/html/main/coverage_dashboard/all/index_dmi_wrapper.v.html +++ b/html/main/coverage_dashboard/all/index_dmi_wrapper.v.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -137,7 +137,7 @@ 33 : 34 : // Processor Signals 35 328 : input core_rst_n, // Core reset - 36 61850958 : input core_clk, // Core clock + 36 61258457 : input core_clk, // Core clock 37 0 : input [31:1] jtag_id, // JTAG ID 38 14 : input [31:0] rd_data, // 32 bit Read data from Processor 39 22 : output [31:0] reg_wr_data, // 32 bit Write data to Processor diff --git a/html/main/coverage_dashboard/all/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all/index_el2_dbg.sv.html index 143a95d7231..12d72312e22 100644 --- a/html/main/coverage_dashboard/all/index_el2_dbg.sv.html +++ b/html/main/coverage_dashboard/all/index_el2_dbg.sv.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -140,7 +140,7 @@ 36 317 : output logic dbg_core_rst_l, // core reset from dm 37 : 38 : // inputs back from the core/dec - 39 314049 : input logic [31:0] core_dbg_rddata, + 39 314035 : input logic [31:0] core_dbg_rddata, 40 0 : input logic core_dbg_cmd_done, // This will be treated like a valid signal 41 0 : input logic core_dbg_cmd_fail, // Exception during command run 42 : @@ -211,8 +211,8 @@ 107 316 : input logic dbg_bus_clk_en, 108 : 109 : // general inputs - 110 61843746 : input logic clk, - 111 61843746 : input logic free_clk, + 110 61251245 : input logic clk, + 111 61251245 : input logic free_clk, 112 316 : input logic rst_l, // This includes both top rst and debug rst 113 316 : input logic dbg_rst_l, 114 0 : input logic clk_override, @@ -356,10 +356,10 @@ 252 : 253 : //clken 254 240 : logic dbg_free_clken; - 255 61843746 : logic dbg_free_clk; + 255 61251245 : logic dbg_free_clk; 256 : 257 240 : logic sb_free_clken; - 258 61843746 : logic sb_free_clk; + 258 61251245 : logic sb_free_clk; 259 : 260 : // clocking 261 : // used for the abstract commands. @@ -575,10 +575,10 @@ 471 317 : sb_abmem_data_done_en = 1'b0; 472 : 473 317 : case (dbg_state) - 474 24263282 : IDLE: begin - 475 24263282 : dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core - 476 24263282 : dbg_state_en = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only; // when the jtag writes the halt bit in the DM register, OR when the status indicates H - 477 24263282 : dbg_halt_req = dmcontrol_reg[31]; // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes + 474 24134865 : IDLE: begin + 475 24134865 : dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core + 476 24134865 : dbg_state_en = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only; // when the jtag writes the halt bit in the DM register, OR when the status indicates H + 477 24134865 : dbg_halt_req = dmcontrol_reg[31]; // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes 478 : end 479 0 : HALTING : begin 480 0 : dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK @@ -705,13 +705,13 @@ 601 317 : sbcs_sberror_din[2:0] = 3'b0; 602 317 : sbaddress0_reg_wren1 = 1'b0; 603 317 : case (sb_state) - 604 24263142 : SBIDLE: begin - 605 24263142 : sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD; - 606 24263142 : sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22]; - 607 24263142 : sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command - 608 24263142 : sbcs_sbbusy_din = 1'b1; - 609 24263142 : sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits - 610 24263142 : sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; + 604 24134725 : SBIDLE: begin + 605 24134725 : sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD; + 606 24134725 : sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22]; + 607 24134725 : sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command + 608 24134725 : sbcs_sbbusy_din = 1'b1; + 609 24134725 : sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits + 610 24134725 : sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; 611 : end 612 8 : WAIT_RD: begin 613 8 : sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD; diff --git a/html/main/coverage_dashboard/all/index_el2_dec.sv.html b/html/main/coverage_dashboard/all/index_el2_dec.sv.html index 943a7bb5509..7869191e9de 100644 --- a/html/main/coverage_dashboard/all/index_el2_dec.sv.html +++ b/html/main/coverage_dashboard/all/index_el2_dec.sv.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -136,24 +136,24 @@ 32 : #( 33 : `include "el2_param.vh" 34 : ) ( - 35 61843746 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. - 36 61843746 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. - 37 61843746 : input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in. - 38 61843746 : input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. + 35 61251245 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. + 36 61251245 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. + 37 61251245 : input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in. + 38 61251245 : input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. 39 : 40 4 : input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle 41 : 42 0 : output logic dec_extint_stall, // Stall on external interrupt 43 : - 44 6190087 : output logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked + 44 6153554 : output logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked 45 0 : output logic dec_pause_state_cg, // to top for active state clock gating 46 : - 47 2091300 : output logic dec_tlu_core_empty, + 47 2081032 : output logic dec_tlu_core_empty, 48 : 49 316 : input logic rst_l, // reset, active low 50 0 : input logic [31:1] rst_vec, // reset vector, from core pins 51 : - 52 17 : input logic nmi_int, // NMI pin + 52 15 : input logic nmi_int, // NMI pin 53 0 : input logic [31:1] nmi_vec, // NMI vector, from pins 54 : 55 0 : input logic i_cpu_halt_req, // Asynchronous Halt request to CPU @@ -174,27 +174,27 @@ 70 316 : output logic mpc_debug_run_ack, // Run ack 71 0 : output logic debug_brkpt_status, // debug breakpoint 72 : - 73 409754 : input logic exu_pmu_i0_br_misp, // slot 0 branch misp - 74 2868109 : input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken - 75 3459682 : input logic exu_pmu_i0_pc4, // slot 0 4 byte branch + 73 408472 : input logic exu_pmu_i0_br_misp, // slot 0 branch misp + 74 2862323 : input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken + 75 3452000 : input logic exu_pmu_i0_pc4, // slot 0 4 byte branch 76 : 77 : - 78 881640 : input logic lsu_nonblock_load_valid_m, // valid nonblock load at m - 79 504869 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag + 78 875716 : input logic lsu_nonblock_load_valid_m, // valid nonblock load at m + 79 502857 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag 80 0 : input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r - 81 504866 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag - 82 920896 : input logic lsu_nonblock_load_data_valid, // valid nonblock load data back + 81 502854 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag + 82 914818 : input logic lsu_nonblock_load_data_valid, // valid nonblock load data back 83 0 : input logic lsu_nonblock_load_data_error, // nonblock load bus error - 84 36662 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag - 85 71560 : input logic [31:0] lsu_nonblock_load_data, // nonblock load data + 84 36598 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag + 85 71538 : input logic [31:0] lsu_nonblock_load_data, // nonblock load data 86 : - 87 1667379 : input logic lsu_pmu_bus_trxn, // D side bus transaction - 88 36420 : input logic lsu_pmu_bus_misaligned, // D side bus misaligned + 87 1655267 : input logic lsu_pmu_bus_trxn, // D side bus transaction + 88 36414 : input logic lsu_pmu_bus_misaligned, // D side bus misaligned 89 0 : input logic lsu_pmu_bus_error, // D side bus error - 90 67818 : input logic lsu_pmu_bus_busy, // D side bus busy - 91 48786 : input logic lsu_pmu_misaligned_m, // D side load or store misaligned - 92 891764 : input logic lsu_pmu_load_external_m, // D side bus load - 93 806110 : input logic lsu_pmu_store_external_m, // D side bus store + 90 67790 : input logic lsu_pmu_bus_busy, // D side bus busy + 91 48780 : input logic lsu_pmu_misaligned_m, // D side load or store misaligned + 92 885840 : input logic lsu_pmu_load_external_m, // D side bus load + 93 800418 : input logic lsu_pmu_store_external_m, // D side bus store 94 0 : input logic dma_pmu_dccm_read, // DMA DCCM read 95 0 : input logic dma_pmu_dccm_write, // DMA DCCM write 96 0 : input logic dma_pmu_any_read, // DMA read @@ -203,13 +203,13 @@ 99 24694 : input logic [31:1] lsu_fir_addr, // Fast int address 100 0 : input logic [ 1:0] lsu_fir_error, // Fast int lookup error 101 : - 102 6190087 : input logic ifu_pmu_instr_aligned, // aligned instructions - 103 614530 : input logic ifu_pmu_fetch_stall, // fetch unit stalled - 104 5893104 : input logic ifu_pmu_ic_miss, // icache miss + 102 6153554 : input logic ifu_pmu_instr_aligned, // aligned instructions + 103 613228 : input logic ifu_pmu_fetch_stall, // fetch unit stalled + 104 5856146 : input logic ifu_pmu_ic_miss, // icache miss 105 744124 : input logic ifu_pmu_ic_hit, // icache hit 106 0 : input logic ifu_pmu_bus_error, // Instruction side bus error 107 4463637 : input logic ifu_pmu_bus_busy, // Instruction side bus busy - 108 10356722 : input logic ifu_pmu_bus_trxn, // Instruction side bus transaction + 108 10319765 : input logic ifu_pmu_bus_trxn, // Instruction side bus transaction 109 : 110 0 : input logic ifu_ic_error_start, // IC single bit error 111 8 : input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error @@ -228,11 +228,11 @@ 124 86 : input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst 125 2 : input logic ifu_i0_dbecc, // icache/iccm double-bit error 126 : - 127 1346967 : input logic lsu_idle_any, // lsu idle for halting + 127 1337985 : input logic lsu_idle_any, // lsu idle for halting 128 : - 129 200759 : input el2_br_pkt_t i0_brp, // branch packet - 130 651076 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index - 131 631672 : input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR + 129 200545 : input el2_br_pkt_t i0_brp, // branch packet + 130 650118 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index + 131 619214 : input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR 132 21217 : input logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag 133 0 : input logic [ $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index 134 : @@ -241,39 +241,39 @@ 137 : 138 0 : input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error 139 0 : input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error - 140 401 : input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address + 140 400 : input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address 141 : 142 24784 : input logic [31:0] exu_div_result, // final div result - 143 156868 : input logic exu_div_wren, // Divide write enable to GPR + 143 156836 : input logic exu_div_wren, // Divide write enable to GPR 144 : 145 3978 : input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction 146 : 147 38395 : input logic [31:0] lsu_result_m, // load result 148 29134 : input logic [31:0] lsu_result_corr_r, // load result - corrected load data 149 : - 150 49050 : input logic lsu_load_stall_any, // This is for blocking loads - 151 59374 : input logic lsu_store_stall_any, // This is for blocking stores + 150 48988 : input logic lsu_load_stall_any, // This is for blocking loads + 151 59312 : input logic lsu_store_stall_any, // This is for blocking stores 152 0 : input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event 153 26 : input logic dma_iccm_stall_any, // iccm stalled, pmu event 154 : 155 0 : input logic iccm_dma_sb_error, // ICCM DMA single bit error 156 : - 157 672565 : input logic exu_flush_final, // slot0 flush + 157 671016 : input logic exu_flush_final, // slot0 flush 158 : 159 313 : input logic [31:1] exu_npc_r, // next PC 160 : - 161 614701 : input logic [31:0] exu_i0_result_x, // alu result x + 161 613793 : input logic [31:0] exu_i0_result_x, // alu result x 162 : 163 : - 164 6006883 : input logic ifu_i0_valid, // fetch valids to instruction buffer - 165 468420 : input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer + 164 5971582 : input logic ifu_i0_valid, // fetch valids to instruction buffer + 165 467652 : input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer 166 1288 : input logic [31:1] ifu_i0_pc, // pc's for instruction buffer - 167 5735369 : input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst + 167 5716269 : input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst 168 308 : input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's 169 : 170 0 : input logic mexintpend, // External interrupt pending - 171 18 : input logic timer_int, // Timer interrupt pending (from pin) - 172 17 : input logic soft_int, // Software interrupt pending (from pin) + 171 14 : input logic timer_int, // Timer interrupt pending (from pin) + 172 13 : input logic soft_int, // Software interrupt pending (from pin) 173 : 174 0 : input logic [7:0] pic_claimid, // PIC claimid 175 0 : input logic [3:0] pic_pl, // PIC priv level @@ -290,7 +290,7 @@ 186 : // Debug start 187 0 : input logic dbg_halt_req, // DM requests a halt 188 0 : input logic dbg_resume_req, // DM requests a resume - 189 5892108 : input logic ifu_miss_state_idle, // I-side miss buffer empty + 189 5855150 : input logic ifu_miss_state_idle, // I-side miss buffer empty 190 : 191 0 : output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command 192 0 : output logic dec_tlu_debug_mode, // Core is in debug mode @@ -303,7 +303,7 @@ 199 : 200 0 : output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode 201 : - 202 314049 : output logic [31:0] dec_dbg_rddata, // debug command read data + 202 314035 : output logic [31:0] dec_dbg_rddata, // debug command read data 203 : 204 0 : output logic dec_dbg_cmd_done, // abstract command is done 205 0 : output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address) @@ -313,81 +313,81 @@ 209 0 : output logic dec_tlu_force_halt, // halt has been forced 210 : // Debug end 211 : // branch info from pipe0 for errors or counter updates - 212 2679213 : input logic [1:0] exu_i0_br_hist_r, // history + 212 2673781 : input logic [1:0] exu_i0_br_hist_r, // history 213 26468 : input logic exu_i0_br_error_r, // error 214 9608 : input logic exu_i0_br_start_error_r, // start error - 215 2970681 : input logic exu_i0_br_valid_r, // valid - 216 409754 : input logic exu_i0_br_mp_r, // mispredict - 217 2381498 : input logic exu_i0_br_middle_r, // middle of bank + 215 2962465 : input logic exu_i0_br_valid_r, // valid + 216 408472 : input logic exu_i0_br_mp_r, // mispredict + 217 2370984 : input logic exu_i0_br_middle_r, // middle of bank 218 : 219 : // branch info from pipe1 for errors or counter updates 220 : - 221 2110900 : input logic exu_i0_br_way_r, // way hit or repl + 221 2108159 : input logic exu_i0_br_way_r, // way hit or repl 222 : - 223 5130925 : output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data - 224 3565563 : output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data - 225 407880 : output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data - 226 598740 : output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data + 223 5100391 : output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data + 224 3549089 : output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data + 225 407844 : output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data + 226 598744 : output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data 227 : - 228 2134567 : output logic [31:0] dec_i0_immed_d, // immediate data - 229 123446 : output logic [12:1] dec_i0_br_immed_d, // br immediate data + 228 2132673 : output logic [31:0] dec_i0_immed_d, // immediate data + 229 122230 : output logic [12:1] dec_i0_br_immed_d, // br immediate data 230 : 231 1460 : output el2_alu_pkt_t i0_ap, // alu packet 232 : - 233 5393904 : output logic dec_i0_alu_decode_d, // schedule on D-stage alu - 234 3841554 : output logic dec_i0_branch_d, // Branch in D-stage + 233 5367615 : output logic dec_i0_alu_decode_d, // schedule on D-stage alu + 234 3829589 : output logic dec_i0_branch_d, // Branch in D-stage 235 : - 236 554879 : output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's + 236 553923 : output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's 237 : 238 1288 : output logic [31:1] dec_i0_pc_d, // pc's at decode - 239 80872 : output logic [ 3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable - 240 8634 : output logic [ 3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable + 239 79850 : output logic [ 3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable + 240 8622 : output logic [ 3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable 241 : - 242 314049 : output logic [31:0] dec_i0_result_r, // Result R-stage + 242 314035 : output logic [31:0] dec_i0_result_r, // Result R-stage 243 : - 244 623945 : output el2_lsu_pkt_t lsu_p, // lsu packet - 245 5476447 : output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands + 244 621353 : output el2_lsu_pkt_t lsu_p, // lsu packet + 245 5449748 : output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands 246 0 : output el2_mul_pkt_t mul_p, // mul packet - 247 78138 : output el2_div_pkt_t div_p, // div packet + 247 78122 : output el2_div_pkt_t div_p, // div packet 248 2628 : output logic dec_div_cancel, // cancel divide operation 249 : - 250 270518 : output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses + 250 269944 : output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses 251 : - 252 75092 : output logic dec_csr_ren_d, // CSR read enable - 253 6941 : output logic [31:0] dec_csr_rddata_d, // CSR read data + 252 74910 : output logic dec_csr_ren_d, // CSR read enable + 253 8136 : output logic [31:0] dec_csr_rddata_d, // CSR read data 254 : - 255 58638 : output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int - 256 58638 : output logic dec_tlu_flush_lower_wb, - 257 24686 : output logic [31:1] dec_tlu_flush_path_r, // tlu flush target + 255 58568 : output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int + 256 58568 : output logic dec_tlu_flush_lower_wb, + 257 24680 : output logic [31:1] dec_tlu_flush_path_r, // tlu flush target 258 29654 : output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state 259 18866 : output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache 260 : - 261 138654 : output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage + 261 137876 : output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage 262 : - 263 782203 : output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet + 263 779462 : output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet 264 : 265 340148 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc 266 514626 : output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc 267 312914 : output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc 268 48468 : output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc 269 : - 270 506364 : output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus - 271 631672 : output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr - 272 651076 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index + 270 504423 : output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus + 271 619214 : output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr + 272 650118 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index 273 21217 : output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag 274 : 275 0 : output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index 276 : - 277 2276073 : output logic dec_lsu_valid_raw_d, + 277 2264531 : output logic dec_lsu_valid_raw_d, 278 : 279 0 : output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control 280 : - 281 6189473 : output logic [1:0] dec_data_en, // clock-gate control logic - 282 5991939 : output logic [1:0] dec_ctl_en, + 281 6152939 : output logic [1:0] dec_data_en, // clock-gate control logic + 282 5955435 : output logic [1:0] dec_ctl_en, 283 : - 284 1427542 : input logic [15:0] ifu_i0_cinst, // 16b compressed instruction + 284 1422550 : input logic [15:0] ifu_i0_cinst, // 16b compressed instruction 285 : - 286 5519898 : output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet + 286 5496224 : output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet 287 : 288 : // PMP signals 289 0 : output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES], @@ -396,9 +396,9 @@ 292 : `ifdef RV_USER_MODE 293 : 294 : // Privilege mode - 295 866 : output logic priv_mode, - 296 960 : output logic priv_mode_eff, - 297 866 : output logic priv_mode_ns, + 295 841 : output logic priv_mode, + 296 931 : output logic priv_mode_eff, + 297 841 : output logic priv_mode_ns, 298 : 299 : // mseccfg CSR content for PMP 300 2 : output el2_mseccfg_pkt_t mseccfg, @@ -423,7 +423,7 @@ 319 0 : output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating 320 0 : output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating 321 : - 322 6162256 : output logic dec_tlu_i0_commit_cmt, // committed i0 instruction + 322 6125722 : output logic dec_tlu_i0_commit_cmt, // committed i0 instruction 323 0 : input logic scan_mode // Flop scan mode control 324 : 325 : ); @@ -432,44 +432,44 @@ 328 0 : logic dec_tlu_dec_clk_override; // to and from dec blocks 329 0 : logic clk_override; 330 : - 331 6006883 : logic dec_ib0_valid_d; + 331 5971582 : logic dec_ib0_valid_d; 332 : - 333 6190087 : logic dec_pmu_instr_decoded; - 334 238142 : logic dec_pmu_decode_stall; + 333 6153554 : logic dec_pmu_instr_decoded; + 334 236732 : logic dec_pmu_decode_stall; 335 264 : logic dec_pmu_presync_stall; - 336 14500 : logic dec_pmu_postsync_stall; + 336 14454 : logic dec_pmu_postsync_stall; 337 : 338 0 : logic dec_tlu_wr_pause_r; // CSR write to pause reg is at R. 339 : - 340 2497511 : logic [4:0] dec_i0_rs1_d; - 341 4174324 : logic [4:0] dec_i0_rs2_d; + 340 2486977 : logic [4:0] dec_i0_rs1_d; + 341 4163722 : logic [4:0] dec_i0_rs2_d; 342 : - 343 468420 : logic [31:0] dec_i0_instr_d; + 343 467652 : logic [31:0] dec_i0_instr_d; 344 : 345 0 : logic dec_tlu_trace_disable; 346 0 : logic dec_tlu_pipelining_disable; 347 : 348 : - 349 2809689 : logic [4:0] dec_i0_waddr_r; - 350 5678794 : logic dec_i0_wen_r; - 351 314049 : logic [31:0] dec_i0_wdata_r; - 352 41826 : logic dec_csr_wen_r; // csr write enable at wb - 353 1559962 : logic [11:0] dec_csr_rdaddr_r; // read address for csrs - 354 406 : logic [11:0] dec_csr_wraddr_r; // write address for csryes + 349 2798269 : logic [4:0] dec_i0_waddr_r; + 350 5660354 : logic dec_i0_wen_r; + 351 314035 : logic [31:0] dec_i0_wdata_r; + 352 41778 : logic dec_csr_wen_r; // csr write enable at wb + 353 1551842 : logic [11:0] dec_csr_rdaddr_r; // read address for csrs + 354 412 : logic [11:0] dec_csr_wraddr_r; // write address for csryes 355 1640 : logic [31:0] dec_csr_wrdata_r; // csr write data at wb 356 : - 357 906 : logic [11:0] dec_csr_rdaddr_d; // read address for csr - 358 83741 : logic dec_csr_legal_d; // csr indicates legal operation + 357 910 : logic [11:0] dec_csr_rdaddr_d; // read address for csr + 358 83511 : logic dec_csr_legal_d; // csr indicates legal operation 359 : - 360 41991 : logic dec_csr_wen_unq_d; // valid csr with write - for csr legal - 361 83863 : logic dec_csr_any_unq_d; // valid csr - for csr legal - 362 1346 : logic dec_csr_stall_int_ff; // csr is mie/mstatus + 360 41943 : logic dec_csr_wen_unq_d; // valid csr with write - for csr legal + 361 83633 : logic dec_csr_any_unq_d; // valid csr - for csr legal + 362 1330 : logic dec_csr_stall_int_ff; // csr is mie/mstatus 363 : - 364 264 : el2_trap_pkt_t dec_tlu_packet_r; + 364 258 : el2_trap_pkt_t dec_tlu_packet_r; 365 : - 366 5735369 : logic dec_i0_pc4_d; + 366 5716269 : logic dec_i0_pc4_d; 367 510 : logic dec_tlu_presync_d; - 368 20293 : logic dec_tlu_postsync_d; + 368 20137 : logic dec_tlu_postsync_d; 369 0 : logic dec_tlu_debug_stall; 370 : 371 18 : logic [31:0] dec_illegal_inst; @@ -480,18 +480,18 @@ 376 86 : logic dec_i0_icaf_second_d; 377 0 : logic [3:0] dec_i0_trigger_match_d; 378 0 : logic dec_debug_fence_d; - 379 920884 : logic dec_nonblock_load_wen; - 380 368914 : logic [4:0] dec_nonblock_load_waddr; + 379 914806 : logic dec_nonblock_load_wen; + 380 368026 : logic [4:0] dec_nonblock_load_waddr; 381 0 : logic dec_tlu_flush_pause_r; - 382 200759 : el2_br_pkt_t dec_i0_brp; - 383 651076 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index; - 384 631672 : logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr; + 382 200545 : el2_br_pkt_t dec_i0_brp; + 383 650118 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index; + 384 619214 : logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr; 385 21217 : logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag; 386 0 : logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index; // Fully associt btb index 387 : 388 308 : logic [31:1] dec_tlu_i0_pc_r; 389 29654 : logic dec_tlu_i0_kill_writeb_wb; - 390 6189442 : logic dec_tlu_i0_valid_r; + 390 6152908 : logic dec_tlu_i0_valid_r; 391 : 392 0 : logic dec_pause_state; 393 : @@ -499,15 +499,15 @@ 395 : 396 0 : logic dec_tlu_flush_extint; // Fast ext int started 397 : - 398 579528 : logic [31:0] dec_i0_inst_wb; + 398 575173 : logic [31:0] dec_i0_inst_wb; 399 308 : logic [31:1] dec_i0_pc_wb; - 400 6125550 : logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1; + 400 6096026 : logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1; 401 0 : logic [ 4:0] dec_tlu_exc_cause_wb1; - 402 54 : logic [31:0] dec_tlu_mtval_wb1; - 403 5118 : logic dec_tlu_i0_exc_valid_wb1; + 402 52 : logic [31:0] dec_tlu_mtval_wb1; + 403 5092 : logic dec_tlu_i0_exc_valid_wb1; 404 : - 405 21351 : logic [ 4:0] div_waddr_wb; - 406 159496 : logic dec_div_active; + 405 21350 : logic [ 4:0] div_waddr_wb; + 406 159464 : logic dec_div_active; 407 : 408 0 : logic dec_debug_valid_d; 409 : diff --git a/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_m.svh.html index d4fed36fa2b..104035df078 100644 --- a/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_m.svh.html +++ b/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_m.svh.html @@ -51,7 +51,7 @@ Test Date: - 19-09-2024 + 25-09-2024 @@ -102,25 +102,25 @@ 
            Line data    Source code
-       1          138 : logic csr_misa;
+       1          144 : logic csr_misa;
        2            4 : logic csr_mvendorid;
        3           36 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5          176 : logic csr_mhartid;
-       6        49132 : logic csr_mstatus;
-       7          160 : logic csr_mtvec;
+       6        49178 : logic csr_mstatus;
+       7          164 : logic csr_mtvec;
        8           44 : logic csr_mip;
-       9          132 : logic csr_mie;
-      10           16 : logic csr_mcyclel;
+       9          136 : logic csr_mie;
+      10           12 : logic csr_mcyclel;
       11            8 : logic csr_mcycleh;
-      12            2 : logic csr_minstretl;
-      13            2 : logic csr_minstreth;
+      12            4 : logic csr_minstretl;
+      13            4 : logic csr_minstreth;
       14        31252 : logic csr_mscratch;
-      15        10282 : logic csr_mepc;
-      16         6346 : logic csr_mcause;
+      15        10290 : logic csr_mepc;
+      16         6358 : logic csr_mcause;
       17           28 : logic csr_mscause;
       18            4 : logic csr_mtval;
-      19           29 : logic csr_mrac;
+      19           27 : logic csr_mrac;
       20            2 : logic csr_dmst;
       21           34 : logic csr_mdseac;
       22           10 : logic csr_meihap;
@@ -130,7 +130,7 @@
       26            6 : logic csr_meicidpl;
       27            0 : logic csr_dcsr;
       28            6 : logic csr_mcgc;
-      29           48 : logic csr_mfdc;
+      29           46 : logic csr_mfdc;
       30            2 : logic csr_dpc;
       31            4 : logic csr_mtsel;
       32            6 : logic csr_mtdata1;
@@ -177,14 +177,14 @@
       73            0 : logic csr_dicad0;
       74            0 : logic csr_dicad1;
       75            2 : logic csr_dicago;
-      76          164 : logic csr_pmpcfg;
-      77          162 : logic csr_pmpaddr0;
+      76          170 : logic csr_pmpcfg;
+      77          168 : logic csr_pmpaddr0;
       78            4 : logic csr_pmpaddr16;
       79            2 : logic csr_pmpaddr32;
       80            4 : logic csr_pmpaddr48;
       81           42 : logic valid_only;
-      82           96 : logic presync;
-      83        38623 : logic postsync;
+      82           98 : logic presync;
+      83        38661 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370        51765 : logic legal;
+     370        51825 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_mu.svh.html
index f68634ffa3b..dad6a9d9b88 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -102,25 +102,25 @@
 
 
            Line data    Source code

 
-       1          166 : logic csr_misa;
+       1          160 : logic csr_misa;
        2            8 : logic csr_mvendorid;
        3           10 : logic csr_marchid;
        4            8 : logic csr_mimpid;
        5          136 : logic csr_mhartid;
-       6        29432 : logic csr_mstatus;
-       7          182 : logic csr_mtvec;
+       6        29222 : logic csr_mstatus;
+       7          178 : logic csr_mtvec;
        8           10 : logic csr_mip;
-       9          152 : logic csr_mie;
-      10           24 : logic csr_mcyclel;
+       9          148 : logic csr_mie;
+      10           28 : logic csr_mcyclel;
       11           16 : logic csr_mcycleh;
-      12           14 : logic csr_minstretl;
-      13           14 : logic csr_minstreth;
+      12           12 : logic csr_minstretl;
+      13           12 : logic csr_minstreth;
       14        19076 : logic csr_mscratch;
-      15         3908 : logic csr_mepc;
-      16         2968 : logic csr_mcause;
+      15         3810 : logic csr_mepc;
+      16         2882 : logic csr_mcause;
       17           10 : logic csr_mscause;
       18          174 : logic csr_mtval;
-      19           22 : logic csr_mrac;
+      19           24 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            8 : logic csr_mdseac;
       22           12 : logic csr_meihap;
@@ -130,7 +130,7 @@
       26           10 : logic csr_meicidpl;
       27            0 : logic csr_dcsr;
       28           10 : logic csr_mcgc;
-      29            8 : logic csr_mfdc;
+      29           10 : logic csr_mfdc;
       30            0 : logic csr_dpc;
       31           12 : logic csr_mtsel;
       32           10 : logic csr_mtdata1;
@@ -180,12 +180,12 @@
       76            2 : logic csr_dicago;
       77           20 : logic csr_menvcfg;
       78           16 : logic csr_menvcfgh;
-      79          732 : logic csr_pmpcfg;
-      80          640 : logic csr_pmpaddr0;
+      79          726 : logic csr_pmpcfg;
+      80          634 : logic csr_pmpaddr0;
       81           12 : logic csr_pmpaddr16;
       82            8 : logic csr_pmpaddr32;
       83           10 : logic csr_pmpaddr48;
-      84        32044 : logic csr_cyclel;
+      84        31752 : logic csr_cyclel;
       85           46 : logic csr_cycleh;
       86           44 : logic csr_instretl;
       87           44 : logic csr_instreth;
@@ -200,8 +200,8 @@
       96          110 : logic csr_mseccfgl;
       97           14 : logic csr_mseccfgh;
       98           82 : logic valid_only;
-      99          502 : logic presync;
-     100        25278 : logic postsync;
+      99          500 : logic presync;
+     100        25166 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444        31978 : logic legal;
+     444        31688 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_dec_decode_ctl.sv.html
index 05cdfd066f2..8bdd7da15fe 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,18 +133,18 @@
       29              : 
       30            0 :    output logic dec_extint_stall,            // Stall from external interrupt
       31              : 
-      32      1427542 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
-      33       579528 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
+      32      1422550 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
+      33       575173 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
       34          308 :    output logic [31:1] dec_i0_pc_wb,         // 31b pc at wb+1 for trace encoder
       35              : 
       36              : 
-      37       881640 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
-      38       504869 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
+      37       875716 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
+      38       502857 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
       39            0 :    input logic                                lsu_nonblock_load_inv_r,         // invalidate request for nonblock load r
-      40       504866 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
-      41       920896 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
+      40       502854 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
+      41       914818 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
       42            0 :    input logic                                lsu_nonblock_load_data_error,    // nonblock load bus error
-      43        36662 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
+      43        36598 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
       44              : 
       45              : 
       46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
@@ -154,7 +154,7 @@
       50              : 
       51            0 :    input logic [3:0]  lsu_trigger_match_m,            // lsu trigger matches
       52              : 
-      53        48786 :    input logic lsu_pmu_misaligned_m,                  // perf mon: load/store misalign
+      53        48780 :    input logic lsu_pmu_misaligned_m,                  // perf mon: load/store misalign
       54            0 :    input logic dec_tlu_debug_stall,                   // debug stall decode
       55            0 :    input logic dec_tlu_flush_leak_one_r,              // leak1 instruction
       56              : 
@@ -168,137 +168,137 @@
       64              : 
       65            2 :    input logic dec_i0_dbecc_d,                        // icache/iccm double-bit error
       66              : 
-      67       200759 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
-      68       651076 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69       631672 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      67       200545 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
+      68       650118 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      69       619214 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70        21217 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
-      73      1346967 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
+      73      1337985 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
       74              : 
-      75        49050 :    input logic lsu_load_stall_any,                    // stall any load at decode
-      76        59374 :    input logic lsu_store_stall_any,                   // stall any store at decode
+      75        48988 :    input logic lsu_load_stall_any,                    // stall any load at decode
+      76        59312 :    input logic lsu_store_stall_any,                   // stall any store at decode
       77            0 :    input logic dma_dccm_stall_any,                    // stall any load/store at decode
       78              : 
-      79       156868 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
+      79       156836 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
       80              : 
       81        29654 :    input logic dec_tlu_i0_kill_writeb_wb,             // I0 is flushed, don't writeback any results to arch state
-      82        58638 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
+      82        58568 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
       83        29654 :    input logic dec_tlu_i0_kill_writeb_r,              // I0 is flushed, don't writeback any results to arch state
-      84        58638 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
+      84        58568 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
       85            0 :    input logic dec_tlu_flush_pause_r,                 // don't clear pause state on initial lower flush
       86          510 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
-      87        20293 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
+      87        20137 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89      5735369 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89      5716269 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91         6941 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92        83741 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91         8136 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92        83511 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94         3978 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
       96        38395 :    input logic [31:0] lsu_result_m,                   // load result
       97        29134 :    input logic [31:0] lsu_result_corr_r,              // load result - corrected data for writing gpr's, not for bypassing
       98              : 
-      99       672565 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
+      99       671016 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
      100              : 
      101          308 :    input logic [31:1] exu_i0_pc_x,                    // pcs at e1
      102              : 
-     103       468420 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
+     103       467652 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
      104              : 
-     105      6006883 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
+     105      5971582 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
      106              : 
-     107       614701 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
+     107       613793 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109     61843746 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110     61843746 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111     61843746 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109     61251245 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110     61251245 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111     61251245 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114          316 :    input logic  rst_l,                                // Flop reset
      115              : 
      116              : 
      117              : 
-     118      5130925 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
-     119      3565563 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
+     118      5100391 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
+     119      3549089 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
-     121      2497511 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122      4174324 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     121      2486977 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
+     122      4163722 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124      2134567 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124      2132673 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
-     127       123446 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
+     127       122230 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
      128              : 
      129         1460 :    output el2_alu_pkt_t i0_ap,                       // alu packets
      130              : 
-     131      6190087 :    output logic        dec_i0_decode_d,               // i0 decode
+     131      6153554 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
-     133      5393904 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134      3841554 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     133      5367615 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
+     134      3829589 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
-     136      2809689 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137      5678794 :    output logic        dec_i0_wen_r,                  // i0 write enable
-     138       314049 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
+     136      2798269 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
+     137      5660354 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     138       314035 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
-     140       554879 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
+     140       553923 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
      141              : 
-     142        80872 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
-     143         8634 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
-     144       314049 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
+     142        79850 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
+     143         8622 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
+     144       314035 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
      145              : 
-     146       623945 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
-     147      5476447 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
+     146       621353 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
+     147      5449748 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
      148              : 
      149            0 :    output el2_mul_pkt_t    mul_p,                    // multiply packet
      150              : 
-     151        78138 :    output el2_div_pkt_t    div_p,                    // divide packet
-     152        21351 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
+     151        78122 :    output el2_div_pkt_t    div_p,                    // divide packet
+     152        21350 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
      153         2628 :    output logic             dec_div_cancel,           // cancel the divide operation
      154              : 
-     155      2276073 :    output logic        dec_lsu_valid_raw_d,
-     156       270518 :    output logic [11:0] dec_lsu_offset_d,
+     155      2264531 :    output logic        dec_lsu_valid_raw_d,
+     156       269944 :    output logic [11:0] dec_lsu_offset_d,
      157              : 
-     158        75092 :    output logic        dec_csr_ren_d,                 // valid csr decode
-     159        41991 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
-     160        83863 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
-     161          906 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
-     162        41826 :    output logic        dec_csr_wen_r,                 // csr write enable at r
-     163      1559962 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
-     164          406 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
+     158        74910 :    output logic        dec_csr_ren_d,                 // valid csr decode
+     159        41943 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
+     160        83633 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
+     161          910 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
+     162        41778 :    output logic        dec_csr_wen_r,                 // csr write enable at r
+     163      1551842 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
+     164          412 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
      165         1640 :    output logic [31:0] dec_csr_wrdata_r,              // csr write data at r
-     166         1346 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
+     166         1330 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
      167              : 
-     168      6189442 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
+     168      6152908 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
      169              : 
-     170          264 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
+     170          258 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
      171              : 
      172          308 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
      173              : 
      174           18 :    output logic [31:0] dec_illegal_inst,              // illegal inst
-     175       138654 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
+     175       137876 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
-     177       506364 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178       631672 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
-     179       651076 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
+     177       504423 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
+     178       619214 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     179       650118 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180        21217 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      183              : 
-     184      6189473 :    output logic [1:0] dec_data_en,                    // clock-gating logic
-     185      5991939 :    output logic [1:0] dec_ctl_en,
+     184      6152939 :    output logic [1:0] dec_data_en,                    // clock-gating logic
+     185      5955435 :    output logic [1:0] dec_ctl_en,
      186              : 
-     187      6190087 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
-     188       238142 :    output logic       dec_pmu_decode_stall,           // decode is stalled
+     187      6153554 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
+     188       236732 :    output logic       dec_pmu_decode_stall,           // decode is stalled
      189          264 :    output logic       dec_pmu_presync_stall,          // decode has presync stall
-     190        14500 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
+     190        14454 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
      191              : 
-     192       920884 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
-     193       368914 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
+     192       914806 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
+     193       368026 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
      194            0 :    output logic       dec_pause_state,                // core in pause state
      195            0 :    output logic       dec_pause_state_cg,             // pause state for clock-gating
      196              : 
-     197       159496 :    output logic       dec_div_active,                 // non-block divide is active
+     197       159464 :    output logic       dec_div_active,                 // non-block divide is active
      198              : 
      199            0 :    input  logic       scan_mode
      200              :    );
@@ -308,27 +308,27 @@
      204              : 
      205        13730 :    el2_dec_pkt_t           i0_dp_raw, i0_dp;
      206              : 
-     207       468420 :    logic [31:0]        i0;
-     208      6006883 :    logic               i0_valid_d;
+     207       467652 :    logic [31:0]        i0;
+     208      5971582 :    logic               i0_valid_d;
      209              : 
-     210       314049 :    logic [31:0]        i0_result_r;
+     210       314035 :    logic [31:0]        i0_result_r;
      211              : 
-     212        25118 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
+     212        24956 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
      213              : 
-     214       442798 :    logic               i0_jalimm20;
-     215       430821 :    logic               i0_uiimm20;
+     214       442030 :    logic               i0_jalimm20;
+     215       430139 :    logic               i0_uiimm20;
      216              : 
-     217      2280185 :    logic               lsu_decode_d;
-     218      2134567 :    logic [31:0]        i0_immed_d;
+     217      2268605 :    logic               lsu_decode_d;
+     218      2132673 :    logic [31:0]        i0_immed_d;
      219        70084 :    logic               i0_presync;
-     220       120087 :    logic               i0_postsync;
+     220       118235 :    logic               i0_postsync;
      221              : 
-     222       110610 :    logic               postsync_stall;
-     223       110610 :    logic               ps_stall;
+     222       110390 :    logic               postsync_stall;
+     223       110390 :    logic               ps_stall;
      224              : 
-     225      5991939 :    logic               prior_inflight, prior_inflight_wb;
+     225      5955435 :    logic               prior_inflight, prior_inflight_wb;
      226              : 
-     227        10618 :    logic               csr_clr_d, csr_set_d, csr_write_d;
+     227        10570 :    logic               csr_clr_d, csr_set_d, csr_write_d;
      228              : 
      229         7868 :    logic               csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
      230         4282 :    logic [31:0]        csr_mask_x;
@@ -339,61 +339,61 @@
      235              : 
      236        10844 :    logic [4:0]         csrimm_x;
      237              : 
-     238         1554 :    logic [31:0]        csr_rddata_x;
+     238         1552 :    logic [31:0]        csr_rddata_x;
      239              : 
      240       250948 :    logic               mul_decode_d;
-     241       159496 :    logic               div_decode_d;
-     242       159496 :    logic               div_e1_to_r;
+     241       159464 :    logic               div_decode_d;
+     242       159464 :    logic               div_e1_to_r;
      243         2628 :    logic               div_flush;
-     244       159496 :    logic               div_active_in;
-     245       159496 :    logic               div_active;
+     244       159464 :    logic               div_active_in;
+     245       159464 :    logic               div_active;
      246         8228 :    logic               i0_nonblock_div_stall;
      247         1472 :    logic               i0_div_prior_div_stall;
      248         2628 :    logic               nonblock_div_cancel;
      249              : 
-     250      5997067 :    logic               i0_legal;
-     251          258 :    logic               shift_illegal;
-     252          258 :    logic               illegal_inst_en;
-     253          258 :    logic               illegal_lockout_in, illegal_lockout;
-     254      6189849 :    logic               i0_legal_decode_d;
-     255       315576 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
+     250      5963290 :    logic               i0_legal;
+     251          254 :    logic               shift_illegal;
+     252          254 :    logic               illegal_inst_en;
+     253          254 :    logic               illegal_lockout_in, illegal_lockout;
+     254      6153320 :    logic               i0_legal_decode_d;
+     255       314030 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
-     257      1376313 :    logic [12:1]        last_br_immed_d;
-     258      1920488 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
+     257      1369717 :    logic [12:1]        last_br_immed_d;
+     258      1919302 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259       170364 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
-     261       159496 :    logic               i0_div_decode_d;
+     261       159464 :    logic               i0_div_decode_d;
      262            0 :    logic               i0_load_block_d;
      263       155352 :    logic [1:0]         i0_rs1_depth_d, i0_rs2_depth_d;
      264              : 
-     265        27508 :    logic               i0_load_stall_d;
-     266         6856 :    logic               i0_store_stall_d;
+     265        27470 :    logic               i0_load_stall_d;
+     266         6832 :    logic               i0_store_stall_d;
      267              : 
-     268       767143 :    logic               i0_predict_nt, i0_predict_t;
+     268       762036 :    logic               i0_predict_nt, i0_predict_t;
      269              : 
-     270        28608 :    logic               i0_notbr_error, i0_br_toffset_error;
+     270        27044 :    logic               i0_notbr_error, i0_br_toffset_error;
      271          396 :    logic               i0_ret_error;
-     272        38500 :    logic               i0_br_error;
-     273        38510 :    logic               i0_br_error_all;
-     274      1571805 :    logic [11:0]        i0_br_offset;
+     272        36868 :    logic               i0_br_error;
+     273        36878 :    logic               i0_br_error_all;
+     274      1563856 :    logic [11:0]        i0_br_offset;
      275              : 
-     276      1432006 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
-     277      5586531 :    logic               i0_pcall_12b_offset;
-     278       122488 :    logic               i0_pcall_raw;
-     279       122818 :    logic               i0_pcall_case;
-     280       122134 :    logic               i0_pcall;
+     276      1427266 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
+     277      5554974 :    logic               i0_pcall_12b_offset;
+     278       122252 :    logic               i0_pcall_raw;
+     279       122582 :    logic               i0_pcall_case;
+     280       121898 :    logic               i0_pcall;
      281              : 
-     282       312544 :    logic               i0_pja_raw;
-     283       321698 :    logic               i0_pja_case;
-     284       311586 :    logic               i0_pja;
+     282       312012 :    logic               i0_pja_raw;
+     283       321158 :    logic               i0_pja_case;
+     284       311054 :    logic               i0_pja;
      285              : 
-     286       167480 :    logic               i0_pret_case;
-     287       167480 :    logic               i0_pret_raw, i0_pret;
+     286       167248 :    logic               i0_pret_case;
+     287       167248 :    logic               i0_pret_raw, i0_pret;
      288              : 
-     289       106068 :    logic               i0_jal;                                // jal's that are not predicted
+     289       105892 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292      3700988 :    logic               i0_predict_br;
+     292      3690831 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298       234134 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301      5735369 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301      5716269 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303      6449133 :    logic               i0_rd_en_d;
+     303      6425435 :    logic               i0_rd_en_d;
      304              : 
      305        69392 :    logic               load_ldst_bypass_d;
      306              : 
@@ -412,43 +412,43 @@
      308            0 :    logic               leak1_i1_stall_in, leak1_i1_stall;
      309            0 :    logic               leak1_mode;
      310              : 
-     311         8779 :    logic               i0_csr_write_only_d;
+     311         8731 :    logic               i0_csr_write_only_d;
      312              : 
-     313      5992087 :    logic               prior_inflight_x, prior_inflight_eff;
-     314        83863 :    logic               any_csr_d;
+     313      5955583 :    logic               prior_inflight_x, prior_inflight_eff;
+     314        83633 :    logic               any_csr_d;
      315              : 
-     316         8776 :    logic               prior_csr_write;
+     316         8728 :    logic               prior_csr_write;
      317              : 
-     318      6189398 :    logic [3:0]        i0_pipe_en;
-     319      5991905 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
-     320      6189448 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
+     318      6152864 :    logic [3:0]        i0_pipe_en;
+     319      5955401 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
+     320      6152914 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
      321              : 
      322            0 :    logic              debug_fence_i;
      323            0 :    logic              debug_fence;
      324              : 
-     325        25025 :    logic              i0_csr_write;
+     325        24977 :    logic              i0_csr_write;
      326          264 :    logic              presync_stall;
      327              : 
      328          198 :    logic              i0_instr_error;
      329          198 :    logic              i0_icaf_d;
      330              : 
-     331        58638 :    logic              clear_pause;
+     331        58568 :    logic              clear_pause;
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335      3092343 :    logic              i0_brp_valid;
-     336       737208 :    logic              nonblock_load_cancel;
-     337      1346966 :    logic              lsu_idle;
-     338        48786 :    logic              lsu_pmu_misaligned_r;
-     339        74956 :    logic              csr_ren_qual_d;
-     340        74956 :    logic              csr_read_x;
-     341       349570 :    logic              i0_block_d;
-     342       315576 :    logic              i0_block_raw_d;  // This is use to create the raw valid
-     343       110611 :    logic              ps_stall_in;
-     344       660429 :    logic [31:0]       i0_result_x;
+     335      3082497 :    logic              i0_brp_valid;
+     336       732630 :    logic              nonblock_load_cancel;
+     337      1337984 :    logic              lsu_idle;
+     338        48780 :    logic              lsu_pmu_misaligned_r;
+     339        74774 :    logic              csr_ren_qual_d;
+     340        74774 :    logic              csr_read_x;
+     341       347962 :    logic              i0_block_d;
+     342       314030 :    logic              i0_block_raw_d;  // This is use to create the raw valid
+     343       110391 :    logic              ps_stall_in;
+     344       659105 :    logic [31:0]       i0_result_x;
      345              : 
-     346        31368 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
-     347        31368 :    el2_dest_pkt_t         x_d_in, r_d_in;
+     346        29602 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
+     347        29602 :    el2_dest_pkt_t         x_d_in, r_d_in;
      348              : 
      349            0 :    el2_trap_pkt_t         d_t, x_t, x_t_in, r_t_in, r_t;
      350              : 
@@ -456,16 +456,16 @@
      352              : 
      353          308 :    logic [31:1]       dec_i0_pc_r;
      354              : 
-     355        41933 :    logic csr_read, csr_write;
-     356       106068 :    logic i0_br_unpred;
+     355        41877 :    logic csr_read, csr_write;
+     356       105892 :    logic i0_br_unpred;
      357              : 
-     358       881494 :    logic nonblock_load_valid_m_delay;
-     359      6514124 :    logic i0_wen_r;
+     358       875570 :    logic nonblock_load_valid_m_delay;
+     359      6490314 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
      363              : 
-     364       672564 :    logic flush_final_r;
+     364       671014 :    logic flush_final_r;
      365              : 
      366          317 :    logic bitmanip_zbb_legal;
      367          317 :    logic bitmanip_zbs_legal;
@@ -489,52 +489,52 @@
      385              :    localparam NBLOAD_TAG_MSB  = pt.LSU_NUM_NBLOAD_WIDTH-1;
      386              : 
      387              : 
-     388       920896 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
-     389        36662 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
-     390         5812 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
+     388       914818 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
+     389        36598 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
+     390         5806 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
      391              : 
-     392        36662 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
-     393         6392 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
+     392        36598 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
+     393         6386 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
      394              : 
-     395         5811 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
-     396         5811 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
-     397         5811 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
+     395         5805 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
+     396         5805 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
+     397         5805 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
      398              : 
-     399       531394 :    logic [4:0] nonblock_load_rd;
-     400       190690 :    logic i0_nonblock_load_stall;
-     401        89472 :    logic i0_nonblock_boundary_stall;
+     399       530478 :    logic [4:0] nonblock_load_rd;
+     400       189364 :    logic i0_nonblock_load_stall;
+     401        88294 :    logic i0_nonblock_boundary_stall;
      402              : 
-     403        26942 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
+     403        26930 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
      404              : 
-     405       881494 :    logic i0_load_kill_wen_r;
+     405       875570 :    logic i0_load_kill_wen_r;
      406              : 
-     407         2411 :    logic found;
+     407         2409 :    logic found;
      408              : 
-     409         5808 :    logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;
+     409         5802 :    logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;
      410              : 
      411            0 :    logic debug_fence_raw;
      412              : 
-     413       314049 :    logic [31:0] i0_result_r_raw;
-     414       314049 :    logic [31:0] i0_result_corr_r;
+     413       314035 :    logic [31:0] i0_result_r_raw;
+     414       314035 :    logic [31:0] i0_result_corr_r;
      415              : 
-     416      1134323 :    logic [12:1] last_br_immed_x;
+     416      1128183 :    logic [12:1] last_br_immed_x;
      417              : 
-     418       897486 :    logic [31:0]        i0_inst_d;
-     419       579534 :    logic [31:0]        i0_inst_x;
-     420       579533 :    logic [31:0]        i0_inst_r;
-     421       579533 :    logic [31:0]        i0_inst_wb_in;
-     422       579528 :    logic [31:0]        i0_inst_wb;
+     418       892642 :    logic [31:0]        i0_inst_d;
+     419       575179 :    logic [31:0]        i0_inst_x;
+     420       575178 :    logic [31:0]        i0_inst_r;
+     421       575178 :    logic [31:0]        i0_inst_wb_in;
+     422       575173 :    logic [31:0]        i0_inst_wb;
      423              : 
      424          308 :    logic [31:1]        i0_pc_wb;
      425              : 
-     426      6189448 :    logic               i0_wb_en;
+     426      6152914 :    logic               i0_wb_en;
      427              : 
      428          317 :    logic               trace_enable;
      429              : 
      430            0 :    logic               debug_valid_x;
      431              : 
-     432      2152010 :    el2_inst_pkt_t i0_itype;
-     433      2345922 :    el2_reg_pkt_t i0r;
+     432      2141623 :    el2_inst_pkt_t i0_itype;
+     433      2335414 :    el2_reg_pkt_t i0r;
      434              : 
      435              : 
      436              :    rvdffie  #(8) misc1ff (.*,
@@ -631,14 +631,14 @@
      527              : 
      528          317 :    always_comb begin
      529          317 :       i0_dp = i0_dp_raw;
-     530      1744660 :       if (i0_br_error_all | i0_instr_error) begin
-     531        40180 :          i0_dp          =   '0;
-     532        40180 :          i0_dp.alu      = 1'b1;
-     533        40180 :          i0_dp.rs1      = 1'b1;
-     534        40180 :          i0_dp.rs2      = 1'b1;
-     535        40180 :          i0_dp.lor      = 1'b1;
-     536        40180 :          i0_dp.legal    = 1'b1;
-     537        40180 :          i0_dp.postsync = 1'b1;
+     530      1840732 :       if (i0_br_error_all | i0_instr_error) begin
+     531        39000 :          i0_dp          =   '0;
+     532        39000 :          i0_dp.alu      = 1'b1;
+     533        39000 :          i0_dp.rs1      = 1'b1;
+     534        39000 :          i0_dp.rs2      = 1'b1;
+     535        39000 :          i0_dp.lor      = 1'b1;
+     536        39000 :          i0_dp.legal    = 1'b1;
+     537        39000 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -709,16 +709,16 @@
      605          317 :       found = 0;
      606          317 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607        10974 :          if (~found) begin
-     608      2573985 :             if (~cam[i].valid) begin
-     609     23580095 :                cam_wen[i] = cam_write;
-     610     23580095 :                found = 1'b1;
+     608      2568198 :             if (~cam[i].valid) begin
+     609     23455235 :                cam_wen[i] = cam_write;
+     610     23455235 :                found = 1'b1;
      611              :             end
-     612      2573985 :             else begin
-     613      2573985 :                cam_wen[i] = 0;
+     612      2568198 :             else begin
+     613      2568198 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617     81057788 :             cam_wen[i] = 0;
+     617     80630465 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,28 +756,28 @@
      652              : 
      653         1268 :          cam[i] = cam_raw[i];
      654              : 
-     655     16946563 :          if (cam_data_reset_val[i])
-     656       472907 :            cam[i].valid = 1'b0;
+     655     16535812 :          if (cam_data_reset_val[i])
+     656       472348 :            cam[i].valid = 1'b0;
      657              : 
      658         1268 :          cam_in[i] = '0;
      659              : 
-     660      1418800 :          if (cam_wen[i]) begin
-     661      1418800 :             cam_in[i].valid    = 1'b1;
-     662      1418800 :             cam_in[i].wb       = 1'b0;
-     663      1418800 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
-     664      1418800 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
+     660      1417123 :          if (cam_wen[i]) begin
+     661      1417123 :             cam_in[i].valid    = 1'b1;
+     662      1417123 :             cam_in[i].wb       = 1'b0;
+     663      1417123 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
+     664      1417123 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666     16654726 :          else if ( (cam_inv_reset_val[i]) |
+     666     16244479 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
-     668        56444 :            cam_in[i].valid = 1'b0;
+     668        56389 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670    106615504 :            cam_in[i] = cam[i];
+     670    106047472 :            cam_in[i] = cam[i];
      671              : 
-     672     17892695 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
-     673      1418727 :            cam_in[i].wb = 1'b1;
+     672     17480826 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     673      1417050 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676     97053128 :          if (dec_tlu_force_halt)
+     676     96539460 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743          317 :    always_comb begin
      744          317 :       i0_itype = NULL_OP;
      745              : 
-     746      4523319 :       if (i0_legal_decode_d) begin
-     747      1942801 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748      2801549 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749      2380807 :          if (i0_dp.store)                i0_itype = STORE;
-     750      3778541 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751      8195979 :          if (i0_dp.zbb | i0_dp.zbs |
+     746      4496922 :       if (i0_legal_decode_d) begin
+     747      1946155 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748      2790451 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749      2390666 :          if (i0_dp.store)                i0_itype = STORE;
+     750      3777474 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751      8180253 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755        25713 :                                          i0_itype = BITMANIPU;
-     756      2039335 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757       328213 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758      6967003 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759      8035924 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760      4867703 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761      6734755 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762      7048285 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763      4850509 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764      1799266 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765       419543 :          if (i0_dp.jal)                  i0_itype = JAL;
+     756      2050039 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757       327975 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758      6934514 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759      8012049 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760      4878241 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761      6719029 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762      7032559 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763      4861053 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764      1802903 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765       419288 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859          317 :    always_comb  begin
      860          317 :       lsu_p = '0;
      861              : 
-     862     24263282 :       if (dec_extint_stall) begin
+     862     24134865 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868     24263282 :       else begin
-     869     24263282 :          lsu_p.valid = lsu_decode_d;
+     868     24134865 :       else begin
+     869     24134865 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871     24263282 :          lsu_p.load                         =  i0_dp.load ;
-     872     24263282 :          lsu_p.store                        =  i0_dp.store;
-     873     24263282 :          lsu_p.by                           =  i0_dp.by   ;
-     874     24263282 :          lsu_p.half                         =  i0_dp.half ;
-     875     24263282 :          lsu_p.word                         =  i0_dp.word ;
-     876     24263282 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871     24134865 :          lsu_p.load                         =  i0_dp.load ;
+     872     24134865 :          lsu_p.store                        =  i0_dp.store;
+     873     24134865 :          lsu_p.by                           =  i0_dp.by   ;
+     874     24134865 :          lsu_p.half                         =  i0_dp.half ;
+     875     24134865 :          lsu_p.word                         =  i0_dp.word ;
+     876     24134865 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878     24263282 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879     24263282 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880     24263282 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878     24134865 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879     24134865 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880     24134865 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882     24263282 :          lsu_p.unsign  =  i0_dp.unsign;
+     882     24134865 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1380,7 +1380,7 @@
     1276          317 :       r_t_in.i0trigger[3:0]              = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
     1277          317 :       r_t_in.pmu_lsu_misaligned          = lsu_pmu_misaligned_r;   // only valid if a load/store is valid in DC3 stage
     1278              : 
-    1279        29372 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
+    1279        29369 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
     1280              : 
     1281              :    end
     1282              : 
@@ -1614,11 +1614,11 @@
     1510              : module el2_dec_dec_ctl
     1511              :   import el2_pkg::*;
     1512              : (
-    1513       468420 :     input logic [31:0] inst,
+    1513       467652 :     input logic [31:0] inst,
     1514         7440 :     output el2_dec_pkt_t out
     1515              : );
     1516              : 
-    1517       468420 :   logic [31:0] i;
+    1517       467652 :   logic [31:0] i;
     1518              : 
     1519              :   assign i[31:0] = inst[31:0];
     1520              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_dec_gpr_ctl.sv.html
index 352da75193b..1bd867297b5 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -122,26 +122,26 @@
       18              : #(
       19              :    `include "el2_param.vh"
       20              :  )  (
-      21      2497511 :     input logic [4:0]  raddr0,       // logical read addresses
-      22      4174324 :     input logic [4:0]  raddr1,
+      21      2486977 :     input logic [4:0]  raddr0,       // logical read addresses
+      22      4163722 :     input logic [4:0]  raddr1,
       23              : 
-      24      5678794 :     input logic        wen0,         // write enable
-      25      2809689 :     input logic [4:0]  waddr0,       // write address
-      26       314049 :     input logic [31:0] wd0,          // write data
+      24      5660354 :     input logic        wen0,         // write enable
+      25      2798269 :     input logic [4:0]  waddr0,       // write address
+      26       314035 :     input logic [31:0] wd0,          // write data
       27              : 
-      28       920884 :     input logic        wen1,         // write enable
-      29       368914 :     input logic [4:0]  waddr1,       // write address
-      30        71560 :     input logic [31:0] wd1,          // write data
+      28       914806 :     input logic        wen1,         // write enable
+      29       368026 :     input logic [4:0]  waddr1,       // write address
+      30        71538 :     input logic [31:0] wd1,          // write data
       31              : 
-      32       156868 :     input logic        wen2,         // write enable
-      33        21351 :     input logic [4:0]  waddr2,       // write address
+      32       156836 :     input logic        wen2,         // write enable
+      33        21350 :     input logic [4:0]  waddr2,       // write address
       34        24784 :     input logic [31:0] wd2,          // write data
       35              : 
-      36     61843746 :     input logic        clk,
+      36     61251245 :     input logic        clk,
       37          316 :     input logic        rst_l,
       38              : 
-      39       407880 :     output logic [31:0] rd0,         // read data
-      40       598740 :     output logic [31:0] rd1,
+      39       407844 :     output logic [31:0] rd0,         // read data
+      40       598744 :     output logic [31:0] rd1,
       41              : 
       42            0 :     input  logic        scan_mode
       43              : );
@@ -149,7 +149,7 @@
       45              :    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
       46              :    logic [31:1] [31:0] gpr_in;
       47         1324 :    logic [31:1] w0v,w1v,w2v;
-      48        63550 :    logic [31:1] gpr_wr_en;
+      48        63462 :    logic [31:1] gpr_wr_en;
       49              : 
       50              :    // GPR Write Enables
       51              :    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_dec_ib_ctl.sv.html
index ef5e3505f69..65a1b899a3b 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,36 +129,36 @@
       25            0 :    input logic [1:0]           dbg_cmd_type,                       // dbg type
       26          349 :    input logic [31:0]          dbg_cmd_addr,                       // expand to 31:0
       27              : 
-      28       200759 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
-      29       651076 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30       631672 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      28       200545 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
+      29       650118 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
+      30       619214 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31        21217 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34      5735369 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
-      35      6006883 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
+      34      5716269 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      35      5971582 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36          196 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37          270 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
       38              : 
       39           86 :    input logic   ifu_i0_icaf_second,                               // i0 has access fault on second 2B of 4B inst
       40            2 :    input logic   ifu_i0_dbecc,                                     // i0 double-bit error
-      41       468882 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
+      41       468114 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
       42         1288 :    input logic [31:1]  ifu_i0_pc,                                  // i0 pc from the aligner
       43              : 
       44              : 
-      45      6006884 :    output logic dec_ib0_valid_d,                                   // ib0 valid
+      45      5971583 :    output logic dec_ib0_valid_d,                                   // ib0 valid
       46            1 :    output logic dec_debug_valid_d,                                 // Debug read or write at D-stage
       47              : 
       48              : 
-      49       468421 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
+      49       467653 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
       50              : 
       51         1288 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53      5735369 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53      5716269 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
-      55       200759 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
-      56       651076 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57       631672 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      55       200545 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
+      56       650118 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      57       619214 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58        21217 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
@@ -185,7 +185,7 @@
       81          374 :    logic         debug_read_csr;
       82          371 :    logic         debug_write_csr;
       83              : 
-      84       604160 :    logic [34:0]  ifu_i0_pcdata, pc0;
+      84       603277 :    logic [34:0]  ifu_i0_pcdata, pc0;
       85              : 
       86              :    assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
       87              :                                   ifu_i0_pc[31:1], ifu_i0_pc4 };
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_dec_pmp_ctl.sv.html
index 711c77f43a4..a988ff33db4 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,14 +133,14 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32     61843746 :    input logic clk,
-      33     61843746 :    input logic free_l2clk,
-      34     61843746 :    input logic csr_wr_clk,
+      32     61251245 :    input logic clk,
+      33     61251245 :    input logic free_l2clk,
+      34     61251245 :    input logic csr_wr_clk,
       35          316 :    input logic rst_l,
-      36        41826 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
-      37          406 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
+      36        41778 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+      37          412 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
       38         1640 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
-      39          906 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
+      39          910 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
       40              : 
       41          896 :    input logic csr_pmpcfg,
       42          802 :    input logic csr_pmpaddr0,
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_dec_tlu_ctl.sv.html
index 396249ac06a..03471949b0d 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,14 +133,14 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32     61843746 :    input logic clk,
-      33     61843746 :    input logic free_clk,
-      34     61843746 :    input logic free_l2clk,
+      32     61251245 :    input logic clk,
+      33     61251245 :    input logic free_clk,
+      34     61251245 :    input logic free_l2clk,
       35          316 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
       38            0 :    input logic [31:1] rst_vec, // reset vector, from core pins
-      39           17 :    input logic        nmi_int, // nmi pin
+      39           15 :    input logic        nmi_int, // nmi pin
       40            0 :    input logic [31:1] nmi_vec, // nmi vector
       41            0 :    input logic  i_cpu_halt_req,    // Asynchronous Halt request to CPU
       42            0 :    input logic  i_cpu_run_req,     // Asynchronous Restart request to CPU
@@ -149,29 +149,29 @@
       45              : 
       46              : 
       47              :    // perf counter inputs
-      48      6190087 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
-      49       614530 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
-      50      5893104 :    input logic       ifu_pmu_ic_miss, // icache miss
+      48      6153554 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
+      49       613228 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
+      50      5856146 :    input logic       ifu_pmu_ic_miss, // icache miss
       51       744124 :    input logic       ifu_pmu_ic_hit, // icache hit
       52            0 :    input logic       ifu_pmu_bus_error, // Instruction side bus error
       53      4463637 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
-      54     10356722 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
-      55      6190087 :    input logic       dec_pmu_instr_decoded, // decoded instructions
-      56       238142 :    input logic       dec_pmu_decode_stall, // decode stall
+      54     10319765 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
+      55      6153554 :    input logic       dec_pmu_instr_decoded, // decoded instructions
+      56       236732 :    input logic       dec_pmu_decode_stall, // decode stall
       57          264 :    input logic       dec_pmu_presync_stall, // decode stall due to presync'd inst
-      58        14500 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
-      59        59374 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
+      58        14454 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
+      59        59312 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
       60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61           26 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
-      62       409754 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63      2868109 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64      3459682 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
-      65      1667379 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
-      66        36420 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
+      62       408472 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
+      63      2862323 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64      3452000 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      65      1655267 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
+      66        36414 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
-      68        67818 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
-      69       891764 :    input logic       lsu_pmu_load_external_m, // D side bus load
-      70       806110 :    input logic       lsu_pmu_store_external_m, // D side bus store
+      68        67790 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
+      69       885840 :    input logic       lsu_pmu_load_external_m, // D side bus load
+      70       800418 :    input logic       lsu_pmu_store_external_m, // D side bus store
       71            0 :    input logic       dma_pmu_dccm_read,          // DMA DCCM read
       72            0 :    input logic       dma_pmu_dccm_write,         // DMA DCCM write
       73            0 :    input logic       dma_pmu_any_read,           // DMA read
@@ -188,43 +188,43 @@
       84            0 :    input logic dec_pause_state, // Pause counter not zero
       85            0 :    input logic         lsu_imprecise_error_store_any,      // store bus error
       86            0 :    input logic         lsu_imprecise_error_load_any,      // store bus error
-      87          401 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
+      87          400 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
       88              : 
-      89        41991 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
-      90        83863 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
-      91          906 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
+      89        41943 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
+      90        83633 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
+      91          910 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
       92              : 
-      93        41826 :    input logic        dec_csr_wen_r,      // csr write enable at wb
-      94      1559962 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
-      95          406 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+      93        41778 :    input logic        dec_csr_wen_r,      // csr write enable at wb
+      94      1551842 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
+      95          412 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
       96         1640 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       97              : 
-      98         1346 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
+      98         1330 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
       99              : 
-     100      6189442 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
+     100      6152908 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
      101              : 
      102          313 :    input logic [31:1] exu_npc_r, // for NPC tracking
      103              : 
      104          308 :    input logic [31:1] dec_tlu_i0_pc_r, // for PC/NPC tracking
      105              : 
-     106          264 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
+     106          258 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
      107              : 
      108           18 :    input logic [31:0] dec_illegal_inst, // For mtval
-     109      6190087 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
+     109      6153554 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112      2679213 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112      2673781 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113        26468 :    input logic        exu_i0_br_error_r, // error
      114         9608 :    input logic        exu_i0_br_start_error_r, // start error
-     115      2970681 :    input logic        exu_i0_br_valid_r, // valid
-     116       409754 :    input logic        exu_i0_br_mp_r, // mispredict
-     117      2381498 :    input logic        exu_i0_br_middle_r, // middle of bank
+     115      2962465 :    input logic        exu_i0_br_valid_r, // valid
+     116       408472 :    input logic        exu_i0_br_mp_r, // mispredict
+     117      2370984 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
      119              :    // branch info from pipe1 for errors or counter updates
      120              : 
-     121      2110900 :    input logic             exu_i0_br_way_r, // way hit or repl
+     121      2108159 :    input logic             exu_i0_br_way_r, // way hit or repl
      122              : 
-     123      2091300 :    output logic dec_tlu_core_empty,  // core is empty
+     123      2081032 :    output logic dec_tlu_core_empty,  // core is empty
      124              :    // Debug start
      125            0 :    output logic dec_dbg_cmd_done, // abstract command done
      126            0 :    output logic dec_dbg_cmd_fail, // abstract command failed
@@ -243,9 +243,9 @@
      139              : 
      140            0 :    input  logic dbg_halt_req, // DM requests a halt
      141            0 :    input  logic dbg_resume_req, // DM requests a resume
-     142      5892108 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
-     143      1346967 :    input  logic lsu_idle_any, // lsu is idle
-     144       159496 :    input  logic dec_div_active, // oop div is active
+     142      5855150 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
+     143      1337985 :    input  logic lsu_idle_any, // lsu is idle
+     144       159464 :    input  logic dec_div_active, // oop div is active
      145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
      146              : 
      147            0 :    input logic  ifu_ic_error_start,     // IC single bit error
@@ -262,8 +262,8 @@
      158            0 :    input logic       mhwakeup, // high priority external int, wakeup if halted
      159              : 
      160            0 :    input logic mexintpend, // external interrupt pending
-     161           18 :    input logic timer_int, // timer interrupt pending
-     162           17 :    input logic soft_int, // software interrupt pending
+     161           14 :    input logic timer_int, // timer interrupt pending
+     162           13 :    input logic soft_int, // software interrupt pending
      163              : 
      164            0 :    output logic o_cpu_halt_status, // PMU interface, halted
      165            0 :    output logic o_cpu_halt_ack, // halt req ack
@@ -284,24 +284,24 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183         6941 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184        83741 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183         8136 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184        83511 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
-     186       782203 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
+     186       779462 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
      188        29654 :    output logic dec_tlu_i0_kill_writeb_wb,    // I0 is flushed, don't writeback any results to arch state
-     189        58638 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
-     190      6162256 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
+     189        58568 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
+     190      6125722 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
      191              : 
      192        29654 :    output logic dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
-     193        58638 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
-     194        24686 :    output logic [31:1] dec_tlu_flush_path_r, // flush pc
+     193        58568 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
+     194        24680 :    output logic [31:1] dec_tlu_flush_path_r, // flush pc
      195        18866 :    output logic dec_tlu_fence_i_r,           // flush is a fence_i rfnpc, flush icache
      196            0 :    output logic dec_tlu_wr_pause_r,           // CSR write to pause reg is at R.
      197            0 :    output logic dec_tlu_flush_pause_r,        // Flush is due to pause
      198              : 
      199          510 :    output logic dec_tlu_presync_d,            // CSR read needs to be presync'd
-     200        20293 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
+     200        20137 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
      201              : 
      202              : 
      203            0 :    output logic [31:0] dec_tlu_mrac_ff,        // CSR for memory region control
@@ -313,11 +313,11 @@
      209       312914 :    output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc
      210        48468 :    output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
      211              : 
-     212         5118 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
-     213      6161964 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
-     214           28 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
+     212         5092 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
+     213      6125436 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
+     214           22 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
      215            0 :    output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
-     216           54 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
+     216           52 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
      217              : 
      218              :    // feature disable from mfdc
      219            0 :    output logic  dec_tlu_external_ldfwd_disable, // disable external load forwarding
@@ -344,9 +344,9 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243          866 :    output logic  priv_mode,
-     244          960 :    output logic  priv_mode_eff,
-     245          866 :    output logic  priv_mode_ns,
+     243          841 :    output logic  priv_mode,
+     244          931 :    output logic  priv_mode_eff,
+     245          841 :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
      248            2 :    output logic [2:0] mseccfg,
@@ -358,7 +358,7 @@
      254              :    output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES]
      255              :    );
      256              : 
-     257           12 :    logic         clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f,
+     257           10 :    logic         clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f,
      258            0 :                  nmi_lsu_store_type_f, allow_dbg_halt_csr_write, dbg_cmd_done_ns, i_cpu_run_req_d1_raw, debug_mode_status, lsu_single_ecc_error_r_d1,
      259            2 :                  sel_npc_r, sel_npc_resume, ce_int,
      260            0 :                  nmi_in_debug_mode, dpc_capture_npc, dpc_capture_pc, tdata_load, tdata_opcode, tdata_action, perfcnt_halted, tdata_chain,
@@ -379,7 +379,7 @@
      275           36 :    logic wr_mcounteren_r;
      276            6 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277           40 :    logic wr_mseccfg_r;
-     278         2789 :    logic [2:0] mseccfg_ns;
+     278         2781 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -389,22 +389,22 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286        29654 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288           55 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288           52 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290         3466 :    logic [1:0]  mstatus_ns, mstatus;
+     290         3467 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
      294            0 :    logic        force_halt;
      295            0 :    logic [5:0]  mfdht, mfdht_ns;
-     296          892 :    logic mstatus_mie_ns;
+     296          868 :    logic mstatus_mie_ns;
      297            0 :    logic [30:0] mtvec_ns, mtvec;
      298            0 :    logic [15:2] dcsr_ns, dcsr;
      299            2 :    logic [5:0] mip_ns, mip;
      300            0 :    logic [5:0] mie_ns, mie;
-     301        47082 :    logic [31:0] mcyclel_ns, mcyclel;
+     301        46815 :    logic [31:0] mcyclel_ns, mcyclel;
      302            0 :    logic [31:0] mcycleh_ns, mcycleh;
-     303        14380 :    logic [31:0] minstretl_ns, minstretl;
+     303        14337 :    logic [31:0] minstretl_ns, minstretl;
      304            0 :    logic [31:0] minstreth_ns, minstreth;
      305            0 :    logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;
      306            0 :    logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;
@@ -420,16 +420,16 @@
      316            0 :    logic [3:0] meipt_ns, meipt;
      317            0 :    logic [31:0] mdseac;
      318            0 :    logic mdseac_locked_ns, mdseac_locked_f, mdseac_en, nmi_lsu_detected;
-     319          156 :    logic [31:1] mepc_ns, mepc;
+     319          155 :    logic [31:1] mepc_ns, mepc;
      320            0 :    logic [31:1] dpc_ns, dpc;
      321            0 :    logic [31:0] mcause_ns, mcause;
      322            0 :    logic [3:0] mscause_ns, mscause, mscause_type;
-     323           54 :    logic [31:0] mtval_ns, mtval;
+     323           52 :    logic [31:0] mtval_ns, mtval;
      324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
-     325        58638 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
-     326          280 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
-     327      6161964 :    logic i0_valid_wb;
-     328      6162256 :    logic tlu_i0_commit_cmt;
+     325        58568 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
+     326          279 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
+     327      6125436 :    logic i0_valid_wb;
+     328      6125722 :    logic tlu_i0_commit_cmt;
      329            6 :    logic [31:1] vectored_path, interrupt_path;
      330            0 :    logic [16:0] dicawics_ns, dicawics;
      331            0 :    logic        wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
@@ -441,25 +441,25 @@
      337            0 :                 ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r;
      338            0 :    logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready,
      339            0 :          take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible;
-     340         5146 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
-     341        52860 :    logic synchronous_flush_r;
+     340         5114 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
+     341        52834 :    logic synchronous_flush_r;
      342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
-     343       188615 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
-     344        47083 :    logic [31:0] mcyclel_inc;
+     343       187547 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
+     344        46816 :    logic [31:0] mcyclel_inc;
      345            0 :    logic [31:0] mcycleh_inc;
      346              : 
-     347        57930 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
+     347        57758 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
      348              : 
-     349        14380 :    logic [31:0] minstretl_inc, minstretl_read;
+     349        14337 :    logic [31:0] minstretl_inc, minstretl_read;
      350            0 :    logic [31:0] minstreth_inc, minstreth_read;
      351          312 :    logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;
-     352        83743 :    logic valid_csr;
+     352        83513 :    logic valid_csr;
      353        28866 :    logic rfpc_i0_r;
      354            4 :    logic lsu_i0_rfnpc_r;
-     355      2377932 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355      2370402 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356           40 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
-     357        57666 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
-     358      6189442 :    logic i0_trigger_eval_r;
+     357        57596 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
+     358      6152908 :    logic i0_trigger_eval_r;
      359              : 
      360            0 :    logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
      361          632 :    logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
@@ -481,7 +481,7 @@
      377            0 :    logic i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, pmu_fw_halt_req_ns, pmu_fw_halt_req_f, int_timer_stalled,
      378            0 :          fw_halt_req, enter_pmu_fw_halt_req, pmu_fw_tlu_halted, pmu_fw_tlu_halted_f, internal_pmu_fw_halt_mode,
      379            0 :          internal_pmu_fw_halt_mode_f, int_timer0_int_hold, int_timer1_int_hold, int_timer0_int_hold_f, int_timer1_int_hold_f;
-     380           12 :    logic nmi_int_delayed, nmi_int_detected;
+     380           10 :    logic nmi_int_delayed, nmi_int_detected;
      381            0 :    logic [3:0] trigger_execute, trigger_data, trigger_store;
      382            0 :    logic dec_tlu_pmu_fw_halted;
      383              : 
@@ -506,19 +506,19 @@
      402         1738 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405     61843746 :    logic csr_wr_clk;
+     405     61251245 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
-     407       672506 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
+     407       666772 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
      409            4 :    logic lsu_single_ecc_error_r;
      410            2 :    logic [31:0] lsu_error_pkt_addr_r;
      411          317 :    logic mcyclel_cout_in;
-     412      6185912 :    logic i0_valid_no_ebreak_ecall_r;
-     413      6158676 :    logic minstret_enable_f;
-     414        58639 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
-     415      6189442 :    logic pc0_valid_r;
+     412      6149404 :    logic i0_valid_no_ebreak_ecall_r;
+     413      6122168 :    logic minstret_enable_f;
+     414        58569 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
+     415      6152908 :    logic pc0_valid_r;
      416         1991 :    logic [15:0] mfdc_int, mfdc_ns;
-     417          392 :    logic [31:0] mrac_in;
+     417          388 :    logic [31:0] mrac_in;
      418          752 :    logic [31:27] csr_sat;
      419            0 :    logic [8:6] dcsr_cause;
      420            0 :    logic enter_debug_halt_req_le, dcsr_cause_upgradeable;
@@ -535,22 +535,22 @@
      431       312914 :    logic            mhpmc5h_wr_en0, mhpmc5h_wr_en;
      432        48468 :    logic            mhpmc6h_wr_en0, mhpmc6h_wr_en;
      433           46 :    logic [63:0]     mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;
-     434        11315 :    logic perfcnt_halted_d1, zero_event_r;
+     434        11271 :    logic perfcnt_halted_d1, zero_event_r;
      435            0 :    logic [3:0] perfcnt_during_sleep;
      436           28 :    logic [9:0] event_r;
      437              : 
-     438      2151829 :    el2_inst_pkt_t pmu_i0_itype_qual;
+     438      2141441 :    el2_inst_pkt_t pmu_i0_itype_qual;
      439              : 
-     440        41826 :    logic dec_csr_wen_r_mod;
+     440        41778 :    logic dec_csr_wen_r_mod;
      441              : 
-     442          668 :    logic flush_clkvalid;
+     442          662 :    logic flush_clkvalid;
      443            0 :    logic sel_fir_addr;
      444          268 :    logic wr_mie_r;
-     445         3816 :    logic mtval_capture_pc_r;
+     445         3812 :    logic mtval_capture_pc_r;
      446            0 :    logic mtval_capture_pc_plus2_r;
-     447          262 :    logic mtval_capture_inst_r;
+     447          256 :    logic mtval_capture_inst_r;
      448           64 :    logic mtval_capture_lsu_r;
-     449         1004 :    logic mtval_clear_r;
+     449          982 :    logic mtval_clear_r;
      450            0 :    logic wr_mcgc_r;
      451           24 :    logic wr_mfdc_r;
      452            0 :    logic wr_mdeau_r;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483          612 :    logic  csr_acc_r;    // CSR access error
-     484        16682 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485      1131188 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484        16610 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485      1185055 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -2685,7 +2685,7 @@
     2581              :    // trace
     2582              :    //--------------------------------------------------------------------------------
     2583            0 :    logic [4:0] dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2;
-    2584           28 :    logic       dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2;
+    2584           22 :    logic       dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2;
     2585              : 
     2586              :    assign {dec_tlu_i0_valid_wb1,
     2587              :            dec_tlu_i0_exc_valid_wb1,
@@ -2828,12 +2828,12 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727     61843746 :    input logic clk,
-    2728     61843746 :    input logic free_l2clk,
-    2729     61843746 :    input logic csr_wr_clk,
+    2727     61251245 :    input logic clk,
+    2728     61251245 :    input logic free_l2clk,
+    2729     61251245 :    input logic csr_wr_clk,
     2730          316 :    input logic rst_l,
-    2731        41826 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
-    2732          406 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+    2731        41778 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
+    2732          412 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
     2733         1640 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
     2734              : 
     2735           12 :    input logic csr_mitctl0,
@@ -2859,12 +2859,12 @@
     2755              :    localparam MITCTL_ENABLE_HALTED      = 1;
     2756              :    localparam MITCTL_ENABLE_PAUSED      = 2;
     2757              : 
-    2758        47083 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
+    2758        46816 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
     2759            0 :    logic [2:0] mitctl0_ns, mitctl0;
     2760            0 :    logic [3:0] mitctl1_ns, mitctl1;
     2761            0 :    logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
     2762          317 :    logic mitcnt0_inc_ok, mitcnt1_inc_ok;
-    2763       188615 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
+    2763       187547 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
     2764            0 :  logic mit0_match_ns;
     2765            0 :  logic mit1_match_ns;
     2766            0 :  logic mitctl0_0_b_ns;
diff --git a/html/main/coverage_dashboard/all/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all/index_el2_dec_trigger.sv.html
index 89f1929edb8..c6b071279fd 100644
--- a/html/main/coverage_dashboard/all/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all/index_el2_dma_ctrl.sv.html
index 8a3e0fd634e..c520ca31c4a 100644
--- a/html/main/coverage_dashboard/all/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29     61888056 :    input logic         clk,
-      30     61888056 :    input logic         free_clk,
+      29     61295555 :    input logic         clk,
+      30     61295555 :    input logic         free_clk,
       31          340 :    input logic         rst_l,
       32          324 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -173,8 +173,8 @@
       69         2509 :    output logic        dma_active,         // DMA is busy
       70         1240 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
       71         1298 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
-      72      2226512 :    input logic         dccm_ready, // dccm ready to accept DMA request
-      73       638070 :    input logic         iccm_ready, // iccm ready to accept DMA request
+      72      2214970 :    input logic         dccm_ready, // dccm ready to accept DMA request
+      73       636519 :    input logic         iccm_ready, // iccm ready to accept DMA request
       74          321 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
       75              : 
       76              :    // PMU signals
@@ -286,8 +286,8 @@
      182              : 
      183         3065 :    logic                    dma_buffer_c1_clken;
      184         2873 :    logic                    dma_free_clken;
-     185     61856293 :    logic                    dma_buffer_c1_clk;
-     186     61875241 :    logic                    dma_free_clk;
+     185     61263792 :    logic                    dma_buffer_c1_clk;
+     186     61282740 :    logic                    dma_free_clk;
      187        44310 :    logic                    dma_bus_clk;
      188              : 
      189         1564 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all/index_el2_exu.sv.html b/html/main/coverage_dashboard/all/index_el2_exu.sv.html
index f9f4a8803eb..982a5969f09 100644
--- a/html/main/coverage_dashboard/all/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,139 +124,139 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23     61843746 :    input logic          clk,                                           // Top level clock
+      23     61251245 :    input logic          clk,                                           // Top level clock
       24          316 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
-      27      6189473 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
-      28      5991939 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
+      27      6152939 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
+      28      5955435 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
       29            0 :    input logic  [31:0]  dbg_cmd_wrdata,                                // Debug data   to primary I0 RS1
       30         1460 :    input el2_alu_pkt_t i0_ap,                                         // DEC alu {valid,predecodes}
       31              : 
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
-      34       506364 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35       631672 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
-      36       651076 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
+      34       504423 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
+      35       619214 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      36       650118 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37        21217 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
       39        38395 :    input logic  [31:0]  lsu_result_m,                                  // Load result M-stage
-      40        71560 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
-      41      5130925 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
-      42      3565563 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
-      43       407880 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
-      44       598740 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45      2134567 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
-      46       314049 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
-      47       123446 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
-      48      5393904 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49      3841554 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
-      50       554879 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
+      40        71538 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
+      41      5100391 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
+      42      3549089 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
+      43       407844 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
+      44       598744 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
+      45      2132673 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      46       314035 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
+      47       122230 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
+      48      5367615 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
+      49      3829589 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      50       553923 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51         1288 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
-      52        80872 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      53         8634 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      54        75092 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55         6941 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      52        79850 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      53         8622 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      54        74910 :    input logic          dec_csr_ren_d,                                 // CSR read select
+      55         8136 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57      5476447 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57      5449748 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
-      59        78138 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
+      59        78122 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60         2628 :    input logic          dec_div_cancel,                                // Cancel the divide operation
       61              : 
-      62       138654 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
+      62       137876 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
       63              : 
-      64        58638 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
-      65        24686 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
+      64        58568 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
+      65        24680 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
       66              : 
       67              : 
       68            0 :    input logic         dec_extint_stall,                               // External stall mux select
       69            0 :    input logic [31:2]  dec_tlu_meihap,                                 // External stall mux data
       70              : 
       71              : 
-      72       413833 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
-      73        81386 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
+      72       411891 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
+      73        81344 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
       74              : 
-      75       672565 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
-      76       226946 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
+      75       671016 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
+      76       226504 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
       77              : 
-      78       614701 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
+      78       613793 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
       79          308 :    output logic [31:1]  exu_i0_pc_x,                                   // Primary PC  result to DEC
       80         3978 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82          313 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83      2679213 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83      2673781 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84        26468 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85         9608 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
-      86       187548 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87      2970681 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
-      88       409754 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
-      89      2381498 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90       367119 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
-      91      2110900 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
+      86       187344 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
+      87      2962465 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      88       408472 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
+      89      2370984 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
+      90       364503 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      91      2108159 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
-      93        34458 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
-      94       299672 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95       378995 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      96       196032 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      93        34372 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
+      94       298770 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
+      95       376379 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      96       195586 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97       115620 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
-     100       409754 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101      2868109 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102      3459682 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     100       408472 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
+     101      2862323 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102      3452000 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105        24784 :    output logic [31:0]  exu_div_result,                                // Divide result
-     106       156868 :    output logic         exu_div_wren                                   // Divide write enable to GPR
+     106       156836 :    output logic         exu_div_wren                                   // Divide write enable to GPR
      107              :   );
      108              : 
      109              : 
      110              : 
      111              : 
-     112        62241 :    logic [31:0]                i0_rs1_bypass_data_d;
-     113        13122 :    logic [31:0]                i0_rs2_bypass_data_d;
-     114       909537 :    logic                       i0_rs1_bypass_en_d;
-     115       461832 :    logic                       i0_rs2_bypass_en_d;
-     116       381189 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
-     117       357805 :    logic [31:0]                muldiv_rs1_d;
-     118       138647 :    logic [31:1]                pred_correct_npc_r;
-     119      2921795 :    logic                       i0_pred_correct_upper_r;
+     112        62095 :    logic [31:0]                i0_rs1_bypass_data_d;
+     113        13118 :    logic [31:0]                i0_rs2_bypass_data_d;
+     114       905679 :    logic                       i0_rs1_bypass_en_d;
+     115       461658 :    logic                       i0_rs2_bypass_en_d;
+     116       381153 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
+     117       357769 :    logic [31:0]                muldiv_rs1_d;
+     118       137869 :    logic [31:1]                pred_correct_npc_r;
+     119      2913633 :    logic                       i0_pred_correct_upper_r;
      120          313 :    logic [31:1]                i0_flush_path_upper_r;
-     121       167933 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
-     122      5991939 :    logic                       x_ctl_en,  r_ctl_en;
+     121       167751 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
+     122      5955435 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124       382153 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125       382153 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126      3056934 :    logic                       i0_taken_d;
-     127      3056919 :    logic                       i0_taken_x;
-     128      3085033 :    logic                       i0_valid_d;
-     129      3085019 :    logic                       i0_valid_x;
-     130       378995 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124       379537 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125       379537 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126      3051127 :    logic                       i0_taken_d;
+     127      3051111 :    logic                       i0_taken_x;
+     128      3076817 :    logic                       i0_valid_d;
+     129      3076803 :    logic                       i0_valid_x;
+     130       376379 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
-     132        31484 :    el2_predict_pkt_t          final_predict_mp;
-     133       506364 :    el2_predict_pkt_t          i0_predict_newp_d;
+     132        31458 :    el2_predict_pkt_t          final_predict_mp;
+     133       504423 :    el2_predict_pkt_t          i0_predict_newp_d;
      134              : 
      135            0 :    logic                       flush_in_d;
-     136       568363 :    logic [31:0]                alu_result_x;
+     136       567455 :    logic [31:0]                alu_result_x;
      137              : 
      138       250948 :    logic                       mul_valid_x;
      139        17509 :    logic [31:0]                mul_result_x;
      140              : 
-     141       350197 :    el2_predict_pkt_t          i0_pp_r;
+     141       349079 :    el2_predict_pkt_t          i0_pp_r;
      142              : 
-     143       613955 :    logic                       i0_flush_upper_d;
-     144         2370 :    logic [31:1]                i0_flush_path_d;
-     145       506364 :    el2_predict_pkt_t          i0_predict_p_d;
-     146      2921809 :    logic                       i0_pred_correct_upper_d;
+     143       612476 :    logic                       i0_flush_upper_d;
+     144         2354 :    logic [31:1]                i0_flush_path_d;
+     145       504423 :    el2_predict_pkt_t          i0_predict_p_d;
+     146      2913647 :    logic                       i0_pred_correct_upper_d;
      147              : 
-     148       613954 :    logic                       i0_flush_upper_x;
+     148       612474 :    logic                       i0_flush_upper_x;
      149          313 :    logic [31:1]                i0_flush_path_x;
-     150       350197 :    el2_predict_pkt_t          i0_predict_p_x;
-     151      2921798 :    logic                       i0_pred_correct_upper_x;
-     152      3841539 :    logic                       i0_branch_x;
+     150       349079 :    el2_predict_pkt_t          i0_predict_p_x;
+     151      2913636 :    logic                       i0_pred_correct_upper_x;
+     152      3829573 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
-     155        55403 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
+     155        54839 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
      156              : 
      157              : 
      158              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_exu_alu_ctl.sv.html
index eb025753ebd..2e35582213b 100644
--- a/html/main/coverage_dashboard/all/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,52 +124,52 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23     61849896 :    input  logic                  clk,                // Top level clock
+      23     61257395 :    input  logic                  clk,                // Top level clock
       24          364 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
-      27       613954 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
-      28        58638 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
-      29      6190093 :    input  logic                  enable,             // Clock enable
-      30      5396604 :    input  logic                  valid_in,           // Valid
+      27       612474 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
+      28        58568 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
+      29      6153560 :    input  logic                  enable,             // Clock enable
+      30      5370315 :    input  logic                  valid_in,           // Valid
       31         1460 :    input  el2_alu_pkt_t         ap,                 // predecodes
-      32        75092 :    input  logic                  csr_ren_in,         // CSR select
-      33         6941 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34       359544 :    input  logic signed [31:0]    a_in,               // A operand
-      35      2494553 :    input  logic        [31:0]    b_in,               // B operand
+      32        74910 :    input  logic                  csr_ren_in,         // CSR select
+      33         8136 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34       359508 :    input  logic signed [31:0]    a_in,               // A operand
+      35      2492541 :    input  logic        [31:0]    b_in,               // B operand
       36         1288 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
-      37       506364 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
-      38       123446 :    input  logic        [12:1]    brimm_in,           // Branch offset
+      37       504423 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
+      38       122230 :    input  logic        [12:1]    brimm_in,           // Branch offset
       39              : 
       40              : 
-      41       568818 :    output logic        [31:0]    result_ff,          // final result
-      42       613955 :    output logic                  flush_upper_out,    // Branch flush
-      43       672565 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
-      44         2370 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
+      41       567910 :    output logic        [31:0]    result_ff,          // final result
+      42       612476 :    output logic                  flush_upper_out,    // Branch flush
+      43       671016 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
+      44         2354 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45          308 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46      2921809 :    output logic                  pred_correct_out,   // NPC control
-      47       506364 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
+      46      2913647 :    output logic                  pred_correct_out,   // NPC control
+      47       504423 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
       50              : 
-      51       359552 :    logic               [31:0]    zba_a_in;
-      52       878911 :    logic               [31:0]    aout;
-      53       277648 :    logic                         cout,ov,neg;
-      54       121745 :    logic               [31:0]    lout;
-      55       343325 :    logic               [31:0]    sout;
-      56       648649 :    logic                         sel_shift;
-      57      3894049 :    logic                         sel_adder;
-      58        59366 :    logic                         slt_one;
-      59      3083810 :    logic                         actual_taken;
+      51       359516 :    logic               [31:0]    zba_a_in;
+      52       877955 :    logic               [31:0]    aout;
+      53       277148 :    logic                         cout,ov,neg;
+      54       121733 :    logic               [31:0]    lout;
+      55       343289 :    logic               [31:0]    sout;
+      56       647575 :    logic                         sel_shift;
+      57      3870726 :    logic                         sel_adder;
+      58        59364 :    logic                         slt_one;
+      59      3077909 :    logic                         actual_taken;
       60         1288 :    logic               [31:1]    pcout;
-      61       391957 :    logic                         cond_mispredict;
-      62       148978 :    logic                         target_mispredict;
-      63      3858410 :    logic                         eq, ne, lt, ge;
-      64       707268 :    logic                         any_jal;
-      65      2893552 :    logic               [1:0]     newhist;
-      66       707268 :    logic                         sel_pc;
-      67       357190 :    logic               [31:0]    csr_write_data;
-      68       726161 :    logic               [31:0]    result;
+      61       389788 :    logic                         cond_mispredict;
+      62       148834 :    logic                         target_mispredict;
+      63      3836264 :    logic                         eq, ne, lt, ge;
+      64       706092 :    logic                         any_jal;
+      65      2883773 :    logic               [1:0]     newhist;
+      66       706092 :    logic                         sel_pc;
+      67       357154 :    logic               [31:0]    csr_write_data;
+      68       725211 :    logic               [31:0]    result;
       69              : 
       70              : 
       71              : 
@@ -348,7 +348,7 @@
      244              :                                 ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |
      245              :                                 ( {32{~ap_zba   }} &  a_in[31:0]       );
      246              : 
-     247      2574746 :    logic        [31:0]    bm;
+     247      2563745 :    logic        [31:0]    bm;
      248              : 
      249              :    assign bm[31:0]            = ( ap.sub )  ?  ~b_in[31:0]  :  b_in[31:0];
      250              : 
@@ -383,8 +383,8 @@
      279              : 
      280        11014 :    logic        [5:0]     shift_amount;
      281          323 :    logic        [31:0]    shift_mask;
-     282       155951 :    logic        [62:0]    shift_extend;
-     283      1097270 :    logic        [62:0]    shift_long;
+     282       151829 :    logic        [62:0]    shift_extend;
+     283      1093204 :    logic        [62:0]    shift_long;
      284              : 
      285              : 
      286              :    assign shift_amount[5:0]            = ( { 6{ap.sll}}   & (6'd32 - {1'b0,b_in[4:0]}) ) |   // [5] unused
@@ -416,7 +416,7 @@
      312              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CLZ,CTZ      * * * * * * * * * * * * * * * * * *
      313              : 
      314         1906 :    logic                  bitmanip_clz_ctz_sel;
-     315       360108 :    logic        [31:0]    bitmanip_a_reverse_ff;
+     315       360072 :    logic        [31:0]    bitmanip_a_reverse_ff;
      316          416 :    logic        [31:0]    bitmanip_lzd_in;
      317          425 :    logic        [5:0]     bitmanip_dw_lzd_enc;
      318           90 :    logic        [5:0]     bitmanip_clz_ctz_result;
@@ -443,8 +443,8 @@
      339              : 
      340          323 :         for (int i=0; i<32; i++) begin
      341        62496 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342    865145792 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343    865145792 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342    860587680 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343    860587680 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346        62496 :               found=1'b1;
@@ -460,7 +460,7 @@
      356              : 
      357              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CPOP         * * * * * * * * * * * * * * * * * *
      358              : 
-     359        46630 :    logic        [5:0]     bitmanip_cpop;
+     359        46636 :    logic        [5:0]     bitmanip_cpop;
      360          104 :    logic        [5:0]     bitmanip_cpop_result;
      361              : 
      362              : 
@@ -499,7 +499,7 @@
      395              : 
      396              :    assign bitmanip_minmax_sel          =  ap_min | ap_max;
      397              : 
-     398      4293403 :    logic                  bitmanip_minmax_sel_a;
+     398      4271257 :    logic                  bitmanip_minmax_sel_a;
      399              : 
      400              :    assign bitmanip_minmax_sel_a        =  ge  ^ ap_min;
      401              : 
@@ -557,7 +557,7 @@
      453              : 
      454              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  ZBSET, ZBCLR, ZBINV  * * * * * * * * * * * * * *
      455              : 
-     456        39756 :    logic        [31:0]    bitmanip_sb_1hot;
+     456        39686 :    logic        [31:0]    bitmanip_sb_1hot;
      457         1983 :    logic        [31:0]    bitmanip_sb_data;
      458              : 
      459              :    assign bitmanip_sb_1hot[31:0]       = ( 32'h00000001 << b_in[4:0] );
diff --git a/html/main/coverage_dashboard/all/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_exu_div_ctl.sv.html
index 72d63717c63..43f62d21359 100644
--- a/html/main/coverage_dashboard/all/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,18 +124,18 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23     61846819 :    input logic           clk,                       // Top level clock
+      23     61254318 :    input logic           clk,                       // Top level clock
       24          321 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
-      27        78139 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
-      28       357864 :    input logic  [31:0]   dividend,                  // Numerator
-      29      2494040 :    input logic  [31:0]   divisor,                   // Denominator
+      27        78123 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
+      28       357828 :    input logic  [31:0]   dividend,                  // Numerator
+      29      2492028 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31         2628 :    input logic           cancel,                    // Cancel divide
       32              : 
       33              : 
-      34       157168 :    output logic          finish_dly,                // Finish to match data
+      34       157136 :    output logic          finish_dly,                // Finish to match data
       35        24906 :    output logic [31:0]   out                        // Result
       36              :   );
       37              : 
@@ -1414,80 +1414,80 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313     61846819 :    input  logic            clk,                       // Top level clock
+    1313     61254318 :    input  logic            clk,                       // Top level clock
     1314          321 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
     1317         2628 :    input  logic            cancel,                    // Flush pipeline
-    1318       159796 :    input  logic            valid_in,
-    1319       889075 :    input  logic            signed_in,
-    1320        78159 :    input  logic            rem_in,
-    1321       357864 :    input  logic [31:0]     dividend_in,
-    1322      2494040 :    input  logic [31:0]     divisor_in,
+    1318       159764 :    input  logic            valid_in,
+    1319       884017 :    input  logic            signed_in,
+    1320        78143 :    input  logic            rem_in,
+    1321       357828 :    input  logic [31:0]     dividend_in,
+    1322      2492028 :    input  logic [31:0]     divisor_in,
     1323              : 
-    1324       157168 :    output logic            valid_out,
+    1324       157136 :    output logic            valid_out,
     1325        38062 :    output logic [31:0]     data_out
     1326              :   );
     1327              : 
     1328              : 
-    1329       159796 :    logic                   valid_ff_in, valid_ff;
-    1330       157168 :    logic                   finish_raw, finish, finish_ff;
-    1331       155404 :    logic                   running_state;
-    1332       157970 :    logic                   misc_enable;
+    1329       159764 :    logic                   valid_ff_in, valid_ff;
+    1330       157136 :    logic                   finish_raw, finish, finish_ff;
+    1331       155374 :    logic                   running_state;
+    1332       157938 :    logic                   misc_enable;
     1333        12298 :    logic         [2:0]     control_in, control_ff;
-    1334        32184 :    logic                   dividend_sign_ff, divisor_sign_ff, rem_ff;
-    1335       108204 :    logic                   count_enable;
+    1334        32168 :    logic                   dividend_sign_ff, divisor_sign_ff, rem_ff;
+    1335       108188 :    logic                   count_enable;
     1336            0 :    logic         [6:0]     count_in, count_ff;
     1337              : 
-    1338        22580 :    logic                   smallnum_case;
+    1338        22564 :    logic                   smallnum_case;
     1339        17338 :    logic         [3:0]     smallnum;
     1340              : 
-    1341       108204 :    logic                   a_enable, a_shift;
+    1341       108188 :    logic                   a_enable, a_shift;
     1342        23497 :    logic        [31:0]     a_in, a_ff;
     1343              : 
-    1344       138624 :    logic                   b_enable, b_twos_comp;
-    1345      2559883 :    logic        [32:0]     b_in;
-    1346        19375 :    logic        [37:0]     b_ff;
+    1344       138592 :    logic                   b_enable, b_twos_comp;
+    1345      2557839 :    logic        [32:0]     b_in;
+    1346        19374 :    logic        [37:0]     b_ff;
     1347              : 
     1348        24739 :    logic        [31:0]     q_in, q_ff;
     1349              : 
-    1350       159768 :    logic                   rq_enable;
+    1350       159736 :    logic                   rq_enable;
     1351        12210 :    logic                   r_sign_sel;
-    1352        87466 :    logic                   r_restore_sel;
+    1352        87450 :    logic                   r_restore_sel;
     1353         5576 :    logic                   r_adder01_sel, r_adder02_sel, r_adder03_sel;
     1354         4924 :    logic                   r_adder04_sel, r_adder05_sel, r_adder06_sel, r_adder07_sel;
     1355         2990 :    logic                   r_adder08_sel, r_adder09_sel, r_adder10_sel, r_adder11_sel;
-    1356         3208 :    logic                   r_adder12_sel, r_adder13_sel, r_adder14_sel, r_adder15_sel;
+    1356         3206 :    logic                   r_adder12_sel, r_adder13_sel, r_adder14_sel, r_adder15_sel;
     1357        22646 :    logic        [32:0]     r_in, r_ff;
     1358              : 
-    1359        67404 :    logic                   twos_comp_q_sel, twos_comp_b_sel;
-    1360        17431 :    logic        [31:0]     twos_comp_in, twos_comp_out;
+    1359        67372 :    logic                   twos_comp_q_sel, twos_comp_b_sel;
+    1360        17399 :    logic        [31:0]     twos_comp_in, twos_comp_out;
     1361              : 
-    1362       157251 :    logic        [15:1]     quotient_raw;
-    1363       185924 :    logic         [3:0]     quotient_new;
-    1364        69367 :    logic        [34:0]     adder01_out;
-    1365        55801 :    logic        [35:0]     adder02_out;
-    1366        69498 :    logic        [36:0]     adder03_out;
-    1367        52162 :    logic        [37:0]     adder04_out;
-    1368        69522 :    logic        [37:0]     adder05_out;
-    1369        55902 :    logic        [37:0]     adder06_out;
-    1370        69542 :    logic        [37:0]     adder07_out;
-    1371        49658 :    logic        [37:0]     adder08_out;
-    1372        69523 :    logic        [37:0]     adder09_out;
-    1373        55895 :    logic        [37:0]     adder10_out;
-    1374        69533 :    logic        [37:0]     adder11_out;
-    1375        52165 :    logic        [37:0]     adder12_out;
-    1376        69446 :    logic        [37:0]     adder13_out;
-    1377        55799 :    logic        [37:0]     adder14_out;
-    1378        69271 :    logic        [37:0]     adder15_out;
+    1362       157220 :    logic        [15:1]     quotient_raw;
+    1363       185887 :    logic         [3:0]     quotient_new;
+    1364        69353 :    logic        [34:0]     adder01_out;
+    1365        55787 :    logic        [35:0]     adder02_out;
+    1366        69484 :    logic        [36:0]     adder03_out;
+    1367        52161 :    logic        [37:0]     adder04_out;
+    1368        69508 :    logic        [37:0]     adder05_out;
+    1369        55888 :    logic        [37:0]     adder06_out;
+    1370        69528 :    logic        [37:0]     adder07_out;
+    1371        49649 :    logic        [37:0]     adder08_out;
+    1372        69509 :    logic        [37:0]     adder09_out;
+    1373        55881 :    logic        [37:0]     adder10_out;
+    1374        69519 :    logic        [37:0]     adder11_out;
+    1375        52164 :    logic        [37:0]     adder12_out;
+    1376        69432 :    logic        [37:0]     adder13_out;
+    1377        55785 :    logic        [37:0]     adder14_out;
+    1378        69257 :    logic        [37:0]     adder15_out;
     1379              : 
     1380        13679 :    logic        [64:0]     ar_shifted;
     1381         8550 :    logic         [5:0]     shortq;
-    1382       119888 :    logic         [4:0]     shortq_shift;
-    1383        43231 :    logic         [4:0]     shortq_decode;
-    1384       119888 :    logic         [4:0]     shortq_shift_ff;
-    1385       148820 :    logic                   shortq_enable;
-    1386       148820 :    logic                   shortq_enable_ff;
+    1382       119860 :    logic         [4:0]     shortq_shift;
+    1383        43215 :    logic         [4:0]     shortq_decode;
+    1384       119860 :    logic         [4:0]     shortq_shift_ff;
+    1385       148792 :    logic                   shortq_enable;
+    1386       148792 :    logic                   shortq_enable_ff;
     1387        13673 :    logic        [32:0]     shortq_dividend;
     1388              : 
     1389        27136 :    logic                   by_zero_case;
@@ -1746,7 +1746,7 @@
     1642              : 
     1643            0 :    logic [5:0]  dw_a_enc;
     1644            0 :    logic [5:0]  dw_b_enc;
-    1645        46100 :    logic [6:0]  dw_shortq_raw;
+    1645        46081 :    logic [6:0]  dw_shortq_raw;
     1646              : 
     1647              : 
     1648              : 
@@ -1821,14 +1821,14 @@
     1717              : 
     1718              : module el2_exu_div_cls
     1719              :   (
-    1720        54330 :    input  logic [32:0] operand,
+    1720        54317 :    input  logic [32:0] operand,
     1721              : 
-    1722        73255 :    output logic [4:0]  cls                  // Count leading sign bits - "n" format ignoring [32]
+    1722        73226 :    output logic [4:0]  cls                  // Count leading sign bits - "n" format ignoring [32]
     1723              :    );
     1724              : 
     1725              : 
-    1726        61282 :    logic [4:0]   cls_zeros;
-    1727        64590 :    logic [4:0]   cls_ones;
+    1726        61273 :    logic [4:0]   cls_zeros;
+    1727        64559 :    logic [4:0]   cls_ones;
     1728              : 
     1729              : 
     1730              : assign cls_zeros[4:0]             = ({5{operand[31]    ==  {           1'b1} }} & 5'd00) |
diff --git a/html/main/coverage_dashboard/all/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_exu_mul_ctl.sv.html
index f5a26683db0..c4c633fcbbb 100644
--- a/html/main/coverage_dashboard/all/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23     61843973 :    input logic          clk,              // Top level clock
+      23     61251472 :    input logic          clk,              // Top level clock
       24          317 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,10 +310,10 @@
      206          318 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207        10176 :          begin
      208        10176 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209    438942656 :              if (bcompress_test_bit_d)
-     210       715744 :                begin
-     211       715744 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
-     212       715744 :                   bcompress_j                  =  bcompress_j + 1;
+     209    437980832 :              if (bcompress_test_bit_d)
+     210       686272 :                begin
+     211       686272 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
+     212       686272 :                   bcompress_j                  =  bcompress_j + 1;
      213              :                end  // IF  bcompress_test_bit
      214              :          end        // FOR bcompress_i
      215              :      end            // ALWAYS_COMB
@@ -337,10 +337,10 @@
      233          318 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234        10176 :          begin
      235        10176 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236    438942656 :              if (bdecompress_test_bit_d)
-     237       715744 :                begin
-     238       715744 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
-     239       715744 :                   bdecompress_j                =  bdecompress_j + 1;
+     236    437980832 :              if (bdecompress_test_bit_d)
+     237       686272 :                begin
+     238       686272 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
+     239       686272 :                   bdecompress_j                =  bdecompress_j + 1;
      240              :                end  // IF  bdecompress_test_bit
      241              :          end        // FOR bdecompress_i
      242              :      end            // ALWAYS_COMB
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu.sv.html
index 9cac9fb56cc..5a4c93145fc 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,18 +129,18 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28     61843746 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29     61843746 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30     61843746 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28     61251245 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29     61251245 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30     61251245 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31          316 :    input logic rst_l,                        // reset, active low
       32              : 
-      33      6190087 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
+      33      6153554 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
       34              : 
-      35       672565 :    input logic exu_flush_final, // flush, includes upper and lower
-      36      6162256 :    input logic dec_tlu_i0_commit_cmt , // committed i0
+      35       671016 :    input logic exu_flush_final, // flush, includes upper and lower
+      36      6125722 :    input logic dec_tlu_i0_commit_cmt , // committed i0
       37            8 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
       38            0 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
-      39       226946 :    input logic [31:1] exu_flush_path_final, // flush fetch address
+      39       226504 :    input logic [31:1] exu_flush_path_final, // flush fetch address
       40              : 
       41            0 :    input logic [31:0]  dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
       42        18866 :    input logic         dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
@@ -172,10 +172,10 @@
       68            0 :    output logic                            ifu_axi_bready,
       69              : 
       70              :    // AXI Read Channels
-      71      5892901 :    output logic                            ifu_axi_arvalid,
-      72     10357032 :    input  logic                            ifu_axi_arready,
-      73      3589406 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      74      2454016 :    output logic [31:0]                     ifu_axi_araddr,
+      71      5855944 :    output logic                            ifu_axi_arvalid,
+      72     10320074 :    input  logic                            ifu_axi_arready,
+      73      3563620 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      74      2443704 :    output logic [31:0]                     ifu_axi_araddr,
       75          320 :    output logic [3:0]                      ifu_axi_arregion,
       76            0 :    output logic [7:0]                      ifu_axi_arlen,
       77            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -185,10 +185,10 @@
       81          317 :    output logic [2:0]                      ifu_axi_arprot,
       82            0 :    output logic [3:0]                      ifu_axi_arqos,
       83              : 
-      84     11804512 :    input  logic                            ifu_axi_rvalid,
+      84     11730597 :    input  logic                            ifu_axi_rvalid,
       85          317 :    output logic                            ifu_axi_rready,
-      86      1181687 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-      87       985574 :    input  logic [63:0]                     ifu_axi_rdata,
+      86      1173244 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+      87       981979 :    input  logic [63:0]                     ifu_axi_rdata,
       88            0 :    input  logic [1:0]                      ifu_axi_rresp,
       89              : 
       90          316 :    input  logic                      ifu_bus_clk_en,
@@ -206,10 +206,10 @@
      102            0 :    output logic                      iccm_dma_rvalid,
      103            0 :    output logic [63:0]               iccm_dma_rdata,
      104           12 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     105       636913 :    output logic                      iccm_ready,
+     105       635362 :    output logic                      iccm_ready,
      106              : 
-     107      6190087 :    output logic       ifu_pmu_instr_aligned,
-     108       614530 :    output logic       ifu_pmu_fetch_stall,
+     107      6153554 :    output logic       ifu_pmu_instr_aligned,
+     108       613228 :    output logic       ifu_pmu_fetch_stall,
      109            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
      110              : 
      111              : //   I$ & ITAG Ports
@@ -217,8 +217,8 @@
      113        10432 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      114       680092 :    output logic                      ic_rd_en,           // Icache read  enable.
      115              : 
-     116       560657 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     117      2137063 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     116       558675 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     117      2129109 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      118       231247 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      119            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
      120            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
@@ -227,8 +227,8 @@
      123              : 
      124            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
      125            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     126      1739005 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     127      5603285 :    output logic                      ic_sel_premux_data, // Select the premux data.
+     126      1731051 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     127      5573723 :    output logic                      ic_sel_premux_data, // Select the premux data.
      128              : 
      129            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      130            0 :    output logic                      ic_debug_rd_en,     // Icache debug rd
@@ -244,14 +244,14 @@
      140              : 
      141              : 
      142              :    // ICCM ports
-     143       160248 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
+     143       160008 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
      144           74 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
-     145       133458 :    output logic                      iccm_rden,          // ICCM read enable.
+     145       133416 :    output logic                      iccm_rden,          // ICCM read enable.
      146           14 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
      147            0 :    output logic [2:0]                iccm_wr_size,       // ICCM write location within DW.
      148              : 
-     149       136544 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
-     150       161276 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
+     149       136542 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
+     150       161274 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
      151              : 
      152              :    // ICCM ECC status
      153            0 :    output logic                      ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.
@@ -259,46 +259,46 @@
      155            4 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
      156              : 
      157              : // Perf counter sigs
-     158      5893104 :    output logic       ifu_pmu_ic_miss, // ic miss
+     158      5856146 :    output logic       ifu_pmu_ic_miss, // ic miss
      159       744124 :    output logic       ifu_pmu_ic_hit, // ic hit
      160            0 :    output logic       ifu_pmu_bus_error, // iside bus error
      161      4463637 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
-     162     10356722 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
+     162     10319765 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
      163              : 
      164              : 
      165          196 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
      166          270 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
      167              : 
-     168      6006883 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
+     168      5971582 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
      169           86 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
      170            2 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
-     172       468420 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
+     172       467652 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173         1288 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174      5735369 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174      5716269 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
-     176      5892108 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
+     176      5855150 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
-     178       200759 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
-     179       651076 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180       631672 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     178       200545 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
+     179       650118 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
+     180       619214 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181        21217 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
-     184        34458 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
-     185       299672 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186       378995 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-     187       196032 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+     184        34372 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+     185       298770 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
+     186       376379 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     187       195586 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188       115620 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
-     190       782203 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191       367119 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-     192       187548 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+     190       779462 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
+     191       364503 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     192       187344 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
-     195        58638 :    input dec_tlu_flush_lower_wb,
+     195        58568 :    input dec_tlu_flush_lower_wb,
      196              : 
-     197      1427542 :    output logic [15:0] ifu_i0_cinst,
+     197      1422550 :    output logic [15:0] ifu_i0_cinst,
      198              : 
      199          310 :     output logic [31:1] ifu_pmp_addr,
      200          110 :     input  logic        ifu_pmp_error,
@@ -315,12 +315,12 @@
      211              :    localparam TAGWIDTH = 2 ;
      212              :    localparam IDWIDTH  = 2 ;
      213              : 
-     214       249402 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
+     214       247400 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
      215          310 :    logic [31:1]            ifc_fetch_addr_f;
      216          310 :    logic [31:1]            ifc_fetch_addr_bf;
      217              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
      218              : 
-     219      6336890 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
+     219      6303330 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
      220          310 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
      221              : 
      222            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
@@ -329,33 +329,33 @@
      225              :    assign ifu_ic_error_start = ic_error_start;
      226              : 
      227              : 
-     228      2633488 :    logic        ic_write_stall;
+     228      2619202 :    logic        ic_write_stall;
      229           16 :    logic        ic_dma_active;
-     230       639182 :    logic        ifc_dma_access_ok;
+     230       637611 :    logic        ifc_dma_access_ok;
      231          170 :    logic [1:0]  ic_access_fault_f;
      232          170 :    logic [1:0]  ic_access_fault_type_f;
-     233      5913236 :    logic        ifu_ic_mb_empty;
+     233      5876254 :    logic        ifu_ic_mb_empty;
      234              : 
-     235      6786478 :    logic ic_hit_f;
+     235      6749550 :    logic ic_hit_f;
      236              : 
-     237      2367091 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238      3127797 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
-     239       518755 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240      2362013 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
-     241      2025664 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
-     242      1824438 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243      2135303 :    logic [11:0] ifu_bp_poffset_f; // predicted target
-     244        70444 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
-     245       408201 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
-     246       956691 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247       376810 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     237      2362503 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
+     238      3121591 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     239       517285 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
+     240      2359203 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     241      2019588 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
+     242      1818194 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
+     243      2132321 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     244        70318 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
+     245       405857 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
+     246       952355 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
+     247       374194 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
-     251      6336890 :    logic [1:0]   ic_fetch_val_f;
-     252      2167656 :    logic [31:0] ic_data_f;
-     253      2167656 :    logic [31:0] ifu_fetch_data_f;
-     254      3715756 :    logic ifc_fetch_req_f;
+     251      6303330 :    logic [1:0]   ic_fetch_val_f;
+     252      2159702 :    logic [31:0] ic_data_f;
+     253      2159702 :    logic [31:0] ifu_fetch_data_f;
+     254      3697544 :    logic ifc_fetch_req_f;
      255            0 :    logic ifc_fetch_req_f_raw;
      256            0 :    logic iccm_dma_rd_ecc_double_err;
      257            4 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
@@ -369,9 +369,9 @@
      265              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
      266              : 
      267          335 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
-     268      3715794 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
+     268      3697582 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
      269          316 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
-     270          106 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
+     270          102 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
      271            0 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
      272              : 
      273              :    // fetch control
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_aln_ctl.sv.html
index 0fc022e3e8c..d893f0b0557 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29          316 :    input logic                                    rst_l,                    // reset, active low
-      30     61843746 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31     61843746 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30     61251245 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31     61251245 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            8 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -141,118 +141,118 @@
       37          170 :    input logic [1:0]                              ic_access_fault_f,        // Instruction access fault for the current fetch.
       38          170 :    input logic [1:0]                              ic_access_fault_type_f,   // Instruction access fault types
       39              : 
-      40       672565 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
+      40       671016 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
       41              : 
-      42      6190087 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
+      42      6153554 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
       43              : 
-      44      2167656 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
+      44      2159702 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
       45              : 
-      46      6336890 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
+      46      6303330 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
       47          310 :    input logic [31:1]                             ifu_fetch_pc,             // starting pc of fetch
       48              : 
       49              : 
       50              : 
-      51      6006883 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
+      51      5971582 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
       52          196 :    output logic                                   ifu_i0_icaf,              // Instruction 0 has access fault
       53          270 :    output logic [1:0]                             ifu_i0_icaf_type,         // Instruction 0 access fault type
       54           86 :    output logic                                   ifu_i0_icaf_second,       // Instruction 0 has access fault on second 2B of 4B inst
       55              : 
       56            2 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
-      57       468420 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
+      57       467652 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58         1288 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59      5735369 :    output logic                                   ifu_i0_pc4,
+      59      5716269 :    output logic                                   ifu_i0_pc4,
       60              : 
-      61      5976194 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62      1719108 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      61      5947216 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
+      62      1717100 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65       376810 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
-      66       518755 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67      2135303 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      65       374194 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      66       517285 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
+      67      2132321 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
-      70      1824438 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
-      71      2025664 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
-      72       408201 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
-      73      2367091 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
-      74       956691 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
-      75        70444 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
+      70      1818194 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
+      71      2019588 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
+      72       405857 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
+      73      2362503 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
+      74       952355 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
+      75        70318 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
       76              : 
       77              : 
-      78       200759 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
-      79       651076 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80       631672 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      78       200545 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
+      79       650118 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
+      80       619214 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81        21217 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
       84              : 
-      85      6190087 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
+      85      6153554 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
       86              : 
-      87      1427542 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
+      87      1422550 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
       88              :    );
       89              : 
       90              : 
       91              : 
-      92      6786478 :    logic                                          ifvalid;
-      93        51602 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
-      94       270980 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
+      92      6749550 :    logic                                          ifvalid;
+      93        51564 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
+      94       270940 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
       95              : 
-      96       685700 :    logic [1:0]                                    f2val_in, f2val;
-      97      1516369 :    logic [1:0]                                    f1val_in, f1val;
-      98      4312982 :    logic [1:0]                                    f0val_in, f0val;
-      99        77629 :    logic [1:0]                                    sf1val, sf0val;
+      96       685660 :    logic [1:0]                                    f2val_in, f2val;
+      97      1505610 :    logic [1:0]                                    f1val_in, f1val;
+      98      4289276 :    logic [1:0]                                    f0val_in, f0val;
+      99        77441 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
-     101      1361273 :    logic [31:0]                                   aligndata;
-     102      5735370 :    logic                                          first4B, first2B;
+     101      1356256 :    logic [31:0]                                   aligndata;
+     102      5716270 :    logic                                          first4B, first2B;
      103              : 
-     104       241352 :    logic [31:0]                                   uncompress0;
-     105      6190087 :    logic                                          i0_shift;
-     106      4336836 :    logic                                          shift_2B, shift_4B;
-     107      3270013 :    logic                                          f1_shift_2B;
-     108       570413 :    logic                                          f2_valid, sf1_valid, sf0_valid;
+     104       240648 :    logic [31:0]                                   uncompress0;
+     105      6153554 :    logic                                          i0_shift;
+     106      4323796 :    logic                                          shift_2B, shift_4B;
+     107      3258200 :    logic                                          f1_shift_2B;
+     108       561430 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
-     110      1361273 :    logic [31:0]                                   ifirst;
-     111      4648847 :    logic [1:0]                                    alignval;
-     112      2125638 :    logic [31:1]                                   firstpc, secondpc;
+     110      1356256 :    logic [31:0]                                   ifirst;
+     111      4624861 :    logic [1:0]                                    alignval;
+     112      2121651 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114      2031241 :    logic [11:0]                                   f1poffset;
-     115       553276 :    logic [11:0]                                   f0poffset;
-     116       395754 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117       605991 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
-     118      1874371 :    logic [1:0]                                    f1hist1;
-     119      2526664 :    logic [1:0]                                    f0hist1;
-     120      1631147 :    logic [1:0]                                    f1hist0;
-     121      2345199 :    logic [1:0]                                    f0hist0;
+     114      2028193 :    logic [11:0]                                   f1poffset;
+     115       550811 :    logic [11:0]                                   f0poffset;
+     116       391724 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117       596123 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     118      1869197 :    logic [1:0]                                    f1hist1;
+     119      2521369 :    logic [1:0]                                    f0hist1;
+     120      1626145 :    logic [1:0]                                    f1hist0;
+     121      2338611 :    logic [1:0]                                    f0hist0;
      122              : 
      123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
      124              : 
      125          126 :    logic [1:0]                                    f1ictype;
      126          184 :    logic [1:0]                                    f0ictype;
      127              : 
-     128       310470 :    logic [1:0]                                    f1pc4;
-     129       477183 :    logic [1:0]                                    f0pc4;
+     128       308418 :    logic [1:0]                                    f1pc4;
+     129       472594 :    logic [1:0]                                    f0pc4;
      130              : 
      131        13698 :    logic [1:0]                                    f1ret;
-     132        79374 :    logic [1:0]                                    f0ret;
-     133      3365627 :    logic [1:0]                                    f1way;
-     134      3948316 :    logic [1:0]                                    f0way;
+     132        79298 :    logic [1:0]                                    f0ret;
+     133      3363459 :    logic [1:0]                                    f1way;
+     134      3946038 :    logic [1:0]                                    f0way;
      135              : 
-     136       513538 :    logic [1:0]                                    f1brend;
-     137       803346 :    logic [1:0]                                    f0brend;
+     136       510038 :    logic [1:0]                                    f1brend;
+     137       800328 :    logic [1:0]                                    f0brend;
      138              : 
-     139      2231832 :    logic [1:0]                                    alignbrend;
-     140      2083045 :    logic [1:0]                                    alignpc4;
+     139      2229316 :    logic [1:0]                                    alignbrend;
+     140      2077335 :    logic [1:0]                                    alignpc4;
      141              : 
-     142        81904 :    logic [1:0]                                    alignret;
-     143      4338791 :    logic [1:0]                                    alignway;
-     144      4609861 :    logic [1:0]                                    alignhist1;
-     145      4115473 :    logic [1:0]                                    alignhist0;
-     146      4070506 :    logic [1:1]                                    alignfromf1;
-     147      2322832 :    logic                                          i0_ends_f1;
+     142        81764 :    logic [1:0]                                    alignret;
+     143      4334429 :    logic [1:0]                                    alignway;
+     144      4602043 :    logic [1:0]                                    alignhist1;
+     145      4108949 :    logic [1:0]                                    alignhist0;
+     146      4059500 :    logic [1:1]                                    alignfromf1;
+     147      2317398 :    logic                                          i0_ends_f1;
      148         9628 :    logic                                          i0_br_start_error;
      149              : 
-     150       381760 :    logic [31:1]                                   f1prett;
-     151       439643 :    logic [31:1]                                   f0prett;
+     150       380306 :    logic [31:1]                                   f1prett;
+     151       438542 :    logic [31:1]                                   f0prett;
      152            2 :    logic [1:0]                                    f1dbecc;
      153            2 :    logic [1:0]                                    f0dbecc;
      154          126 :    logic [1:0]                                    f1icaf;
@@ -260,47 +260,47 @@
      156              : 
      157            2 :    logic [1:0]                                    aligndbecc;
      158          110 :    logic [1:0]                                    alignicaf;
-     159      2508127 :    logic                                          i0_brp_pc4;
+     159      2502417 :    logic                                          i0_brp_pc4;
      160              : 
-     161       611304 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
+     161       610418 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165      4395846 :    logic [1:0]                                    wrptr, wrptr_in;
-     166      3605586 :    logic [1:0]                                    rdptr, rdptr_in;
-     167      4240925 :    logic [2:0]                                    qwen;
-     168       321636 :    logic [31:0]                                   q2,q1,q0;
-     169      2717737 :    logic                                          q2off_in, q2off;
-     170      2710515 :    logic                                          q1off_in, q1off;
-     171      2742708 :    logic                                          q0off_in, q0off;
-     172      3731007 :    logic                                          f0_shift_2B;
+     165      4383493 :    logic [1:0]                                    wrptr, wrptr_in;
+     166      3594415 :    logic [1:0]                                    rdptr, rdptr_in;
+     167      4229122 :    logic [2:0]                                    qwen;
+     168       320566 :    logic [31:0]                                   q2,q1,q0;
+     169      2710162 :    logic                                          q2off_in, q2off;
+     170      2702913 :    logic                                          q1off_in, q1off;
+     171      2734744 :    logic                                          q0off_in, q0off;
+     172      3708138 :    logic                                          f0_shift_2B;
      173              : 
-     174      1290596 :    logic [31:0]                                   q0eff;
-     175       899593 :    logic [31:0]                                   q0final;
-     176      4864039 :    logic                                          q0ptr;
-     177      4864039 :    logic [1:0]                                    q0sel;
+     174      1285093 :    logic [31:0]                                   q0eff;
+     175       895524 :    logic [31:0]                                   q0final;
+     176      4845958 :    logic                                          q0ptr;
+     177      4845958 :    logic [1:0]                                    q0sel;
      178              : 
-     179      1134626 :    logic [31:0]                                   q1eff;
-     180      1321548 :    logic [15:0]                                   q1final;
-     181      3384249 :    logic                                          q1ptr;
-     182      3384249 :    logic [1:0]                                    q1sel;
+     179      1129460 :    logic [31:0]                                   q1eff;
+     180      1314833 :    logic [15:0]                                   q1final;
+     181      3371761 :    logic                                          q1ptr;
+     182      3371761 :    logic [1:0]                                    q1sel;
      183              : 
-     184      3605578 :    logic [2:0]                                    qren;
+     184      3594407 :    logic [2:0]                                    qren;
      185              : 
-     186      1844488 :    logic                                          consume_fb1, consume_fb0;
+     186      1843199 :    logic                                          consume_fb1, consume_fb0;
      187          112 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
      190              :    localparam                                     BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
-     191        60262 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
-     192       192799 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
-     193       178331 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
+     191        59899 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
+     192       192895 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
+     193       178255 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
      194              : 
      195              :    localparam                                     MHI   = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
-     198       142581 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199       513903 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     198       141581 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
+     199       507349 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201        16653 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_bp_ctl.sv.html
index 5033f0ee05e..259a0a0d86f 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,47 +135,47 @@
       31              :  )
       32              :   (
       33              : 
-      34     61843746 :    input logic clk,
+      34     61251245 :    input logic clk,
       35          316 :    input logic rst_l,
       36              : 
-      37      6786478 :    input logic ic_hit_f,      // Icache hit, enables F address capture
+      37      6749550 :    input logic ic_hit_f,      // Icache hit, enables F address capture
       38              : 
       39          310 :    input logic [31:1] ifc_fetch_addr_f, // look up btb address
-      40      3715756 :    input logic ifc_fetch_req_f,  // F1 valid
+      40      3697544 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
-      42       782203 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43       367119 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-      44       187548 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+      42       779462 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
+      43       364503 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      44       187344 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
       47              : 
-      48        58638 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
+      48        58568 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
       49            0 :    input logic dec_tlu_flush_leak_one_wb, // don't hit for leak one fetches
       50              : 
       51            0 :    input logic dec_tlu_bpred_disable, // disable all branch prediction
       52              : 
-      53        34458 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+      53        34372 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
-      55       299672 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56       378995 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      57       196032 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      55       298770 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
+      56       376379 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      57       195586 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58       115620 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
-      60       672565 :    input logic exu_flush_final, // all flushes
+      60       671016 :    input logic exu_flush_final, // all flushes
       61              : 
-      62      3127797 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
-      63       518755 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64      2362013 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      62      3121591 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      63       517285 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      64      2359203 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66       376810 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66       374194 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
-      68      2367091 :    output logic [1:0] ifu_bp_way_f, // way
-      69        70444 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
-      70      2025664 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
-      71      1824438 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
-      72       408201 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
-      73       956691 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74      2135303 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      68      2362503 :    output logic [1:0] ifu_bp_way_f, // way
+      69        70318 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
+      70      2019588 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
+      71      1818194 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
+      72       405857 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
+      73       952355 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
+      74      2132321 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -205,56 +205,56 @@
      101              :    localparam BHT_NO_ADDR_MATCH  = ( pt.BHT_ARRAY_DEPTH <= 16 );
      102              : 
      103              : 
-     104       200312 :    logic exu_mp_valid_write;
-     105       522818 :    logic exu_mp_ataken;
-     106       507918 :    logic exu_mp_valid; // conditional branch mispredict
-     107       229966 :    logic exu_mp_boffset; // branch offsett
-     108       272822 :    logic exu_mp_pc4; // branch is a 4B inst
-     109        47200 :    logic exu_mp_call; // branch is a call inst
-     110       148962 :    logic exu_mp_ret; // branch is a ret inst
-     111        80218 :    logic exu_mp_ja; // branch is a jump always
-     112       282730 :    logic [1:0] exu_mp_hist; // new history
-     113        89890 :    logic [11:0] exu_mp_tgt; // target offset
-     114       196032 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115      2871038 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116      2679213 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
-     117       187548 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
+     104       200024 :    logic exu_mp_valid_write;
+     105       521668 :    logic exu_mp_ataken;
+     106       506614 :    logic exu_mp_valid; // conditional branch mispredict
+     107       229164 :    logic exu_mp_boffset; // branch offsett
+     108       272130 :    logic exu_mp_pc4; // branch is a 4B inst
+     109        47088 :    logic exu_mp_call; // branch is a call inst
+     110       148818 :    logic exu_mp_ret; // branch is a ret inst
+     111        80166 :    logic exu_mp_ja; // branch is a jump always
+     112       282580 :    logic [1:0] exu_mp_hist; // new history
+     113        89338 :    logic [11:0] exu_mp_tgt; // target offset
+     114       195586 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
+     115      2863508 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116      2673781 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     117       187344 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118        28846 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119         9608 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120       367119 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120       364503 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122         4946 :    logic use_mp_way, use_mp_way_p1;
-     123          124 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
-     124       230670 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
+     123          105 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
+     124       230412 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127      2135303 :    logic [11:0]       btb_rd_tgt_f;
-     128       497844 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
-     129      1435715 :    logic [1:1]        bp_total_branch_offset_f;
+     127      2132321 :    logic [11:0]       btb_rd_tgt_f;
+     128       496910 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
+     129      1432135 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
      131          310 :    logic [31:1]       bp_btb_target_adder_f;
      132          310 :    logic [31:1]       bp_rs_call_target_f;
-     133       203004 :    logic              rs_push, rs_pop, rs_hold;
-     134       126300 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
+     133       202749 :    logic              rs_push, rs_pop, rs_hold;
+     134       126072 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
      135        12199 :    logic [pt.BTB_BTAG_SIZE-1:0] btb_wr_tag, fetch_rd_tag_f, fetch_rd_tag_p1_f;
-     136        55590 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
-     137       101152 :    logic               btb_wr_en_way0, btb_wr_en_way1;
+     136        55416 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
+     137       101126 :    logic               btb_wr_en_way0, btb_wr_en_way1;
      138              : 
      139              : 
-     140       260602 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
-     141       187548 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
+     140       259298 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
+     141       187344 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
      142         2406 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144         1040 :    logic  branch_error_bank_conflict_f;
-     145       372998 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145       370382 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146        74753 :    logic [1:0] num_valids;
      147          232 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
      148        14768 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
      149          366 :                         mp_wrindex_dec, mp_wrlru_b0;
-     150      1635105 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
-     151       539560 :    logic  tag_match_way0_f, tag_match_way1_f;
-     152       754438 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
-     153       361282 :    logic [1:0] bht_valid_f, bht_force_taken_f;
+     150      1628280 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
+     151       538896 :    logic  tag_match_way0_f, tag_match_way1_f;
+     152       751634 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
+     153       360932 :    logic [1:0] bht_valid_f, bht_force_taken_f;
      154              : 
      155            0 :    logic leak_one_f, leak_one_f_d1;
      156              : 
@@ -262,38 +262,38 @@
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161      2629034 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
-     162       461791 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
+     161      2627222 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     162       461657 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
-     164      1078106 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
-     165       459054 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
+     164      1076650 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
+     165       458936 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
      166              : 
-     167       277615 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
+     167       277103 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169      3127797 :    logic                                         final_h;
-     170       176376 :    logic                                         btb_fg_crossing_f;
-     171       284364 :    logic                                         middle_of_bank;
+     169      3121591 :    logic                                         final_h;
+     170       175514 :    logic                                         btb_fg_crossing_f;
+     171       283726 :    logic                                         middle_of_bank;
      172              : 
      173              : 
-     174      1782489 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
+     174      1776749 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
      175          982 :    logic                                         branch_error_bank_conflict_p1_f;
-     176       595724 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
+     176       595056 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
      177              : 
      178       162871 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
      179          310 :    logic [31:2] fetch_addr_p1_f;
      180              : 
      181              : 
-     182       202496 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
-     183       173604 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
+     182       202418 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
+     183       173728 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185      1772809 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185      1772003 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
-     187       196707 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
+     187       196077 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
-     190      1704053 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191      1957430 :     logic [1:0]                                  bht_bank1_rd_data_f;
-     192      1797591 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
+     190      1699025 :     logic [1:0]                                  bht_bank0_rd_data_f;
+     191      1951520 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     192      1792151 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
      195              :    assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict
@@ -348,7 +348,7 @@
      244              :    // set on leak one, hold until next flush without leak one
      245              :    assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
      246              : 
-     247       672564 : logic exu_flush_final_d1;
+     247       671014 : logic exu_flush_final_d1;
      248              : 
      249              :  if(!pt.BTB_FULLYA) begin : genblock1
      250              :    assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
@@ -461,8 +461,8 @@
      357              : 
      358              :  end // if (!pt.BTB_FULLYA)
      359              :    // Detect end of cache line and mask as needed
-     360       745777 :    logic eoc_near;
-     361       193490 :    logic eoc_mask;
+     360       743720 :    logic eoc_near;
+     361       192583 :    logic eoc_mask;
      362              :    assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];
      363              :    assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));
      364              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372      1950064 :    logic [16:1] btb_sel_data_f;
+     372      1949348 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -484,7 +484,7 @@
      380              :                                     ({16{btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]) );
      381              : 
      382              : 
-     383        70444 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
+     383        70318 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
      384              : 
      385              :    // a valid taken target needs to kill the next fetch as we compute the target address
      386              :    assign ifu_bp_hit_taken_f = |(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f & ~leak_one_f_d1 & ~dec_tlu_bpred_disable;
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460       378995 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460       376379 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500      2540236 : logic [1:0] bloc_f;
-     501      2316341 : logic use_fa_plus;
+     500      2536506 : logic [1:0] bloc_f;
+     501      2311399 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -719,8 +719,8 @@
      615              :                                                 exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
-     618       263348 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619      1615966 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     618       263198 :    logic [1:0] bht_wr_data0, bht_wr_data2;
+     619      1615528 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -732,9 +732,9 @@
      628              : 
      629              : 
      630              : 
-     631       151744 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
+     631       151046 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
      632              : 
-     633       151744 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
+     633       151046 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
      634              :    el2_btb_ghr_hash #(.pt(pt)) mpghrhs  (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      635              :    el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      636              :    el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
@@ -777,18 +777,18 @@
      673          317 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675          317 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676     24263282 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676     24134865 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678     24263282 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679     24263282 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678     24134865 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679     24134865 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683          317 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684     24263282 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684     24134865 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686     24263282 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687     24263282 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686     24134865 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687     24134865 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -933,7 +933,7 @@
      829              : 
      830              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0]      bht_bank_wr_data ;
      831              :    logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0]                bht_bank_rd_data_out ;
-     832        11506 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
+     832        11472 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
      833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
      834              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0]           bht_bank_sel   ;
      835              : 
@@ -978,12 +978,12 @@
      874          317 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875          317 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876          317 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877     24263282 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878     24263282 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879     24263282 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877     24134865 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878     24134865 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879     24134865 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881     24263282 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882     24263282 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881     24134865 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882     24134865 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_compress_ctl.sv.html
index 4ddc7eb8b8f..425ac578bcd 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,14 +127,14 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26       534926 :    input  logic [15:0] din,        // 16-bit   compressed instruction
-      27       241353 :    output logic [31:0] dout        // 32-bit uncompressed instruction
+      26       532030 :    input  logic [15:0] din,        // 16-bit   compressed instruction
+      27       240649 :    output logic [31:0] dout        // 32-bit uncompressed instruction
       28              :    );
       29              : 
       30              : 
-      31      4281649 :    logic               legal;
+      31      4268733 :    logic               legal;
       32              : 
-      33       534926 :    logic [15:0]  i;
+      33       532030 :    logic [15:0]  i;
       34              : 
       35          943 :    logic [31:0]  o,l1,l2,l3;
       36              : 
@@ -144,27 +144,27 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43      3376592 :    logic rdrd;
-      44      2773012 :    logic rdrs1;
-      45       840552 :    logic rs2rs2;
-      46       252083 :    logic rdprd;
-      47       790473 :    logic rdprs1;
-      48       238106 :    logic rs2prs2;
-      49      4256967 :    logic rs2prd;
-      50      4267309 :    logic uimm9_2;
-      51       169732 :    logic ulwimm6_2;
-      52       149272 :    logic ulwspimm7_2;
-      53        37052 :    logic rdeq2;
-      54       150142 :    logic rdeq1;
-      55      4112641 :    logic rs1eq2;
-      56       378274 :    logic sbroffset8_1;
-      57        37052 :    logic simm9_4;
-      58      2621149 :    logic simm5_0;
-      59       280884 :    logic sjaloffset11_1;
-      60        50540 :    logic sluimm17_12;
-      61       160810 :    logic uimm5_0;
-      62        86246 :    logic uswimm6_2;
-      63       148652 :    logic uswspimm7_2;
+      43      3366618 :    logic rdrd;
+      44      2766884 :    logic rdrs1;
+      45       833770 :    logic rs2rs2;
+      46       251375 :    logic rdprd;
+      47       787767 :    logic rdprs1;
+      48       237908 :    logic rs2prs2;
+      49      4244095 :    logic rs2prd;
+      50      4254393 :    logic uimm9_2;
+      51       169172 :    logic ulwimm6_2;
+      52       148798 :    logic ulwspimm7_2;
+      53        36812 :    logic rdeq2;
+      54       149962 :    logic rdeq1;
+      55      4100887 :    logic rs1eq2;
+      56       376244 :    logic sbroffset8_1;
+      57        36812 :    logic simm9_4;
+      58      2616021 :    logic simm5_0;
+      59       280190 :    logic sjaloffset11_1;
+      60        50508 :    logic sluimm17_12;
+      61       159914 :    logic uimm5_0;
+      62        86194 :    logic uswimm6_2;
+      63       147792 :    logic uswspimm7_2;
       64              : 
       65              : 
       66              : 
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115      2403412 :    logic [5:0] simm5d;
-     116       831174 :    logic [9:2] uimm9d;
+     115      2399210 :    logic [5:0] simm5d;
+     116       826978 :    logic [9:2] uimm9d;
      117              : 
-     118      2403412 :    logic [9:4] simm9d;
-     119      2358526 :    logic [6:2] ulwimm6d;
-     120      2403410 :    logic [7:2] ulwspimm7d;
-     121      2403412 :    logic [5:0] uimm5d;
-     122       831174 :    logic [20:1] sjald;
+     118      2399210 :    logic [9:4] simm9d;
+     119      2354324 :    logic [6:2] ulwimm6d;
+     120      2399208 :    logic [7:2] ulwspimm7d;
+     121      2399210 :    logic [5:0] uimm5d;
+     122       826978 :    logic [20:1] sjald;
      123              : 
-     124      2403412 :    logic [31:12] sluimmd;
+     124      2399210 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,9 +272,9 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171      2351294 :    logic [8:1]   sbr8d;
-     172      2358526 :    logic [6:2]   uswimm6d;
-     173       834816 :    logic [7:2]   uswspimm7d;
+     171      2347092 :    logic [8:1]   sbr8d;
+     172      2354324 :    logic [6:2]   uswimm6d;
+     173       829748 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
      176              :    assign sbr8d[8:1] =   { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_ic_mem.sv.html
index 5de136069b3..2802e85e0e2 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26     61843746 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27     61843746 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26     61251245 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27     61251245 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28          316 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            8 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -141,11 +141,11 @@
       37            0 :       input logic                                   ic_debug_wr_en,     // Icache debug wr
       38            0 :       input logic                                   ic_debug_tag_array, // Debug tag array
       39            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_debug_way,       // Debug way. Rd or Wr.
-      40      1739005 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-      41      5603285 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
+      40      1731051 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+      41      5573723 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
       42              : 
-      43       560657 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
-      44      2137063 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      43       558675 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
+      44      2129109 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       45       231247 :       output logic [70:0]                           ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       46            0 :       output logic [25:0]                           ictag_debug_rd_data,// Debug icache tag.
       47            0 :       input logic  [70:0]                           ic_debug_wr_data,   // Debug wr cache.
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91     61843746 :       input logic clk,
-      92     61843746 :       input logic active_clk,
+      91     61251245 :       input logic clk,
+      92     61251245 :       input logic active_clk,
       93          316 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -201,8 +201,8 @@
       97        10432 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en,
       98       680092 :       input logic                          ic_rd_en,           // Read enable
       99              : 
-     100       560657 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
-     101      2137063 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     100       558675 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
+     101      2129109 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      102            0 :       input  logic [70:0]                             ic_debug_wr_data,   // Debug wr cache.
      103       231247 :       output logic [70:0]                             ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      104            0 :       output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
@@ -212,8 +212,8 @@
      108            0 :       input logic                            ic_debug_wr_en,      // Icache debug wr
      109            0 :       input logic                            ic_debug_tag_array,  // Debug tag array
      110            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way,        // Debug way. Rd or Wr.
-     111      1739005 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-     112      5603285 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
+     111      1731051 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+     112      5573723 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
      113              : 
      114       109586 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
      115            0 :       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
@@ -221,7 +221,7 @@
      117              : 
      118              :       ) ;
      119              : 
-     120       459411 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
+     120       457969 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
      121        10432 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_wren;    //bank x ways
      122      1002822 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_rden;    //bank x ways
      123              : 
@@ -231,9 +231,9 @@
      127            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                ic_debug_sel_sb;
      128              : 
      129              :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0]                  wb_dout ;       //  ways x bank
-     130       560657 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
+     130       558675 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
      131              :    logic [pt.ICACHE_NUM_WAYS-1:0] [141:0]                                         wb_dout_way_pre;
-     132      1925349 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
+     132      1917395 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
      133       217563 :    logic [141:0]                                                                  wb_dout_ecc;
      134              : 
      135       462049 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                bank_check_en;
@@ -245,11 +245,11 @@
      141            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en;    // debug wr_way
      142            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en_ff; // debug wr_way
      143            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_wr_way_en;    // debug wr_way
-     144        84653 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
+     144        84413 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
      145              : 
-     146        85233 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
+     146        84993 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
      147              : 
-     148        85955 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
+     148        85725 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
      149       109586 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_rd_hit_q;
      150              : 
      151              : 
@@ -278,7 +278,7 @@
      174              : 
      175              : 
      176          326 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr;
-     177       242032 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
+     177       241792 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
      178              : 
      179            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_up;
      180            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only_up;
@@ -296,7 +296,7 @@
      192              :    assign  ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      193              :    assign  ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      194              : 
-     195       876954 :    logic end_of_cache_line;
+     195       873246 :    logic end_of_cache_line;
      196              :    assign end_of_cache_line = (pt.ICACHE_LN_SZ==7'h40) ? (&ic_rw_addr_q[5:4]) : ic_rw_addr_q[4];
      197          317 :    always_comb begin : clkens
      198          317 :       ic_bank_way_clken  = '0;
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803     61843746 :       input logic                                                   clk,
-     804     61843746 :       input logic                                                   active_clk,
+     803     61251245 :       input logic                                                   clk,
+     804     61251245 :       input logic                                                   active_clk,
      805          316 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            8 :       input logic                                                   dec_tlu_core_ecc_disable,
@@ -939,13 +939,13 @@
      835            0 :    logic [pt.ICACHE_NUM_WAYS-1:0] [06:0]                           ic_tag_corrected_ecc_unc;
      836            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_single_ecc_error;
      837            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_double_ecc_error;
-     838        17534 :    logic [6:0]                                                     ic_tag_ecc;
+     838        17530 :    logic [6:0]                                                     ic_tag_ecc;
      839              : 
      840            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_way_perr ;
      841            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en ;
      842            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en_ff ;
      843              : 
-     844        85233 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
+     844        84993 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
      845          336 :    logic [31:pt.ICACHE_TAG_LO]                                     ic_rw_addr_ff;
      846       680092 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_rden_q;          // way
      847         2608 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_wren;          // way
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_iccm_mem.sv.html
index c40cc9f6ea5..c709b4feb36 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,14 +129,14 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28     61847773 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29     61847773 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28     61255272 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29     61255272 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30          317 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
       33         1074 :    input logic                                        iccm_wren,                           // ICCM write enable
-      34       134458 :    input logic                                        iccm_rden,                           // ICCM read enable
-      35       160598 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
+      34       134416 :    input logic                                        iccm_rden,                           // ICCM read enable
+      35       160358 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
       36            8 :    input logic                                        iccm_buf_correct_ecc,                // ICCM is doing a single bit error correct cycle
       37            8 :    input logic                                        iccm_correction_state,               // ICCM under a correction - This is needed to guard replacements when hit
       38            1 :    input logic [2:0]                                  iccm_wr_size,                        // ICCM write size
@@ -144,25 +144,25 @@
       40              : 
       41              :    el2_mem_if.veer_iccm                               iccm_mem_export,                     // RAM repositioned in testbench and connected by this interface
       42              : 
-      43       136811 :    output logic [63:0]                                iccm_rd_data,                        // ICCM read data
-      44       161543 :    output logic [77:0]                                iccm_rd_data_ecc,                    // ICCM read ecc
+      43       136809 :    output logic [63:0]                                iccm_rd_data,                        // ICCM read data
+      44       161541 :    output logic [77:0]                                iccm_rd_data_ecc,                    // ICCM read ecc
       45            0 :    input  logic                                       scan_mode                            // Scan mode control
       46              : 
       47              : );
       48              : 
       49              : 
       50           16 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                wren_bank;
-      51       262168 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
-      52       262184 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
-      53       160070 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
+      51       262148 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
+      52       262164 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
+      53       159830 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
       54              : 
-      55        22063 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
+      55        22061 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56          248 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
-      57       159885 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58      4214855 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
-      59       467893 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
-      60       161543 :    logic             [63:0]              iccm_rd_data_pre;
-      61       136811 :    logic             [63:0]              iccm_data;
+      57       159657 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
+      58      4204766 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      59       466451 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
+      60       161541 :    logic             [63:0]              iccm_rd_data_pre;
+      61       136809 :    logic             [63:0]              iccm_data;
       62            1 :    logic [1:0]                           addr_incr;
       63          248 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data_vec;
       64              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_ifc_ctl.sv.html
index 2b75f96b0b4..2464c1c27da 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,27 +130,27 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29     61843746 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30     61843746 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29     61251245 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30     61251245 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32          316 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
       34              : 
-      35      6786478 :    input logic ic_hit_f,      // Icache hit
-      36      5913236 :    input logic ifu_ic_mb_empty, // Miss buffer empty
+      35      6749550 :    input logic ic_hit_f,      // Icache hit
+      36      5876254 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
-      38      5976194 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39      1719108 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      38      5947216 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
+      39      1717100 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
       41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
-      42       672565 :    input logic exu_flush_final, // FLush
-      43       226946 :    input logic [31:1] exu_flush_path_final, // Flush path
+      42       671016 :    input logic exu_flush_final, // FLush
+      43       226504 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45      3127797 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
-      46       518755 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      45      3121591 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      46       517285 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
       48           16 :    input logic ic_dma_active, // IC DMA active, stop fetching
-      49      2633488 :    input logic ic_write_stall, // IC is writing, stop fetching
+      49      2619202 :    input logic ic_write_stall, // IC is writing, stop fetching
       50           26 :    input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
       51              : 
       52            0 :    input logic [31:0]  dec_tlu_mrac_ff ,   // side_effect and cacheable for each region
@@ -158,34 +158,34 @@
       54          310 :    output logic [31:1] ifc_fetch_addr_f, // fetch addr F
       55          310 :    output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
       56              : 
-      57      3715756 :    output logic  ifc_fetch_req_f,  // fetch request valid F
+      57      3697544 :    output logic  ifc_fetch_req_f,  // fetch request valid F
       58              : 
-      59       614530 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
+      59       613228 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
       60              : 
       61          335 :    output logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. BF stage
-      62      3715794 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
+      62      3697582 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
       63          316 :    output logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. BF stage
-      64          106 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
+      64          102 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       65            0 :    output logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       66              : 
-      67       639182 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
+      67       637611 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
       68              : 
       69              : 
       70              :    );
       71              : 
       72          310 :    logic [31:1]  fetch_addr_bf;
       73          310 :    logic [31:1]  fetch_addr_next;
-      74       446302 :    logic [3:0]   fb_write_f, fb_write_ns;
+      74       442338 :    logic [3:0]   fb_write_f, fb_write_ns;
       75              : 
-      76      1084440 :    logic     fb_full_f_ns, fb_full_f;
+      76      1080476 :    logic     fb_full_f_ns, fb_full_f;
       77          345 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
-      78      5888633 :    logic     sel_last_addr_bf, sel_next_addr_bf;
-      79      8573536 :    logic     miss_f, miss_a;
+      78      5856823 :    logic     sel_last_addr_bf, sel_next_addr_bf;
+      79      8522141 :    logic     miss_f, miss_a;
       80           26 :    logic     flush_fb, dma_iccm_stall_any_f;
       81          632 :    logic     mb_empty_mod, goto_idle, leave_idle;
-      82      3662496 :    logic     fetch_bf_en;
-      83       619937 :    logic         line_wrap;
-      84       465236 :    logic         fetch_addr_next_1;
+      82      3644376 :    logic     fetch_bf_en;
+      83       618180 :    logic         line_wrap;
+      84       463881 :    logic         fetch_addr_next_1;
       85              : 
       86              :    // FSM assignment
       87              :     typedef enum logic [1:0] { IDLE  = 2'b00 ,
diff --git a/html/main/coverage_dashboard/all/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_ifu_mem_ctl.sv.html
index 834e933324f..125e51a1ea9 100644
--- a/html/main/coverage_dashboard/all/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,40 +131,40 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30     61843746 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31     61843746 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32     61843746 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30     61251245 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31     61251245 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32     61251245 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33          316 :    input logic rst_l,                                               // reset, active low
       34              : 
-      35       672565 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
-      36        58638 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
+      35       671016 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
+      36        58568 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
       37            8 :    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
-      38      6162256 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
+      38      6125722 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
       39            0 :    input logic                       dec_tlu_force_halt,            // force halt.
       40              : 
       41          310 :    input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
       42          335 :    input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
-      43      3715794 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
+      43      3697582 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
       44          316 :    input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
-      45          106 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
+      45          102 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
-      47       639182 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
+      47       637611 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48        18866 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49      3127797 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49      3121591 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51      2362013 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51      2359203 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
-      53      5892108 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
-      54      5913236 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
+      53      5855150 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
+      54      5876254 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
       55           16 :    output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
-      56      2633488 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
+      56      2619202 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
       57              : 
       58              : /// PMU signals
-      59      5893104 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
+      59      5856146 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
       60       744124 :    output logic                      ifu_pmu_ic_hit,                // IC hit event
       61            0 :    output logic                      ifu_pmu_bus_error,             // Bus error event
       62      4463637 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
-      63     10356722 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
+      63     10319765 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
       64              : 
       65              :   //-------------------------- IFU AXI signals--------------------------
       66              :    // AXI Write Channels
@@ -188,10 +188,10 @@
       84            0 :    output logic                            ifu_axi_bready,
       85              : 
       86              :    // AXI Read Channels
-      87      5892901 :    output logic                            ifu_axi_arvalid,
-      88     10357032 :    input  logic                            ifu_axi_arready,
-      89      3589406 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      90      2454016 :    output logic [31:0]                     ifu_axi_araddr,
+      87      5855944 :    output logic                            ifu_axi_arvalid,
+      88     10320074 :    input  logic                            ifu_axi_arready,
+      89      3563620 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      90      2443704 :    output logic [31:0]                     ifu_axi_araddr,
       91          320 :    output logic [3:0]                      ifu_axi_arregion,
       92            0 :    output logic [7:0]                      ifu_axi_arlen,
       93            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -201,10 +201,10 @@
       97          317 :    output logic [2:0]                      ifu_axi_arprot,
       98            0 :    output logic [3:0]                      ifu_axi_arqos,
       99              : 
-     100     11804512 :    input  logic                            ifu_axi_rvalid,
+     100     11730597 :    input  logic                            ifu_axi_rvalid,
      101          317 :    output logic                            ifu_axi_rready,
-     102      1181687 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     103       985574 :    input  logic [63:0]                     ifu_axi_rdata,
+     102      1173244 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     103       981979 :    input  logic [63:0]                     ifu_axi_rdata,
      104            0 :    input  logic [1:0]                      ifu_axi_rresp,
      105              : 
      106          316 :     input  logic                     ifu_bus_clk_en,
@@ -221,7 +221,7 @@
      117            0 :    output logic                      iccm_dma_rvalid,   //   Data read from iccm is valid
      118            0 :    output logic [63:0]               iccm_dma_rdata,    //   dma data read from iccm
      119           12 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     120       636913 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
+     120       635362 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
      121              : 
      122              : 
      123              : //   I$ & ITAG Ports
@@ -229,8 +229,8 @@
      125        10432 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      126       680092 :    output logic                      ic_rd_en,           // Icache read  enable.
      127              : 
-     128       560657 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
-     129      2137063 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     128       558675 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
+     129      2129109 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      130       231247 :    input  logic [70:0]               ic_debug_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      131            0 :    input  logic [25:0]               ictag_debug_rd_data,  // Debug icache tag.
      132            0 :    output logic [70:0]               ic_debug_wr_data,     // Debug wr cache.
@@ -253,17 +253,17 @@
      149            0 :    input  logic                      ic_tag_perr,        // Icache Tag parity error
      150              : 
      151              :    // ICCM ports
-     152       160248 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
+     152       160008 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
      153           74 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
-     154       133458 :    output logic                      iccm_rden,          // ICCM read enable.
+     154       133416 :    output logic                      iccm_rden,          // ICCM read enable.
      155           14 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
      156            0 :    output logic [2:0]                iccm_wr_size,       // ICCM write location within DW.
      157              : 
-     158       136544 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
-     159       161276 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
-     160      6336890 :    input  logic [1:0]                ifu_fetch_val,
+     158       136542 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
+     159       161274 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
+     160      6303330 :    input  logic [1:0]                ifu_fetch_val,
      161              :    // IFU control signals
-     162      6786478 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
+     162      6749550 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
      163          170 :    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
      164          170 :    output logic [1:0]                ic_access_fault_type_f, // Access fault types
      165            8 :    output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
@@ -274,10 +274,10 @@
      170              : 
      171            8 :    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
      172            0 :    output logic                      iccm_dma_sb_error,      // Single Bit ECC error from a DMA access
-     173      6336890 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
-     174      2167656 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
-     175      1739005 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
-     176      5603285 :    output logic                      ic_sel_premux_data,     // Select premux data.
+     173      6303330 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
+     174      2159702 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
+     175      1731051 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
+     176      5573723 :    output logic                      ic_sel_premux_data,     // Select premux data.
      177              : 
      178              : /////  Debug
      179            0 :    input  el2_cache_debug_pkt_t     dec_tlu_ic_diag_pkt ,       // Icache/tag debug read/write packet
@@ -304,8 +304,8 @@
      200              : 
      201              : 
      202              : 
-     203     11804512 :    logic           bus_ifu_wr_en     ;
-     204     11804245 :    logic           bus_ifu_wr_en_ff  ;
+     203     11730597 :    logic           bus_ifu_wr_en     ;
+     204     11730329 :    logic           bus_ifu_wr_en_ff  ;
      205        25080 :    logic           bus_ifu_wr_en_ff_q  ;
      206        31320 :    logic           bus_ifu_wr_en_ff_wo_err  ;
      207        10432 :    logic [pt.ICACHE_NUM_WAYS-1:0]     bus_ic_wr_en ;
@@ -333,36 +333,36 @@
      229            0 :    logic           scnd_miss_index_match ;
      230              : 
      231              : 
-     232       636913 :    logic           ifc_dma_access_q_ok;
-     233          106 :    logic           ifc_iccm_access_f ;
+     232       635362 :    logic           ifc_dma_access_q_ok;
+     233          102 :    logic           ifc_iccm_access_f ;
      234            0 :    logic           ifc_region_acc_fault_f;
      235          170 :    logic           ifc_region_acc_fault_final_f;
      236            0 :    logic  [1:0]    ifc_bus_acc_fault_f;
-     237      5893133 :    logic           ic_act_miss_f;
+     237      5856175 :    logic           ic_act_miss_f;
      238         1226 :    logic           ic_miss_under_miss_f;
-     239       352738 :    logic           ic_ignore_2nd_miss_f;
+     239       351764 :    logic           ic_ignore_2nd_miss_f;
      240       744124 :    logic           ic_act_hit_f;
-     241      5891791 :    logic           miss_pending;
+     241      5854833 :    logic           miss_pending;
      242          310 :    logic [31:1]    imb_in , imb_ff  ;
      243          310 :    logic [31:pt.ICACHE_BEAT_ADDR_HI+1]    miss_addr_in , miss_addr  ;
-     244       575664 :    logic           miss_wrap_f ;
-     245       672564 :    logic           flush_final_f;
-     246      4265983 :    logic           ifc_fetch_req_f;
-     247      3717086 :    logic           ifc_fetch_req_f_raw;
-     248      6786478 :    logic           fetch_req_f_qual   ;
-     249      3717124 :    logic           ifc_fetch_req_qual_bf ;
+     244       572663 :    logic           miss_wrap_f ;
+     245       671014 :    logic           flush_final_f;
+     246      4246554 :    logic           ifc_fetch_req_f;
+     247      3698874 :    logic           ifc_fetch_req_f_raw;
+     248      6749550 :    logic           fetch_req_f_qual   ;
+     249      3698912 :    logic           ifc_fetch_req_qual_bf ;
      250       657304 :    logic [pt.ICACHE_NUM_WAYS-1:0]     replace_way_mb_any;
-     251      5892583 :    logic           last_beat;
-     252      8616294 :    logic           reset_beat_cnt  ;
-     253      2930753 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
-     254      5578509 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
+     251      5855624 :    logic           last_beat;
+     252      8564899 :    logic           reset_beat_cnt  ;
+     253      2916041 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
+     254      5541444 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
      255          310 :    logic [31:1]    ifu_fetch_addr_int_f ;
      256          326 :    logic [31:1]    ifu_ic_rw_int_addr ;
-     257      5892881 :    logic           crit_wd_byp_ok_ff ;
-     258      5878664 :    logic           ic_crit_wd_rdy_new_ff;
-     259      1200642 :    logic   [79:0]  ic_byp_data_only_pre_new;
-     260       961570 :    logic   [79:0]  ic_byp_data_only_new;
-     261      5880224 :    logic           ic_byp_hit_f ;
+     257      5855924 :    logic           crit_wd_byp_ok_ff ;
+     258      5841775 :    logic           ic_crit_wd_rdy_new_ff;
+     259      1196832 :    logic   [79:0]  ic_byp_data_only_pre_new;
+     260       958192 :    logic   [79:0]  ic_byp_data_only_new;
+     261      5843338 :    logic           ic_byp_hit_f ;
      262        10325 :    logic           ic_valid ;
      263        10324 :    logic           ic_valid_ff;
      264        18866 :    logic           reset_all_tags;
@@ -380,94 +380,94 @@
      276              : 
      277         3738 :    logic           reset_ic_in ;
      278         3738 :    logic           reset_ic_ff ;
-     279       455163 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
+     279       453721 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
      280          314 :    logic [31:1]    ifu_status_wr_addr;
      281        30306 :    logic           sel_mb_addr ;
      282        30306 :    logic           sel_mb_addr_ff ;
      283        11496 :    logic           sel_mb_status_addr ;
-     284      2137063 :    logic [63:0]    ic_final_data;
+     284      2129109 :    logic [63:0]    ic_final_data;
      285              : 
      286       615724 :    logic [pt.ICACHE_STATUS_BITS-1:0]                              way_status_new_ff ;
      287       749542 :    logic                                    way_status_wr_en_ff ;
      288           14 :    logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0]        way_status_out ;
      289            0 :    logic [1:0]                              ic_debug_way_enc;
      290              : 
-     291      1181670 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
+     291      1173226 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
      292              : 
-     293      4103781 :    logic         fetch_req_icache_f;
-     294       162038 :    logic         fetch_req_iccm_f;
-     295       162038 :    logic         ic_iccm_hit_f;
+     293      4084394 :    logic         fetch_req_icache_f;
+     294       161996 :    logic         fetch_req_iccm_f;
+     295       161996 :    logic         ic_iccm_hit_f;
      296          334 :    logic         fetch_uncacheable_ff;
      297       749542 :    logic         way_status_wr_en;
-     298      5441261 :    logic         sel_byp_data;
-     299      5603670 :    logic         sel_ic_data;
-     300       162038 :    logic         sel_iccm_data;
+     298      5411741 :    logic         sel_byp_data;
+     299      5574110 :    logic         sel_ic_data;
+     300       161996 :    logic         sel_iccm_data;
      301            0 :    logic         ic_rd_parity_final_err;
-     302      5893104 :    logic         ic_act_miss_f_delayed;
+     302      5856146 :    logic         ic_act_miss_f_delayed;
      303            0 :    logic         bus_ifu_wr_data_error;
      304            0 :    logic         bus_ifu_wr_data_error_ff;
      305       749542 :    logic         way_status_wr_en_w_debug;
      306            0 :    logic         ic_debug_tag_val_rd_out;
-     307      5893133 :    logic         ifu_pmu_ic_miss_in;
+     307      5856175 :    logic         ifu_pmu_ic_miss_in;
      308       744124 :    logic         ifu_pmu_ic_hit_in;
      309            0 :    logic         ifu_pmu_bus_error_in;
-     310     10356968 :    logic         ifu_pmu_bus_trxn_in;
+     310     10320011 :    logic         ifu_pmu_bus_trxn_in;
      311      4463866 :    logic         ifu_pmu_bus_busy_in;
      312            0 :    logic         ic_debug_ict_array_sel_in;
      313            0 :    logic         ic_debug_ict_array_sel_ff;
      314            0 :    logic         debug_data_clken;
-     315      5891521 :    logic         last_data_recieved_in ;
-     316      5891475 :    logic         last_data_recieved_ff ;
+     315      5854562 :    logic         last_data_recieved_in ;
+     316      5854517 :    logic         last_data_recieved_ff ;
      317              : 
-     318     11804512 :    logic                          ifu_bus_rvalid           ;
-     319     11804245 :    logic                          ifu_bus_rvalid_ff        ;
-     320     11804245 :    logic                          ifu_bus_rvalid_unq_ff    ;
-     321     10357032 :    logic                          ifu_bus_arready_unq       ;
-     322     10356769 :    logic                          ifu_bus_arready_unq_ff    ;
-     323      5892901 :    logic                          ifu_bus_arvalid           ;
-     324      5892856 :    logic                          ifu_bus_arvalid_ff        ;
-     325     10357032 :    logic                          ifu_bus_arready           ;
-     326     10356769 :    logic                          ifu_bus_arready_ff        ;
-     327       985553 :    logic [63:0]                   ifu_bus_rdata_ff        ;
+     318     11730597 :    logic                          ifu_bus_rvalid           ;
+     319     11730329 :    logic                          ifu_bus_rvalid_ff        ;
+     320     11730329 :    logic                          ifu_bus_rvalid_unq_ff    ;
+     321     10320074 :    logic                          ifu_bus_arready_unq       ;
+     322     10319811 :    logic                          ifu_bus_arready_unq_ff    ;
+     323      5855944 :    logic                          ifu_bus_arvalid           ;
+     324      5855899 :    logic                          ifu_bus_arvalid_ff        ;
+     325     10320074 :    logic                          ifu_bus_arready           ;
+     326     10319811 :    logic                          ifu_bus_arready_ff        ;
+     327       981958 :    logic [63:0]                   ifu_bus_rdata_ff        ;
      328            0 :    logic [1:0]                    ifu_bus_rresp_ff          ;
-     329     11804512 :    logic                          ifu_bus_rsp_valid ;
+     329     11730597 :    logic                          ifu_bus_rsp_valid ;
      330          317 :    logic                          ifu_bus_rsp_ready ;
-     331      1181687 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
-     332       985574 :    logic [63:0]                   ifu_bus_rsp_rdata;
+     331      1173244 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
+     332       981979 :    logic [63:0]                   ifu_bus_rsp_rdata;
      333            0 :    logic [1:0]                    ifu_bus_rsp_opc;
      334              : 
-     335      1229124 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
+     335      1223582 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
      336            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    wr_data_c1_clk;
-     337      1229076 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
-     338      1229066 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
+     337      1223534 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
+     338      1223524 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
      339            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error_in;
      340            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error;
-     341       455163 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
-     342       998318 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
+     341       453721 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
+     342       994248 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
      343          316 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_1;
-     344      1039773 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
-     345      1039773 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
+     344      1037330 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
+     345      1037330 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
      346          316 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_1;
-     347      8434985 :    logic          miss_buff_hit_unq_f ;
+     347      8382477 :    logic          miss_buff_hit_unq_f ;
      348         5898 :    logic          stream_hit_f ;
      349         1450 :    logic          stream_miss_f ;
      350          574 :    logic          stream_eol_f ;
-     351      5878246 :    logic          crit_byp_hit_f ;
-     352      1181670 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
+     351      5841358 :    logic          crit_byp_hit_f ;
+     352      1173226 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
      353              :    logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;
-     354      1012845 :    logic [63:0] ic_miss_buff_half;
+     354      1009209 :    logic [63:0] ic_miss_buff_half;
      355         1044 :    logic        scnd_miss_req, scnd_miss_req_q;
      356         1360 :    logic        scnd_miss_req_in;
      357              : 
      358              : 
      359            0 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_ff;
-     360       158146 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
+     360       157916 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
      361            2 :    logic [38:0]                         iccm_ecc_corr_data_ff;
      362            8 :    logic                                iccm_ecc_write_status     ;
      363            8 :    logic                                iccm_rd_ecc_single_err_ff   ;
      364            8 :    logic                                iccm_error_start;     // start the error fsm
      365            8 :    logic                                perr_state_en;
-     366     13540149 :    logic                                miss_state_en;
+     366     13460338 :    logic                                miss_state_en;
      367              : 
      368            0 :    logic        busclk;
      369            0 :    logic        busclk_force;
@@ -475,46 +475,46 @@
      371          316 :    logic        bus_ifu_bus_clk_en_ff;
      372          316 :    logic        bus_ifu_bus_clk_en ;
      373              : 
-     374      5893116 :    logic        ifc_bus_ic_req_ff_in;
-     375      5892901 :    logic        ifu_bus_cmd_valid ;
-     376     10357032 :    logic        ifu_bus_cmd_ready ;
+     374      5856158 :    logic        ifc_bus_ic_req_ff_in;
+     375      5855944 :    logic        ifu_bus_cmd_valid ;
+     376     10320074 :    logic        ifu_bus_cmd_ready ;
      377              : 
-     378      5911662 :    logic        bus_inc_data_beat_cnt     ;
-     379      8616294 :    logic        bus_reset_data_beat_cnt   ;
-     380     14528273 :    logic        bus_hold_data_beat_cnt    ;
+     378      5874705 :    logic        bus_inc_data_beat_cnt     ;
+     379      8564899 :    logic        bus_reset_data_beat_cnt   ;
+     380     14439921 :    logic        bus_hold_data_beat_cnt    ;
      381              : 
-     382     10356968 :    logic        bus_inc_cmd_beat_cnt     ;
+     382     10320011 :    logic        bus_inc_cmd_beat_cnt     ;
      383         6270 :    logic        bus_reset_cmd_beat_cnt_0   ;
-     384      5886863 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
-     385     10357314 :    logic        bus_hold_cmd_beat_cnt    ;
+     384      5849905 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
+     385     10320357 :    logic        bus_hold_cmd_beat_cnt    ;
      386              : 
      387         6270 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_data_beat_count  ;
      388         6270 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_data_beat_count      ;
      389              : 
-     390      5893087 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
-     391      5892901 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
+     390      5856129 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
+     391      5855944 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
      392              : 
      393              : 
-     394      2930821 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
-     395      2930753 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
+     394      2916109 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
+     395      2916041 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
      396              : 
      397              : 
-     398     10356968 :    logic        bus_cmd_sent           ;
-     399      5892632 :    logic        bus_last_data_beat     ;
+     398     10320011 :    logic        bus_cmd_sent           ;
+     399      5855674 :    logic        bus_last_data_beat     ;
      400              : 
      401              : 
      402        10432 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren            ;
      403              : 
      404         2608 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren_last       ;
      405         2608 :    logic [pt.ICACHE_NUM_WAYS-1:0]       wren_reset_miss      ;
-     406       639182 :    logic        ifc_dma_access_ok_d;
-     407       639180 :    logic        ifc_dma_access_ok_prev;
+     406       637611 :    logic        ifc_dma_access_ok_d;
+     407       637608 :    logic        ifc_dma_access_ok_prev;
      408              : 
-     409      5893133 :    logic   bus_cmd_req_in ;
-     410      5893104 :    logic   bus_cmd_req_hold ;
+     409      5856175 :    logic   bus_cmd_req_in ;
+     410      5856146 :    logic   bus_cmd_req_hold ;
      411              : 
-     412      3002786 :    logic   second_half_available ;
-     413      3004023 :    logic   write_ic_16_bytes ;
+     412      2985993 :    logic   second_half_available ;
+     413      2987230 :    logic   write_ic_16_bytes ;
      414              : 
      415          170 :    logic   ifc_region_acc_fault_final_bf;
      416          170 :    logic   ifc_region_acc_fault_memory_bf;
@@ -523,21 +523,21 @@
      419              : 
      420            8 :    logic   iccm_correct_ecc;
      421            0 :    logic   dma_sb_err_state, dma_sb_err_state_ff;
-     422      4895844 :    logic   two_byte_instr;
+     422      4874795 :    logic   two_byte_instr;
      423              : 
      424              :    typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;
-     425        21202 :    miss_state_t miss_state, miss_nxtstate;
+     425        21178 :    miss_state_t miss_state, miss_nxtstate;
      426              : 
      427              :    typedef enum logic [1:0] {ERR_STOP_IDLE=2'b00, ERR_FETCH1=2'b01 , ERR_FETCH2=2'b10 , ERR_STOP_FETCH=2'b11} err_stop_state_t;
      428            8 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
      429           24 :    logic   err_stop_state_en ;
      430            8 :    logic   err_stop_fetch ;
      431              : 
-     432      5878691 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
+     432      5841802 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434      2821879 :    logic   ifu_bp_hit_taken_q_f;
-     435     11804512 :    logic   ifu_bus_rvalid_unq;
-     436     10356997 :    logic   bus_cmd_beat_en;
+     434      2816755 :    logic   ifu_bp_hit_taken_q_f;
+     435     11730597 :    logic   ifu_bus_rvalid_unq;
+     436     10320040 :    logic   bus_cmd_beat_en;
      437              : 
      438              : 
      439              : // ---- Clock gating section -----
@@ -587,21 +587,21 @@
      483          317 :       miss_nxtstate   = IDLE;
      484          317 :       miss_state_en   = 1'b0;
      485          317 :       case (miss_state)
-     486      8830950 :          IDLE: begin : idle
-     487      8830950 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488      8830950 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486      8811824 :          IDLE: begin : idle
+     487      8811824 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488      8811824 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490     10143677 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491     10143677 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492     10143677 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493     10143677 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494     10143677 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495     10143677 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496     10143677 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497     10143677 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498     10143677 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499     10143677 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500     10143677 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490     10073452 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491     10073452 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492     10073452 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493     10073452 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494     10073452 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495     10073452 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496     10073452 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497     10073452 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498     10073452 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499     10073452 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500     10073452 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,24 +611,24 @@
      507        21588 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508        21588 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510      5059796 :          MISS_WAIT: begin : miss_wait
-     511      5059796 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512      5059796 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510      5020794 :          MISS_WAIT: begin : miss_wait
+     511      5020794 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512      5020794 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514       181095 :          HIT_U_MISS: begin : hit_u_miss
-     515       181095 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516       181095 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517       181095 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514       181039 :          HIT_U_MISS: begin : hit_u_miss
+     515       181039 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516       181039 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517       181039 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519         2907 :          SCND_MISS: begin : scnd_miss
      520         2907 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
      521         2907 :                                     exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;
      522         2907 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      523              :          end
-     524        23269 :          STALL_SCND_MISS: begin : stall_scnd_miss
-     525        23269 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
-     526        23269 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
-     527        23269 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
+     524        23261 :          STALL_SCND_MISS: begin : stall_scnd_miss
+     525        23261 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
+     526        23261 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
+     527        23261 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      528              :          end
      529            0 :          default: begin : def_case
      530            0 :                   miss_nxtstate   = IDLE;
@@ -638,7 +638,7 @@
      534              :    end
      535              :    rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en),   .*);
      536              : 
-     537      5891837 :   logic    sel_hold_imb     ;
+     537      5854878 :   logic    sel_hold_imb     ;
      538              : 
      539              :    assign miss_pending       =  (miss_state != IDLE) ;
      540              :    assign crit_wd_byp_ok_ff  =  (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
@@ -902,7 +902,7 @@
      798              : /////////////////////////////////////////////////////////////////////////////////////
      799              : //  Create full buffer...                                                          //
      800              : /////////////////////////////////////////////////////////////////////////////////////
-     801       985574 :      logic [63:0]       ic_miss_buff_data_in;
+     801       981979 :      logic [63:0]       ic_miss_buff_data_in;
      802              :      assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
      803              : 
      804              :      for (genvar i=0; i<pt.ICACHE_NUM_BEATS; i++) begin :  wr_flop
@@ -939,10 +939,10 @@
      835              : /////////////////////////////////////////////////////////////////////////////////////
      836              : // New bypass ready                                                                //
      837              : /////////////////////////////////////////////////////////////////////////////////////
-     838       419849 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
-     839       969140 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
-     840      5892841 :    logic   bypass_data_ready_in;
-     841      5878757 :    logic   ic_crit_wd_rdy_new_in;
+     838       418439 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
+     839       966937 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
+     840      5855878 :    logic   bypass_data_ready_in;
+     841      5841869 :    logic   ic_crit_wd_rdy_new_in;
      842              : 
      843              :    assign bypass_index[pt.ICACHE_BEAT_ADDR_HI:1] = imb_ff[pt.ICACHE_BEAT_ADDR_HI:1] ;
      844              :    assign bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3] = bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] + 1 ;
@@ -1046,10 +1046,10 @@
      942          317 :       perr_sb_write_status     = 1'b0;
      943              : 
      944          317 :     case (perr_state)
-     945     24263274 :       ERR_IDLE: begin : err_idle
-     946     24263274 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947     24263274 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948     24263274 :         perr_sb_write_status = perr_state_en;
+     945     24134857 :       ERR_IDLE: begin : err_idle
+     946     24134857 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947     24134857 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948     24134857 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987          317 :       iccm_correction_state        = 1'b0;
      988              : 
      989          317 :       case (err_stop_state)
-     990     24263258 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991     24263258 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992     24263258 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990     24134841 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991     24134841 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992     24134841 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994           12 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995           12 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1469,7 +1469,7 @@
     1365              :                               ((miss_state == CRIT_BYP_OK) &  miss_state_en &  (miss_nxtstate == MISS_WAIT))  ))  |
     1366              :                              ( ifc_fetch_req_bf & exu_flush_final  & ~ifc_fetch_uncacheable_bf & ~ifc_iccm_access_bf )     ;
     1367              : 
-    1368      6690060 : logic   ic_real_rd_wp_unused;
+    1368      6652456 : logic   ic_real_rd_wp_unused;
     1369              : assign  ic_real_rd_wp_unused  =  (ifc_fetch_req_bf &  ~ifc_iccm_access_bf  &  ~ifc_region_acc_fault_final_bf & ~dec_tlu_fence_i_wb & ~stream_miss_f & ~ic_act_miss_f &
     1370              :                             ~(((miss_state == STREAM) & ~miss_state_en) |
     1371              :                               ((miss_state == CRIT_BYP_OK) & ~miss_state_en & ~(miss_nxtstate == MISS_WAIT)) |
@@ -1547,8 +1547,8 @@
     1443          317 :   always_comb begin : way_status_out_mux
     1444          317 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445          317 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446     24263282 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447     24263282 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446     24134865 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447     24134865 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506          317 :   always_comb begin : tag_valid_out_mux
     1507          317 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508          317 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509     24263282 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510     24263282 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511     48526564 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509     24134865 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510     24134865 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511     48269730 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all/index_el2_lib.sv.html b/html/main/coverage_dashboard/all/index_el2_lib.sv.html
index 45b6743b6b4..8d4acc17040 100644
--- a/html/main/coverage_dashboard/all/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35      3393638 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
-      36      3515658 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
+      35      3388026 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
+      36      3508524 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
       37              :                         );
       38              : 
       39              : 
@@ -158,9 +158,9 @@
       54              : #(
       55              : `include "el2_param.vh"
       56              :  )(
-      57       983532 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58      1448724 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59      1943755 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      57       982040 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
+      58      1439928 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59      1934685 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu.sv.html
index e0da9c6dd16..ce7adab405a 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : (
       34              : 
       35            0 :    input logic                             clk_override,             // Override non-functional clock gating
-      36        58638 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
+      36        58568 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
       37        29654 :    input logic                             dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
       38            0 :    input logic                             dec_tlu_force_halt,       // This will be high till TLU goes to debug halt
       39              : 
@@ -147,21 +147,21 @@
       43          301 :    input logic                             dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
       44            8 :    input logic                             dec_tlu_core_ecc_disable,          // disable the generation of the ecc
       45              : 
-      46       413833 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
-      47        81386 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
-      48       270518 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
+      46       411891 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
+      47        81344 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
+      48       269944 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
       49              : 
-      50       623945 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
-      51      2276073 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
+      50       621353 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
+      51      2264531 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
       52            0 :    input logic [31:0]                      dec_tlu_mrac_ff,       // CSR for memory region control
       53              : 
       54        38395 :    output logic [31:0]                     lsu_result_m,          // lsu load data
       55        29134 :    output logic [31:0]                     lsu_result_corr_r,     // This is the ECC corrected data going to RF
-      56        49050 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
-      57        59374 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
+      56        48988 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
+      57        59312 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
       58            4 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
-      59      1346967 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
-      60      1346650 :    output logic                            lsu_active,            // Used to turn off top level clk
+      59      1337985 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
+      60      1337668 :    output logic                            lsu_active,            // Used to turn off top level clk
       61              : 
       62        24694 :    output logic [31:1]                     lsu_fir_addr,        // fast interrupt address
       63            0 :    output logic [1:0]                      lsu_fir_error,       // Error during fast interrupt lookup
@@ -170,25 +170,25 @@
       66            4 :    output el2_lsu_error_pkt_t             lsu_error_pkt_r,               // lsu exception packet
       67            0 :    output logic                            lsu_imprecise_error_load_any,  // bus load imprecise error
       68            0 :    output logic                            lsu_imprecise_error_store_any, // bus store imprecise error
-      69          401 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
+      69          400 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
       70              : 
       71              :    // Non-blocking loads
-      72       881640 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
-      73       504869 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
+      72       875716 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
+      73       502857 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
       74            0 :    output logic                               lsu_nonblock_load_inv_r,        // invalidate signal for the cam entry for non block loads
-      75       504866 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
-      76       920896 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
+      75       502854 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
+      76       914818 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
       77            0 :    output logic                               lsu_nonblock_load_data_error,   // non block load has an error
-      78        36662 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
-      79        71560 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
+      78        36598 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
+      79        71538 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
       80              : 
-      81       891764 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
-      82       806110 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
-      83        48786 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
-      84      1667379 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
-      85        36420 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
+      81       885840 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
+      82       800418 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
+      83        48780 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
+      84      1655267 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
+      85        36414 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
       86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
-      87        67818 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
+      87        67790 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
       88              : 
       89              :    // Trigger signals
       90            0 :    input                                   el2_trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode
@@ -199,8 +199,8 @@
       95       561000 :    output logic                            dccm_rden,       // DCCM read enable
       96        18811 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo, // DCCM write address low bank
       97        18811 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi, // DCCM write address hi bank
-      98       471780 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
-      99       678187 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
+      98       470114 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
+      99       676449 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
      100         5374 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo, // DCCM write data for lo bank
      101         5374 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi, // DCCM write data for hi bank
      102              : 
@@ -211,16 +211,16 @@
      107            0 :    output logic                            picm_wren,    // PIC memory write enable
      108            0 :    output logic                            picm_rden,    // PIC memory read enable
      109            0 :    output logic                            picm_mken,    // Need to read the mask for stores to determine which bits to write/forward
-     110          430 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
-     111          430 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
-     112        92644 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
+     110          429 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
+     111          429 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
+     112        92616 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
      113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
      114              : 
      115              :    // AXI Write Channels
-     116       855209 :    output logic                            lsu_axi_awvalid,
-     117      1107817 :    input  logic                            lsu_axi_awready,
+     116       849023 :    output logic                            lsu_axi_awvalid,
+     117      1095685 :    input  logic                            lsu_axi_awready,
      118            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     119          401 :    output logic [31:0]                     lsu_axi_awaddr,
+     119          400 :    output logic [31:0]                     lsu_axi_awaddr,
      120          314 :    output logic [3:0]                      lsu_axi_awregion,
      121            0 :    output logic [7:0]                      lsu_axi_awlen,
      122            0 :    output logic [2:0]                      lsu_axi_awsize,
@@ -230,22 +230,22 @@
      126            0 :    output logic [2:0]                      lsu_axi_awprot,
      127            0 :    output logic [3:0]                      lsu_axi_awqos,
      128              : 
-     129       855209 :    output logic                            lsu_axi_wvalid,
-     130      1107817 :    input  logic                            lsu_axi_wready,
-     131        31411 :    output logic [63:0]                     lsu_axi_wdata,
-     132       224989 :    output logic [7:0]                      lsu_axi_wstrb,
+     129       849023 :    output logic                            lsu_axi_wvalid,
+     130      1095685 :    input  logic                            lsu_axi_wready,
+     131        31367 :    output logic [63:0]                     lsu_axi_wdata,
+     132       224179 :    output logic [7:0]                      lsu_axi_wstrb,
      133          317 :    output logic                            lsu_axi_wlast,
      134              : 
-     135       868520 :    input  logic                            lsu_axi_bvalid,
+     135       862312 :    input  logic                            lsu_axi_bvalid,
      136          317 :    output logic                            lsu_axi_bready,
      137            0 :    input  logic [1:0]                      lsu_axi_bresp,
      138            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      139              : 
      140              :    // AXI Read Channels
-     141       868958 :    output logic                            lsu_axi_arvalid,
-     142      1115481 :    input  logic                            lsu_axi_arready,
+     141       863034 :    output logic                            lsu_axi_arvalid,
+     142      1103367 :    input  logic                            lsu_axi_arready,
      143            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     144          401 :    output logic [31:0]                     lsu_axi_araddr,
+     144          400 :    output logic [31:0]                     lsu_axi_araddr,
      145          314 :    output logic [3:0]                      lsu_axi_arregion,
      146            0 :    output logic [7:0]                      lsu_axi_arlen,
      147            0 :    output logic [2:0]                      lsu_axi_arsize,
@@ -255,10 +255,10 @@
      151            0 :    output logic [2:0]                      lsu_axi_arprot,
      152            0 :    output logic [3:0]                      lsu_axi_arqos,
      153              : 
-     154       929722 :    input  logic                            lsu_axi_rvalid,
+     154       923642 :    input  logic                            lsu_axi_rvalid,
      155          317 :    output logic                            lsu_axi_rready,
      156            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     157        28838 :    input  logic [63:0]                     lsu_axi_rdata,
+     157        28760 :    input  logic [63:0]                     lsu_axi_rdata,
      158            0 :    input  logic [1:0]                      lsu_axi_rresp,
      159       672602 :    input  logic                            lsu_axi_rlast,
      160              : 
@@ -276,32 +276,32 @@
      172            4 :    output logic                            dccm_dma_ecc_error,  // DMA load had ecc error
      173           12 :    output logic [2:0]                      dccm_dma_rtag,       // DMA request tag
      174        39560 :    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
-     175      2225276 :    output logic                            dccm_ready,          // lsu ready for DMA access
+     175      2213734 :    output logic                            dccm_ready,          // lsu ready for DMA access
      176              : 
      177              :    // DCCM ECC status
      178            4 :    output logic                            lsu_dccm_rd_ecc_single_err,
      179            4 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182     61843746 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183     61843746 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182     61251245 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183     61251245 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184          316 :     input logic                             rst_l,               // reset, active low
      185              : 
-     186       594111 :     output logic [31:0] lsu_pmp_addr_start,
-     187       594149 :     output logic [31:0] lsu_pmp_addr_end,
-     188       167732 :     input  logic        lsu_pmp_error_start,
-     189       167732 :     input  logic        lsu_pmp_error_end,
-     190      1065445 :     output logic        lsu_pmp_we,
-     191      1424320 :     output logic        lsu_pmp_re
+     186       592373 :     output logic [31:0] lsu_pmp_addr_start,
+     187       592411 :     output logic [31:0] lsu_pmp_addr_end,
+     188       162421 :     input  logic        lsu_pmp_error_start,
+     189       162421 :     input  logic        lsu_pmp_error_end,
+     190      1059753 :     output logic        lsu_pmp_we,
+     191      1418396 :     output logic        lsu_pmp_re
      192              : 
      193              :    );
      194              : 
      195       561000 :    logic        lsu_dccm_rden_m;
      196       561000 :    logic        lsu_dccm_rden_r;
-     197        81386 :    logic [31:0] store_data_m;
-     198        56474 :    logic [31:0] store_data_r;
-     199        91102 :    logic [31:0] store_data_hi_r, store_data_lo_r;
-     200        62394 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
+     197        81344 :    logic [31:0] store_data_m;
+     198        56432 :    logic [31:0] store_data_r;
+     199        91074 :    logic [31:0] store_data_hi_r, store_data_lo_r;
+     200        62366 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
      201        47172 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
      202            2 :    logic [31:0] sec_data_lo_r, sec_data_hi_r;
      203              : 
@@ -324,12 +324,12 @@
      220              : 
      221            0 :    logic [31:0] picm_mask_data_m;
      222              : 
-     223       594109 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
-     224       594509 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
+     223       592371 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
+     224       592771 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
      225              :   assign lsu_pmp_addr_start = lsu_addr_d;
      226              :   assign lsu_pmp_addr_end   = end_addr_d;
      227              : 
-     228       478181 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
+     228       475589 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
      229            0 :    logic        lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
      230              :   assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
      231              :   assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
@@ -338,12 +338,12 @@
      234       258930 :    logic        store_stbuf_reqvld_r;
      235       258930 :    logic        ldst_stbuf_reqvld_r;
      236              : 
-     237      2279496 :    logic        lsu_commit_r;
+     237      2267916 :    logic        lsu_commit_r;
      238           60 :    logic        lsu_exc_m;
      239              : 
      240       614420 :    logic        addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
      241            0 :    logic        addr_in_pic_d, addr_in_pic_m, addr_in_pic_r;
-     242        36568 :    logic        ldst_dual_d, ldst_dual_m, ldst_dual_r;
+     242        36562 :    logic        ldst_dual_d, ldst_dual_m, ldst_dual_r;
      243       614746 :    logic        addr_external_m;
      244              : 
      245       258446 :    logic                          stbuf_reqvld_any;
@@ -365,11 +365,11 @@
      261        10324 :    logic        lsu_stbuf_full_any;
      262              : 
      263              :     // Bus signals
-     264      1659482 :    logic        lsu_busreq_r;
-     265       808157 :    logic        lsu_bus_buffer_pend_any;
-     266      1187701 :    logic        lsu_bus_buffer_empty_any;
-     267        49046 :    logic        lsu_bus_buffer_full_any;
-     268      1669696 :    logic        lsu_busreq_m;
+     264      1647902 :    logic        lsu_busreq_r;
+     265       802237 :    logic        lsu_bus_buffer_pend_any;
+     266      1177737 :    logic        lsu_bus_buffer_empty_any;
+     267        48984 :    logic        lsu_bus_buffer_full_any;
+     268      1658116 :    logic        lsu_busreq_m;
      269          200 :    logic [31:0] bus_read_data_m;
      270              : 
      271        29654 :    logic        flush_m_up, flush_r;
@@ -381,16 +381,16 @@
      277            0 :    logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
      278              : 
      279              :    // Clocks
-     280      1088274 :    logic        lsu_busm_clken;
-     281      2035983 :    logic        lsu_bus_obuf_c1_clken;
-     282     61843746 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283     61843746 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284     61843746 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     280      1078918 :    logic        lsu_busm_clken;
+     281      2018773 :    logic        lsu_bus_obuf_c1_clken;
+     282     61251245 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283     61251245 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284     61251245 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286     61843746 :    logic        lsu_stbuf_c1_clk;
-     287     61843746 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286     61251245 :    logic        lsu_stbuf_c1_clk;
+     287     61251245 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289     61843746 :    logic        lsu_free_c2_clk;
+     289     61251245 :    logic        lsu_free_c2_clk;
      290              : 
      291        18834 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292        18768 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_addrcheck.sv.html
index 216d7dda205..1434232d975 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,16 +131,16 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30     61843746 :    input logic          lsu_c2_m_clk,              // clock
+      30     61251245 :    input logic          lsu_c2_m_clk,              // clock
       31          316 :    input logic          rst_l,                     // reset
       32              : 
-      33       594111 :    input logic [31:0]   start_addr_d,              // start address for lsu
-      34       594149 :    input logic [31:0]   end_addr_d,                // end address for lsu
-      35       478232 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
+      33       592373 :    input logic [31:0]   start_addr_d,              // start address for lsu
+      34       592411 :    input logic [31:0]   end_addr_d,                // end address for lsu
+      35       475640 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
       36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
-      37      1440947 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
+      37      1437077 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
       38              : 
-      39       476238 :    input logic [31:0]   rs1_d,                     // address rs operand
+      39       474296 :    input logic [31:0]   rs1_d,                     // address rs operand
       40              : 
       41        29240 :    output logic         is_sideeffects_m,          // is sideffects space
       42       614420 :    output logic         addr_in_dccm_d,            // address in dccm
@@ -154,20 +154,20 @@
       50            0 :    output logic         fir_dccm_access_error_d,   // Fast interrupt dccm access error
       51            0 :    output logic         fir_nondccm_access_error_d,// Fast interrupt dccm access error
       52              : 
-      53       167732 :     input logic lsu_pmp_error_start,
-      54       167732 :     input logic lsu_pmp_error_end,
+      53       162421 :     input logic lsu_pmp_error_start,
+      54       162421 :     input logic lsu_pmp_error_end,
       55              : 
       56            0 :    input  logic         scan_mode                  // Scan mode
       57              : );
       58              : 
       59              : 
       60            0 :    logic        non_dccm_access_ok;
-      61        56799 :    logic        is_sideeffects_d, is_aligned_d;
+      61        56793 :    logic        is_sideeffects_d, is_aligned_d;
       62       614420 :    logic        start_addr_in_dccm_d, end_addr_in_dccm_d;
       63       614430 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
       64            0 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
       65       614430 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
-      66       817391 :    logic [4:0]  csr_idx;
+      66       813521 :    logic [4:0]  csr_idx;
       67         5858 :    logic        addr_in_iccm;
       68       614430 :    logic        start_addr_dccm_or_pic;
       69       614422 :    logic        base_reg_dccm_or_pic;
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_bus_buffer.sv.html
index 784d6712831..d3d263cd73f 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31     61843746 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31     61251245 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33          316 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -142,73 +142,73 @@
       38            0 :    input logic                          dec_tlu_force_halt,
       39              : 
       40              :    // various clocks needed for the bus reads and writes
-      41      2035983 :    input logic                          lsu_bus_obuf_c1_clken,
-      42      1088274 :    input logic                          lsu_busm_clken,
-      43     61843746 :    input logic                          lsu_c2_r_clk,
-      44     61843746 :    input logic                          lsu_bus_ibuf_c1_clk,
+      41      2018773 :    input logic                          lsu_bus_obuf_c1_clken,
+      42      1078918 :    input logic                          lsu_busm_clken,
+      43     61251245 :    input logic                          lsu_c2_r_clk,
+      44     61251245 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46     61843746 :    input logic                          lsu_bus_buf_c1_clk,
-      47     61843746 :    input logic                          lsu_free_c2_clk,
+      46     61251245 :    input logic                          lsu_bus_buf_c1_clk,
+      47     61251245 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
-      51      2276073 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
-      52       478184 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
-      53       478181 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
+      51      2264531 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
+      52       475592 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
+      53       475589 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
       54              : 
-      55       350819 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
-      56       351009 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
-      57       347000 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
-      58       347184 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
-      59        54816 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
+      55       349081 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
+      56       349271 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
+      57       345262 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
+      58       345446 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
+      59        54774 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
       60              : 
-      61       119084 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
-      62        98804 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
-      63      1669696 :    input logic                          lsu_busreq_m,                   // bus request is in m
-      64      1659482 :    output logic                         lsu_busreq_r,                   // bus request is in r
+      61       118190 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
+      62        98168 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
+      63      1658116 :    input logic                          lsu_busreq_m,                   // bus request is in m
+      64      1647902 :    output logic                         lsu_busreq_r,                   // bus request is in r
       65        10332 :    input logic                          ld_full_hit_m,                  // load can get all its byte from a write buffer entry
-      66        58638 :    input logic                          flush_m_up,                     // flush
+      66        58568 :    input logic                          flush_m_up,                     // flush
       67        29654 :    input logic                          flush_r,                        // flush
-      68      2279496 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
+      68      2267916 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
       69        29230 :    input logic                          is_sideeffects_r,               // lsu attribute is side_effects
-      70        36568 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
-      71        36568 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
-      72        36568 :    input logic                          ldst_dual_r,                    // load/store is unaligned at 32 bit boundary
+      70        36562 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
+      71        36562 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
+      72        36562 :    input logic                          ldst_dual_r,                    // load/store is unaligned at 32 bit boundary
       73              : 
       74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
       75              : 
-      76       808157 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
-      77        49046 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
-      78      1187701 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
+      76       802237 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
+      77        48984 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
+      78      1177737 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
       79              : 
       80            0 :    output logic [3:0]                   ld_byte_hit_buf_lo, ld_byte_hit_buf_hi,    // Byte enables for forwarding data
       81           74 :    output logic [31:0]                  ld_fwddata_buf_lo, ld_fwddata_buf_hi,      // load forwarding data
       82              : 
       83            0 :    output logic                         lsu_imprecise_error_load_any,     // imprecise load bus error
       84            0 :    output logic                         lsu_imprecise_error_store_any,    // imprecise store bus error
-      85          401 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
+      85          400 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
       86              : 
       87              :    // Non-blocking loads
-      88       881640 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
-      89       504869 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
+      88       875716 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
+      89       502857 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
       90            0 :    output logic                               lsu_nonblock_load_inv_r,       // invalidate signal for the cam entry for non block loads
-      91       504866 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
-      92       920896 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
+      91       502854 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
+      92       914818 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
       93            0 :    output logic                               lsu_nonblock_load_data_error,  // non block load has an error
-      94        36662 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
-      95        71560 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
+      94        36598 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
+      95        71538 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
       96              : 
       97              :    // PMU events
-      98      1667379 :    output logic                         lsu_pmu_bus_trxn,
-      99        36420 :    output logic                         lsu_pmu_bus_misaligned,
+      98      1655267 :    output logic                         lsu_pmu_bus_trxn,
+      99        36414 :    output logic                         lsu_pmu_bus_misaligned,
      100            0 :    output logic                         lsu_pmu_bus_error,
-     101        67818 :    output logic                         lsu_pmu_bus_busy,
+     101        67790 :    output logic                         lsu_pmu_bus_busy,
      102              : 
      103              :    // AXI Write Channels
-     104       855209 :    output logic                            lsu_axi_awvalid,
-     105      1107817 :    input  logic                            lsu_axi_awready,
+     104       849023 :    output logic                            lsu_axi_awvalid,
+     105      1095685 :    input  logic                            lsu_axi_awready,
      106            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     107          401 :    output logic [31:0]                     lsu_axi_awaddr,
+     107          400 :    output logic [31:0]                     lsu_axi_awaddr,
      108          314 :    output logic [3:0]                      lsu_axi_awregion,
      109            0 :    output logic [7:0]                      lsu_axi_awlen,
      110            0 :    output logic [2:0]                      lsu_axi_awsize,
@@ -218,22 +218,22 @@
      114            0 :    output logic [2:0]                      lsu_axi_awprot,
      115            0 :    output logic [3:0]                      lsu_axi_awqos,
      116              : 
-     117       855209 :    output logic                            lsu_axi_wvalid,
-     118      1107817 :    input  logic                            lsu_axi_wready,
-     119        31411 :    output logic [63:0]                     lsu_axi_wdata,
-     120       224989 :    output logic [7:0]                      lsu_axi_wstrb,
+     117       849023 :    output logic                            lsu_axi_wvalid,
+     118      1095685 :    input  logic                            lsu_axi_wready,
+     119        31367 :    output logic [63:0]                     lsu_axi_wdata,
+     120       224179 :    output logic [7:0]                      lsu_axi_wstrb,
      121          317 :    output logic                            lsu_axi_wlast,
      122              : 
-     123       868520 :    input  logic                            lsu_axi_bvalid,
+     123       862312 :    input  logic                            lsu_axi_bvalid,
      124          317 :    output logic                            lsu_axi_bready,
      125            0 :    input  logic [1:0]                      lsu_axi_bresp,
      126            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      127              : 
      128              :    // AXI Read Channels
-     129       868958 :    output logic                            lsu_axi_arvalid,
-     130      1115481 :    input  logic                            lsu_axi_arready,
+     129       863034 :    output logic                            lsu_axi_arvalid,
+     130      1103367 :    input  logic                            lsu_axi_arready,
      131            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     132          401 :    output logic [31:0]                     lsu_axi_araddr,
+     132          400 :    output logic [31:0]                     lsu_axi_araddr,
      133          314 :    output logic [3:0]                      lsu_axi_arregion,
      134            0 :    output logic [7:0]                      lsu_axi_arlen,
      135            0 :    output logic [2:0]                      lsu_axi_arsize,
@@ -243,10 +243,10 @@
      139            0 :    output logic [2:0]                      lsu_axi_arprot,
      140            0 :    output logic [3:0]                      lsu_axi_arqos,
      141              : 
-     142       929722 :    input  logic                            lsu_axi_rvalid,
+     142       923642 :    input  logic                            lsu_axi_rvalid,
      143          317 :    output logic                            lsu_axi_rready,
      144            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     145        28838 :    input  logic [63:0]                     lsu_axi_rdata,
+     145        28760 :    input  logic [63:0]                     lsu_axi_rdata,
      146            0 :    input  logic [1:0]                      lsu_axi_rresp,
      147              : 
      148          316 :    input logic                             lsu_bus_clk_en,
@@ -264,7 +264,7 @@
      160              :    localparam TIMER_MAX = TIMER - 1;  // Maximum value of timer
      161              :    localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);
      162              : 
-     163       434262 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
+     163       430634 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
      164         2450 :    logic [DEPTH-1:0]                    ld_addr_hitvec_lo, ld_addr_hitvec_hi;
      165            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvec_lo, ld_byte_hitvec_hi;
      166            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;
@@ -273,82 +273,82 @@
      169            0 :    logic [3:0]                          ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;
      170              : 
      171         8172 :    logic [3:0]                          ldst_byteen_r;
-     172       431718 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
-     173        62092 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
-     174        56512 :    logic                                is_aligned_r;                   // Aligned load/store
-     175        18349 :    logic                                ldst_samedw_r;
+     172       428090 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
+     173        62064 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
+     174        56506 :    logic                                is_aligned_r;                   // Aligned load/store
+     175        18347 :    logic                                ldst_samedw_r;
      176              : 
-     177       881494 :    logic                                lsu_nonblock_load_valid_r;
-     178        45442 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
-     179       206010 :    logic [1:0]                          lsu_nonblock_addr_offset;
-     180       129683 :    logic [1:0]                          lsu_nonblock_sz;
-     181       243322 :    logic                                lsu_nonblock_unsign;
-     182       920896 :    logic                                lsu_nonblock_load_data_ready;
+     177       875570 :    logic                                lsu_nonblock_load_valid_r;
+     178        45342 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
+     179       204056 :    logic [1:0]                          lsu_nonblock_addr_offset;
+     180       129339 :    logic [1:0]                          lsu_nonblock_sz;
+     181       239414 :    logic                                lsu_nonblock_unsign;
+     182       914818 :    logic                                lsu_nonblock_load_data_ready;
      183              : 
      184         4572 :    logic [DEPTH-1:0]                    CmdPtr0Dec, CmdPtr1Dec;
-     185          798 :    logic [DEPTH-1:0]                    RspPtrDec;
+     185          778 :    logic [DEPTH-1:0]                    RspPtrDec;
      186        18787 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
-     187         2718 :    logic [DEPTH_LOG2-1:0]               RspPtr;
-     188       504866 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
-     189       563828 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
+     187         2668 :    logic [DEPTH_LOG2-1:0]               RspPtr;
+     188       502854 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
+     189       561546 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
      190        14100 :    logic                                found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;
      191            0 :    logic [3:0]                          buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;
-     192        23634 :    logic                                any_done_wait_state;
+     192        23434 :    logic                                any_done_wait_state;
      193        15181 :    logic                                bus_sideeffect_pend;
      194           20 :    logic                                bus_coalescing_disable;
      195              : 
-     196        87222 :    logic                                bus_addr_match_pending;
-     197      1662861 :    logic                                bus_cmd_sent, bus_cmd_ready;
-     198       864881 :    logic                                bus_wcmd_sent, bus_wdata_sent;
-     199       722090 :    logic                                bus_rsp_read, bus_rsp_write;
+     196        86732 :    logic                                bus_addr_match_pending;
+     197      1650749 :    logic                                bus_cmd_sent, bus_cmd_ready;
+     198       858695 :    logic                                bus_wcmd_sent, bus_wdata_sent;
+     199       716010 :    logic                                bus_rsp_read, bus_rsp_write;
      200            0 :    logic [pt.LSU_BUS_TAG-1:0]           bus_rsp_read_tag, bus_rsp_write_tag;
      201            0 :    logic                                bus_rsp_read_error, bus_rsp_write_error;
-     202        28838 :    logic [63:0]                         bus_rsp_rdata;
+     202        28760 :    logic [63:0]                         bus_rsp_rdata;
      203              : 
      204              :    // Bus buffer signals
-     205        12908 :    state_t [DEPTH-1:0]                  buf_state;
-     206         1239 :    logic   [DEPTH-1:0][1:0]             buf_sz;
+     205        12884 :    state_t [DEPTH-1:0]                  buf_state;
+     206         1237 :    logic   [DEPTH-1:0][1:0]             buf_sz;
      207           20 :    logic   [DEPTH-1:0][31:0]            buf_addr;
-     208         2643 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
+     208         2641 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
      209            4 :    logic   [DEPTH-1:0]                  buf_sideeffect;
-     210         2144 :    logic   [DEPTH-1:0]                  buf_write;
+     210         2141 :    logic   [DEPTH-1:0]                  buf_write;
      211          584 :    logic   [DEPTH-1:0]                  buf_unsign;
      212           62 :    logic   [DEPTH-1:0]                  buf_dual;
-     213         1120 :    logic   [DEPTH-1:0]                  buf_samedw;
+     213         1118 :    logic   [DEPTH-1:0]                  buf_samedw;
      214         3044 :    logic   [DEPTH-1:0]                  buf_nomerge;
      215           62 :    logic   [DEPTH-1:0]                  buf_dualhi;
-     216          610 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
-     217          798 :    logic   [DEPTH-1:0]                  buf_ldfwd;
-     218         1138 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
+     216          608 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
+     217          778 :    logic   [DEPTH-1:0]                  buf_ldfwd;
+     218         1120 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
      219            0 :    logic   [DEPTH-1:0]                  buf_error;
      220         1245 :    logic   [DEPTH-1:0][31:0]            buf_data;
      221            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age, buf_age_younger;
      222            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage, buf_rsp_pickage;
      223              : 
-     224        13092 :    state_t [DEPTH-1:0]                  buf_nxtstate;
-     225        12908 :    logic   [DEPTH-1:0]                  buf_rst;
-     226        64458 :    logic   [DEPTH-1:0]                  buf_state_en;
-     227        24620 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
-     228        24142 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
-     229        43086 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
-     230        36382 :    logic   [DEPTH-1:0]                  buf_dual_in;
-     231        18271 :    logic   [DEPTH-1:0]                  buf_samedw_in;
-     232       102968 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
+     224        13068 :    state_t [DEPTH-1:0]                  buf_nxtstate;
+     225        12884 :    logic   [DEPTH-1:0]                  buf_rst;
+     226        64372 :    logic   [DEPTH-1:0]                  buf_state_en;
+     227        24584 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
+     228        24106 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
+     229        43014 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
+     230        36376 :    logic   [DEPTH-1:0]                  buf_dual_in;
+     231        18269 :    logic   [DEPTH-1:0]                  buf_samedw_in;
+     232       102332 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
      233        26802 :    logic   [DEPTH-1:0]                  buf_sideeffect_in;
-     234       531344 :    logic   [DEPTH-1:0]                  buf_unsign_in;
-     235       462466 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
-     236      1060944 :    logic   [DEPTH-1:0]                  buf_write_in;
-     237        24624 :    logic   [DEPTH-1:0]                  buf_wr_en;
+     234       526824 :    logic   [DEPTH-1:0]                  buf_unsign_in;
+     235       459874 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
+     236      1055276 :    logic   [DEPTH-1:0]                  buf_write_in;
+     237        24588 :    logic   [DEPTH-1:0]                  buf_wr_en;
      238         4480 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
-     239       564429 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
-     240        14636 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
-     241        24622 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
-     242         2896 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
-     243       432760 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
-     244       347724 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
-     245        65090 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
+     239       562147 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
+     240        14594 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
+     241        24586 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
+     242         2878 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
+     243       429130 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
+     244       345986 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
+     245        65080 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
      246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
-     247        37352 :    logic   [DEPTH-1:0]                  buf_data_en;
+     247        37292 :    logic   [DEPTH-1:0]                  buf_data_en;
      248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
      249            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_ageQ;
      250            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage_set;
@@ -356,104 +356,104 @@
      252            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspageQ;
      253              : 
      254              :    // Input buffer signals
-     255       792047 :    logic                               ibuf_valid;
+     255       786389 :    logic                               ibuf_valid;
      256        12414 :    logic                               ibuf_dual;
      257         7882 :    logic                               ibuf_samedw;
      258          254 :    logic                               ibuf_nomerge;
-     259        49236 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
-     260        44004 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
+     259        49008 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
+     260        43776 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
      261          202 :    logic                               ibuf_sideeffect;
      262            2 :    logic                               ibuf_unsign;
      263          374 :    logic                               ibuf_write;
-     264        51687 :    logic [1:0]                         ibuf_sz;
-     265        53388 :    logic [3:0]                         ibuf_byteen;
-     266          332 :    logic [31:0]                        ibuf_addr;
-     267        43177 :    logic [31:0]                        ibuf_data;
-     268       763200 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
+     264        51607 :    logic [1:0]                         ibuf_sz;
+     265        53250 :    logic [3:0]                         ibuf_byteen;
+     266          331 :    logic [31:0]                        ibuf_addr;
+     267        43125 :    logic [31:0]                        ibuf_data;
+     268       757566 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
      269              : 
-     270       933790 :    logic                               ibuf_byp;
-     271       800872 :    logic                               ibuf_wr_en;
-     272       792033 :    logic                               ibuf_rst;
-     273       312538 :    logic                               ibuf_force_drain;
-     274       792573 :    logic                               ibuf_drain_vld;
-     275        11750 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
-     276       505998 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
-     277       504866 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
-     278       458640 :    logic [1:0]                         ibuf_sz_in;
-     279       347184 :    logic [31:0]                        ibuf_addr_in;
-     280       405384 :    logic [3:0]                         ibuf_byteen_in;
-     281        63168 :    logic [31:0]                        ibuf_data_in;
-     282       763210 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
-     283        53568 :    logic [3:0]                         ibuf_byteen_out;
-     284        43225 :    logic [31:0]                        ibuf_data_out;
-     285         1305 :    logic                               ibuf_merge_en, ibuf_merge_in;
+     270       927358 :    logic                               ibuf_byp;
+     271       795214 :    logic                               ibuf_wr_en;
+     272       786375 :    logic                               ibuf_rst;
+     273       312528 :    logic                               ibuf_force_drain;
+     274       786915 :    logic                               ibuf_drain_vld;
+     275        11738 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
+     276       503986 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
+     277       502854 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
+     278       456048 :    logic [1:0]                         ibuf_sz_in;
+     279       345446 :    logic [31:0]                        ibuf_addr_in;
+     280       401756 :    logic [3:0]                         ibuf_byteen_in;
+     281        63140 :    logic [31:0]                        ibuf_data_in;
+     282       757576 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
+     283        53430 :    logic [3:0]                         ibuf_byteen_out;
+     284        43173 :    logic [31:0]                        ibuf_data_out;
+     285         1299 :    logic                               ibuf_merge_en, ibuf_merge_in;
      286              : 
      287              :    // Output buffer signals
-     288      1569521 :    logic                               obuf_valid;
-     289       281646 :    logic                               obuf_write;
-     290        23634 :    logic                               obuf_nosend;
-     291       911064 :    logic                               obuf_rdrsp_pend;
+     288      1557449 :    logic                               obuf_valid;
+     289       277662 :    logic                               obuf_write;
+     290        23434 :    logic                               obuf_nosend;
+     291       905140 :    logic                               obuf_rdrsp_pend;
      292         2668 :    logic                               obuf_sideeffect;
-     293          401 :    logic [31:0]                        obuf_addr;
-     294        31411 :    logic [63:0]                        obuf_data;
-     295       124860 :    logic [1:0]                         obuf_sz;
-     296       424295 :    logic [7:0]                         obuf_byteen;
-     297         8190 :    logic                               obuf_merge;
+     293          400 :    logic [31:0]                        obuf_addr;
+     294        31367 :    logic [63:0]                        obuf_data;
+     295       124516 :    logic [1:0]                         obuf_sz;
+     296       422343 :    logic [7:0]                         obuf_byteen;
+     297         8186 :    logic                               obuf_merge;
      298            0 :    logic                               obuf_cmd_done, obuf_data_done;
      299            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0;
      300            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1;
      301            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag;
      302              : 
-     303       809676 :    logic                               ibuf_buf_byp;
-     304        65546 :    logic                               obuf_force_wr_en;
+     303       803504 :    logic                               ibuf_buf_byp;
+     304        65532 :    logic                               obuf_force_wr_en;
      305       314770 :    logic                               obuf_wr_wait;
-     306      1606909 :    logic                               obuf_wr_en, obuf_wr_enQ;
-     307      1569517 :    logic                               obuf_rst;
-     308       333238 :    logic                               obuf_write_in;
-     309       714540 :    logic                               obuf_nosend_in;
+     306      1594813 :    logic                               obuf_wr_en, obuf_wr_enQ;
+     307      1557445 :    logic                               obuf_rst;
+     308       329228 :    logic                               obuf_write_in;
+     309       710014 :    logic                               obuf_nosend_in;
      310          316 :    logic                               obuf_rdrsp_pend_en;
-     311       911064 :    logic                               obuf_rdrsp_pend_in;
+     311       905140 :    logic                               obuf_rdrsp_pend_in;
      312         2812 :    logic                               obuf_sideeffect_in;
-     313        46727 :    logic                               obuf_aligned_in;
-     314          401 :    logic [31:0]                        obuf_addr_in;
-     315        67746 :    logic [63:0]                        obuf_data_in;
-     316       151902 :    logic [1:0]                         obuf_sz_in;
-     317       458692 :    logic [7:0]                         obuf_byteen_in;
-     318        15566 :    logic                               obuf_merge_in;
+     313        46721 :    logic                               obuf_aligned_in;
+     314          400 :    logic [31:0]                        obuf_addr_in;
+     315        67520 :    logic [63:0]                        obuf_data_in;
+     316       151558 :    logic [1:0]                         obuf_sz_in;
+     317       456624 :    logic [7:0]                         obuf_byteen_in;
+     318        15560 :    logic                               obuf_merge_in;
      319            0 :    logic                               obuf_cmd_done_in, obuf_data_done_in;
      320            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0_in;
      321            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1_in;
      322            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag_in;
      323              : 
-     324        15566 :    logic                               obuf_merge_en;
+     324        15560 :    logic                               obuf_merge_en;
      325       288436 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
-     326       290998 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
-     327        46595 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
+     326       289608 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
+     327        46385 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
      328              : 
-     329       854945 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
-     330       854945 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
-     331       879147 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
+     329       848759 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
+     330       848759 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
+     331       873223 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
      332          314 :    logic                               lsu_axi_bvalid_q, lsu_axi_bready_q;
      333          314 :    logic                               lsu_axi_rvalid_q, lsu_axi_rready_q;
      334            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_axi_bid_q, lsu_axi_rid_q;
      335            0 :    logic [1:0]                         lsu_axi_bresp_q, lsu_axi_rresp_q;
      336            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_imprecise_error_store_tag;
-     337        28837 :    logic [63:0]                        lsu_axi_rdata_q;
+     337        28759 :    logic [63:0]                        lsu_axi_rdata_q;
      338              : 
      339              :    //------------------------------------------------------------------------------
      340              :    // Load forwarding logic start
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344     74791394 :    function automatic logic [2:0] f_Enc8to3;
+     344     74381999 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348     74791394 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349     74791394 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350     74791394 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348     74381999 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349     74381999 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350     74381999 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352     74791394 :       return Enc_value[2:0];
+     352     74381999 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -663,20 +663,20 @@
      559              : 
      560              :       // Find first write pointer
      561          317 :       for (int i=0; i<DEPTH; i++) begin
-     562        88926 :          if (~found_wrptr0) begin
-     563        88618 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     564        88618 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     565        88618 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     562        89238 :          if (~found_wrptr0) begin
+     563        88930 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     564        88930 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     565        88930 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      566              :          end
      567              :       end
      568              : 
      569              :       // Find second write pointer
      570          317 :       for (int i=0; i<DEPTH; i++) begin
-     571       152937 :          if (~found_wrptr1) begin
-     572       152629 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     573       152629 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     574       152629 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
-     575       152629 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     571       153384 :          if (~found_wrptr1) begin
+     572       153076 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     573       153076 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     574       153076 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
+     575       153076 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      576              :          end
      577              :       end
      578              :    end
@@ -758,71 +758,71 @@
      654         1268 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656         1268 :          case (buf_state[i])
-     657     92666200 :             IDLE: begin
-     658     92666200 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659     92666200 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660     92666200 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661     92666200 :                      buf_wr_en[i]    = buf_state_en[i];
-     662     92666200 :                      buf_data_en[i]  = buf_state_en[i];
-     663     92666200 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664     92666200 :                      buf_cmd_state_bus_en[i]  = '0;
+     657     92157899 :             IDLE: begin
+     658     92157899 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659     92157899 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660     92157899 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661     92157899 :                      buf_wr_en[i]    = buf_state_en[i];
+     662     92157899 :                      buf_data_en[i]  = buf_state_en[i];
+     663     92157899 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664     92157899 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671      2423662 :             CMD: begin
-     672      2423662 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673      2423662 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674      2423662 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675      2423662 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676      2423662 :                      buf_ldfwd_in[i]          = 1'b1;
-     677      2423662 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678      2423662 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679      2423662 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680      2423662 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681      2423662 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671      2426349 :             CMD: begin
+     672      2426349 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673      2426349 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674      2426349 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675      2426349 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676      2426349 :                      buf_ldfwd_in[i]          = 1'b1;
+     677      2426349 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678      2426349 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679      2426349 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680      2426349 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681      2426349 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683      1460609 :             RESP: begin
-     684      1460609 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685      1460609 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686      1460609 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687      1460609 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688      1460609 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689      1460609 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690      1460609 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691      1460609 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692      1460609 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693      1460609 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694      1460609 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695      1460609 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683      1453089 :             RESP: begin
+     684      1453089 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685      1453089 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686      1453089 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687      1453089 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688      1453089 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689      1453089 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690      1453089 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691      1453089 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692      1453089 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693      1453089 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694      1453089 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695      1453089 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697      1460609 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698      1460609 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699      1460609 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700      1460609 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701      1460609 :                      buf_cmd_state_bus_en[i]  = '0;
+     697      1453089 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698      1453089 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699      1453089 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700      1453089 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701      1453089 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
-     703         8824 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
-     704         8824 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
-     705         8824 :                      buf_state_bus_en[i]       = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
-     706         8824 :                                                                  (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
-     707         8824 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     708         8824 :                      buf_cmd_state_bus_en[i]  = '0;
+     703         8826 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
+     704         8826 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
+     705         8826 :                      buf_state_bus_en[i]       = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
+     706         8826 :                                                                  (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
+     707         8826 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     708         8826 :                      buf_cmd_state_bus_en[i]  = '0;
      709              :             end
-     710        12005 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
-     711        12005 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
-     712        12005 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
-     713        12005 :                       buf_cmd_state_bus_en[i]  = '0;
+     710        12025 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
+     711        12025 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
+     712        12025 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
+     713        12025 :                       buf_cmd_state_bus_en[i]  = '0;
      714              :             end
-     715       481828 :             DONE: begin
-     716       481828 :                      buf_nxtstate[i]           = IDLE;
-     717       481828 :                      buf_rst[i]                = 1'b1;
-     718       481828 :                      buf_state_en[i]           = 1'b1;
-     719       481828 :                      buf_ldfwd_in[i]           = 1'b0;
-     720       481828 :                      buf_ldfwd_en[i]           = buf_state_en[i];
-     721       481828 :                      buf_cmd_state_bus_en[i]  = '0;
+     715       481272 :             DONE: begin
+     716       481272 :                      buf_nxtstate[i]           = IDLE;
+     717       481272 :                      buf_rst[i]                = 1'b1;
+     718       481272 :                      buf_state_en[i]           = 1'b1;
+     719       481272 :                      buf_ldfwd_in[i]           = 1'b0;
+     720       481272 :                      buf_ldfwd_en[i]           = buf_state_en[i];
+     721       481272 :                      buf_cmd_state_bus_en[i]  = '0;
      722              :             end
      723            0 :             default : begin
      724            0 :                      buf_nxtstate[i]          = IDLE;
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_bus_intf.sv.html
index 687d6ba4062..630eaa31ca4 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30     61843746 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30     61251245 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32          316 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -140,71 +140,71 @@
       36          301 :    input logic                          dec_tlu_sideeffect_posted_disable,  // disable the posted sideeffect load store to the bus
       37              : 
       38              :    // various clocks needed for the bus reads and writes
-      39      2035983 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
-      40      1088274 :    input logic                          lsu_busm_clken,                     // bus clock enable
+      39      2018773 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
+      40      1078918 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42     61843746 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43     61843746 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44     61843746 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42     61251245 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43     61251245 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44     61251245 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46     61843746 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47     61843746 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48     61843746 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46     61251245 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47     61251245 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48     61251245 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
-      51      2276073 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
-      52      1669696 :    input logic                          lsu_busreq_m,                      // bus request is in m
+      51      2264531 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
+      52      1658116 :    input logic                          lsu_busreq_m,                      // bus request is in m
       53              : 
-      54       478184 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
-      55       478181 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
+      54       475592 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
+      55       475589 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
       56              : 
-      57       350819 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
-      58       347000 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
+      57       349081 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
+      58       345262 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
       59              : 
-      60       351009 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
-      61       347184 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
+      60       349271 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
+      61       345446 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
       62              : 
-      63        54816 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
+      63        54774 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
       64            0 :    input logic                          dec_tlu_force_halt,
       65              : 
-      66      2279496 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
+      66      2267916 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
       67        29240 :    input logic                          is_sideeffects_m,                  // lsu attribute is side_effects
-      68        58638 :    input logic                          flush_m_up,                        // flush
+      68        58568 :    input logic                          flush_m_up,                        // flush
       69        29654 :    input logic                          flush_r,                           // flush
-      70        36568 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
+      70        36562 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71              : 
-      72      1659482 :    output logic                         lsu_busreq_r,                      // bus request is in r
-      73       808157 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      74        49046 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
-      75      1187701 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
+      72      1647902 :    output logic                         lsu_busreq_r,                      // bus request is in r
+      73       802237 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      74        48984 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
+      75      1177737 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
       76          200 :    output logic [31:0]                  bus_read_data_m,                   // the bus return data
       77              : 
       78              : 
       79            0 :    output logic                         lsu_imprecise_error_load_any,      // imprecise load bus error
       80            0 :    output logic                         lsu_imprecise_error_store_any,     // imprecise store bus error
-      81          401 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
+      81          400 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
       82              : 
       83              :    // Non-blocking loads
-      84       881640 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
-      85       504869 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
+      84       875716 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
+      85       502857 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
       86            0 :    output logic                               lsu_nonblock_load_inv_r,     // invalidate signal for the cam entry for non block loads
-      87       504866 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
-      88       920896 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
+      87       502854 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
+      88       914818 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
       89            0 :    output logic                               lsu_nonblock_load_data_error,// non block load has an error
-      90        36662 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
-      91        71560 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
+      90        36598 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
+      91        71538 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
       92              : 
       93              :    // PMU events
-      94      1667379 :    output logic                         lsu_pmu_bus_trxn,
-      95        36420 :    output logic                         lsu_pmu_bus_misaligned,
+      94      1655267 :    output logic                         lsu_pmu_bus_trxn,
+      95        36414 :    output logic                         lsu_pmu_bus_misaligned,
       96            0 :    output logic                         lsu_pmu_bus_error,
-      97        67818 :    output logic                         lsu_pmu_bus_busy,
+      97        67790 :    output logic                         lsu_pmu_bus_busy,
       98              : 
       99              :    // AXI Write Channels
-     100       855209 :    output logic                        lsu_axi_awvalid,
-     101      1107817 :    input  logic                        lsu_axi_awready,
+     100       849023 :    output logic                        lsu_axi_awvalid,
+     101      1095685 :    input  logic                        lsu_axi_awready,
      102            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_awid,
-     103          401 :    output logic [31:0]                 lsu_axi_awaddr,
+     103          400 :    output logic [31:0]                 lsu_axi_awaddr,
      104          314 :    output logic [3:0]                  lsu_axi_awregion,
      105            0 :    output logic [7:0]                  lsu_axi_awlen,
      106            0 :    output logic [2:0]                  lsu_axi_awsize,
@@ -214,22 +214,22 @@
      110            0 :    output logic [2:0]                  lsu_axi_awprot,
      111            0 :    output logic [3:0]                  lsu_axi_awqos,
      112              : 
-     113       855209 :    output logic                        lsu_axi_wvalid,
-     114      1107817 :    input  logic                        lsu_axi_wready,
-     115        31411 :    output logic [63:0]                 lsu_axi_wdata,
-     116       224989 :    output logic [7:0]                  lsu_axi_wstrb,
+     113       849023 :    output logic                        lsu_axi_wvalid,
+     114      1095685 :    input  logic                        lsu_axi_wready,
+     115        31367 :    output logic [63:0]                 lsu_axi_wdata,
+     116       224179 :    output logic [7:0]                  lsu_axi_wstrb,
      117          317 :    output logic                        lsu_axi_wlast,
      118              : 
-     119       868520 :    input  logic                        lsu_axi_bvalid,
+     119       862312 :    input  logic                        lsu_axi_bvalid,
      120          317 :    output logic                        lsu_axi_bready,
      121            0 :    input  logic [1:0]                  lsu_axi_bresp,
      122            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_bid,
      123              : 
      124              :    // AXI Read Channels
-     125       868958 :    output logic                        lsu_axi_arvalid,
-     126      1115481 :    input  logic                        lsu_axi_arready,
+     125       863034 :    output logic                        lsu_axi_arvalid,
+     126      1103367 :    input  logic                        lsu_axi_arready,
      127            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_arid,
-     128          401 :    output logic [31:0]                 lsu_axi_araddr,
+     128          400 :    output logic [31:0]                 lsu_axi_araddr,
      129          314 :    output logic [3:0]                  lsu_axi_arregion,
      130            0 :    output logic [7:0]                  lsu_axi_arlen,
      131            0 :    output logic [2:0]                  lsu_axi_arsize,
@@ -239,10 +239,10 @@
      135            0 :    output logic [2:0]                  lsu_axi_arprot,
      136            0 :    output logic [3:0]                  lsu_axi_arqos,
      137              : 
-     138       929722 :    input  logic                        lsu_axi_rvalid,
+     138       923642 :    input  logic                        lsu_axi_rvalid,
      139          317 :    output logic                        lsu_axi_rready,
      140            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_rid,
-     141        28838 :    input  logic [63:0]                 lsu_axi_rdata,
+     141        28760 :    input  logic [63:0]                 lsu_axi_rdata,
      142            0 :    input  logic [1:0]                  lsu_axi_rresp,
      143              : 
      144          316 :    input logic                         lsu_bus_clk_en
@@ -256,16 +256,16 @@
      152         8172 :    logic [3:0]        ldst_byteen_m, ldst_byteen_r;
      153            0 :    logic [7:0]        ldst_byteen_ext_m, ldst_byteen_ext_r;
      154            0 :    logic [3:0]        ldst_byteen_hi_m, ldst_byteen_hi_r;
-     155       431586 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
+     155       427958 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
      156        29230 :    logic              is_sideeffects_r;
      157              : 
-     158       125038 :    logic [63:0]       store_data_ext_r;
+     158       124906 :    logic [63:0]       store_data_ext_r;
      159         1948 :    logic [31:0]       store_data_hi_r;
-     160        63402 :    logic [31:0]       store_data_lo_r;
+     160        63374 :    logic [31:0]       store_data_lo_r;
      161              : 
-     162      1701223 :    logic              addr_match_dw_lo_r_m;
-     163      1659527 :    logic              addr_match_word_lo_r_m;
-     164        98804 :    logic              no_word_merge_r, no_dword_merge_r;
+     162      1689181 :    logic              addr_match_dw_lo_r_m;
+     163      1647959 :    logic              addr_match_word_lo_r_m;
+     164        98168 :    logic              no_word_merge_r, no_dword_merge_r;
      165              : 
      166          654 :    logic              ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
      167            0 :    logic [3:0]        ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
@@ -282,7 +282,7 @@
      178           74 :    logic [63:0]       ld_fwddata_lo, ld_fwddata_hi;
      179          804 :    logic [63:0]       ld_fwddata_m;
      180              : 
-     181         5698 :    logic              ld_full_hit_hi_m, ld_full_hit_lo_m;
+     181         5697 :    logic              ld_full_hit_hi_m, ld_full_hit_lo_m;
      182        10332 :    logic              ld_full_hit_m;
      183              : 
      184              :    assign ldst_byteen_m[3:0] = ({4{lsu_pkt_m.by}}   & 4'b0001) |
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_clkdomain.sv.html
index f67099fe17e..3e2051e072e 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31     61843746 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32     61843746 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31     61251245 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32     61251245 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33          316 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -144,52 +144,52 @@
       40              : 
       41       258446 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
       42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
-      43      1659482 :    input logic      lsu_busreq_r,                      // busreq in r
-      44       808157 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      45      1187701 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
+      43      1647902 :    input logic      lsu_busreq_r,                      // busreq in r
+      44       802237 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      45      1177737 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
       46       258763 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
       47              : 
       48          316 :    input logic      lsu_bus_clk_en,                    // bus clock enable
       49              : 
-      50       623945 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
-      51       478232 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
-      52       478184 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
-      53       478181 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
+      50       621353 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
+      51       475640 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
+      52       475592 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
+      53       475589 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
       54              : 
       55              :    // Outputs
-      56      2035983 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
-      57      1088274 :    output logic     lsu_busm_clken,                    // bus clock enable
+      56      2018773 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
+      57      1078918 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59     61843746 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60     61843746 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59     61251245 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60     61251245 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62     61843746 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63     61843746 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62     61251245 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63     61251245 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65     61843746 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66     61843746 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65     61251245 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66     61251245 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68     61843746 :    output logic     lsu_stbuf_c1_clk,
+      68     61251245 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70     61843746 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71     61843746 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70     61251245 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71     61251245 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74     61843746 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74     61251245 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
       78              : 
-      79      2279570 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
-      80      2034186 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
-      81      2279556 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
-      82      1065040 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
+      79      2267990 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
+      80      2022618 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
+      81      2267976 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
+      82      1059348 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
       83              : 
       84              : 
       85       200944 :    logic lsu_stbuf_c1_clken;
-      86      1088274 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
+      86      1078918 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
       87              : 
-      88       856312 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
+      88       847464 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
       89              : 
       90              :    //-------------------------------------------------------------------------------------------
       91              :    // Clock Enable logic
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_dccm_ctl.sv.html
index 3a516c68d49..90e616c20b4 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,37 +136,37 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35     61843746 :    input logic                             lsu_c2_m_clk,            // clocks
-      36     61843746 :    input logic                             lsu_c2_r_clk,            // clocks
-      37     61843746 :    input logic                             lsu_c1_r_clk,            // clocks
-      38     61843746 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39     61843746 :    input logic                             lsu_free_c2_clk,         // clocks
+      35     61251245 :    input logic                             lsu_c2_m_clk,            // clocks
+      36     61251245 :    input logic                             lsu_c2_r_clk,            // clocks
+      37     61251245 :    input logic                             lsu_c1_r_clk,            // clocks
+      38     61251245 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39     61251245 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41     61843746 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41     61251245 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43          316 :    input logic                             rst_l,                   // reset, active low
       44              : 
-      45       478181 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
-      46       478184 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
-      47       478232 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
+      45       475589 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
+      46       475592 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
+      47       475640 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
       48       614420 :    input logic                             addr_in_dccm_d,          // address maps to dccm
       49            0 :    input logic                             addr_in_pic_d,           // address maps to pic
       50            0 :    input logic                             addr_in_pic_m,           // address maps to pic
       51       614420 :    input logic                             addr_in_dccm_m, addr_in_dccm_r,   // address in dccm per pipe stage
       52            0 :    input logic                             addr_in_pic_r,                    // address in pic  per pipe stage
       53        18768 :    input logic                             lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
-      54      2279496 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
-      55        36568 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
+      54      2267916 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
+      55        36562 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
       56              : 
       57              :    // lsu address down the pipe
-      58       594111 :    input logic [31:0]                      lsu_addr_d,
-      59       471774 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
-      60       594109 :    input logic [31:0]                      lsu_addr_r,
+      58       592373 :    input logic [31:0]                      lsu_addr_d,
+      59       470108 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
+      60       592371 :    input logic [31:0]                      lsu_addr_r,
       61              : 
       62              :    // lsu address down the pipe - needed to check unaligned
-      63       678187 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
-      64       678348 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
-      65       678346 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
+      63       676449 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
+      64       676610 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
+      65       676608 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
       66              : 
       67              : 
       68       258446 :    input logic                             stbuf_reqvld_any,        // write enable
@@ -206,7 +206,7 @@
      102        47172 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_hi_m,           // corrected dccm data
      103        47172 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_lo_m,           // corrected dccm data
      104              : 
-     105        81386 :    input logic [31:0]                      store_data_m,            // Store data M-stage
+     105        81344 :    input logic [31:0]                      store_data_m,            // Store data M-stage
      106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
      107            0 :    input logic                             dma_pic_wen,             // Perform PIC writes
      108           12 :    input logic [2:0]                       dma_mem_tag_m,           // DMA Buffer entry number M-stage
@@ -218,10 +218,10 @@
      114        50849 :    input logic [pt.DCCM_ECC_WIDTH-1:0]     dma_dccm_wdata_ecc_lo,   // ECC bits for the DMA wdata
      115              : 
      116         1716 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_hi_r,
-     117        92644 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
+     117        92616 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
      118         1920 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
-     119        92644 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
-     120        56474 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
+     119        92616 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
+     120        56432 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
      121            4 :    output logic                            ld_single_ecc_error_r,
      122            4 :    output logic                            ld_single_ecc_error_r_ff,
      123              : 
@@ -240,8 +240,8 @@
      136       561000 :    output logic                            dccm_rden,               // dccm interface -- write
      137        18811 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo,         // dccm interface -- wr addr for lo bank
      138        18811 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi,         // dccm interface -- wr addr for hi bank
-     139       471780 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
-     140       678187 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
+     139       470114 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
+     140       676449 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
      141         5374 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,         // dccm write data for lo bank
      142         5374 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,         // dccm write data for hi bank
      143              : 
@@ -252,9 +252,9 @@
      148            0 :    output logic                            picm_wren,               // write to pic
      149            0 :    output logic                            picm_rden,               // read to pick
      150            0 :    output logic                            picm_mken,               // write to pic need a mask
-     151          430 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
-     152          430 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
-     153        92644 :    output logic [31:0]                     picm_wr_data,            // write data
+     151          429 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
+     152          429 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
+     153        92616 :    output logic [31:0]                     picm_wr_data,            // write data
      154            0 :    input logic [31:0]                      picm_rd_data,            // read data
      155              : 
      156            0 :    input logic                             scan_mode                // scan mode
@@ -277,7 +277,7 @@
      173            0 :    logic                           kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
      174              : 
      175              :     // byte_en flowing down
-     176       648834 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
+     176       647596 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
      177            0 :    logic [7:0]                     store_byteen_ext_m, store_byteen_ext_r;
      178              : 
      179              :    if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_dccm_mem.sv.html
index 4a63fa3b9b6..eb6a7d815e3 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35     61847773 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36     61847773 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35     61255272 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36     61255272 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37          317 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
@@ -145,8 +145,8 @@
       41       562000 :    input logic         dccm_rden,                                       // read enable
       42        18924 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,                     // write address
       43        18924 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,                     // write address
-      44       471893 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
-      45       678300 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
+      44       470227 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
+      45       676562 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
       46         5613 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,              // write data
       47         5613 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,              // write data
       48              :    el2_mem_if.veer_dccm                   dccm_mem_export,              // RAM repositioned in testbench and connected by this interface
@@ -164,7 +164,7 @@
       60              : 
       61        59820 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        wren_bank;
       62       143252 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        rden_bank;
-      63       689342 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
+      63       687604 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
       64            0 :    logic [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+DCCM_WIDTH_BITS)]           rd_addr_even, rd_addr_odd;
       65            0 :    logic                                                                rd_unaligned, wr_unaligned;
       66         1846 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0]              dccm_bank_dout;
@@ -172,8 +172,8 @@
       68              : 
       69         5613 :    logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0]               wr_data_bank;
       70              : 
-      71      1201391 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
-      72      1201485 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
+      71      1197115 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
+      72      1197207 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
       73              : 
       74       190014 :    logic [pt.DCCM_NUM_BANKS-1:0]            dccm_clken;
       75              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_ecc.sv.html
index 8d9ee5bd4f7..da0be09647a 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,22 +135,22 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34     61843746 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35     61843746 :    input logic                           lsu_c2_r_clk,       // clock
+      34     61251245 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35     61251245 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37          316 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
       39              : 
-      40       478184 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
-      41       478181 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
+      40       475592 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
+      41       475589 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
       42         7574 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  stbuf_data_any,
       43              : 
       44            8 :    input logic                           dec_tlu_core_ecc_disable,  // disables the ecc computation and error flagging
       45              : 
       46       561000 :    input logic                           lsu_dccm_rden_r,          // dccm rden
       47       614420 :    input logic                           addr_in_dccm_r,           // address in dccm
-      48       471772 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
-      49       678346 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
+      48       470106 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
+      49       676608 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
       50            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r,          // data from the dccm
       51            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r,          // data from the dccm
       52            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_r,       // data from the dccm + ecc
@@ -164,8 +164,8 @@
       60            4 :    input logic                           ld_single_ecc_error_r_ff,  // ld has a single ecc error
       61       561000 :    input logic                           lsu_dccm_rden_m,           // dccm rden
       62       614420 :    input logic                           addr_in_dccm_m,            // address in dccm
-      63       471774 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
-      64       678348 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
+      63       470108 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
+      64       676610 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
       65        47172 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m,           // raw data from mem
       66        47172 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m,           // raw data from mem
       67       154095 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_m,        // ecc read out from mem
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_lsc_ctl.sv.html
index b77f0ad23b7..162ff6edb95 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,14 +136,14 @@
       32              :  )(
       33          316 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35     61843746 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35     61251245 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38     61843746 :    input logic                lsu_c1_m_clk,
-      39     61843746 :    input logic                lsu_c1_r_clk,
-      40     61843746 :    input logic                lsu_c2_m_clk,
-      41     61843746 :    input logic                lsu_c2_r_clk,
-      42     61843746 :    input logic                lsu_store_c1_m_clk,
+      38     61251245 :    input logic                lsu_c1_m_clk,
+      39     61251245 :    input logic                lsu_c1_r_clk,
+      40     61251245 :    input logic                lsu_c2_m_clk,
+      41     61251245 :    input logic                lsu_c2_r_clk,
+      42     61251245 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45        24694 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
@@ -154,38 +154,38 @@
       50            4 :    input logic                lsu_single_ecc_error_m,    // ECC single bit error M-stage
       51            4 :    input logic                lsu_double_ecc_error_m,    // ECC double bit error M-stage
       52              : 
-      53        58638 :    input logic                flush_m_up,                // Flush M and D stage
+      53        58568 :    input logic                flush_m_up,                // Flush M and D stage
       54        29654 :    input logic                flush_r,                   // Flush R-stage
-      55        36568 :    input logic                ldst_dual_d,               // load/store is unaligned at 32 bit boundary D-stage
-      56        36568 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
-      57        36568 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
+      55        36562 :    input logic                ldst_dual_d,               // load/store is unaligned at 32 bit boundary D-stage
+      56        36562 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
+      57        36562 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
       58              : 
-      59       413833 :    input logic [31:0]         exu_lsu_rs1_d,             // address
-      60        81386 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
+      59       411891 :    input logic [31:0]         exu_lsu_rs1_d,             // address
+      60        81344 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
       61              : 
-      62       623945 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
-      63      2276073 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
-      64       270518 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
+      62       621353 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
+      63      2264531 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
+      64       269944 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
       65              : 
       66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
       67          200 :    input  logic [31:0]        bus_read_data_m,           // the bus return data
       68        38395 :    output logic [31:0]        lsu_result_m,              // lsu load data
       69        29134 :    output logic [31:0]        lsu_result_corr_r,         // This is the ECC corrected data going to RF
       70              :    // lsu address down the pipe
-      71       594111 :    output logic [31:0]        lsu_addr_d,
-      72       594110 :    output logic [31:0]        lsu_addr_m,
-      73       594109 :    output logic [31:0]        lsu_addr_r,
+      71       592373 :    output logic [31:0]        lsu_addr_d,
+      72       592372 :    output logic [31:0]        lsu_addr_m,
+      73       592371 :    output logic [31:0]        lsu_addr_r,
       74              :    // lsu address down the pipe - needed to check unaligned
-      75       594149 :    output logic [31:0]        end_addr_d,
-      76       594510 :    output logic [31:0]        end_addr_m,
-      77       594509 :    output logic [31:0]        end_addr_r,
+      75       592411 :    output logic [31:0]        end_addr_d,
+      76       592772 :    output logic [31:0]        end_addr_m,
+      77       592771 :    output logic [31:0]        end_addr_r,
       78              :    // store data down the pipe
-      79        81386 :    output logic [31:0]        store_data_m,
+      79        81344 :    output logic [31:0]        store_data_m,
       80              : 
       81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
       82           60 :    output logic                lsu_exc_m,                // Access or misaligned fault
       83        29240 :    output logic                is_sideeffects_m,         // is sideffects space
-      84      2279496 :    output logic                lsu_commit_r,             // lsu instruction in r commits
+      84      2267916 :    output logic                lsu_commit_r,             // lsu instruction in r commits
       85            4 :    output logic                lsu_single_ecc_error_incr,// LSU inc SB error counter
       86            4 :    output el2_lsu_error_pkt_t lsu_error_pkt_r,          // lsu exception packet
       87              : 
@@ -211,25 +211,25 @@
      107           12 :    input logic [63:0]         dma_mem_wdata,
      108              : 
      109              :    // Store buffer related signals
-     110       478232 :    output el2_lsu_pkt_t      lsu_pkt_d,
-     111       478184 :    output el2_lsu_pkt_t      lsu_pkt_m,
-     112       478181 :    output el2_lsu_pkt_t      lsu_pkt_r,
+     110       475640 :    output el2_lsu_pkt_t      lsu_pkt_d,
+     111       475592 :    output el2_lsu_pkt_t      lsu_pkt_m,
+     112       475589 :    output el2_lsu_pkt_t      lsu_pkt_r,
      113              : 
-     114       167732 :     input logic lsu_pmp_error_start,
-     115       167732 :     input logic lsu_pmp_error_end,
+     114       162421 :     input logic lsu_pmp_error_start,
+     115       162421 :     input logic lsu_pmp_error_end,
      116              : 
      117            0 :    input  logic               scan_mode                  // Scan mode
      118              : 
      119              :    );
      120              : 
-     121           13 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
-     122       594111 :    logic [31:0]        full_addr_d;
-     123       594149 :    logic [31:0]        full_end_addr_d;
-     124       476238 :    logic [31:0]        lsu_rs1_d;
-     125       270136 :    logic [11:0]        lsu_offset_d;
-     126       476238 :    logic [31:0]        rs1_d;
-     127       270136 :    logic [11:0]        offset_d;
-     128       283348 :    logic [12:0]        end_addr_offset_d;
+     121           12 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
+     122       592373 :    logic [31:0]        full_addr_d;
+     123       592411 :    logic [31:0]        full_end_addr_d;
+     124       474296 :    logic [31:0]        lsu_rs1_d;
+     125       269562 :    logic [11:0]        lsu_offset_d;
+     126       474296 :    logic [31:0]        rs1_d;
+     127       269562 :    logic [11:0]        offset_d;
+     128       282774 :    logic [12:0]        end_addr_offset_d;
      129            0 :    logic [2:0]         addr_offset_d;
      130              : 
      131           12 :    logic [63:0]        dma_mem_wdata_shifted;
@@ -242,12 +242,12 @@
      138            0 :    logic               fir_dccm_access_error_m, fir_nondccm_access_error_m;
      139              : 
      140            0 :    logic [3:0]         exc_mscause_d, exc_mscause_m;
-     141       476238 :    logic [31:0]        rs1_d_raw;
-     142        81386 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
+     141       474296 :    logic [31:0]        rs1_d_raw;
+     142        81344 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
      143          198 :    logic [31:0]        bus_read_data_r;
      144              : 
      145           18 :    el2_lsu_pkt_t           dma_pkt_d;
-     146       478184 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
+     146       475592 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
      147            4 :    el2_lsu_error_pkt_t     lsu_error_pkt_m;
      148              : 
      149              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_stbuf.sv.html
index 2cab8ded0f2..b80902eec04 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,20 +137,20 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36     61843746 :    input logic                           clk,                         // core clock
+      36     61251245 :    input logic                           clk,                         // core clock
       37          316 :    input logic                           rst_l,                       // reset
       38              : 
-      39     61843746 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40     61843746 :    input logic                           lsu_free_c2_clk,             // free clk
+      39     61251245 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40     61251245 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43       258930 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
-      44      2279496 :    input logic                           lsu_commit_r,                // lsu commits
-      45      2276073 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
+      44      2267916 :    input logic                           lsu_commit_r,                // lsu commits
+      45      2264531 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
       46         1716 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_hi_r,             // merged data from the dccm for stores. This is used for fwding
-      47        92644 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
+      47        92616 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
       48         1920 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
-      49        92644 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
+      49        92616 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
       50              : 
       51              :    // Store Buffer output
       52       258446 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
@@ -163,22 +163,22 @@
       59       258763 :    output logic                          lsu_stbuf_empty_any,         // stbuf is empty
       60       258930 :    output logic                          ldst_stbuf_reqvld_r,         // needed for clocking
       61              : 
-      62       471780 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
-      63       594110 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
-      64       594109 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
+      62       470114 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
+      63       592372 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
+      64       592371 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
       65              : 
-      66       678187 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
-      67       594510 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
-      68       594509 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
+      66       676449 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
+      67       592772 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
+      68       592771 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
       69              : 
-      70        36568 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
+      70        36562 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71       614420 :    input logic                           addr_in_dccm_m,              // address is in dccm
       72       614420 :    input logic                           addr_in_dccm_r,              // address is in dccm
       73              : 
       74              :    // Forwarding signals
       75       614428 :    input logic                           lsu_cmpen_m,                 // needed for forwarding stbuf - load
-      76       478184 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
-      77       478181 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
+      76       475592 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
+      77       475589 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
       78              : 
       79         5218 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m,          // stbuf data
       80         4892 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m,          // stbuf data
@@ -206,13 +206,13 @@
      102        85454 :    logic [DEPTH-1:0]                     stbuf_wr_en;
      103            0 :    logic [DEPTH-1:0]                     stbuf_dma_kill_en;
      104        85454 :    logic [DEPTH-1:0]                     stbuf_reset;
-     105       655432 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
+     105       653694 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
      106        15488 :    logic [DEPTH-1:0][DATA_WIDTH-1:0]     stbuf_datain;
      107        73705 :    logic [DEPTH-1:0][BYTE_WIDTH-1:0]     stbuf_byteenin;
      108              : 
      109            0 :    logic [7:0]             store_byteen_ext_r;
      110            0 :    logic [BYTE_WIDTH-1:0]  store_byteen_hi_r;
-     111       697750 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
+     111       696402 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
      112              : 
      113       258730 :    logic                   WrPtrEn, RdPtrEn;
      114        85460 :    logic [DEPTH_LOG2-1:0]  WrPtr, RdPtr;
@@ -225,7 +225,7 @@
      121            0 :    logic [3:0]             stbuf_numvld_any, stbuf_specvld_any;
      122            0 :    logic [1:0]             stbuf_specvld_m, stbuf_specvld_r;
      123              : 
-     124       678188 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
+     124       676450 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
      125              : 
      126              :    // variables to detect matching from the store queue
      127         3558 :    logic [DEPTH-1:0]                 stbuf_match_hi, stbuf_match_lo;
@@ -241,7 +241,7 @@
      137          120 :    logic [BYTE_WIDTH-1:0]  ld_byte_hit_hi, ld_byte_rhit_hi;
      138              : 
      139            0 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_hi_r;
-     140       648029 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
+     140       644401 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
      141              :    // byte_en flowing down
      142            0 :    logic [7:0]             ldst_byteen_r;
      143            0 :    logic [7:0]             ldst_byteen_ext_r;
diff --git a/html/main/coverage_dashboard/all/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all/index_el2_lsu_trigger.sv.html
index 9dab017c592..705b38b3809 100644
--- a/html/main/coverage_dashboard/all/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,9 +132,9 @@
       28              : `include "el2_param.vh"
       29              :  )(
       30            1 :    input el2_trigger_pkt_t [3:0] trigger_pkt_any,            // trigger packet from dec
-      31       478185 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
-      32       596547 :    input logic [31:0]             lsu_addr_m,                 // address
-      33        83823 :    input logic [31:0]             store_data_m,               // store data
+      31       475593 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
+      32       594809 :    input logic [31:0]             lsu_addr_m,                 // address
+      33        83781 :    input logic [31:0]             store_data_m,               // store data
       34              : 
       35         2450 :    output logic [3:0]             lsu_trigger_match_m         // match result
       36              : );
diff --git a/html/main/coverage_dashboard/all/index_el2_mem.sv.html b/html/main/coverage_dashboard/all/index_el2_mem.sv.html
index 5a0515b4139..987d38ce7fc 100644
--- a/html/main/coverage_dashboard/all/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25     61843746 :    input logic         clk,
+      25     61251245 :    input logic         clk,
       26          316 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -137,8 +137,8 @@
       33       561000 :    input logic         dccm_rden,
       34        18811 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,
       35        18811 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,
-      36       471780 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
-      37       678187 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
+      36       470114 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
+      37       676449 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
       38         5374 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
       39         5374 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
       40              : 
@@ -147,16 +147,16 @@
       43        47172 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
       44              : 
       45              :    //ICCM ports
-      46       160248 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
+      46       160008 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
       47            8 :    input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
       48            8 :    input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
       49           74 :    input logic         iccm_wren,
-      50       133458 :    input logic         iccm_rden,
+      50       133416 :    input logic         iccm_rden,
       51            0 :    input logic [2:0]   iccm_wr_size,
       52           14 :    input logic [77:0]  iccm_wr_data,
       53              : 
-      54       136544 :    output logic [63:0] iccm_rd_data,
-      55       161276 :    output logic [77:0] iccm_rd_data_ecc,
+      54       136542 :    output logic [63:0] iccm_rd_data,
+      55       161274 :    output logic [77:0] iccm_rd_data_ecc,
       56              : 
       57              :    // Icache and Itag Ports
       58              : 
@@ -164,12 +164,12 @@
       60       255918 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
       61        10432 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
       62       680092 :    input  logic         ic_rd_en,
-      63      1739005 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-      64      5603285 :    input  logic         ic_sel_premux_data, // Premux data sel
+      63      1731051 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+      64      5573723 :    input  logic         ic_sel_premux_data, // Premux data sel
       65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
       66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
       67              : 
-      68       560657 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+      68       558675 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
       69            0 :    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
       70       231247 :    output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       71            0 :    input  logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -178,7 +178,7 @@
       74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
       75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
       76              : 
-      77      2137063 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      77      2129109 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
       79              : 
       80              : 
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92     61843746 :    logic active_clk;
+      92     61251245 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all/index_el2_mem_if.sv.html
index b0c13fa467f..a532f3e1aff 100644
--- a/html/main/coverage_dashboard/all/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,26 +130,26 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29    145092138 :   logic                                                               clk;
+      29    144272184 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
       33              :   // ICCM
-      34       786552 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
+      34       786492 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
       35           48 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_wren_bank;
-      36       479510 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
+      36       478790 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
       37              : 
       38          260 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_wr_data;
       39           12 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
-      40        66189 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_dout;
-      41       159453 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;
+      40        66183 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_dout;
+      41       159447 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;
       42              : 
       43              : 
       44              :   //////////////////////////////////////////
       45              :   // DCCM
       46       569098 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_clken;
       47       178988 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
-      48      2067548 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
+      48      2062334 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
       49        22958 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
       50       152547 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
       51         5381 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
diff --git a/html/main/coverage_dashboard/all/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all/index_el2_pic_ctrl.sv.html
index 5e04cd80cb3..fb7c03f9799 100644
--- a/html/main/coverage_dashboard/all/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,15 +131,15 @@
       27              :  )
       28              :                   (
       29              : 
-      30     61945511 :                      input  logic                   clk,                  // Core clock
-      31     61945511 :                      input  logic                   free_clk,             // free clock
+      30     61353010 :                      input  logic                   clk,                  // Core clock
+      31     61353010 :                      input  logic                   free_clk,             // free clock
       32          321 :                      input  logic                   rst_l,                // Reset for all flops
       33            2 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34          319 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
       35          100 :                      input  logic [pt.PIC_TOTAL_INT_PLUS1-1:0]   extintsrc_req,  // Interrupt requests
-      36          430 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
-      37          430 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
-      38        92644 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
+      36          429 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
+      37          429 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
+      38        92616 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
       39        30392 :                      input  logic                   picm_wren,            // Write enable to the register
       40         9300 :                      input  logic                   picm_rden,            // Read enable for the register
       41            0 :                      input  logic                   picm_mken,            // Read the Mask for the register
@@ -185,11 +185,11 @@
       81              : 
       82          520 : logic  raddr_config_pic_match ;
       83         4652 : logic  raddr_intenable_base_match;
-      84      2110169 : logic  raddr_intpriority_base_match;
+      84      2102497 : logic  raddr_intpriority_base_match;
       85        11742 : logic  raddr_config_gw_base_match ;
       86              : 
       87          524 : logic  waddr_config_pic_match ;
-      88      2110412 : logic  waddr_intpriority_base_match;
+      88      2102740 : logic  waddr_intpriority_base_match;
       89         4844 : logic  waddr_intenable_base_match;
       90        11913 : logic  waddr_config_gw_base_match ;
       91         2418 : logic  addr_clear_gw_base_match ;
@@ -228,15 +228,15 @@
      124            1 : logic                                        intpriord;
      125            4 : logic                                        config_reg_we ;
      126            0 : logic                                        config_reg_re ;
-     127       572297 : logic                                        config_reg_in ;
+     127       570219 : logic                                        config_reg_in ;
      128            0 : logic                                        prithresh_reg_write , prithresh_reg_read;
      129         3100 : logic                                        intpriority_reg_read ;
      130         3100 : logic                                        intenable_reg_read   ;
      131         3100 : logic                                        gw_config_reg_read   ;
      132         9300 : logic                                        picm_wren_ff , picm_rden_ff ;
-     133          430 : logic [31:0]                                 picm_raddr_ff;
-     134          430 : logic [31:0]                                 picm_waddr_ff;
-     135        92644 : logic [31:0]                                 picm_wr_data_ff;
+     133          429 : logic [31:0]                                 picm_raddr_ff;
+     134          429 : logic [31:0]                                 picm_waddr_ff;
+     135        92616 : logic [31:0]                                 picm_wr_data_ff;
      136          568 : logic [3:0]                                  mask;
      137            0 : logic                                        picm_mken_ff;
      138            0 : logic [ID_BITS-1:0]                          claimid_in ;
@@ -256,11 +256,11 @@
      152        12402 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155     61853086 :    logic                                     pic_raddr_c1_clk;
-     156     61874178 :    logic                                     pic_data_c1_clk;
-     157     61856186 :    logic                                     pic_pri_c1_clk;
-     158     61856186 :    logic                                     pic_int_c1_clk;
-     159     61856186 :    logic                                     gw_config_c1_clk;
+     155     61260585 :    logic                                     pic_raddr_c1_clk;
+     156     61281677 :    logic                                     pic_data_c1_clk;
+     157     61263685 :    logic                                     pic_pri_c1_clk;
+     158     61263685 :    logic                                     pic_int_c1_clk;
+     159     61263685 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497          322 :          intpriority_rd_out =  '0 ;
      498          322 :          gw_config_rd_out =  '0 ;
      499          322 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500    782350228 :               if (intenable_reg_re[i]) begin
+     500    778240884 :               if (intenable_reg_re[i]) begin
      501         9300 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503    782350228 :               if (intpriority_reg_re[i]) begin
+     503    778240884 :               if (intpriority_reg_re[i]) begin
      504         9300 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506    782350228 :               if (gw_config_reg_re[i]) begin
+     506    778240884 :               if (gw_config_reg_re[i]) begin
      507         9300 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -627,7 +627,7 @@
      523              : 
      524              : assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0] ;
      525              : 
-     526       479848 : logic [14:0] address;
+     526       478182 : logic [14:0] address;
      527              : 
      528              : assign address[14:0] = picm_raddr_ff[14:0];
      529              : 
@@ -663,10 +663,10 @@
      559              : 
      560              : module el2_configurable_gw (
      561      3127890 :                              input logic gw_clk,
-     562   1502440592 :                              input logic rawclk,
+     562   1493967734 :                              input logic rawclk,
      563        10063 :                              input logic clken,
      564         9960 :                              input logic rst_l,
-     565         3421 :                              input logic extintsrc_req ,
+     565         3423 :                              input logic extintsrc_req ,
      566          763 :                              input logic meigwctrl_polarity ,
      567          842 :                              input logic meigwctrl_type ,
      568         2498 :                              input logic meigwclr ,
diff --git a/html/main/coverage_dashboard/all/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all/index_el2_pmp.sv.html
index 1b5cedca4b4..2b5a751c10b 100644
--- a/html/main/coverage_dashboard/all/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,7 +127,7 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26     61851105 :     input logic clk,       // Top level clock
+      26     61258604 :     input logic clk,       // Top level clock
       27          316 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
@@ -136,20 +136,20 @@
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35          866 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36          960 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35          841 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36          931 :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
       39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
       40              :     input logic             [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],
       41              : 
-      42       594235 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
+      42       592497 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
       43          769 :     input  el2_pmp_type_pkt_t        pmp_chan_type[PMP_CHANNELS],
-      44       138112 :     output logic                     pmp_chan_err [PMP_CHANNELS]
+      44       132801 :     output logic                     pmp_chan_err [PMP_CHANNELS]
       45              : );
       46              : 
       47              :   logic [                33:0]                     csr_pmp_addr_i          [pt.PMP_ENTRIES];
-      48       789538 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
+      48       787800 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
       49              : 
       50              :   logic [                33:0]                     region_start_addr       [pt.PMP_ENTRIES];
       51              :   logic [33:PMP_GRANULARITY+2]                     region_addr_mask        [pt.PMP_ENTRIES];
@@ -161,7 +161,7 @@
       57          328 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60           75 :   logic any_region_enabled;
+      60           72 :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133   1298655216 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133   1291818336 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139   1298655216 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139   1291818336 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168          960 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169    475872372 :       if (!matched && match_all[r]) begin
-     170     39027540 :         access_fail = ~final_perm_check[r];
-     171     39027540 :         matched = 1'b1;
+     169    480095385 :       if (!matched && match_all[r]) begin
+     170     38495145 :         access_fail = ~final_perm_check[r];
+     171     38495145 :         matched = 1'b1;
      172              :       end
      173              :     end
      174          960 :     return access_fail;
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223          874 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223          849 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -348,12 +348,12 @@
      244        15360 :       always_comb begin
      245        15360 :         region_match_all[c][r] = 1'b0;
      246        15360 :         unique case (pmp_pmpcfg[r].mode)
-     247   1078080969 :           OFF:     region_match_all[c][r] = 1'b0;
+     247   1072588131 :           OFF:     region_match_all[c][r] = 1'b0;
      248        77241 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249     37419627 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250     49942851 :           TOR: begin
-     251     49942851 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252     49942851 :                                      region_match_lt[c][r];
+     250     49271673 :           TOR: begin
+     251     49271673 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252     49271673 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all/index_el2_veer.sv.html b/html/main/coverage_dashboard/all/index_el2_veer.sv.html
index 820537ac7a5..3ef85175d88 100644
--- a/html/main/coverage_dashboard/all/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,24 +130,24 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29     61843746 :    input logic                  clk,
+      29     61251245 :    input logic                  clk,
       30          316 :    input logic                  rst_l,
       31          316 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
-      33           17 :    input logic                  nmi_int,
+      33           15 :    input logic                  nmi_int,
       34            0 :    input logic [31:1]           nmi_vec,
       35          316 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37     61843746 :    output logic                 active_l2clk,
-      38     61843746 :    output logic                 free_l2clk,
+      37     61251245 :    output logic                 active_l2clk,
+      38     61251245 :    output logic                 free_l2clk,
       39              : 
-      40       579528 :    output logic [31:0] trace_rv_i_insn_ip,
+      40       575173 :    output logic [31:0] trace_rv_i_insn_ip,
       41          308 :    output logic [31:0] trace_rv_i_address_ip,
-      42      6162982 :    output logic   trace_rv_i_valid_ip,
-      43         5146 :    output logic   trace_rv_i_exception_ip,
+      42      6126446 :    output logic   trace_rv_i_valid_ip,
+      43         5114 :    output logic   trace_rv_i_exception_ip,
       44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
-      45           28 :    output logic   trace_rv_i_interrupt_ip,
-      46           54 :    output logic [31:0] trace_rv_i_tval_ip,
+      45           22 :    output logic   trace_rv_i_interrupt_ip,
+      46           52 :    output logic [31:0] trace_rv_i_tval_ip,
       47              : 
       48              : 
       49            0 :    output logic                 dccm_clk_override,
@@ -182,8 +182,8 @@
       78       561000 :    output logic                          dccm_rden,
       79        18811 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_lo,
       80        18811 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_hi,
-      81       471780 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
-      82       678187 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
+      81       470114 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
+      82       676449 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
       83         5374 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
       84         5374 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_hi,
       85              : 
@@ -191,16 +191,16 @@
       87        47172 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_hi,
       88              : 
       89              :    // ICCM ports
-      90       160248 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
+      90       160008 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
       91           74 :    output logic                  iccm_wren,
-      92       133458 :    output logic                  iccm_rden,
+      92       133416 :    output logic                  iccm_rden,
       93            0 :    output logic [2:0]            iccm_wr_size,
       94           14 :    output logic [77:0]           iccm_wr_data,
       95            8 :    output logic                  iccm_buf_correct_ecc,
       96            8 :    output logic                  iccm_correction_state,
       97              : 
-      98       136544 :    input  logic [63:0]          iccm_rd_data,
-      99       161276 :    input  logic [77:0]           iccm_rd_data_ecc,
+      98       136542 :    input  logic [63:0]          iccm_rd_data,
+      99       161274 :    input  logic [77:0]           iccm_rd_data_ecc,
      100              : 
      101              :    // ICache , ITAG  ports
      102          326 :    output logic [31:1]           ic_rw_addr,
@@ -208,16 +208,16 @@
      104        10432 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_wr_en,
      105       680092 :    output logic                  ic_rd_en,
      106              : 
-     107       560657 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     108      2137063 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     107       558675 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     108      2129109 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      109       231247 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      112              : 
      113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
      114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     115      1739005 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     116      5603285 :    output logic                      ic_sel_premux_data, // Select premux data
+     115      1731051 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     116      5573723 :    output logic                      ic_sel_premux_data, // Select premux data
      117              : 
      118              : 
      119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -233,10 +233,10 @@
      129              : 
      130              :    //-------------------------- LSU AXI signals--------------------------
      131              :    // AXI Write Channels
-     132       855209 :    output logic                            lsu_axi_awvalid,
+     132       849023 :    output logic                            lsu_axi_awvalid,
      133       661105 :    input  logic                            lsu_axi_awready,
      134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     135          401 :    output logic [31:0]                     lsu_axi_awaddr,
+     135          400 :    output logic [31:0]                     lsu_axi_awaddr,
      136          314 :    output logic [3:0]                      lsu_axi_awregion,
      137            0 :    output logic [7:0]                      lsu_axi_awlen,
      138            0 :    output logic [2:0]                      lsu_axi_awsize,
@@ -246,10 +246,10 @@
      142            0 :    output logic [2:0]                      lsu_axi_awprot,
      143            0 :    output logic [3:0]                      lsu_axi_awqos,
      144              : 
-     145       855209 :    output logic                            lsu_axi_wvalid,
+     145       849023 :    output logic                            lsu_axi_wvalid,
      146       661105 :    input  logic                            lsu_axi_wready,
-     147        31411 :    output logic [63:0]                     lsu_axi_wdata,
-     148       224989 :    output logic [7:0]                      lsu_axi_wstrb,
+     147        31367 :    output logic [63:0]                     lsu_axi_wdata,
+     148       224179 :    output logic [7:0]                      lsu_axi_wstrb,
      149          317 :    output logic                            lsu_axi_wlast,
      150              : 
      151       660866 :    input  logic                            lsu_axi_bvalid,
@@ -258,10 +258,10 @@
      154            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      155              : 
      156              :    // AXI Read Channels
-     157       868958 :    output logic                            lsu_axi_arvalid,
+     157       863034 :    output logic                            lsu_axi_arvalid,
      158       672873 :    input  logic                            lsu_axi_arready,
      159            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     160          401 :    output logic [31:0]                     lsu_axi_araddr,
+     160          400 :    output logic [31:0]                     lsu_axi_araddr,
      161          314 :    output logic [3:0]                      lsu_axi_arregion,
      162            0 :    output logic [7:0]                      lsu_axi_arlen,
      163            0 :    output logic [2:0]                      lsu_axi_arsize,
@@ -305,10 +305,10 @@
      201            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      202              : 
      203              :    // AXI Read Channels
-     204      5892901 :    output logic                            ifu_axi_arvalid,
+     204      5855944 :    output logic                            ifu_axi_arvalid,
      205      8909222 :    input  logic                            ifu_axi_arready,
-     206      3589406 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-     207      2454016 :    output logic [31:0]                     ifu_axi_araddr,
+     206      3563620 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     207      2443704 :    output logic [31:0]                     ifu_axi_araddr,
      208          320 :    output logic [3:0]                      ifu_axi_arregion,
      209            0 :    output logic [7:0]                      ifu_axi_arlen,
      210            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -419,24 +419,24 @@
      315            0 :    output logic                  hmastlock,
      316            0 :    output logic [3:0]            hprot,
      317            0 :    output logic [2:0]            hsize,
-     318      1447798 :    output logic [1:0]            htrans,
+     318      1410841 :    output logic [1:0]            htrans,
      319            0 :    output logic                  hwrite,
      320              : 
-     321       241201 :    input  logic [63:0]           hrdata,
+     321       237605 :    input  logic [63:0]           hrdata,
      322           18 :    input  logic                  hready,
      323            0 :    input  logic                  hresp,
      324              : 
      325              :    // LSU AHB Master
-     326          119 :    output logic [31:0]          lsu_haddr,
+     326          118 :    output logic [31:0]          lsu_haddr,
      327            0 :    output logic [2:0]           lsu_hburst,
      328            0 :    output logic                 lsu_hmastlock,
      329            0 :    output logic [3:0]           lsu_hprot,
      330            0 :    output logic [2:0]           lsu_hsize,
-     331       445830 :    output logic [1:0]           lsu_htrans,
-     332        89317 :    output logic                 lsu_hwrite,
-     333         5438 :    output logic [63:0]          lsu_hwdata,
+     331       433702 :    output logic [1:0]           lsu_htrans,
+     332        85333 :    output logic                 lsu_hwrite,
+     333         5269 :    output logic [63:0]          lsu_hwdata,
      334              : 
-     335         2338 :    input  logic [63:0]          lsu_hrdata,
+     335         2260 :    input  logic [63:0]          lsu_hrdata,
      336           18 :    input  logic                 lsu_hready,
      337            0 :    input  logic                 lsu_hresp,
      338              : 
@@ -488,20 +488,20 @@
      384            4 :    output logic                 dccm_ecc_double_error,
      385              : 
      386            0 :    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
-     387           18 :    input logic                   timer_int,
-     388           17 :    input logic                   soft_int,
+     387           14 :    input logic                   timer_int,
+     388           13 :    input logic                   soft_int,
      389            0 :    input logic                   scan_mode
      390              : );
      391              : 
      392              : 
      393              : 
      394              : 
-     395       192980 :    logic [63:0]                  hwdata_nc;
+     395       189510 :    logic [63:0]                  hwdata_nc;
      396              :    //----------------------------------------------------------------------
      397              :    //
      398              :    //----------------------------------------------------------------------
      399              : 
-     400      6190087 :    logic                         ifu_pmu_instr_aligned;
+     400      6153554 :    logic                         ifu_pmu_instr_aligned;
      401            0 :    logic                         ifu_ic_error_start;
      402            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
      403            8 :    logic                         ifu_iccm_rd_ecc_single_err;
@@ -509,55 +509,55 @@
      405            4 :    logic                         lsu_dccm_rd_ecc_single_err;
      406            4 :    logic                         lsu_dccm_rd_ecc_double_err;
      407              : 
-     408       446712 :    logic                         lsu_axi_awready_ahb;
-     409       446712 :    logic                         lsu_axi_wready_ahb;
-     410       207654 :    logic                         lsu_axi_bvalid_ahb;
+     408       434580 :    logic                         lsu_axi_awready_ahb;
+     409       434580 :    logic                         lsu_axi_wready_ahb;
+     410       201446 :    logic                         lsu_axi_bvalid_ahb;
      411            0 :    logic                         lsu_axi_bready_ahb;
      412            0 :    logic [1:0]                   lsu_axi_bresp_ahb;
      413            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
-     414       442608 :    logic                         lsu_axi_arready_ahb;
-     415       257146 :    logic                         lsu_axi_rvalid_ahb;
+     414       430494 :    logic                         lsu_axi_arready_ahb;
+     415       251066 :    logic                         lsu_axi_rvalid_ahb;
      416            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
-     417         2338 :    logic [63:0]                  lsu_axi_rdata_ahb;
+     417         2260 :    logic [63:0]                  lsu_axi_rdata_ahb;
      418            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
      419           18 :    logic                         lsu_axi_rlast_ahb;
      420              : 
-     421      1107817 :    logic                         lsu_axi_awready_int;
-     422      1107817 :    logic                         lsu_axi_wready_int;
-     423       868520 :    logic                         lsu_axi_bvalid_int;
+     421      1095685 :    logic                         lsu_axi_awready_int;
+     422      1095685 :    logic                         lsu_axi_wready_int;
+     423       862312 :    logic                         lsu_axi_bvalid_int;
      424          299 :    logic                         lsu_axi_bready_int;
      425            0 :    logic [1:0]                   lsu_axi_bresp_int;
      426            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
-     427      1115481 :    logic                         lsu_axi_arready_int;
-     428       929722 :    logic                         lsu_axi_rvalid_int;
+     427      1103367 :    logic                         lsu_axi_arready_int;
+     428       923642 :    logic                         lsu_axi_rvalid_int;
      429            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
-     430        28838 :    logic [63:0]                  lsu_axi_rdata_int;
+     430        28760 :    logic [63:0]                  lsu_axi_rdata_int;
      431            0 :    logic [1:0]                   lsu_axi_rresp_int;
      432       672602 :    logic                         lsu_axi_rlast_int;
      433              : 
-     434      1447810 :    logic                         ifu_axi_awready_ahb;
-     435      1447810 :    logic                         ifu_axi_wready_ahb;
+     434      1410852 :    logic                         ifu_axi_awready_ahb;
+     435      1410852 :    logic                         ifu_axi_wready_ahb;
      436            0 :    logic                         ifu_axi_bvalid_ahb;
      437            0 :    logic                         ifu_axi_bready_ahb;
      438            0 :    logic [1:0]                   ifu_axi_bresp_ahb;
-     439       285739 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
-     440      1447810 :    logic                         ifu_axi_arready_ahb;
-     441      2895588 :    logic                         ifu_axi_rvalid_ahb;
-     442       285739 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
-     443       241199 :    logic [63:0]                  ifu_axi_rdata_ahb;
+     439       277296 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
+     440      1410852 :    logic                         ifu_axi_arready_ahb;
+     441      2821673 :    logic                         ifu_axi_rvalid_ahb;
+     442       277296 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
+     443       237604 :    logic [63:0]                  ifu_axi_rdata_ahb;
      444            0 :    logic [1:0]                   ifu_axi_rresp_ahb;
      445           18 :    logic                         ifu_axi_rlast_ahb;
      446              : 
-     447      1447810 :    logic                         ifu_axi_awready_int;
-     448      1447810 :    logic                         ifu_axi_wready_int;
+     447      1410852 :    logic                         ifu_axi_awready_int;
+     448      1410852 :    logic                         ifu_axi_wready_int;
      449            0 :    logic                         ifu_axi_bvalid_int;
      450            0 :    logic                         ifu_axi_bready_int;
      451            0 :    logic [1:0]                   ifu_axi_bresp_int;
-     452       285739 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
-     453     10357032 :    logic                         ifu_axi_arready_int;
-     454     11804512 :    logic                         ifu_axi_rvalid_int;
-     455      1181687 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
-     456       985574 :    logic [63:0]                  ifu_axi_rdata_int;
+     452       277296 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
+     453     10320074 :    logic                         ifu_axi_arready_int;
+     454     11730597 :    logic                         ifu_axi_rvalid_int;
+     455      1173244 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
+     456       981979 :    logic [63:0]                  ifu_axi_rdata_int;
      457            0 :    logic [1:0]                   ifu_axi_rresp_int;
      458      8908942 :    logic                         ifu_axi_rlast_int;
      459              : 
@@ -636,13 +636,13 @@
      532            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
      533              : 
      534              : 
-     535      5130925 :    logic         dec_i0_rs1_en_d;
-     536      3565563 :    logic         dec_i0_rs2_en_d;
-     537       407880 :    logic  [31:0] gpr_i0_rs1_d;
-     538       598740 :    logic  [31:0] gpr_i0_rs2_d;
+     535      5100391 :    logic         dec_i0_rs1_en_d;
+     536      3549089 :    logic         dec_i0_rs2_en_d;
+     537       407844 :    logic  [31:0] gpr_i0_rs1_d;
+     538       598744 :    logic  [31:0] gpr_i0_rs2_d;
      539              : 
-     540       314049 :    logic [31:0] dec_i0_result_r;
-     541       614701 :    logic [31:0] exu_i0_result_x;
+     540       314035 :    logic [31:0] dec_i0_result_r;
+     541       613793 :    logic [31:0] exu_i0_result_x;
      542          308 :    logic [31:1] exu_i0_pc_x;
      543          313 :    logic [31:1] exu_npc_r;
      544              : 
@@ -653,38 +653,38 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552      2134567 :    logic [31:0] dec_i0_immed_d;
-     553       123446 :    logic [12:1] dec_i0_br_immed_d;
-     554       554879 :    logic         dec_i0_select_pc_d;
+     552      2132673 :    logic [31:0] dec_i0_immed_d;
+     553       122230 :    logic [12:1] dec_i0_br_immed_d;
+     554       553923 :    logic         dec_i0_select_pc_d;
      555              : 
      556         1288 :    logic [31:1] dec_i0_pc_d;
-     557        80872 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
-     558         8634 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
+     557        79850 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
+     558         8622 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
-     560      5393904 :    logic         dec_i0_alu_decode_d;
-     561      3841554 :    logic         dec_i0_branch_d;
+     560      5367615 :    logic         dec_i0_alu_decode_d;
+     561      3829589 :    logic         dec_i0_branch_d;
      562              : 
-     563      5892108 :    logic         ifu_miss_state_idle;
+     563      5855150 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
      565            0 :    logic         dec_tlu_flush_leak_one_r;
      566            8 :    logic         dec_tlu_flush_err_r;
-     567      6006883 :    logic         ifu_i0_valid;
-     568       468420 :    logic [31:0]  ifu_i0_instr;
+     567      5971582 :    logic         ifu_i0_valid;
+     568       467652 :    logic [31:0]  ifu_i0_instr;
      569         1288 :    logic [31:1]  ifu_i0_pc;
      570              : 
-     571       672565 :    logic        exu_flush_final;
+     571       671016 :    logic        exu_flush_final;
      572              : 
-     573       226946 :    logic [31:1] exu_flush_path_final;
+     573       226504 :    logic [31:1] exu_flush_path_final;
      574              : 
-     575       413833 :    logic [31:0] exu_lsu_rs1_d;
-     576        81386 :    logic [31:0] exu_lsu_rs2_d;
+     575       411891 :    logic [31:0] exu_lsu_rs1_d;
+     576        81344 :    logic [31:0] exu_lsu_rs2_d;
      577              : 
      578              : 
-     579       623945 :    el2_lsu_pkt_t    lsu_p;
-     580      5476447 :    logic             dec_qual_lsu_d;
+     579       621353 :    el2_lsu_pkt_t    lsu_p;
+     580      5449748 :    logic             dec_qual_lsu_d;
      581              : 
-     582      2276073 :    logic        dec_lsu_valid_raw_d;
-     583       270518 :    logic [11:0] dec_lsu_offset_d;
+     582      2264531 :    logic        dec_lsu_valid_raw_d;
+     583       269944 :    logic [11:0] dec_lsu_offset_d;
      584              : 
      585        38395 :    logic [31:0]  lsu_result_m;
      586        29134 :    logic [31:0]  lsu_result_corr_r;     // This is the ECC corrected data going to RF
@@ -692,73 +692,73 @@
      588            4 :    el2_lsu_error_pkt_t lsu_error_pkt_r;
      589            0 :    logic         lsu_imprecise_error_load_any;
      590            0 :    logic         lsu_imprecise_error_store_any;
-     591          401 :    logic [31:0]  lsu_imprecise_error_addr_any;
-     592        49050 :    logic         lsu_load_stall_any;       // This is for blocking loads
-     593        59374 :    logic         lsu_store_stall_any;      // This is for blocking stores
-     594      1346967 :    logic         lsu_idle_any;             // doesn't include DMA
-     595      1346650 :    logic         lsu_active;               // lsu is active. used for clock
+     591          400 :    logic [31:0]  lsu_imprecise_error_addr_any;
+     592        48988 :    logic         lsu_load_stall_any;       // This is for blocking loads
+     593        59312 :    logic         lsu_store_stall_any;      // This is for blocking stores
+     594      1337985 :    logic         lsu_idle_any;             // doesn't include DMA
+     595      1337668 :    logic         lsu_active;               // lsu is active. used for clock
      596              : 
      597              : 
      598        24694 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
      599            0 :    logic [1:0]   lsu_fir_error;       // Error during fast interrupt lookup
      600              : 
      601              :    // Non-blocking loads
-     602       881640 :    logic                                 lsu_nonblock_load_valid_m;
-     603       504869 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
+     602       875716 :    logic                                 lsu_nonblock_load_valid_m;
+     603       502857 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
      604            0 :    logic                                 lsu_nonblock_load_inv_r;
-     605       504866 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
-     606       920896 :    logic                                 lsu_nonblock_load_data_valid;
-     607        36662 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
-     608        71560 :    logic [31:0]                          lsu_nonblock_load_data;
+     605       502854 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
+     606       914818 :    logic                                 lsu_nonblock_load_data_valid;
+     607        36598 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
+     608        71538 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
-     610        75092 :    logic        dec_csr_ren_d;
-     611         6941 :    logic [31:0] dec_csr_rddata_d;
+     610        74910 :    logic        dec_csr_ren_d;
+     611         8136 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613         3978 :    logic [31:0] exu_csr_rs1_x;
      614              : 
-     615      6162256 :    logic        dec_tlu_i0_commit_cmt;
-     616        58638 :    logic        dec_tlu_flush_lower_r;
-     617        58638 :    logic        dec_tlu_flush_lower_wb;
+     615      6125722 :    logic        dec_tlu_i0_commit_cmt;
+     616        58568 :    logic        dec_tlu_flush_lower_r;
+     617        58568 :    logic        dec_tlu_flush_lower_wb;
      618        29654 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
      619        18866 :    logic        dec_tlu_fence_i_r;            // flush is a fence_i rfnpc, flush icache
      620              : 
-     621        24686 :    logic [31:1] dec_tlu_flush_path_r;
+     621        24680 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624      5735369 :    logic        ifu_i0_pc4;
+     624      5716269 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
-     628        78138 :    el2_div_pkt_t  div_p;
+     628        78122 :    el2_div_pkt_t  div_p;
      629         2628 :    logic           dec_div_cancel;
      630              : 
      631        24784 :    logic [31:0] exu_div_result;
-     632       156868 :    logic exu_div_wren;
+     632       156836 :    logic exu_div_wren;
      633              : 
-     634      6190087 :    logic dec_i0_decode_d;
+     634      6153554 :    logic dec_i0_decode_d;
      635              : 
      636              : 
-     637       138654 :    logic [31:1] pred_correct_npc_x;
+     637       137876 :    logic [31:1] pred_correct_npc_x;
      638              : 
-     639       782203 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
+     639       779462 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
      640              : 
-     641        34458 :    el2_predict_pkt_t  exu_mp_pkt;
-     642       299672 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643       378995 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
-     644       196032 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
+     641        34372 :    el2_predict_pkt_t  exu_mp_pkt;
+     642       298770 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
+     643       376379 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     644       195586 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645       115620 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647       367119 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648      2679213 :    logic [1:0]  exu_i0_br_hist_r;
+     647       364503 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648      2673781 :    logic [1:0]  exu_i0_br_hist_r;
      649        26468 :    logic        exu_i0_br_error_r;
      650         9608 :    logic        exu_i0_br_start_error_r;
-     651      2970681 :    logic        exu_i0_br_valid_r;
-     652       409754 :    logic        exu_i0_br_mp_r;
-     653      2381498 :    logic        exu_i0_br_middle_r;
+     651      2962465 :    logic        exu_i0_br_valid_r;
+     652       408472 :    logic        exu_i0_br_mp_r;
+     653      2370984 :    logic        exu_i0_br_middle_r;
      654              : 
-     655      2110900 :    logic        exu_i0_br_way_r;
+     655      2108159 :    logic        exu_i0_br_way_r;
      656              : 
-     657       187548 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
+     657       187344 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
      658              : 
      659            0 :    logic        dma_dccm_req;
      660           66 :    logic        dma_iccm_req;
@@ -779,8 +779,8 @@
      675              : 
      676            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
      677           26 :    logic        dma_iccm_stall_any;       // Stall the fetch
-     678      2225276 :    logic        dccm_ready;
-     679       636913 :    logic        iccm_ready;
+     678      2213734 :    logic        dccm_ready;
+     679       635362 :    logic        iccm_ready;
      680              : 
      681            0 :    logic        dma_pmu_dccm_read;
      682            0 :    logic        dma_pmu_dccm_write;
@@ -795,28 +795,28 @@
      691            2 :    logic        ifu_i0_dbecc;
      692            0 :    logic        iccm_dma_sb_error;
      693              : 
-     694       200759 :    el2_br_pkt_t i0_brp;
-     695       651076 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696       631672 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     694       200545 :    el2_br_pkt_t i0_brp;
+     695       650118 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
+     696       619214 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697        21217 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
      700            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
      701              : 
      702              : 
-     703       506364 :    el2_predict_pkt_t dec_i0_predict_p_d;
+     703       504423 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705       631672 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
-     706       651076 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
+     705       619214 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     706       650118 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707        21217 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
      709              :    // PIC ports
      710            0 :    logic                  picm_wren;
      711            0 :    logic                  picm_rden;
      712            0 :    logic                  picm_mken;
-     713          430 :    logic [31:0]           picm_rdaddr;
-     714          430 :    logic [31:0]           picm_wraddr;
-     715        92644 :    logic [31:0]           picm_wr_data;
+     713          429 :    logic [31:0]           picm_rdaddr;
+     714          429 :    logic [31:0]           picm_wraddr;
+     715        92616 :    logic [31:0]           picm_wr_data;
      716            0 :    logic [31:0]           picm_rd_data;
      717              : 
      718              :    // feature disable from mfdc
@@ -843,18 +843,18 @@
      739              :   // PMP Signals
      740            0 :   el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
      741              :   logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
-     742       594145 :   logic [31:0]            pmp_chan_addr [3];
+     742       592407 :   logic [31:0]            pmp_chan_addr [3];
      743            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
-     744       137878 :   logic                   pmp_chan_err  [3];
+     744       132567 :   logic                   pmp_chan_err  [3];
      745              : 
      746          310 :   logic [31:1] ifu_pmp_addr;
      747          110 :   logic        ifu_pmp_error;
-     748       594111 :   logic [31:0] lsu_pmp_addr_start;
-     749       167732 :   logic        lsu_pmp_error_start;
-     750       594149 :   logic [31:0] lsu_pmp_addr_end;
-     751       167732 :   logic        lsu_pmp_error_end;
-     752      1065445 :   logic        lsu_pmp_we;
-     753      1424320 :   logic        lsu_pmp_re;
+     748       592373 :   logic [31:0] lsu_pmp_addr_start;
+     749       162421 :   logic        lsu_pmp_error_start;
+     750       592411 :   logic [31:0] lsu_pmp_addr_end;
+     751       162421 :   logic        lsu_pmp_error_end;
+     752      1059753 :   logic        lsu_pmp_we;
+     753      1418396 :   logic        lsu_pmp_re;
      754              : 
      755              :    // -----------------------DEBUG  START -------------------------------
      756              : 
@@ -870,7 +870,7 @@
      766              : 
      767            0 :    logic                   core_dbg_cmd_done;         // Final muxed cmd done to debug
      768            0 :    logic                   core_dbg_cmd_fail;         // Final muxed cmd done to debug
-     769       314049 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
+     769       314035 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
      770              : 
      771            0 :    logic                   dma_dbg_cmd_done;          // Abstarct memory command sent to dma is done
      772            0 :    logic                   dma_dbg_cmd_fail;          // Abstarct memory command sent to dma failed
@@ -879,7 +879,7 @@
      775            0 :    logic                   dbg_dma_bubble;            // Debug needs a bubble to send a valid
      776            0 :    logic                   dma_dbg_ready;             // DMA is ready to accept debug request
      777              : 
-     778       314049 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
+     778       314035 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
      779            0 :    logic                   dec_dbg_cmd_done;          // This will be treated like a valid signal
      780            0 :    logic                   dec_dbg_cmd_fail;          // Abstract command failed
      781            0 :    logic                   dec_tlu_mpc_halted_only;   // Only halted due to MPC
@@ -889,43 +889,43 @@
      785            0 :    logic                   dec_debug_wdata_rs1_d;
      786            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
      787              : 
-     788      6189473 :    logic [1:0]             dec_data_en;
-     789      5991939 :    logic [1:0]             dec_ctl_en;
+     788      6152939 :    logic [1:0]             dec_data_en;
+     789      5955435 :    logic [1:0]             dec_ctl_en;
      790              : 
      791              :    // PMU Signals
-     792       409754 :    logic                   exu_pmu_i0_br_misp;
-     793      2868109 :    logic                   exu_pmu_i0_br_ataken;
-     794      3459682 :    logic                   exu_pmu_i0_pc4;
+     792       408472 :    logic                   exu_pmu_i0_br_misp;
+     793      2862323 :    logic                   exu_pmu_i0_br_ataken;
+     794      3452000 :    logic                   exu_pmu_i0_pc4;
      795              : 
-     796       891764 :    logic                   lsu_pmu_load_external_m;
-     797       806110 :    logic                   lsu_pmu_store_external_m;
-     798        48786 :    logic                   lsu_pmu_misaligned_m;
-     799      1667379 :    logic                   lsu_pmu_bus_trxn;
-     800        36420 :    logic                   lsu_pmu_bus_misaligned;
+     796       885840 :    logic                   lsu_pmu_load_external_m;
+     797       800418 :    logic                   lsu_pmu_store_external_m;
+     798        48780 :    logic                   lsu_pmu_misaligned_m;
+     799      1655267 :    logic                   lsu_pmu_bus_trxn;
+     800        36414 :    logic                   lsu_pmu_bus_misaligned;
      801            0 :    logic                   lsu_pmu_bus_error;
-     802        67818 :    logic                   lsu_pmu_bus_busy;
+     802        67790 :    logic                   lsu_pmu_bus_busy;
      803              : 
-     804       614530 :    logic                   ifu_pmu_fetch_stall;
-     805      5893104 :    logic                   ifu_pmu_ic_miss;
+     804       613228 :    logic                   ifu_pmu_fetch_stall;
+     805      5856146 :    logic                   ifu_pmu_ic_miss;
      806       744124 :    logic                   ifu_pmu_ic_hit;
      807            0 :    logic                   ifu_pmu_bus_error;
      808      4463637 :    logic                   ifu_pmu_bus_busy;
-     809     10356722 :    logic                   ifu_pmu_bus_trxn;
+     809     10319765 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811          317 :    logic                   active_state;
-     812     61843746 :    logic                   free_clk;
-     813     61843746 :    logic                   active_clk;
+     812     61251245 :    logic                   free_clk;
+     813     61251245 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
      817              : 
-     818      1427542 :    logic [15:0]            ifu_i0_cinst;
+     818      1422550 :    logic [15:0]            ifu_i0_cinst;
      819              : 
      820              : // fast interrupt
      821            0 :    logic [31:2]            dec_tlu_meihap;
      822            0 :    logic                   dec_extint_stall;
      823              : 
-     824      5519898 :    el2_trace_pkt_t  trace_rv_trace_pkt;
+     824      5496224 :    el2_trace_pkt_t  trace_rv_trace_pkt;
      825              : 
      826              : 
      827            4 :    logic                   lsu_fastint_stall_any;
@@ -941,7 +941,7 @@
      837            0 :    logic        pause_state;
      838            0 :    logic        halt_state;
      839              : 
-     840      2091300 :    logic        dec_tlu_core_empty;
+     840      2081032 :    logic        dec_tlu_core_empty;
      841              : 
      842              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
      843              : 
@@ -991,11 +991,11 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890          866 :    logic priv_mode;
+     890          841 :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892          960 :    logic priv_mode_eff;
+     892          931 :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894          866 :    logic priv_mode_ns;
+     894          841 :    logic priv_mode_ns;
      895              : 
      896            2 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
diff --git a/html/main/coverage_dashboard/all/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all/index_el2_veer_wrapper.sv.html
index 3006cfbb615..bb538dd2157 100644
--- a/html/main/coverage_dashboard/all/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,22 +131,22 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30     61843746 :    input logic                             clk,
+      30     61251245 :    input logic                             clk,
       31          316 :    input logic                             rst_l,
       32          316 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
-      34           17 :    input logic                             nmi_int,
+      34           15 :    input logic                             nmi_int,
       35            0 :    input logic [31:1]                      nmi_vec,
       36            0 :    input logic [31:1]                      jtag_id,
       37              : 
       38              : 
-      39       579528 :    output logic [31:0]                     trace_rv_i_insn_ip,
+      39       575173 :    output logic [31:0]                     trace_rv_i_insn_ip,
       40          308 :    output logic [31:0]                     trace_rv_i_address_ip,
-      41      6162982 :    output logic                            trace_rv_i_valid_ip,
-      42         5146 :    output logic                            trace_rv_i_exception_ip,
+      41      6126446 :    output logic                            trace_rv_i_valid_ip,
+      42         5114 :    output logic                            trace_rv_i_exception_ip,
       43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
-      44           28 :    output logic                            trace_rv_i_interrupt_ip,
-      45           54 :    output logic [31:0]                     trace_rv_i_tval_ip,
+      44           22 :    output logic                            trace_rv_i_interrupt_ip,
+      45           52 :    output logic [31:0]                     trace_rv_i_tval_ip,
       46              : 
       47              :    // Bus signals
       48              : `ifdef RV_BUILD_AXI4
@@ -339,24 +339,24 @@
      235            0 :    output logic                            hmastlock,
      236            0 :    output logic [3:0]                      hprot,
      237            0 :    output logic [2:0]                      hsize,
-     238      1447798 :    output logic [1:0]                      htrans,
+     238      1410841 :    output logic [1:0]                      htrans,
      239            0 :    output logic                            hwrite,
      240              : 
-     241       241201 :    input logic [63:0]                      hrdata,
+     241       237605 :    input logic [63:0]                      hrdata,
      242           18 :    input logic                             hready,
      243            0 :    input logic                             hresp,
      244              : 
      245              :    // LSU AHB Master
-     246          119 :    output logic [31:0]                     lsu_haddr,
+     246          118 :    output logic [31:0]                     lsu_haddr,
      247            0 :    output logic [2:0]                      lsu_hburst,
      248            0 :    output logic                            lsu_hmastlock,
      249            0 :    output logic [3:0]                      lsu_hprot,
      250            0 :    output logic [2:0]                      lsu_hsize,
-     251       445830 :    output logic [1:0]                      lsu_htrans,
-     252        89317 :    output logic                            lsu_hwrite,
-     253         5438 :    output logic [63:0]                     lsu_hwdata,
+     251       433702 :    output logic [1:0]                      lsu_htrans,
+     252        85333 :    output logic                            lsu_hwrite,
+     253         5269 :    output logic [63:0]                     lsu_hwdata,
      254              : 
-     255         2338 :    input logic [63:0]                      lsu_hrdata,
+     255         2260 :    input logic [63:0]                      lsu_hrdata,
      256           18 :    input logic                             lsu_hready,
      257            0 :    input logic                             lsu_hresp,
      258              :    // Debug Syster Bus AHB
@@ -406,8 +406,8 @@
      302            0 :    input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
      303            0 :    input                                   el2_ic_tag_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
      304              : 
-     305           18 :    input logic                             timer_int,
-     306           17 :    input logic                             soft_int,
+     305           14 :    input logic                             timer_int,
+     306           13 :    input logic                             soft_int,
      307            0 :    input logic [pt.PIC_TOTAL_INT:1]        extintsrc_req,
      308              : 
      309       340148 :    output logic                            dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
@@ -454,16 +454,16 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353     61843746 :    logic                             active_l2clk;
-     354     61843746 :    logic                             free_l2clk;
+     353     61251245 :    logic                             active_l2clk;
+     354     61251245 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357       262892 :    logic         dccm_wren;
      358       561000 :    logic         dccm_rden;
      359        18811 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo;
      360        18811 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi;
-     361       471780 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
-     362       678187 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
+     361       470114 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
+     362       676449 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
      363         5374 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
      364         5374 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi;
      365              : 
@@ -490,28 +490,28 @@
      386            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way;   // Debug way. Rd or Wr.
      387              : 
      388            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
-     389       560657 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
-     390      2137063 :    logic [63:0]  ic_rd_data;
+     389       558675 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
+     390      2129109 :    logic [63:0]  ic_rd_data;
      391       231247 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      392            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
      393              : 
      394            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
      395            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
      396              : 
-     397      1739005 :    logic [63:0]  ic_premux_data;
-     398      5603285 :    logic         ic_sel_premux_data;
+     397      1731051 :    logic [63:0]  ic_premux_data;
+     398      5573723 :    logic         ic_sel_premux_data;
      399              : 
      400              :    // ICCM ports
-     401       160248 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
+     401       160008 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
      402           74 :    logic           iccm_wren;
-     403       133458 :    logic           iccm_rden;
+     403       133416 :    logic           iccm_rden;
      404            0 :    logic [2:0]     iccm_wr_size;
      405           14 :    logic [77:0]    iccm_wr_data;
      406            8 :    logic           iccm_buf_correct_ecc;
      407            8 :    logic           iccm_correction_state;
      408              : 
-     409       136544 :    logic [63:0]    iccm_rd_data;
-     410       161276 :    logic [77:0]    iccm_rd_data_ecc;
+     409       136542 :    logic [63:0]    iccm_rd_data;
+     410       161274 :    logic [77:0]    iccm_rd_data_ecc;
      411              : 
      412          316 :    logic        core_rst_l;                         // Core reset including rst_l and dbg_rst_l
      413              : 
@@ -610,10 +610,10 @@
      506              : 
      507              : 
      508              : `ifdef RV_BUILD_AHB_LITE
-     509       203746 :    wire                            lsu_axi_awvalid;
+     509       197560 :    wire                            lsu_axi_awvalid;
      510            0 :    wire                            lsu_axi_awready;
      511            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid;
-     512          119 :    wire [31:0]                     lsu_axi_awaddr;
+     512          118 :    wire [31:0]                     lsu_axi_awaddr;
      513           17 :    wire [3:0]                      lsu_axi_awregion;
      514            0 :    wire [7:0]                      lsu_axi_awlen;
      515            0 :    wire [2:0]                      lsu_axi_awsize;
@@ -624,10 +624,10 @@
      520            0 :    wire [3:0]                      lsu_axi_awqos;
      521              : 
      522              : 
-     523       203746 :    wire                            lsu_axi_wvalid;
+     523       197560 :    wire                            lsu_axi_wvalid;
      524            0 :    wire                            lsu_axi_wready;
-     525         1650 :    wire [63:0]                     lsu_axi_wdata;
-     526        39284 :    wire [7:0]                      lsu_axi_wstrb;
+     525         1606 :    wire [63:0]                     lsu_axi_wdata;
+     526        38474 :    wire [7:0]                      lsu_axi_wstrb;
      527           18 :    wire                            lsu_axi_wlast;
      528              : 
      529            0 :    wire                            lsu_axi_bvalid;
@@ -636,10 +636,10 @@
      532            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid;
      533              : 
      534              :    // AXI Read Channels
-     535       238488 :    wire                            lsu_axi_arvalid;
+     535       232564 :    wire                            lsu_axi_arvalid;
      536            0 :    wire                            lsu_axi_arready;
      537            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid;
-     538          119 :    wire [31:0]                     lsu_axi_araddr;
+     538          118 :    wire [31:0]                     lsu_axi_araddr;
      539           17 :    wire [3:0]                      lsu_axi_arregion;
      540            0 :    wire [7:0]                      lsu_axi_arlen;
      541            0 :    wire [2:0]                      lsu_axi_arsize;
@@ -694,10 +694,10 @@
      590            0 :    wire [pt.IFU_BUS_TAG-1:0]      ifu_axi_bid;
      591              : 
      592              :    // AXI Read Channels
-     593      1447798 :    wire                            ifu_axi_arvalid;
+     593      1410841 :    wire                            ifu_axi_arvalid;
      594            0 :    wire                            ifu_axi_arready;
-     595       853328 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
-     596       516548 :    wire [31:0]                     ifu_axi_araddr;
+     595       827542 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
+     596       506236 :    wire [31:0]                     ifu_axi_araddr;
      597           20 :    wire [3:0]                      ifu_axi_arregion;
      598            0 :    wire [7:0]                      ifu_axi_arlen;
      599            0 :    wire [2:0]                      ifu_axi_arsize;
diff --git a/html/main/coverage_dashboard/all/index_mem_lib.sv.html b/html/main/coverage_dashboard/all/index_mem_lib.sv.html
index 1a782caf688..98d95e53ae4 100644
--- a/html/main/coverage_dashboard/all/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111    358094741 : `EL2_RAM(4096, 39)
+     111    356040069 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175     79536278 : `EL2_RAM_BE(512, 142)
+     175     78979582 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208     39595198 : `EL2_RAM_BE(128, 52)
+     208     39316850 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all/index_rvjtag_tap.v.html
index 4fab493c12c..8bcc9a13fc9 100644
--- a/html/main/coverage_dashboard/all/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -217,9 +217,9 @@
      113              :     endcase
      114              : end
      115              : 
-     116        13875 : always @ (posedge tck or negedge trst) begin
-     117        12752 :     if(!trst) state <= TEST_LOGIC_RESET_STATE;
-     118        13793 :     else state <= nstate;
+     116        13772 : always @ (posedge tck or negedge trst) begin
+     117        12649 :     if(!trst) state <= TEST_LOGIC_RESET_STATE;
+     118        13690 :     else state <= nstate;
      119              : end
      120              : 
      121              : assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
@@ -238,11 +238,11 @@
      134              : //                      IR register
      135              : ///////////////////////////////////////////////////////
      136              : 
-     137        13875 : always @ (negedge tck or negedge trst) begin
-     138        12752 :    if (!trst) ir <= 5'b1;
-     139        13793 :    else begin
+     137        13772 : always @ (negedge tck or negedge trst) begin
+     138        12649 :    if (!trst) ir <= 5'b1;
+     139        13690 :    else begin
      140           37 :       if (jtag_reset) ir <= 5'b1;
-     141          115 :       else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
+     141          114 :       else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
      142              :    end
      143              : end
      144              : 
@@ -254,12 +254,12 @@
      150              : ///////////////////////////////////////////////////////
      151              : //                      Shift register
      152              : ///////////////////////////////////////////////////////
-     153        13875 : always @ (posedge tck or negedge trst) begin
-     154        12752 :     if(!trst)begin
+     153        13772 : always @ (posedge tck or negedge trst) begin
+     154        12649 :     if(!trst)begin
      155           82 :         sr <= '0;
      156              :     end
-     157        13793 :     else begin
-     158        13793 :         sr <= nsr;
+     157        13690 :     else begin
+     158        13690 :         sr <= nsr;
      159              :     end
      160              : end
      161              : 
@@ -267,33 +267,33 @@
      163          319 : always_comb begin
      164          319 :     nsr = sr;
      165          319 :     case(1)
-     166        20660 :     shift_dr:   begin
-     167        20660 :                     case(1)
-     168        26937 :                     dr_en[1]:   nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
+     166        20578 :     shift_dr:   begin
+     167        20578 :                     case(1)
+     168        26773 :                     dr_en[1]:   nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
      169              : 
      170              :                     dr_en[0],
      171         4789 :                     devid_sel:  nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
      172            0 :                     default:    nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
      173              :                     endcase
      174              :                 end
-     175          474 :     capture_dr: begin
-     176          474 :                     nsr[0] = 1'b0;
-     177          474 :                     case(1)
+     175          472 :     capture_dr: begin
+     176          472 :                     nsr[0] = 1'b0;
+     177          472 :                     case(1)
      178           23 :                     dr_en[0]:   nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
-     179          657 :                     dr_en[1]:   nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
+     179          653 :                     dr_en[1]:   nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
      180           34 :                     devid_sel:  nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
      181              :                     endcase
      182              :                 end
-     183         1034 :     shift_ir:   nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
-     184          206 :     capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
+     183         1029 :     shift_ir:   nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
+     184          205 :     capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
      185              :     endcase
      186              : end
      187              : 
      188              : // TDO retiming
-     189        13870 : always @ (negedge tck ) tdo <= sr[0];
+     189        13767 : always @ (negedge tck ) tdo <= sr[0];
      190              : 
      191              : // DMI CS register
-     192        13875 : always @ (posedge tck or negedge trst) begin
+     192        13772 : always @ (posedge tck or negedge trst) begin
      193           82 :     if(!trst) begin
      194           82 :         dmi_hard_reset <= 1'b0;
      195           82 :         dmi_reset      <= 1'b0;
@@ -302,21 +302,21 @@
      198            5 :         dmi_hard_reset <= sr[17];
      199            5 :         dmi_reset      <= sr[16];
      200              :     end
-     201        13788 :     else begin
-     202        13788 :         dmi_hard_reset <= 1'b0;
-     203        13788 :         dmi_reset      <= 1'b0;
+     201        13685 :     else begin
+     202        13685 :         dmi_hard_reset <= 1'b0;
+     203        13685 :         dmi_reset      <= 1'b0;
      204              :     end
      205              : end
      206              : 
      207              : // DR register
-     208        13875 : always @ (posedge tck or negedge trst) begin
-     209        12752 :     if(!trst)
+     208        13772 : always @ (posedge tck or negedge trst) begin
+     209        12649 :     if(!trst)
      210           82 :         dr <=  '0;
-     211        13793 :     else begin
-     212          231 :         if (update_dr & dr_en[1])
-     213          231 :             dr <= sr;
+     211        13690 :     else begin
+     212          229 :         if (update_dr & dr_en[1])
+     213          229 :             dr <= sr;
      214              :         else
-     215        13562 :             dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
+     215        13461 :             dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
      216              :     end
      217              : end
      218              : 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index.html b/html/main/coverage_dashboard/all_ahb_cmark/index.html
index fba732b0999..49d80d769bf 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        45.0%
+    
+        44.6%
     
     
-        2391
+        2395
     
     
-        5317
+        5364
     
 
       
@@ -83,10 +83,10 @@
         63.7%
     
     
-        680
+        681
     
     
-        1068
+        1069
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    29.5%
+                    29.3%
                 
             
 
             
                 373
                 /
-                1265
+                1275
             
         
             
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    51.4%
+                    52.1%
                 
             
 
             
-                36
+                37
                 /
-                70
+                71
             
         
     
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    47.9%
+                    47.3%
                 
             
 
             
-                473
+                476
                 /
-                987
+                1007
             
         
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.1%
+                    6.9%
                 
             
 
             
-                6
+                7
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design.html
index b95cbc3976f..1b39fc36f72 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        29.5%
+    
+        29.3%
     
     
         373
     
     
-        1265
+        1275
     
 
       
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        51.4%
+    
+        52.1%
     
     
-        36
+        37
     
     
-        70
+        71
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.0%
+                    35.0%
                 
             
 
             
                 7
                 /
-                14
+                20
             
         
             
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    39.2%
+                    40.4%
                 
             
 
             
-                20
+                21
                 /
-                51
+                52
             
         
     
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    36.7%
+                    36.5%
                 
             
 
             
                 230
                 /
-                627
+                631
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dbg.html
index 63dbe1f2966..b383b106a8f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dec.html
index 5e9f68c90b5..427c8315fdb 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        47.9%
+    
+        47.3%
     
     
-        473
+        476
     
     
-        987
+        1007
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    49.8%
+                    49.0%
                 
             
 
             
                 126
                 /
-                253
+                257
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.9%
+                    21.2%
                 
             
 
             
                 7
                 /
-                32
+                33
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.3%
+                    28.0%
                 
             
 
             
-                102
+                105
                 /
-                360
+                375
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dmi.html
index 0d50b2014c8..4ab1dc74b67 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_exu.html
index 0951b0ec851..b9d2e64bcfb 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_ifu.html
index 3f5b64939e3..6d7675b4ae8 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_include.html
index 30d84fd7ba0..6c1674719f6 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        7.1%
+    
+        6.9%
     
     
-        6
+        7
     
     
-        84
+        101
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_m.svh
+            
+                el2_dec_csr_equ_mu.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.1%
+                    6.9%
                 
             
 
             
-                6
+                7
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lib.html
index 47b2255ffe4..f1bebc5eaa1 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lsu.html
index 59384e4538b..8b89ca88857 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_ahb_to_axi4.sv.html
index 49999bbd018..069478e7ef8 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_axi4_to_ahb.sv.html
index 4a5bf4826f1..744b4d4ed48 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_beh_lib.sv.html
index 1fb3c170042..bc722120eae 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_jtag_to_core_sync.v.html
index b2b2af3c0e2..e8329ae618f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_mux.v.html
index aaab2d3be3d..3fcf40df98d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_wrapper.v.html
index 86b77f72bd7..fbe5790394f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dbg.sv.html
index 54fefad8564..401fe882392 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec.sv.html
index 912c11b6e57..080e4b15967 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        49.8%
+    
+        49.0%
     
     
         126
     
     
-        253
+        257
     
 
             
@@ -354,7 +354,7 @@
      250        16568 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252           24 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253         2159 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253         2191 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255          736 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256          736 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_csr_equ_mu.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_csr_equ_mu.svh.html
rename to html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_csr_equ_mu.svh.html
index a89be9853cb..d3cb582760b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    ahb_cmark_dccm
+                    ahb_cmark
                 
                 
                 
@@ -107,11 +107,11 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6            9 : logic csr_mstatus;
-       7            2 : logic csr_mtvec;
+       6           27 : logic csr_mstatus;
+       7            6 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
-      10            4 : logic csr_mcyclel;
+      10           12 : logic csr_mcyclel;
       11            0 : logic csr_mcycleh;
       12            0 : logic csr_minstretl;
       13            0 : logic csr_minstreth;
@@ -120,7 +120,7 @@
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            2 : logic csr_mrac;
+      19            6 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -185,7 +185,7 @@
       81            0 : logic csr_pmpaddr16;
       82            0 : logic csr_pmpaddr32;
       83            0 : logic csr_pmpaddr48;
-      84            9 : logic csr_cyclel;
+      84           27 : logic csr_cyclel;
       85            0 : logic csr_cycleh;
       86            0 : logic csr_instretl;
       87            0 : logic csr_instreth;
@@ -201,7 +201,7 @@
       97            0 : logic csr_mseccfgh;
       98            0 : logic valid_only;
       99            0 : logic presync;
-     100            5 : logic postsync;
+     100           15 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444            8 : logic legal;
+     444           24 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_decode_ctl.sv.html
index c073438294c..36b6b9ab49e 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89       593738 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91         2159 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91         2191 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           48 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_gpr_ctl.sv.html
index aacf68d5815..71674d7dc58 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_ib_ctl.sv.html
index 0f7baddebb7..e6a245217a2 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_pmp_ctl.sv.html
index a38e83b540f..5d4049cd9ae 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.9%
+    
+        21.2%
     
     
         7
     
     
-        32
+        33
     
 
             
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_tlu_ctl.sv.html
index ac8947d105e..de028293ff6 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.3%
+    
+        28.0%
     
     
-        102
+        105
     
     
-        360
+        375
     
 
             
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183         2159 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183         2191 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           48 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186          352 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -586,7 +586,7 @@
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
      484           15 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485       204713 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     485       202873 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_trigger.sv.html
index 265afe0bb8f..c0712fad0bf 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dma_ctrl.sv.html
index ec2b7aa3368..328d920a7e9 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu.sv.html
index 553826d68c2..4c1395e33fb 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52        76216 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53         3788 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54           24 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55         2159 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55         2191 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57       645402 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_alu_ctl.sv.html
index d83587aa91a..e98fe0cc3d2 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30       776328 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32           24 :    input  logic                  csr_ren_in,         // CSR select
-      33         2159 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33         2191 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        84128 :    input  logic signed [31:0]    a_in,               // A operand
       35       204660 :    input  logic        [31:0]    b_in,               // B operand
       36           30 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_div_ctl.sv.html
index 2f650cc189b..365de26250b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_mul_ctl.sv.html
index e20559592dc..a6494b6a0a0 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu.sv.html
index 4b8b923aee5..8665af87992 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_aln_ctl.sv.html
index f3775a69356..9229b7c5318 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_bp_ctl.sv.html
index fad8f10ffe1..197c8ea0d6f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_compress_ctl.sv.html
index 96b3824ad73..f55215ece66 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ic_mem.sv.html
index 06bd00c04a3..e2e173bc764 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_iccm_mem.sv.html
index 4ef8bb6ed0a..e5385be0209 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ifc_ctl.sv.html
index accc96c6c29..e80cdef462a 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_mem_ctl.sv.html
index 4870a8a91aa..65b9a04001a 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lib.sv.html
index ff31e621bea..6e19b72ec33 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu.sv.html
index d240ada6215..d34c34ce17b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_addrcheck.sv.html
index a85000005a2..f1acc4b0046 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_buffer.sv.html
index 0342201b65c..8bec2768716 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_intf.sv.html
index c69834882c1..a66fdb59d7b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_clkdomain.sv.html
index 5bf34c976cf..888f78a2c2b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_ctl.sv.html
index 1574089236f..9b78ea8255f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_mem.sv.html
index 74eb7d6947c..7c76d9ef15b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_ecc.sv.html
index 589912510bc..6fbd4a9939f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_lsc_ctl.sv.html
index d4661586026..cd1c0f92de8 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_stbuf.sv.html
index 995d430212c..3aef751a40d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_trigger.sv.html
index b5ab3013a01..2440631b41c 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem.sv.html
index e7ca27c39b3..1b4fcfd07dd 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem_if.sv.html
index d165aa4ec93..dd4a30f3e42 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pic_ctrl.sv.html
index ac016708aec..5e966b5603e 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pmp.sv.html
index 6b1a0330878..be1c13d9471 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.0%
+    
+        35.0%
     
     
         7
     
     
-        14
+        20
     
 
             
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        39.2%
+    
+        40.4%
     
     
-        20
+        21
     
     
-        51
+        52
     
 
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer.sv.html
index 2c02de6338c..65a2b912ddf 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        36.7%
+    
+        36.5%
     
     
         230
     
     
-        627
+        631
     
 
             
@@ -712,7 +712,7 @@
      608         2940 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610           24 :    logic        dec_csr_ren_d;
-     611         2159 :    logic [31:0] dec_csr_rddata_d;
+     611         2191 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer_wrapper.sv.html
index 5bc9637b830..41763a6bafe 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark/index_mem_lib.sv.html
index 09c4bc874d1..99b62065d6b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_cmark/index_rvjtag_tap.v.html
index 9e958bf8cc5..877417c030a 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index.html
index 3bff432cb30..fa5bfd3c2d2 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        44.9%
+    
+        45.2%
     
     
-        2409
+        2405
     
     
-        5364
+        5317
     
 
       
@@ -83,10 +83,10 @@
         61.6%
     
     
-        659
+        658
     
     
-        1069
+        1068
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.9%
+                    29.2%
                 
             
 
             
                 369
                 /
-                1275
+                1265
             
         
             
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.1%
+                    51.4%
                 
             
 
             
-                37
+                36
                 /
-                71
+                70
             
         
     
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    44.0%
+                    44.6%
                 
             
 
             
-                443
+                440
                 /
-                1007
+                987
             
         
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    6.9%
+                    7.1%
                 
             
 
             
-                7
+                6
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design.html
index dc27735772c..88da8d3d768 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        28.9%
+    
+        29.2%
     
     
         369
     
     
-        1275
+        1265
     
 
       
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        52.1%
+    
+        51.4%
     
     
-        37
+        36
     
     
-        71
+        70
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    35.0%
+                    50.0%
                 
             
 
             
                 7
                 /
-                20
+                14
             
         
             
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.4%
+                    39.2%
                 
             
 
             
-                21
+                20
                 /
-                52
+                51
             
         
     
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    34.9%
+                    35.1%
                 
             
 
             
                 220
                 /
-                631
+                627
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html
index c4fcef13df0..e7d7459bb4c 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html
index 60eb8db705b..bb0d1b72359 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        44.0%
+    
+        44.6%
     
     
-        443
+        440
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.9%
+                    46.6%
                 
             
 
             
                 118
                 /
-                257
+                253
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.2%
+                    21.9%
                 
             
 
             
                 7
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    27.5%
+                    27.8%
                 
             
 
             
-                103
+                100
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html
index 40aa2845b6a..c864681f046 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html
index 80a949c998f..efebd45f5cd 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html
index e1be6c3558b..cab26e7acf4 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_include.html
index 601ad89288f..d1ee449671e 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        6.9%
+    
+        7.1%
     
     
-        7
+        6
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    6.9%
+                    7.1%
                 
             
 
             
-                7
+                6
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html
index 06daa9a192f..dbdd6231640 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html
index f6a10450842..10ef45ee918 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_ahb_to_axi4.sv.html
index 6c824300d90..c8d39fb561f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_axi4_to_ahb.sv.html
index bf19f93ba29..1eb0772ba59 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_beh_lib.sv.html
index 3d3b622f867..82ab072fbc0 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_jtag_to_core_sync.v.html
index a7d929151b9..7fadf6f4d34 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_mux.v.html
index 8ea0665c508..95cd866761b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_wrapper.v.html
index 4aa6f62ebc9..9e838c2062c 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dbg.sv.html
index 32c01155df5..df516048941 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec.sv.html
index 33c18e65b74..3013f38b474 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        45.9%
+    
+        46.6%
     
     
         118
     
     
-        257
+        253
     
 
             
@@ -354,7 +354,7 @@
      250         6904 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            8 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253          587 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253            4 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255          344 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256          344 :     output logic dec_tlu_flush_lower_wb,
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295            0 :     output logic priv_mode,
-     296            0 :     output logic priv_mode_eff,
-     297            0 :     output logic priv_mode_ns,
+     295              :     output logic priv_mode,
+     296              :     output logic priv_mode_eff,
+     297              :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300            0 :     output el2_mseccfg_pkt_t mseccfg,
+     300              :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_csr_equ_m.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_csr_equ_m.svh.html
rename to html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_csr_equ_m.svh.html
index 17e9e87ac84..16a72241bb9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    axi_cmark
+                    ahb_cmark_dccm
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_decode_ctl.sv.html
index 6371770ccb7..5cb1363a65d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89       189726 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91          587 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91            4 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_gpr_ctl.sv.html
index 37346cdc7c2..6012110709c 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_ib_ctl.sv.html
index 984d1c84a99..8b35c52059d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_pmp_ctl.sv.html
index 3f28b6750c3..697a1a9d00d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.2%
+    
+        21.9%
     
     
         7
     
     
-        33
+        32
     
 
             
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52            0 :    input el2_mseccfg_pkt_t mseccfg,
+      52              :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_tlu_ctl.sv.html
index d2793911cf3..9f506fa885d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        27.5%
+    
+        27.8%
     
     
-        103
+        100
     
     
-        375
+        360
     
 
             
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183          587 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183            4 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186          172 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243            0 :    output logic  priv_mode,
-     244            0 :    output logic  priv_mode_eff,
-     245            0 :    output logic  priv_mode_ns,
+     243              :    output logic  priv_mode,
+     244              :    output logic  priv_mode_eff,
+     245              :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248            0 :    output logic [2:0] mseccfg,
+     248              :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275            0 :    logic wr_mcounteren_r;
-     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277            0 :    logic wr_mseccfg_r;
-     278            2 :    logic [2:0] mseccfg_ns;
+     275              :    logic wr_mcounteren_r;
+     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277              :    logic wr_mseccfg_r;
+     278              :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,9 +389,9 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286          340 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290            0 :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483            0 :    logic  csr_acc_r;    // CSR access error
-     484            5 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485        68829 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483              :    logic  csr_acc_r;    // CSR access error
+     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994            0 :    logic csr_wr_acc_r;
-     995            0 :    logic csr_rd_acc_r;
+     994              :    logic csr_wr_acc_r;
+     995              :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568            0 :    logic  pmp_any_region_locked;
+    1568              :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_trigger.sv.html
index 60844d2452d..434d5ae49c4 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dma_ctrl.sv.html
index 818e949d7de..628aca21506 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu.sv.html
index bd38fce68e6..81522574566 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            8 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55          587 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55            4 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57       210058 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_alu_ctl.sv.html
index 7def9bed4ac..700dbe76d2e 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30       235484 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            8 :    input  logic                  csr_ren_in,         // CSR select
-      33          587 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33            4 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        26484 :    input  logic signed [31:0]    a_in,               // A operand
       35        65144 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_div_ctl.sv.html
index 87e51db6f50..57d98fd3872 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_mul_ctl.sv.html
index 2525507abc4..146b2589b62 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu.sv.html
index 52969563147..961a694ba64 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_aln_ctl.sv.html
index 42e5be7e792..8563d9d39c8 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_bp_ctl.sv.html
index 62f83cb6344..7126ba58976 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_compress_ctl.sv.html
index 80c31d2681f..bb4bc5130ce 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ic_mem.sv.html
index 0094b87534f..215ba1bc08b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_iccm_mem.sv.html
index 73b6c0db871..87ce3544a4f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html
index 4c95c5642c4..a57229163d4 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_mem_ctl.sv.html
index fac4f1abbec..67e4ebb15c0 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lib.sv.html
index e900b2d6797..20602a85fbd 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu.sv.html
index 10c7667e1d1..21b32b6afed 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_addrcheck.sv.html
index f77de903f16..05e69ff1347 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_buffer.sv.html
index edc59145bb7..876da437ccc 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_intf.sv.html
index 0801245c070..f3cd86a7fe5 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_clkdomain.sv.html
index 4923ea6ebdd..632ac1b3b50 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html
index ccc93370ba6..5354add1eee 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_mem.sv.html
index 773c0418719..55f65382bb2 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_ecc.sv.html
index 0998f81ea93..82d1df2b2ff 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html
index dae57544e14..ef442a6aa76 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_stbuf.sv.html
index 64c298a91ca..88e33d0f824 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_trigger.sv.html
index 6d566efda79..6da00c66572 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem.sv.html
index 10ad26553d5..ec054e6092e 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem_if.sv.html
index e3aa0d521c8..a177b129ad3 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pic_ctrl.sv.html
index f65586dd06e..44f37d936ab 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pmp.sv.html
index 08142eeaa01..dc99885795f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        35.0%
+    
+        50.0%
     
     
         7
     
     
-        20
+        14
     
 
             
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        40.4%
+    
+        39.2%
     
     
-        21
+        20
     
     
-        52
+        51
     
 
             
@@ -132,12 +132,12 @@
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35            0 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36            0 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36              :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
       39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60            0 :   logic any_region_enabled;
+      60              :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -177,7 +177,7 @@
       73              :   //                                             \--> pmp_chan_err
       74              : 
       75              :   // A wrapper function in which it is decided which form of permission check function gets called
-      76           96 :   function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,
+      76           96 :   function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,
       77              :                                               el2_pmp_cfg_pkt_t csr_pmp_cfg,
       78              :                                               el2_pmp_type_pkt_t req_type,
       79              :                                               logic priv_mode,
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            3 :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223            0 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -332,7 +332,7 @@
      228              :   end
      229              : `endif
      230              : 
-     231            0 :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
+     231            0 :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
      232              :     assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]};  // addr. widening: 32-bit -> 34-bit
      233            0 :     for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
      234              :       // Comparators are sized according to granularity
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer.sv.html
index cd88b59d6fa..23045c6ea86 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        34.9%
+    
+        35.1%
     
     
         220
     
     
-        631
+        627
     
 
             
@@ -712,7 +712,7 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            8 :    logic        dec_csr_ren_d;
-     611          587 :    logic [31:0] dec_csr_rddata_d;
+     611            4 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890            0 :    logic priv_mode;
+     890              :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892            0 :    logic priv_mode_eff;
+     892              :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894            0 :    logic priv_mode_ns;
+     894              :    logic priv_mode_ns;
      895              : 
-     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer_wrapper.sv.html
index 1f35e2190d0..77cf578e0e7 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_mem_lib.sv.html
index d0096389da4..6d81e97b584 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_rvjtag_tap.v.html
index a21d38cfc2f..7238a4638d5 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_dccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index.html
index cc82065d873..8392a1a3620 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        45.1%
+    
+        44.8%
     
     
-        2400
+        2404
     
     
-        5317
+        5364
     
 
       
@@ -83,10 +83,10 @@
         61.6%
     
     
-        658
+        659
     
     
-        1068
+        1069
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    29.2%
+                    28.9%
                 
             
 
             
                 369
                 /
-                1265
+                1275
             
         
             
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    51.4%
+                    52.1%
                 
             
 
             
-                36
+                37
                 /
-                70
+                71
             
         
     
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    43.9%
+                    43.3%
                 
             
 
             
-                433
+                436
                 /
-                987
+                1007
             
         
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.1%
+                    6.9%
                 
             
 
             
-                6
+                7
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design.html
index fd865447d58..4026126f25b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        29.2%
+    
+        28.9%
     
     
         369
     
     
-        1265
+        1275
     
 
       
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diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html
index fbcc2196d26..eee4ccfb217 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html
index 00290379f35..7c56490df7e 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html
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diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html
index b80eecfaaa7..7c25393b8e4 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html
index 521ede1f6d1..459c5e60339 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html
index b74cbb4ea3e..e69fc37db93 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_include.html
index 82f683ec2eb..fc2098c290d 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_include.html
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-                el2_dec_csr_equ_m.svh
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diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html
index 5c57d05b560..6ea842cd7a6 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html
index 9edff138ff3..c5f18c399a6 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_ahb_to_axi4.sv.html
index 7b17f094557..b7354047dd3 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_axi4_to_ahb.sv.html
index aefa4c176bd..72a61967c66 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_beh_lib.sv.html
index 588213dbf62..c48ba6366f6 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_jtag_to_core_sync.v.html
index 357d4a1fe0b..3df4bee33b3 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_mux.v.html
index 2feb2f70fc8..edb5963b454 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_wrapper.v.html
index 7a800a632a5..317c5d41d82 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dbg.sv.html
index 5cdad66c707..a18a976e6de 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec.sv.html
index 16dd7ad562b..fae9da7d5eb 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
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+                    25-09-2024
                 
                 
                 
     
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@@ -354,7 +354,7 @@
      250         2824 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            8 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253          619 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253         1234 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255           48 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256           48 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_csr_equ_mu.svh.html
rename to html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html
index 26b821f90dc..4f6bbe665ff 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    axi_cmark_dccm
+                    ahb_cmark_iccm
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_decode_ctl.sv.html
index f6588fa24a6..06f41447c00 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89       214438 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91          619 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91         1234 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_gpr_ctl.sv.html
index c483232558f..58f56e0b66b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_ib_ctl.sv.html
index 312cdbfc4e2..6df224b6747 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_pmp_ctl.sv.html
index 375ad0af15d..2408646f184 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
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-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
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+        21.2%
     
     
         7
     
     
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@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_tlu_ctl.sv.html
index 73ba1d63648..2d4f06417d4 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        27.5%
+    
+        27.2%
     
     
-        99
+        102
     
     
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+        375
     
 
             
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183          619 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183         1234 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186            8 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -379,7 +379,7 @@
      275            0 :    logic wr_mcounteren_r;
      276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277            0 :    logic wr_mseccfg_r;
-     278            2 :    logic [2:0] mseccfg_ns;
+     278            4 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -391,7 +391,7 @@
      287              : `ifdef RV_USER_MODE
      288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290            0 :    logic [1:0]  mstatus_ns, mstatus;
+     290              :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484            5 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485        66989 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484           10 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485       133978 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_trigger.sv.html
index c634fc9811a..251f04d2dfe 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dma_ctrl.sv.html
index 0f1d7dce8bd..670223a32b7 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu.sv.html
index 6f46a419809..cf064cf9687 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            8 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55          619 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55         1234 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57       225530 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_alu_ctl.sv.html
index d6b9c0236a7..5122dbfb02f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30       253048 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            8 :    input  logic                  csr_ren_in,         // CSR select
-      33          619 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33         1234 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        30212 :    input  logic signed [31:0]    a_in,               // A operand
       35        73644 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_div_ctl.sv.html
index e2f445a2ded..3126f1e7569 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_mul_ctl.sv.html
index 0f7610f0c6a..4ea6a7513ae 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu.sv.html
index 0d5896f8798..ae01e055071 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_aln_ctl.sv.html
index 6ef5413729a..81f0e840222 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_bp_ctl.sv.html
index 2ec089378cc..5bcfe9046f2 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_compress_ctl.sv.html
index ede4bbd6e46..d6871166556 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ic_mem.sv.html
index f865305ac0d..27a4b68bd11 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_iccm_mem.sv.html
index 266b2b9401e..b53452176b7 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html
index cccef694a66..7509db33efb 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_mem_ctl.sv.html
index 58dd28ebb52..a663c86e490 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lib.sv.html
index 27084cb4917..5ded71032b6 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu.sv.html
index 5aad8c2ad91..0a74ce3406f 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_addrcheck.sv.html
index a871b5ae3e5..ef54c486ea1 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_buffer.sv.html
index 7b4d4235d34..0d285187b65 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_intf.sv.html
index ecd7c88287b..1863e34f0ab 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_clkdomain.sv.html
index 3ae8e4bb064..a6b88d82b8b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html
index 8c731fc2399..4f0a475a5a2 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_mem.sv.html
index d6bc5429272..82625215f13 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_ecc.sv.html
index cf7b905e955..bab96a24724 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html
index c742d514d19..40072d03dc4 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_stbuf.sv.html
index 57691f19600..30d1096458a 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_trigger.sv.html
index 99b20d25029..1d9a8829948 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem.sv.html
index bc7b472526f..12b5a277217 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem_if.sv.html
index 37a0192c253..b62baa1bc4b 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pic_ctrl.sv.html
index 9614b32f116..ddbaa77b5aa 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pmp.sv.html
index ab3fa54446b..537a049ef91 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.0%
+    
+        35.0%
     
     
         7
     
     
-        14
+        20
     
 
             
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        39.2%
+    
+        40.4%
     
     
-        20
+        21
     
     
-        51
+        52
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            3 :     logic access_fail = 1'b0;
+     161              :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer.sv.html
index ef741156a86..3b4d0e2b2f8 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        35.1%
+    
+        34.9%
     
     
         220
     
     
-        627
+        631
     
 
             
@@ -712,7 +712,7 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            8 :    logic        dec_csr_ren_d;
-     611          619 :    logic [31:0] dec_csr_rddata_d;
+     611         1234 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer_wrapper.sv.html
index 236fe101528..3fb23733dae 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_mem_lib.sv.html
index 5734c157e6a..720a46f68ab 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_rvjtag_tap.v.html
index 6584e5ce900..8ab87c88bba 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index.html b/html/main/coverage_dashboard/all_ahb_csr_access/index.html
index 6bb7ecc4f34..a8cdf396e29 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design.html
index f9891e36b10..254c483674c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dbg.html
index 156747d0c0c..6928b14dbf9 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dec.html
index 00f2be820ba..915a99eafff 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dmi.html
index 743657d1e07..611949f2b8e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_exu.html
index 6cea5cc06c9..8cf84c3224e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_ifu.html
index 95532eb6f9c..559dbd62bfc 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_include.html
index 8cc9b84cd0b..531ffc538b5 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lib.html
index 24804f8df21..56eeca31826 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lsu.html
index c79d349bd6b..9dabfa0c35c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_ahb_to_axi4.sv.html
index c52da67e606..b3836afffcf 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_axi4_to_ahb.sv.html
index d0f7436e975..77fd9986e82 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_beh_lib.sv.html
index f3a98a0111f..96bc1a1ce3c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_jtag_to_core_sync.v.html
index 3b4947f9947..9fb57d7502b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_mux.v.html
index a9301435033..a481406b6e8 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_wrapper.v.html
index 13021b6ffda..79e91fc7e17 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dbg.sv.html
index c4a12ad3438..3debcc6d573 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec.sv.html
index fb2c2daa1a5..5cbb3304cea 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_csr_equ_mu.svh.html
index 8e6df9bf166..e445521c699 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_decode_ctl.sv.html
index a77b9e4bc08..a3e5eadb6f5 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_gpr_ctl.sv.html
index c67ca3599e6..58514198bd3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_ib_ctl.sv.html
index 68cfd4fef83..1fc7900e648 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_pmp_ctl.sv.html
index defac394dd7..139101830e1 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_tlu_ctl.sv.html
index 2afe064e2c1..62820b9b729 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_trigger.sv.html
index c99290ceb74..93d0b524725 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dma_ctrl.sv.html
index 6ea52ae5e18..6262d274e67 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu.sv.html
index b3a84f59bf9..fe95d2c18fe 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_alu_ctl.sv.html
index 36594f76a1f..f389b5d630e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_div_ctl.sv.html
index 024e076557a..a8b7065475f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_mul_ctl.sv.html
index 47306740f34..36578886fca 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu.sv.html
index 74f63437fca..361e23d8fdc 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_aln_ctl.sv.html
index ed883520f22..adbd417efd4 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_bp_ctl.sv.html
index 0e5caeb5146..bda8ca23acb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_compress_ctl.sv.html
index 003ce54968d..5387e1c5f8e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ic_mem.sv.html
index 1909a602c12..2dd8908b3eb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_iccm_mem.sv.html
index b15218b3496..f1d17630574 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ifc_ctl.sv.html
index 2b0e35ca7ca..74e91bc2cc3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_mem_ctl.sv.html
index c1dd3500cf8..20f7701cb89 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lib.sv.html
index 29d8d413691..0abc84f3af2 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu.sv.html
index 2c59d76a322..47286a648d9 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_addrcheck.sv.html
index 0cbd1ca1b08..fe8b4e0f935 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_buffer.sv.html
index 98cb6df684e..cf5d9866c94 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_intf.sv.html
index da6bfb38114..c082f68e876 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_clkdomain.sv.html
index 80e9738584e..d23b09d6998 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_ctl.sv.html
index 334263468ec..f9267202f85 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_mem.sv.html
index befdee63b3f..cc6694869f1 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_ecc.sv.html
index 9cd2cc6546b..941be0d569c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_lsc_ctl.sv.html
index 8ec76dcd341..ff025f318af 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_stbuf.sv.html
index 96e4ed42fe5..067424f9e91 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_trigger.sv.html
index 15c04dc6c09..1910b5163e7 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem.sv.html
index df8a4f6f9b0..53045c770da 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem_if.sv.html
index a00557fd56c..13e448e7b37 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pic_ctrl.sv.html
index eb271dea431..9c21cbff395 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pmp.sv.html
index 6df25f595d6..b5f5bf6daab 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer.sv.html
index cf50c7cb22f..52d253ac6b2 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer_wrapper.sv.html
index 8d4d1d9f7ba..a55e9d86c66 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_mem_lib.sv.html
index 5726f174d0d..a882feb51aa 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_access/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_csr_access/index_rvjtag_tap.v.html
index 18d3290ea2b..768e658013c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_access/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_access/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index.html
index 8dbd24dbe3c..4b0779af09d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design.html
index dc2d9502f1e..10f5dc9aa10 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dbg.html
index 017e857bf7b..12027147da9 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dec.html
index b3be64416dd..ea1368d76f3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dmi.html
index 7293bdf997e..b985ee4be5d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_exu.html
index f2f2ba3774d..793e2ca486e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_ifu.html
index f1100c6486e..470bbcaaa0f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_include.html
index 7cc9288afcd..dfb6b00dac3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lib.html
index 2be6d8ceb5c..20e8927a970 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lsu.html
index eb4a1c83389..16cf4c5cbb2 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_ahb_to_axi4.sv.html
index 925d9d4cd9f..800cf0a40c3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_axi4_to_ahb.sv.html
index e5e13f68869..de5bcf30b4f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_beh_lib.sv.html
index 9ecdc2fe27f..c4478860663 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_jtag_to_core_sync.v.html
index 06cdf7c2804..5b773788d2d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_mux.v.html
index 70c2d789309..f82a3bc0b36 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_wrapper.v.html
index 82d7a97cab3..4feda4efb9d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dbg.sv.html
index 4f5a0157215..13968a0a643 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec.sv.html
index 2e3df1d7ab6..fef8aa50b7c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_csr_equ_mu.svh.html
index c16782f41a6..443f6164528 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_decode_ctl.sv.html
index a38f4c8370a..5908145d048 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_gpr_ctl.sv.html
index 01927d1b5b8..9b21f3da170 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_ib_ctl.sv.html
index 05142d544bf..1bb46d20bf1 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_pmp_ctl.sv.html
index c30da875cb9..7f26aef9837 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_tlu_ctl.sv.html
index d04e896f189..03dc9d4ce50 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_trigger.sv.html
index 8e88b6bedbc..63acc321e1d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dma_ctrl.sv.html
index fa2b2b17e9b..7fb2a73ed19 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu.sv.html
index 445ee6d33f2..3864055f7e7 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_alu_ctl.sv.html
index 045fdeef9d3..b82a302f385 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_div_ctl.sv.html
index be9ce9de8cc..a42531e4645 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_mul_ctl.sv.html
index 5108c64a76e..9ffa57e9aee 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu.sv.html
index e6ab370046c..7d296613a54 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_aln_ctl.sv.html
index 947529044bb..3ed0535aa04 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_bp_ctl.sv.html
index 430c9e9c816..5db0ab36f31 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_compress_ctl.sv.html
index ac0462a9511..d052e12ec4b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ic_mem.sv.html
index bf460ca6b9a..73b26e54516 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_iccm_mem.sv.html
index 8901de98327..8d7edefc91b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ifc_ctl.sv.html
index 2d7498bd347..15cdcf8c441 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_mem_ctl.sv.html
index 57c48b73741..a9070f5884f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lib.sv.html
index d8d09108b8d..ed37df8a3bc 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu.sv.html
index 6ed9cef2e18..0331f886587 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_addrcheck.sv.html
index 9b82a7e6dfc..fb60f1f7ceb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_buffer.sv.html
index afe8deaeb8c..d886a51d2da 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_intf.sv.html
index c009e912d5f..38c3e5e0971 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_clkdomain.sv.html
index 86382807dd3..240a29596e6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_ctl.sv.html
index 08996986aa8..ac5544e6345 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_mem.sv.html
index dd5bf4f0057..dc9e04dd584 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_ecc.sv.html
index 56249c4ab19..c0db4e78c9c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_lsc_ctl.sv.html
index 818616a5602..80a4e2fff59 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_stbuf.sv.html
index 622fb8ebdb5..64284917911 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_trigger.sv.html
index e36c89aa264..683ed8b3463 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem.sv.html
index 541aef78c31..4fb8eef7be0 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem_if.sv.html
index 8c873262bf4..f0ce7f1e2aa 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pic_ctrl.sv.html
index 7825d6d8e8a..0f1354f6795 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pmp.sv.html
index 7dab1a3eb38..d9771b4a744 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer.sv.html
index 74a3958c8a3..218c942bcb7 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer_wrapper.sv.html
index 89db98f0eed..aaf18c1a499 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_mem_lib.sv.html
index 462c414acfa..985ae2bd2b6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_misa/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_csr_misa/index_rvjtag_tap.v.html
index 9fd4af74e42..3a71be249cd 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_misa/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_misa/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index.html
index 1c44799ea4c..fe6a2eb0e49 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design.html
index d40e0294a3b..5afa3bca574 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html
index 0dd7ccb9142..a5eadf973cc 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html
index 00999d5633f..fd555b27245 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html
index 0a232603557..2912566014f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html
index 9963a91cd5a..9c716837742 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html
index 30bb7712ae1..0aaaebb85ca 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html
index a88d958204a..467abd51a0b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html
index 70fe88a383b..e165aa2ed8b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html
index 94480fb4fca..7edabc3730a 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_ahb_to_axi4.sv.html
index 4b082d4757c..21ddc1e506d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_axi4_to_ahb.sv.html
index 737e2559369..bd564cb4a51 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_beh_lib.sv.html
index e6757281329..8d261869767 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html
index 7b03ef608fc..e5bca744167 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_mux.v.html
index 77fb6613126..790281af82b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_wrapper.v.html
index dc1974a0b0a..be367914674 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dbg.sv.html
index 2192b2969a4..92fb63d5b0c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec.sv.html
index 66664429a6e..00a8ebe2c80 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html
index c43542dfd36..67ded4904a9 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_decode_ctl.sv.html
index b970ef41071..80430e672fa 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html
index c38ef05fc37..f2bbdee4b2d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_ib_ctl.sv.html
index de33b0e4d38..a2fc66a1a6d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html
index cf885f52318..7fa757c3364 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html
index ce7fe42f867..10b541680c3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_trigger.sv.html
index 1cc220816a3..77ceb9b1e74 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dma_ctrl.sv.html
index 434b974db4b..28784b6f600 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu.sv.html
index 90787934f4f..fd3459537d3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_alu_ctl.sv.html
index febef6a7f6a..0f441b42b60 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_div_ctl.sv.html
index 656e4d37fbf..1a2c3c99126 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_mul_ctl.sv.html
index f11ab8148a7..f280df3bb44 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu.sv.html
index 68b74c5d582..21aa1f3bebc 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html
index 82f7c2558ae..3a8ea52f43c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html
index fe8d666ec7f..9d5de1d95ee 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html
index b99dcccdf39..1600a0b32e2 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ic_mem.sv.html
index 1174781c21f..8a3f642da74 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html
index dfe8628b559..8f9ba5b9db6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html
index fdc391548c6..002e885a710 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html
index ce8769f6add..fc09efb92eb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lib.sv.html
index 1e3aaafa1f4..f7742f84921 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu.sv.html
index 3210ae4437f..ed2ad06e7f1 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_addrcheck.sv.html
index cbd801a8ecc..0c49241cdae 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html
index 2fe7ff0fe23..66bcb162392 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_intf.sv.html
index e3ddca563b0..0cc6739240c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_clkdomain.sv.html
index 878cc7ea71e..d08e949f536 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html
index 999ed84fb71..0ed12f950be 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html
index 523f5177f68..ea701067c9a 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_ecc.sv.html
index 0658779bc1b..9b77eaa7f3e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html
index 1298cc5d3ff..ba35f2ea906 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_stbuf.sv.html
index d30adfc589e..277af018f5f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_trigger.sv.html
index dc94dfa40e2..b911b754dc4 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem.sv.html
index a8f5037f471..50351f185f6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem_if.sv.html
index 072581ad1a8..ed56ed50c6a 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pic_ctrl.sv.html
index 7b86e4b0bb0..445a95f3b08 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pmp.sv.html
index eda40326c08..0171f5e05af 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer.sv.html
index 75647e08a7f..4e612d4c112 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer_wrapper.sv.html
index 15a5e90195e..5f1fad5f464 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_mem_lib.sv.html
index 8cef07dc0eb..3aa055797f6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_rvjtag_tap.v.html
index ef645df000a..99dac20f877 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mseccfg/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index.html
index 344f66a24bb..57f23e10c63 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design.html
index 240d2d5c105..fb6ad2d7c3c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html
index 51129bbe3a3..d75626b15e9 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html
index dcca811ba9b..991eb90b1b4 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html
index 8ebb79a7675..c6bd6a5368f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html
index af3f01f1fac..7cad4b6858a 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html
index f2393d0fc6f..43eb7440893 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_include.html
index 60286cd3c20..2260f6d77b6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html
index 477466acf46..f540dc0c921 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html
index 1b81694513b..bb4ff667b56 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_ahb_to_axi4.sv.html
index 326e8668d1f..217fc7bc410 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : )
       29              : //   ,TAG  = 1)
       30              : (
-      31        66208 :    input                   clk,
+      31        14760 :    input                   clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -242,9 +242,9 @@
      138            2 :       buf_read_error_in = 1'b0;              // signal indicating that an error came back with the read from the core
      139            2 :       cmdbuf_wr_en      = 1'b0;              // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
      140            2 :       case (buf_state)
-     141        28550 :          IDLE: begin  // No commands recieved
-     142        28550 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
-     143        28550 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
+     141        16134 :          IDLE: begin  // No commands recieved
+     142        16134 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
+     143        16134 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
      144              :           end
      145            0 :          WR: begin // Write command recieved last cycle
      146            0 :                   buf_nxtstate      = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite  ? WR : RD;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_axi4_to_ahb.sv.html
index 8eaac82026e..81b82bfef1d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : `include "el2_param.vh"
       28              : ,parameter TAG  = 1) (
       29              : 
-      30        64480 :    input                   clk,
-      31        64480 :    input                   free_clk,
+      30        14760 :    input                   clk,
+      31        14760 :    input                   free_clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -389,18 +389,18 @@
      285            2 :       rd_bypass_idle   = 1'b0;
      286              : 
      287            2 :       case (buf_state)
-     288        28550 :          IDLE: begin
-     289        28550 :                   master_ready   = 1'b1;
-     290        28550 :                   buf_write_in = (master_opc[2:1] == 2'b01);
-     291        28550 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
-     292        28550 :                   buf_state_en = master_valid & master_ready;
-     293        28550 :                   buf_wr_en    = buf_state_en;
-     294        28550 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
-     295        28550 :                   buf_cmd_byte_ptr_en   = buf_state_en;
-     296        28550 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
-     297        28550 :                   bypass_en       = buf_state_en;
-     298        28550 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
-     299        28550 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
+     288        16134 :          IDLE: begin
+     289        16134 :                   master_ready   = 1'b1;
+     290        16134 :                   buf_write_in = (master_opc[2:1] == 2'b01);
+     291        16134 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
+     292        16134 :                   buf_state_en = master_valid & master_ready;
+     293        16134 :                   buf_wr_en    = buf_state_en;
+     294        16134 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
+     295        16134 :                   buf_cmd_byte_ptr_en   = buf_state_en;
+     296        16134 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
+     297        16134 :                   bypass_en       = buf_state_en;
+     298        16134 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
+     299        16134 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
      300              :           end
      301            0 :          CMD_RD: begin
      302            0 :                   buf_nxtstate    = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_beh_lib.sv.html
index 9518e0075df..92bb7d6cff7 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22        64480 :      input logic           clk,
+      22        14760 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38        28548 :    always_ff @(posedge clk or negedge rst_l) begin
+      38        16132 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42        28538 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42        16122 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52            0 :      input logic             en,
-      53        64480 :      input logic           clk,
+      53        14760 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -171,10 +171,10 @@
       67              : // rvdff with en and clear
       68              : module rvdffsc #( parameter WIDTH=1, SHORT=0 )
       69              :    (
-      70          240 :      input logic [WIDTH-1:0] din,
+      70           12 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73       264832 :      input logic           clk,
+      73        59040 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -192,13 +192,13 @@
       88              : // _fpga versions
       89              : module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
       90              :    (
-      91         3033 :      input logic [WIDTH-1:0] din,
+      91          926 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94        66208 :      input logic           rawclk,
+      94        14760 :      input logic           rawclk,
       95            2 :      input logic           rst_l,
       96              : 
-      97         3033 :      output logic [WIDTH-1:0] dout
+      97          926 :      output logic [WIDTH-1:0] dout
       98              :      );
       99              : 
      100              : if (SHORT == 1) begin : genblock
@@ -220,7 +220,7 @@
      116            0 :      input logic             en,
      117            0 :      input logic           clk,
      118            6 :      input logic           clken,
-     119       130744 :      input logic           rawclk,
+     119        29632 :      input logic           rawclk,
      120            6 :      input logic           rst_l,
      121              : 
      122            0 :      output logic [WIDTH-1:0] dout
@@ -243,14 +243,14 @@
      139              : module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
      140              :    (
      141           26 :      input logic [WIDTH-1:0] din,
-     142        10771 :      input logic             en,
+     142         2660 :      input logic             en,
      143            0 :      input logic             clear,
-     144        11971 :      input logic             clk,
+     144         4300 :      input logic             clk,
      145            6 :      input logic             clken,
-     146       130744 :      input logic             rawclk,
+     146        29632 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
-     149          887 :      output logic [WIDTH-1:0] dout
+     149          238 :      output logic [WIDTH-1:0] dout
      150              :      );
      151              : 
      152            0 :    logic [WIDTH-1:0]          din_new;
@@ -269,9 +269,9 @@
      165              : 
      166              : module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
      167              :    (
-     168          840 :      input  logic [WIDTH-1:0] din,
+     168         1440 :      input  logic [WIDTH-1:0] din,
      169            0 :      input  logic           en,
-     170        64480 :      input  logic           clk,
+     170        14760 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -309,12 +309,12 @@
      205              : 
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
-     208          266 :      input  logic [WIDTH-1:0] din,
-     209       387216 :      input  logic             clk,
+     208           24 :      input  logic [WIDTH-1:0] din,
+     209        89232 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
-     211        32290 :      input  logic             en,
+     211         7516 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
-     213          266 :      output logic [WIDTH-1:0] dout
+     213           24 :      output logic [WIDTH-1:0] dout
      214              :      );
      215              : 
      216              : 
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            0 :      input  logic [WIDTH-1:0] din,
-     242        64480 :      input  logic             clk,
+     242        14760 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -397,12 +397,12 @@
      293              : // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
-     296          180 :      input  logic [WIDTH-1:0] din,
-     297        66208 :      input  logic             clk,
+     296          176 :      input  logic [WIDTH-1:0] din,
+     297        14760 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
-     299         4304 :      input  logic             en,
+     299          976 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
-     301          180 :      output logic [WIDTH-1:0] dout
+     301          176 :      output logic [WIDTH-1:0] dout
      302              :      );
      303              : 
      304              :    localparam integer RIGHT = 31;
@@ -440,16 +440,16 @@
      336              : 
      337              : module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
      338              :    (
-     339           26 :      input  logic [WIDTH-1:0] din,
+     339            4 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341        66208 :      input  logic           clk,
+     341        14760 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
-     344           26 :      output logic [WIDTH-1:0] dout
+     344            4 :      output logic [WIDTH-1:0] dout
      345              :      );
      346              : 
      347            0 :    logic                      l1clk;
-     348          405 :    logic                      en;
+     348           70 :    logic                      en;
      349              : 
      350              : 
      351              : 
@@ -519,7 +519,7 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418        66208 :      input  logic                 clk,
+     418        14760 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
      420            0 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434      1000308 :      input  logic                 rawclk,
+     434       230516 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -551,17 +551,17 @@
      447              : 
      448              : module rvlsadder
      449              :   (
-     450          140 :     input logic [31:0] rs1,
-     451           52 :     input logic [11:0] offset,
+     450          240 :     input logic [31:0] rs1,
+     451            0 :     input logic [11:0] offset,
      452              : 
-     453          140 :     output logic [31:0] dout
+     453          240 :     output logic [31:0] dout
      454              :     );
      455              : 
-     456           52 :    logic                cout;
-     457           52 :    logic                sign;
+     456            0 :    logic                cout;
+     457            0 :    logic                sign;
      458              : 
-     459          476 :    logic [31:12]        rs1_inc;
-     460          364 :    logic [31:12]        rs1_dec;
+     459          220 :    logic [31:12]        rs1_inc;
+     460           26 :    logic [31:12]        rs1_dec;
      461              : 
      462              :    assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
      463              : 
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480           16 :     input [31:1] pc,
-     481         1445 :     input [12:1] offset,
+     481          472 :     input [12:1] offset,
      482              : 
-     483          266 :     output [31:1] dout
+     483           24 :     output [31:1] dout
      484              :     );
      485              : 
-     486         1427 :    logic          cout;
-     487         1675 :    logic          sign;
+     486          566 :    logic          cout;
+     487          590 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -700,7 +700,7 @@
      596              : // Check if the S_ADDR <= addr < E_ADDR
      597              : module rvrangecheck  #(CCM_SADR = 32'h0,
      598              :                        CCM_SIZE  = 128) (
-     599          280 :    input  logic [31:0]   addr,                             // Address to be checked for range
+     599          480 :    input  logic [31:0]   addr,                             // Address to be checked for range
      600            0 :    output logic          in_range,                            // S_ADDR <= start_addr < E_ADDR
      601            0 :    output logic          in_region
      602              : );
@@ -804,8 +804,8 @@
      700              : endmodule // rvecc_decode
      701              : 
      702              : module rvecc_encode_64  (
-     703         1228 :                       input [63:0] din,
-     704         2488 :                       output [6:0] ecc_out
+     703           48 :                       input [63:0] din,
+     704           64 :                       output [6:0] ecc_out
      705              :                       );
      706              :   assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
      707              : 
@@ -896,10 +896,10 @@
      792              : 
      793              : module rvoclkhdr
      794              :   (
-     795        19196 :    input  logic en,
-     796      1787616 :    input  logic clk,
+     795         5202 :    input  logic en,
+     796       398520 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798      1787616 :    output logic l1clk
+     798       398520 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_jtag_to_core_sync.v.html
index 3f3be4f6652..40a76b4501f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32        66208 : input       clk,        // Core clock
+      32        14760 : input       clk,        // Core clock
       33              : 
       34            0 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35            0 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49        28548 : always @ ( posedge clk or negedge rst_n) begin
+      49        16132 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54        28544 :     else begin
-      55        28544 :         rden <= {rden[1:0], rd_en};
-      56        28544 :         wren <= {wren[1:0], wr_en};
+      54        16128 :     else begin
+      55        16128 :         rden <= {rden[1:0], rd_en};
+      56        16128 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_mux.v.html
index 2f0605abd42..c4b90feba2f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_wrapper.v.html
index 640a035fa81..02e676094b2 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36        66208 :   input              core_clk,            // Core clock                  
+      36        14760 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38            0 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39            0 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dbg.sv.html
index 45f9b8d0d06..5205b1dc0ec 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -140,7 +140,7 @@
       36            2 :    output logic                        dbg_core_rst_l,            // core reset from dm
       37              : 
       38              :    // inputs back from the core/dec
-      39           18 :    input logic [31:0]                  core_dbg_rddata,
+      39           16 :    input logic [31:0]                  core_dbg_rddata,
       40            0 :    input logic                         core_dbg_cmd_done,         // This will be treated like a valid signal
       41            0 :    input logic                         core_dbg_cmd_fail,         // Exception during command run
       42              : 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110        66208 :    input logic                         clk,
-     111        66208 :    input logic                         free_clk,
+     110        14760 :    input logic                         clk,
+     111        14760 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254            0 :    logic              dbg_free_clken;
-     255        66208 :    logic              dbg_free_clk;
+     255        14760 :    logic              dbg_free_clk;
      256              : 
      257            0 :    logic              sb_free_clken;
-     258        66208 :    logic              sb_free_clk;
+     258        14760 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474        28550 :             IDLE: begin
-     475        28550 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476        28550 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477        28550 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474        16134 :             IDLE: begin
+     475        16134 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476        16134 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477        16134 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604        28550 :             SBIDLE: begin
-     605        28550 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606        28550 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607        28550 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608        28550 :                      sbcs_sbbusy_din        = 1'b1;
-     609        28550 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610        28550 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604        16134 :             SBIDLE: begin
+     605        16134 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606        16134 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607        16134 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608        16134 :                      sbcs_sbbusy_din        = 1'b1;
+     609        16134 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610        16134 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec.sv.html
index 4f04c9d41b8..fa826ad1b49 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,19 +136,19 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35        66208 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36        66208 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37        66208 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38        66208 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35        14760 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        14760 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37        14760 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38        14760 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
       42            0 :     output logic dec_extint_stall,  // Stall on external interrupt
       43              : 
-      44         4305 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
+      44          978 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
       45            0 :     output logic dec_pause_state_cg, // to top for active state clock gating
       46              : 
-      47         1280 :     output logic dec_tlu_core_empty,
+      47          268 :     output logic dec_tlu_core_empty,
       48              : 
       49            2 :     input logic        rst_l,   // reset, active low
       50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
@@ -174,27 +174,27 @@
       70            2 :     output logic mpc_debug_run_ack,   // Run ack
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
-      73          314 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74          706 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
-      75          930 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
+      73           64 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
+      74          232 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      75          242 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
-      78          660 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
-      79          202 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
+      78          228 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
+      79           20 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
       80            0 :     input logic lsu_nonblock_load_inv_r,  // invalidate request for nonblock load r
-      81          202 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
-      82          718 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
+      81           20 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
+      82          232 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
       83            0 :     input logic lsu_nonblock_load_data_error,  // nonblock load bus error
-      84           36 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
-      85           14 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
+      84            0 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
+      85            0 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
       86              : 
-      87         1548 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
+      87          468 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
       88            0 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
       89            0 :     input logic lsu_pmu_bus_error,         // D side bus error
       90            0 :     input logic lsu_pmu_bus_busy,          // D side bus busy
       91            0 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
-      92          660 :     input logic lsu_pmu_load_external_m,   // D side bus load
-      93          760 :     input logic lsu_pmu_store_external_m,  // D side bus store
+      92          228 :     input logic lsu_pmu_load_external_m,   // D side bus load
+      93          232 :     input logic lsu_pmu_store_external_m,  // D side bus store
       94            0 :     input logic dma_pmu_dccm_read,         // DMA DCCM read
       95            0 :     input logic dma_pmu_dccm_write,        // DMA DCCM write
       96            0 :     input logic dma_pmu_any_read,          // DMA read
@@ -203,13 +203,13 @@
       99            0 :     input logic [31:1] lsu_fir_addr,  // Fast int address
      100            0 :     input logic [ 1:0] lsu_fir_error, // Fast int lookup error
      101              : 
-     102         4305 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
-     103          272 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
-     104         4336 :     input logic ifu_pmu_ic_miss,        // icache miss
+     102          978 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
+     103           58 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
+     104          988 :     input logic ifu_pmu_ic_miss,        // icache miss
      105            0 :     input logic ifu_pmu_ic_hit,         // icache hit
      106            0 :     input logic ifu_pmu_bus_error,      // Instruction side bus error
      107            0 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
-     108         4336 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
+     108          988 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
      109              : 
      110            0 :     input logic ifu_ic_error_start,         // IC single bit error
      111            0 :     input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
@@ -228,11 +228,11 @@
      124            0 :     input logic ifu_i0_icaf_second,  // i0 has access fault on second 2B of 4B inst
      125            0 :     input logic ifu_i0_dbecc,        // icache/iccm double-bit error
      126              : 
-     127          969 :     input logic lsu_idle_any,  // lsu idle for halting
+     127          236 :     input logic lsu_idle_any,  // lsu idle for halting
      128              : 
-     129           62 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
-     130          122 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
-     131          554 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
+     129           12 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
+     130           20 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
+     131           10 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
      132            0 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
      133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
      134              : 
@@ -241,7 +241,7 @@
      137              : 
      138            0 :     input logic        lsu_imprecise_error_load_any,   // LSU imprecise load bus error
      139            0 :     input logic        lsu_imprecise_error_store_any,  // LSU imprecise store bus error
-     140          111 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
+     140          220 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
      141              : 
      142            0 :     input logic [31:0] exu_div_result,  // final div result
      143            0 :     input logic        exu_div_wren,    // Divide write enable to GPR
@@ -258,17 +258,17 @@
      154              : 
      155            0 :     input logic iccm_dma_sb_error,  // ICCM DMA single bit error
      156              : 
-     157          345 :     input logic exu_flush_final,  // slot0 flush
+     157           70 :     input logic exu_flush_final,  // slot0 flush
      158              : 
      159            2 :     input logic [31:1] exu_npc_r,  // next PC
      160              : 
-     161          110 :     input logic [31:0] exu_i0_result_x,  // alu result x
+     161           16 :     input logic [31:0] exu_i0_result_x,  // alu result x
      162              : 
      163              : 
-     164         4305 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
-     165          132 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
+     164          978 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
+     165           12 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166           10 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167         2237 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167          482 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            2 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
@@ -290,7 +290,7 @@
      186              :     // Debug start
      187            0 :     input logic dbg_halt_req,        // DM requests a halt
      188            0 :     input logic dbg_resume_req,      // DM requests a resume
-     189         4336 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
+     189          988 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
      190              : 
      191            0 :     output logic        dec_tlu_dbg_halted,        // Core is halted and ready for debug command
      192            0 :     output logic        dec_tlu_debug_mode,        // Core is in debug mode
@@ -303,7 +303,7 @@
      199              : 
      200            0 :     output logic dec_debug_wdata_rs1_d,  // insert debug write data into rs1 at decode
      201              : 
-     202           18 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
+     202           16 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
      203              : 
      204            0 :     output logic dec_dbg_cmd_done,  // abstract command is done
      205            0 :     output logic dec_dbg_cmd_fail,  // abstract command failed (illegal reg address)
@@ -313,81 +313,81 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212          576 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212          172 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215          746 :     input  logic       exu_i0_br_valid_r,        // valid
-     216          314 :     input  logic       exu_i0_br_mp_r,           // mispredict
-     217         1268 :     input  logic       exu_i0_br_middle_r,       // middle of bank
+     215          208 :     input  logic       exu_i0_br_valid_r,        // valid
+     216           64 :     input  logic       exu_i0_br_mp_r,           // mispredict
+     217          268 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
      219              :     // branch info from pipe1 for errors or counter updates
      220              : 
-     221          258 :     input logic exu_i0_br_way_r,  // way hit or repl
+     221            8 :     input logic exu_i0_br_way_r,  // way hit or repl
      222              : 
-     223         3562 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
-     224         1556 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
-     225           12 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
-     226           18 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
+     223          924 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
+     224          244 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
+     225            8 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
+     226            8 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228          324 :     output logic [31:0] dec_i0_immed_d,    // immediate data
-     229          238 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
+     228           16 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     229            8 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
-     233         3113 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234         1167 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     233          530 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
+     234          246 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
-     236          244 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
+     236           20 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
      238           10 :     output logic [31:1] dec_i0_pc_d,             // pc's at decode
-     239           40 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
-     240            0 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
+     239            0 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
+     240            0 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
      241              : 
-     242           18 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
+     242           16 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
      243              : 
-     244          402 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
-     245         3081 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
+     244           24 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
+     245          532 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
      246            0 :     output el2_mul_pkt_t mul_p,           // mul packet
      247            0 :     output el2_div_pkt_t div_p,           // div packet
      248            0 :     output logic         dec_div_cancel,  // cancel divide operation
      249              : 
-     250           52 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
+     250            0 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
-     252           24 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253           41 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     252            4 :     output logic        dec_csr_ren_d,    // CSR read enable
+     253            0 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
-     255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+     255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256            4 :     output logic dec_tlu_flush_lower_wb,
      257            0 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
      258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      259            0 :     output logic dec_tlu_fence_i_r,  // flush is a fence_i rfnpc, flush icache
      260              : 
-     261          238 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
+     261           16 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
      262              : 
-     263          258 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
+     263            8 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
      264              : 
      265            0 :     output logic dec_tlu_perfcnt0,  // toggles when slot0 perf counter 0 has an event inc
      266            0 :     output logic dec_tlu_perfcnt1,  // toggles when slot0 perf counter 1 has an event inc
      267            0 :     output logic dec_tlu_perfcnt2,  // toggles when slot0 perf counter 2 has an event inc
      268            0 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
      269              : 
-     270          232 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
-     271          554 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
-     272          122 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
+     270           12 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
+     271           10 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
+     272           20 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
      273            0 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
      274              : 
      275            0 :     output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index,  // Fully associt btb error index
      276              : 
-     277         1420 :     output logic dec_lsu_valid_raw_d,
+     277          460 :     output logic dec_lsu_valid_raw_d,
      278              : 
      279            0 :     output logic [31:0] dec_tlu_mrac_ff,  // CSR for memory region control
      280              : 
-     281         4304 :     output logic [1:0] dec_data_en,  // clock-gate control logic
-     282         4304 :     output logic [1:0] dec_ctl_en,
+     281          976 :     output logic [1:0] dec_data_en,  // clock-gate control logic
+     282          976 :     output logic [1:0] dec_ctl_en,
      283              : 
-     284          704 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
+     284          232 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
      285              : 
-     286         4304 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
+     286          976 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
      287              : 
      288              :     // PMP signals
      289            0 :     output el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295            0 :     output logic priv_mode,
-     296            2 :     output logic priv_mode_eff,
-     297            0 :     output logic priv_mode_ns,
+     295              :     output logic priv_mode,
+     296              :     output logic priv_mode_eff,
+     297              :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300            0 :     output el2_mseccfg_pkt_t mseccfg,
+     300              :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
@@ -423,7 +423,7 @@
      319            0 :     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
      320            0 :     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
      321              : 
-     322         4304 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+     322          976 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
      323            0 :     input  logic scan_mode               // Flop scan mode control
      324              : 
      325              : );
@@ -432,45 +432,45 @@
      328            0 :   logic dec_tlu_dec_clk_override;  // to and from dec blocks
      329            0 :   logic clk_override;
      330              : 
-     331         4305 :   logic dec_ib0_valid_d;
+     331          978 :   logic dec_ib0_valid_d;
      332              : 
-     333         4305 :   logic dec_pmu_instr_decoded;
+     333          978 :   logic dec_pmu_instr_decoded;
      334            0 :   logic dec_pmu_decode_stall;
      335            0 :   logic dec_pmu_presync_stall;
      336            0 :   logic dec_pmu_postsync_stall;
      337              : 
      338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
-     340          886 :   logic [4:0] dec_i0_rs1_d;
-     341         1136 :   logic [4:0] dec_i0_rs2_d;
+     340           12 :   logic [4:0] dec_i0_rs1_d;
+     341           40 :   logic [4:0] dec_i0_rs2_d;
      342              : 
-     343          132 :   logic [31:0] dec_i0_instr_d;
+     343           12 :   logic [31:0] dec_i0_instr_d;
      344              : 
      345            0 :   logic dec_tlu_trace_disable;
      346            0 :   logic dec_tlu_pipelining_disable;
      347              : 
      348              : 
-     349         1492 :   logic [4:0] dec_i0_waddr_r;
-     350         2226 :   logic dec_i0_wen_r;
-     351           18 :   logic [31:0] dec_i0_wdata_r;
-     352           18 :   logic dec_csr_wen_r;  // csr write enable at wb
-     353          970 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
+     349          240 :   logic [4:0] dec_i0_waddr_r;
+     350          304 :   logic dec_i0_wen_r;
+     351           16 :   logic [31:0] dec_i0_wdata_r;
+     352            8 :   logic dec_csr_wen_r;  // csr write enable at wb
+     353           36 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
      354            8 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
      355            4 :   logic [31:0] dec_csr_wrdata_r;  // csr write data at wb
      356              : 
      357            8 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
-     358           42 :   logic dec_csr_legal_d;  // csr indicates legal operation
+     358           12 :   logic dec_csr_legal_d;  // csr indicates legal operation
      359              : 
-     360           18 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
-     361           42 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
-     362           10 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
+     360            8 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
+     361           12 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
+     362            0 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
      363              : 
-     364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
+     364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366         2237 :   logic dec_i0_pc4_d;
+     366          482 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
-     368           30 :   logic dec_tlu_postsync_d;
-     369            0 :   logic dec_tlu_debug_stall;
+     368            0 :   logic dec_tlu_postsync_d;
+     369            0 :   logic dec_tlu_debug_stall;
      370              : 
      371            0 :   logic [31:0] dec_illegal_inst;
      372              : 
@@ -480,18 +480,18 @@
      376            0 :   logic dec_i0_icaf_second_d;
      377            0 :   logic [3:0] dec_i0_trigger_match_d;
      378            0 :   logic dec_debug_fence_d;
-     379          718 :   logic dec_nonblock_load_wen;
-     380          158 :   logic [4:0] dec_nonblock_load_waddr;
+     379          232 :   logic dec_nonblock_load_wen;
+     380            4 :   logic [4:0] dec_nonblock_load_waddr;
      381            0 :   logic dec_tlu_flush_pause_r;
-     382           62 :   el2_br_pkt_t dec_i0_brp;
-     383          122 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
-     384          554 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
+     382           12 :   el2_br_pkt_t dec_i0_brp;
+     383           20 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
+     384           10 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
      385            0 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
      386            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
      387              : 
      388            2 :   logic [31:1] dec_tlu_i0_pc_r;
      389            0 :   logic dec_tlu_i0_kill_writeb_wb;
-     390         4304 :   logic dec_tlu_i0_valid_r;
+     390          976 :   logic dec_tlu_i0_valid_r;
      391              : 
      392            0 :   logic dec_pause_state;
      393              : 
@@ -499,9 +499,9 @@
      395              : 
      396            0 :   logic dec_tlu_flush_extint;  // Fast ext int started
      397              : 
-     398          471 :   logic [31:0] dec_i0_inst_wb;
+     398            8 :   logic [31:0] dec_i0_inst_wb;
      399            2 :   logic [31:1] dec_i0_pc_wb;
-     400         4304 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
+     400          976 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
      401            0 :   logic [ 4:0] dec_tlu_exc_cause_wb1;
      402            0 :   logic [31:0] dec_tlu_mtval_wb1;
      403            0 :   logic        dec_tlu_i0_exc_valid_wb1;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_csr_equ_m.svh.html
index 6a938847572..e5c91599346 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -102,12 +102,12 @@
 
 
            Line data    Source code

 
-       1            2 : logic csr_misa;
+       1            4 : logic csr_misa;
        2            0 : logic csr_mvendorid;
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6            7 : logic csr_mstatus;
+       6           14 : logic csr_mstatus;
        7            0 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
@@ -177,14 +177,14 @@
       73            0 : logic csr_dicad0;
       74            0 : logic csr_dicad1;
       75            0 : logic csr_dicago;
-      76            2 : logic csr_pmpcfg;
-      77            2 : logic csr_pmpaddr0;
+      76            4 : logic csr_pmpcfg;
+      77            4 : logic csr_pmpaddr0;
       78            0 : logic csr_pmpaddr16;
       79            0 : logic csr_pmpaddr32;
       80            0 : logic csr_pmpaddr48;
       81            0 : logic valid_only;
       82            0 : logic presync;
-      83            7 : logic postsync;
+      83           14 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370            6 : logic legal;
+     370           12 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_decode_ctl.sv.html
index 0013b9f864d..876194be4df 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,21 +133,21 @@
       29              : 
       30            0 :    output logic dec_extint_stall,            // Stall from external interrupt
       31              : 
-      32          704 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
-      33          471 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
+      32          232 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
+      33            8 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
       34            2 :    output logic [31:1] dec_i0_pc_wb,         // 31b pc at wb+1 for trace encoder
       35              : 
       36              : 
-      37          660 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
-      38          202 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
+      37          228 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
+      38           20 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
       39            0 :    input logic                                lsu_nonblock_load_inv_r,         // invalidate request for nonblock load r
-      40          202 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
-      41          718 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
+      40           20 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
+      41          232 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
       42            0 :    input logic                                lsu_nonblock_load_data_error,    // nonblock load bus error
-      43           36 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
+      43            0 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
       44              : 
       45              : 
-      46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
+      46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
       47              : 
       48            0 :    input logic dec_tlu_wr_pause_r,                    // pause instruction at r
       49            0 :    input logic dec_tlu_pipelining_disable,            // pipeline disable - presync, i0 decode only
@@ -168,13 +168,13 @@
       64              : 
       65            0 :    input logic dec_i0_dbecc_d,                        // icache/iccm double-bit error
       66              : 
-      67           62 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
-      68          122 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69          554 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      67           12 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
+      68           20 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      69           10 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
-      73          969 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
+      73          236 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
       74              : 
       75            0 :    input logic lsu_load_stall_any,                    // stall any load at decode
       76            0 :    input logic lsu_store_stall_any,                   // stall any store at decode
@@ -188,67 +188,67 @@
       84            4 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
       85            0 :    input logic dec_tlu_flush_pause_r,                 // don't clear pause state on initial lower flush
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
-      87           30 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
+      87            0 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89         2237 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89          482 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91           41 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92           42 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92           12 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
       96            0 :    input logic [31:0] lsu_result_m,                   // load result
       97            0 :    input logic [31:0] lsu_result_corr_r,              // load result - corrected data for writing gpr's, not for bypassing
       98              : 
-      99          345 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
+      99           70 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
      100              : 
      101            2 :    input logic [31:1] exu_i0_pc_x,                    // pcs at e1
      102              : 
-     103          132 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
+     103           12 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
      104              : 
-     105         4305 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
+     105          978 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
      106              : 
-     107          110 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
+     107           16 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109        66208 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110        66208 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111        66208 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109        14760 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110        14760 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111        14760 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
      115              : 
      116              : 
      117              : 
-     118         3562 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
-     119         1556 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
+     118          924 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
+     119          244 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
-     121          886 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122         1136 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     121           12 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
+     122           40 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124          324 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124           16 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
-     127          238 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
+     127            8 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
      128              : 
      129            0 :    output el2_alu_pkt_t i0_ap,                       // alu packets
      130              : 
-     131         4305 :    output logic        dec_i0_decode_d,               // i0 decode
+     131          978 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
-     133         3113 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134         1167 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     133          530 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
+     134          246 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
-     136         1492 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137         2226 :    output logic        dec_i0_wen_r,                  // i0 write enable
-     138           18 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
+     136          240 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
+     137          304 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     138           16 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
-     140          244 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
+     140           20 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
      141              : 
-     142           40 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
-     143            0 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
-     144           18 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
+     142            0 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
+     143            0 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
+     144           16 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
      145              : 
-     146          402 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
-     147         3081 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
+     146           24 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
+     147          532 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
      148              : 
      149            0 :    output el2_mul_pkt_t    mul_p,                    // multiply packet
      150              : 
@@ -256,45 +256,45 @@
      152            0 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
      153            0 :    output logic             dec_div_cancel,           // cancel the divide operation
      154              : 
-     155         1420 :    output logic        dec_lsu_valid_raw_d,
-     156           52 :    output logic [11:0] dec_lsu_offset_d,
+     155          460 :    output logic        dec_lsu_valid_raw_d,
+     156            0 :    output logic [11:0] dec_lsu_offset_d,
      157              : 
-     158           24 :    output logic        dec_csr_ren_d,                 // valid csr decode
-     159           18 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
-     160           42 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
+     158            4 :    output logic        dec_csr_ren_d,                 // valid csr decode
+     159            8 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
+     160           12 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
      161            8 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
-     162           18 :    output logic        dec_csr_wen_r,                 // csr write enable at r
-     163          970 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
+     162            8 :    output logic        dec_csr_wen_r,                 // csr write enable at r
+     163           36 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
      164            8 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
      165            4 :    output logic [31:0] dec_csr_wrdata_r,              // csr write data at r
-     166           10 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
+     166            0 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
      167              : 
-     168         4304 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
+     168          976 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
      169              : 
      170            0 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
      171              : 
      172            2 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
      173              : 
      174            0 :    output logic [31:0] dec_illegal_inst,              // illegal inst
-     175          238 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
+     175           16 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
-     177          232 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178          554 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
-     179          122 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
+     177           12 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
+     178           10 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     179           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      183              : 
-     184         4304 :    output logic [1:0] dec_data_en,                    // clock-gating logic
-     185         4304 :    output logic [1:0] dec_ctl_en,
+     184          976 :    output logic [1:0] dec_data_en,                    // clock-gating logic
+     185          976 :    output logic [1:0] dec_ctl_en,
      186              : 
-     187         4305 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
+     187          978 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
      188            0 :    output logic       dec_pmu_decode_stall,           // decode is stalled
      189            0 :    output logic       dec_pmu_presync_stall,          // decode has presync stall
      190            0 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
      191              : 
-     192          718 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
-     193          158 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
+     192          232 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
+     193            4 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
      194            0 :    output logic       dec_pause_state,                // core in pause state
      195            0 :    output logic       dec_pause_state_cg,             // pause state for clock-gating
      196              : 
@@ -308,27 +308,27 @@
      204              : 
      205            0 :    el2_dec_pkt_t           i0_dp_raw, i0_dp;
      206              : 
-     207          132 :    logic [31:0]        i0;
-     208         4305 :    logic               i0_valid_d;
+     207           12 :    logic [31:0]        i0;
+     208          978 :    logic               i0_valid_d;
      209              : 
-     210           18 :    logic [31:0]        i0_result_r;
+     210           16 :    logic [31:0]        i0_result_r;
      211              : 
-     212           32 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
+     212            0 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
      213              : 
-     214          132 :    logic               i0_jalimm20;
-     215          220 :    logic               i0_uiimm20;
+     214           12 :    logic               i0_jalimm20;
+     215           20 :    logic               i0_uiimm20;
      216              : 
-     217         1420 :    logic               lsu_decode_d;
-     218          324 :    logic [31:0]        i0_immed_d;
+     217          460 :    logic               lsu_decode_d;
+     218           16 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
-     220           64 :    logic               i0_postsync;
+     220            0 :    logic               i0_postsync;
      221              : 
-     222           30 :    logic               postsync_stall;
-     223           30 :    logic               ps_stall;
+     222            0 :    logic               postsync_stall;
+     223            0 :    logic               ps_stall;
      224              : 
-     225         4304 :    logic               prior_inflight, prior_inflight_wb;
+     225          976 :    logic               prior_inflight, prior_inflight_wb;
      226              : 
-     227           18 :    logic               csr_clr_d, csr_set_d, csr_write_d;
+     227            8 :    logic               csr_clr_d, csr_set_d, csr_write_d;
      228              : 
      229            0 :    logic               csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
      230            0 :    logic [31:0]        csr_mask_x;
@@ -351,14 +351,14 @@
      247            0 :    logic               i0_div_prior_div_stall;
      248            0 :    logic               nonblock_div_cancel;
      249              : 
-     250         4271 :    logic               i0_legal;
+     250          978 :    logic               i0_legal;
      251            0 :    logic               shift_illegal;
      252            0 :    logic               illegal_inst_en;
      253            0 :    logic               illegal_lockout_in, illegal_lockout;
-     254         4305 :    logic               i0_legal_decode_d;
-     255           30 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
+     254          978 :    logic               i0_legal_decode_d;
+     255            0 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
-     257          764 :    logic [12:1]        last_br_immed_d;
+     257          200 :    logic [12:1]        last_br_immed_d;
      258            0 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
@@ -369,31 +369,31 @@
      265            0 :    logic               i0_load_stall_d;
      266            0 :    logic               i0_store_stall_d;
      267              : 
-     268          437 :    logic               i0_predict_nt, i0_predict_t;
+     268           70 :    logic               i0_predict_nt, i0_predict_t;
      269              : 
-     270           12 :    logic               i0_notbr_error, i0_br_toffset_error;
-     271            4 :    logic               i0_ret_error;
-     272           34 :    logic               i0_br_error;
-     273           34 :    logic               i0_br_error_all;
-     274         1071 :    logic [11:0]        i0_br_offset;
+     270            0 :    logic               i0_notbr_error, i0_br_toffset_error;
+     271            0 :    logic               i0_ret_error;
+     272            0 :    logic               i0_br_error;
+     273            0 :    logic               i0_br_error_all;
+     274          238 :    logic [11:0]        i0_br_offset;
      275              : 
-     276          640 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
-     277         3911 :    logic               i0_pcall_12b_offset;
-     278           64 :    logic               i0_pcall_raw;
-     279           64 :    logic               i0_pcall_case;
-     280           64 :    logic               i0_pcall;
+     276           12 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
+     277          956 :    logic               i0_pcall_12b_offset;
+     278            8 :    logic               i0_pcall_raw;
+     279            8 :    logic               i0_pcall_case;
+     280            8 :    logic               i0_pcall;
      281              : 
-     282           68 :    logic               i0_pja_raw;
-     283           72 :    logic               i0_pja_case;
-     284           68 :    logic               i0_pja;
+     282            4 :    logic               i0_pja_raw;
+     283            8 :    logic               i0_pja_case;
+     284            4 :    logic               i0_pja;
      285              : 
-     286           64 :    logic               i0_pret_case;
-     287           64 :    logic               i0_pret_raw, i0_pret;
+     286            8 :    logic               i0_pret_case;
+     287            8 :    logic               i0_pret_raw, i0_pret;
      288              : 
-     289           20 :    logic               i0_jal;                                // jal's that are not predicted
+     289            0 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292         1113 :    logic               i0_predict_br;
+     292          246 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301         2237 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301          482 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303         2804 :    logic               i0_rd_en_d;
+     303          528 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -412,21 +412,21 @@
      308            0 :    logic               leak1_i1_stall_in, leak1_i1_stall;
      309            0 :    logic               leak1_mode;
      310              : 
-     311           18 :    logic               i0_csr_write_only_d;
+     311            8 :    logic               i0_csr_write_only_d;
      312              : 
-     313         4304 :    logic               prior_inflight_x, prior_inflight_eff;
-     314           42 :    logic               any_csr_d;
+     313          976 :    logic               prior_inflight_x, prior_inflight_eff;
+     314           12 :    logic               any_csr_d;
      315              : 
-     316           18 :    logic               prior_csr_write;
+     316            8 :    logic               prior_csr_write;
      317              : 
-     318         4304 :    logic [3:0]        i0_pipe_en;
-     319         4304 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
-     320         4304 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
+     318          976 :    logic [3:0]        i0_pipe_en;
+     319          976 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
+     320          976 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
      321              : 
      322            0 :    logic              debug_fence_i;
      323            0 :    logic              debug_fence;
      324              : 
-     325           18 :    logic              i0_csr_write;
+     325            8 :    logic              i0_csr_write;
      326            0 :    logic              presync_stall;
      327              : 
      328            0 :    logic              i0_instr_error;
@@ -436,19 +436,19 @@
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335          780 :    logic              i0_brp_valid;
-     336          382 :    logic              nonblock_load_cancel;
-     337          969 :    logic              lsu_idle;
+     335          208 :    logic              i0_brp_valid;
+     336           12 :    logic              nonblock_load_cancel;
+     337          236 :    logic              lsu_idle;
      338            0 :    logic              lsu_pmu_misaligned_r;
-     339           24 :    logic              csr_ren_qual_d;
-     340           24 :    logic              csr_read_x;
-     341           30 :    logic              i0_block_d;
-     342           30 :    logic              i0_block_raw_d;  // This is use to create the raw valid
-     343           30 :    logic              ps_stall_in;
-     344          144 :    logic [31:0]       i0_result_x;
+     339            4 :    logic              csr_ren_qual_d;
+     340            4 :    logic              csr_read_x;
+     341            0 :    logic              i0_block_d;
+     342            0 :    logic              i0_block_raw_d;  // This is use to create the raw valid
+     343            0 :    logic              ps_stall_in;
+     344           20 :    logic [31:0]       i0_result_x;
      345              : 
-     346          660 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
-     347          660 :    el2_dest_pkt_t         x_d_in, r_d_in;
+     346          228 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
+     347          228 :    el2_dest_pkt_t         x_d_in, r_d_in;
      348              : 
      349            0 :    el2_trap_pkt_t         d_t, x_t, x_t_in, r_t_in, r_t;
      350              : 
@@ -456,16 +456,16 @@
      352              : 
      353            2 :    logic [31:1]       dec_i0_pc_r;
      354              : 
-     355           16 :    logic csr_read, csr_write;
-     356           20 :    logic i0_br_unpred;
+     355            4 :    logic csr_read, csr_write;
+     356            0 :    logic i0_br_unpred;
      357              : 
-     358          660 :    logic nonblock_load_valid_m_delay;
-     359         2804 :    logic i0_wen_r;
+     358          228 :    logic nonblock_load_valid_m_delay;
+     359          528 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
      363              : 
-     364          344 :    logic flush_final_r;
+     364           68 :    logic flush_final_r;
      365              : 
      366            2 :    logic bitmanip_zbb_legal;
      367            2 :    logic bitmanip_zbs_legal;
@@ -489,24 +489,24 @@
      385              :    localparam NBLOAD_TAG_MSB  = pt.LSU_NUM_NBLOAD_WIDTH-1;
      386              : 
      387              : 
-     388          718 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
-     389           36 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
-     390            0 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
+     388          232 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
+     389            0 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
+     390            0 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
      391              : 
-     392           36 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
-     393            0 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
+     392            0 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
+     393            0 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
      394              : 
      395            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
      396            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
      397            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
      398              : 
-     399          166 :    logic [4:0] nonblock_load_rd;
+     399            8 :    logic [4:0] nonblock_load_rd;
      400            0 :    logic i0_nonblock_load_stall;
      401            0 :    logic i0_nonblock_boundary_stall;
      402              : 
      403            0 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
      404              : 
-     405          660 :    logic i0_load_kill_wen_r;
+     405          228 :    logic i0_load_kill_wen_r;
      406              : 
      407            2 :    logic found;
      408              : 
@@ -514,27 +514,27 @@
      410              : 
      411            0 :    logic debug_fence_raw;
      412              : 
-     413           18 :    logic [31:0] i0_result_r_raw;
-     414           18 :    logic [31:0] i0_result_corr_r;
+     413           16 :    logic [31:0] i0_result_r_raw;
+     414           16 :    logic [31:0] i0_result_corr_r;
      415              : 
-     416          633 :    logic [12:1] last_br_immed_x;
+     416          192 :    logic [12:1] last_br_immed_x;
      417              : 
-     418          592 :    logic [31:0]        i0_inst_d;
-     419          471 :    logic [31:0]        i0_inst_x;
-     420          471 :    logic [31:0]        i0_inst_r;
-     421          471 :    logic [31:0]        i0_inst_wb_in;
-     422          471 :    logic [31:0]        i0_inst_wb;
+     418            8 :    logic [31:0]        i0_inst_d;
+     419            8 :    logic [31:0]        i0_inst_x;
+     420            8 :    logic [31:0]        i0_inst_r;
+     421            8 :    logic [31:0]        i0_inst_wb_in;
+     422            8 :    logic [31:0]        i0_inst_wb;
      423              : 
      424            2 :    logic [31:1]        i0_pc_wb;
      425              : 
-     426         4304 :    logic               i0_wb_en;
+     426          976 :    logic               i0_wb_en;
      427              : 
      428            2 :    logic               trace_enable;
      429              : 
      430            0 :    logic               debug_valid_x;
      431              : 
-     432         1133 :    el2_inst_pkt_t i0_itype;
-     433          886 :    el2_reg_pkt_t i0r;
+     432          246 :    el2_inst_pkt_t i0_itype;
+     433           12 :    el2_reg_pkt_t i0r;
      434              : 
      435              : 
      436              :    rvdffie  #(8) misc1ff (.*,
@@ -631,14 +631,14 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530          206 :       if (i0_br_error_all | i0_instr_error) begin
-     531          206 :          i0_dp          =   '0;
-     532          206 :          i0_dp.alu      = 1'b1;
-     533          206 :          i0_dp.rs1      = 1'b1;
-     534          206 :          i0_dp.rs2      = 1'b1;
-     535          206 :          i0_dp.lor      = 1'b1;
-     536          206 :          i0_dp.legal    = 1'b1;
-     537          206 :          i0_dp.postsync = 1'b1;
+     530         1962 :       if (i0_br_error_all | i0_instr_error) begin
+     531          103 :          i0_dp          =   '0;
+     532          103 :          i0_dp.alu      = 1'b1;
+     533          103 :          i0_dp.rs1      = 1'b1;
+     534          103 :          i0_dp.rs2      = 1'b1;
+     535          103 :          i0_dp.lor      = 1'b1;
+     536          103 :          i0_dp.legal    = 1'b1;
+     537          103 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -709,16 +709,16 @@
      605            2 :       found = 0;
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
-     608         3898 :             if (~cam[i].valid) begin
-     609        26972 :                cam_wen[i] = cam_write;
-     610        26972 :                found = 1'b1;
+     608         2351 :             if (~cam[i].valid) begin
+     609        15177 :                cam_wen[i] = cam_write;
+     610        15177 :                found = 1'b1;
      611              :             end
-     612         3898 :             else begin
-     613         3898 :                cam_wen[i] = 0;
+     612         2351 :             else begin
+     613         2351 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617       106902 :             cam_wen[i] = 0;
+     617        60486 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,28 +756,28 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655          612 :          if (cam_data_reset_val[i])
-     656          612 :            cam[i].valid = 1'b0;
+     655          365 :          if (cam_data_reset_val[i])
+     656          365 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
      659              : 
-     660         1836 :          if (cam_wen[i]) begin
-     661         1836 :             cam_in[i].valid    = 1'b1;
-     662         1836 :             cam_in[i].wb       = 1'b0;
-     663         1836 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
-     664         1836 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
+     660         1095 :          if (cam_wen[i]) begin
+     661         1095 :             cam_in[i].valid    = 1'b1;
+     662         1095 :             cam_in[i].wb       = 1'b0;
+     663         1095 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
+     664         1095 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666           90 :          else if ( (cam_inv_reset_val[i]) |
+     666           46 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
-     668           90 :            cam_in[i].valid = 1'b0;
+     668           46 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670       140610 :            cam_in[i] = cam[i];
+     670        79507 :            cam_in[i] = cam[i];
      671              : 
-     672         1836 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
-     673         1836 :            cam_in[i].wb = 1'b1;
+     672         1095 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     673         1095 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676       114200 :          if (dec_tlu_force_halt)
+     676        64536 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746         6072 :       if (i0_legal_decode_d) begin
-     747         6072 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748          828 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749         1056 :          if (i0_dp.store)                i0_itype = STORE;
-     750         2710 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751         6072 :          if (i0_dp.zbb | i0_dp.zbs |
+     746         3309 :       if (i0_legal_decode_d) begin
+     747         3309 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748          479 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749          592 :          if (i0_dp.store)                i0_itype = STORE;
+     750         1430 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751         3309 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756           26 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757           14 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758         6072 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759         6072 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760         6072 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761         6072 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762         6072 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763         6072 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764         1116 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765          322 :          if (i0_dp.jal)                  i0_itype = JAL;
+     756           16 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757            9 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758         3309 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759         3309 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760         3309 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761         3309 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762         3309 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763         3309 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764          615 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765          168 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862        28550 :       if (dec_extint_stall) begin
+     862        16134 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868        28550 :       else begin
-     869        28550 :          lsu_p.valid = lsu_decode_d;
+     868        16134 :       else begin
+     869        16134 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871        28550 :          lsu_p.load                         =  i0_dp.load ;
-     872        28550 :          lsu_p.store                        =  i0_dp.store;
-     873        28550 :          lsu_p.by                           =  i0_dp.by   ;
-     874        28550 :          lsu_p.half                         =  i0_dp.half ;
-     875        28550 :          lsu_p.word                         =  i0_dp.word ;
-     876        28550 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871        16134 :          lsu_p.load                         =  i0_dp.load ;
+     872        16134 :          lsu_p.store                        =  i0_dp.store;
+     873        16134 :          lsu_p.by                           =  i0_dp.by   ;
+     874        16134 :          lsu_p.half                         =  i0_dp.half ;
+     875        16134 :          lsu_p.word                         =  i0_dp.word ;
+     876        16134 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878        28550 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879        28550 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880        28550 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878        16134 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879        16134 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880        16134 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882        28550 :          lsu_p.unsign  =  i0_dp.unsign;
+     882        16134 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1614,11 +1614,11 @@
     1510              : module el2_dec_dec_ctl
     1511              :   import el2_pkg::*;
     1512              : (
-    1513          132 :     input logic [31:0] inst,
+    1513           12 :     input logic [31:0] inst,
     1514            0 :     output el2_dec_pkt_t out
     1515              : );
     1516              : 
-    1517          132 :   logic [31:0] i;
+    1517           12 :   logic [31:0] i;
     1518              : 
     1519              :   assign i[31:0] = inst[31:0];
     1520              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_gpr_ctl.sv.html
index 43cc3b70517..f1da073dbdf 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -122,26 +122,26 @@
       18              : #(
       19              :    `include "el2_param.vh"
       20              :  )  (
-      21          886 :     input logic [4:0]  raddr0,       // logical read addresses
-      22         1136 :     input logic [4:0]  raddr1,
+      21           12 :     input logic [4:0]  raddr0,       // logical read addresses
+      22           40 :     input logic [4:0]  raddr1,
       23              : 
-      24         2226 :     input logic        wen0,         // write enable
-      25         1492 :     input logic [4:0]  waddr0,       // write address
-      26           18 :     input logic [31:0] wd0,          // write data
+      24          304 :     input logic        wen0,         // write enable
+      25          240 :     input logic [4:0]  waddr0,       // write address
+      26           16 :     input logic [31:0] wd0,          // write data
       27              : 
-      28          718 :     input logic        wen1,         // write enable
-      29          158 :     input logic [4:0]  waddr1,       // write address
-      30           14 :     input logic [31:0] wd1,          // write data
+      28          232 :     input logic        wen1,         // write enable
+      29            4 :     input logic [4:0]  waddr1,       // write address
+      30            0 :     input logic [31:0] wd1,          // write data
       31              : 
-      32            0 :     input logic        wen2,         // write enable
+      32            0 :     input logic        wen2,         // write enable
       33            0 :     input logic [4:0]  waddr2,       // write address
       34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36        66208 :     input logic        clk,
+      36        14760 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
-      39           12 :     output logic [31:0] rd0,         // read data
-      40           18 :     output logic [31:0] rd1,
+      39            8 :     output logic [31:0] rd0,         // read data
+      40            8 :     output logic [31:0] rd1,
       41              : 
       42            0 :     input  logic        scan_mode
       43              : );
@@ -149,7 +149,7 @@
       45              :    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
       46              :    logic [31:1] [31:0] gpr_in;
       47            0 :    logic [31:1] w0v,w1v,w2v;
-      48           22 :    logic [31:1] gpr_wr_en;
+      48            4 :    logic [31:1] gpr_wr_en;
       49              : 
       50              :    // GPR Write Enables
       51              :    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_ib_ctl.sv.html
index 0a989b08ca1..2708523302e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,36 +129,36 @@
       25            0 :    input logic [1:0]           dbg_cmd_type,                       // dbg type
       26            0 :    input logic [31:0]          dbg_cmd_addr,                       // expand to 31:0
       27              : 
-      28           62 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
-      29          122 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30          554 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      28           12 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
+      29           20 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
+      30           10 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34         2237 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
-      35         4305 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
+      34          482 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      35          978 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
       38              : 
       39            0 :    input logic   ifu_i0_icaf_second,                               // i0 has access fault on second 2B of 4B inst
       40            0 :    input logic   ifu_i0_dbecc,                                     // i0 double-bit error
-      41          132 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
+      41           12 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
       42           10 :    input logic [31:1]  ifu_i0_pc,                                  // i0 pc from the aligner
       43              : 
       44              : 
-      45         4305 :    output logic dec_ib0_valid_d,                                   // ib0 valid
+      45          978 :    output logic dec_ib0_valid_d,                                   // ib0 valid
       46            0 :    output logic dec_debug_valid_d,                                 // Debug read or write at D-stage
       47              : 
       48              : 
-      49          132 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
+      49           12 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
       50              : 
       51           10 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53         2237 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53          482 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
-      55           62 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
-      56          122 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57          554 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      55           12 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
+      56           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      57           10 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
@@ -185,7 +185,7 @@
       81            0 :    logic         debug_read_csr;
       82            0 :    logic         debug_write_csr;
       83              : 
-      84          118 :    logic [34:0]  ifu_i0_pcdata, pc0;
+      84           16 :    logic [34:0]  ifu_i0_pcdata, pc0;
       85              : 
       86              :    assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
       87              :                                   ifu_i0_pc[31:1], ifu_i0_pc4 };
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_pmp_ctl.sv.html
index 2139ae64f81..36c5ddfa826 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,11 +133,11 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32        66208 :    input logic clk,
-      33        66208 :    input logic free_l2clk,
-      34        66208 :    input logic csr_wr_clk,
+      32        14760 :    input logic clk,
+      33        14760 :    input logic free_l2clk,
+      34        14760 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
-      36           18 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+      36            8 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
       37            8 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
       38            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       39            8 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52            0 :    input el2_mseccfg_pkt_t mseccfg,
+      52              :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_tlu_ctl.sv.html
index a78319ac471..33a3e21dae0 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32        66208 :    input logic clk,
-      33        66208 :    input logic free_clk,
-      34        66208 :    input logic free_l2clk,
+      32        14760 :    input logic clk,
+      33        14760 :    input logic free_clk,
+      34        14760 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
@@ -149,29 +149,29 @@
       45              : 
       46              : 
       47              :    // perf counter inputs
-      48         4305 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
-      49          272 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
-      50         4336 :    input logic       ifu_pmu_ic_miss, // icache miss
+      48          978 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
+      49           58 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
+      50          988 :    input logic       ifu_pmu_ic_miss, // icache miss
       51            0 :    input logic       ifu_pmu_ic_hit, // icache hit
       52            0 :    input logic       ifu_pmu_bus_error, // Instruction side bus error
       53            0 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
-      54         4336 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
-      55         4305 :    input logic       dec_pmu_instr_decoded, // decoded instructions
+      54          988 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
+      55          978 :    input logic       dec_pmu_instr_decoded, // decoded instructions
       56            0 :    input logic       dec_pmu_decode_stall, // decode stall
       57            0 :    input logic       dec_pmu_presync_stall, // decode stall due to presync'd inst
       58            0 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
       59            0 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
       60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
-      62          314 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63          706 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64          930 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
-      65         1548 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
+      62           64 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
+      63          232 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64          242 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      65          468 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
       66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
       68            0 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
-      69          660 :    input logic       lsu_pmu_load_external_m, // D side bus load
-      70          760 :    input logic       lsu_pmu_store_external_m, // D side bus store
+      69          228 :    input logic       lsu_pmu_load_external_m, // D side bus load
+      70          232 :    input logic       lsu_pmu_store_external_m, // D side bus store
       71            0 :    input logic       dma_pmu_dccm_read,          // DMA DCCM read
       72            0 :    input logic       dma_pmu_dccm_write,         // DMA DCCM write
       73            0 :    input logic       dma_pmu_any_read,           // DMA read
@@ -188,20 +188,20 @@
       84            0 :    input logic dec_pause_state, // Pause counter not zero
       85            0 :    input logic         lsu_imprecise_error_store_any,      // store bus error
       86            0 :    input logic         lsu_imprecise_error_load_any,      // store bus error
-      87          111 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
+      87          220 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
       88              : 
-      89           18 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
-      90           42 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
+      89            8 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
+      90           12 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
       91            8 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
       92              : 
-      93           18 :    input logic        dec_csr_wen_r,      // csr write enable at wb
-      94          970 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
+      93            8 :    input logic        dec_csr_wen_r,      // csr write enable at wb
+      94           36 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
       95            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
       96            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       97              : 
-      98           10 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
+      98            0 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
       99              : 
-     100         4304 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
+     100          976 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
      101              : 
      102            2 :    input logic [31:1] exu_npc_r, // for NPC tracking
      103              : 
@@ -210,21 +210,21 @@
      106            0 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
      107              : 
      108            0 :    input logic [31:0] dec_illegal_inst, // For mtval
-     109         4305 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
+     109          978 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112          576 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112          172 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115          746 :    input logic        exu_i0_br_valid_r, // valid
-     116          314 :    input logic        exu_i0_br_mp_r, // mispredict
-     117         1268 :    input logic        exu_i0_br_middle_r, // middle of bank
+     115          208 :    input logic        exu_i0_br_valid_r, // valid
+     116           64 :    input logic        exu_i0_br_mp_r, // mispredict
+     117          268 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
      119              :    // branch info from pipe1 for errors or counter updates
      120              : 
-     121          258 :    input logic             exu_i0_br_way_r, // way hit or repl
+     121            8 :    input logic             exu_i0_br_way_r, // way hit or repl
      122              : 
-     123         1280 :    output logic dec_tlu_core_empty,  // core is empty
+     123          268 :    output logic dec_tlu_core_empty,  // core is empty
      124              :    // Debug start
      125            0 :    output logic dec_dbg_cmd_done, // abstract command done
      126            0 :    output logic dec_dbg_cmd_fail, // abstract command failed
@@ -243,8 +243,8 @@
      139              : 
      140            0 :    input  logic dbg_halt_req, // DM requests a halt
      141            0 :    input  logic dbg_resume_req, // DM requests a resume
-     142         4336 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
-     143          969 :    input  logic lsu_idle_any, // lsu is idle
+     142          988 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
+     143          236 :    input  logic lsu_idle_any, // lsu is idle
      144            0 :    input  logic dec_div_active, // oop div is active
      145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
      146              : 
@@ -284,14 +284,14 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183           41 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184           42 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183            0 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184           12 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
-     186          258 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
+     186            8 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
      188            0 :    output logic dec_tlu_i0_kill_writeb_wb,    // I0 is flushed, don't writeback any results to arch state
      189            4 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
-     190         4304 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
+     190          976 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
      191              : 
      192            0 :    output logic dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      193            4 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
@@ -301,10 +301,10 @@
      197            0 :    output logic dec_tlu_flush_pause_r,        // Flush is due to pause
      198              : 
      199            0 :    output logic dec_tlu_presync_d,            // CSR read needs to be presync'd
-     200           30 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
+     200            0 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
      201              : 
      202              : 
-     203            0 :    output logic [31:0] dec_tlu_mrac_ff,        // CSR for memory region control
+     203            0 :    output logic [31:0] dec_tlu_mrac_ff,        // CSR for memory region control
      204              : 
      205            0 :    output logic dec_tlu_force_halt, // halt has been forced
      206              : 
@@ -314,7 +314,7 @@
      210            0 :    output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
      211              : 
      212            0 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
-     213         4304 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
+     213          976 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
      214            0 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
      215            0 :    output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
      216            0 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243            0 :    output logic  priv_mode,
-     244            2 :    output logic  priv_mode_eff,
-     245            0 :    output logic  priv_mode_ns,
+     243              :    output logic  priv_mode,
+     244              :    output logic  priv_mode_eff,
+     245              :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248            0 :    output logic [2:0] mseccfg,
+     248              :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275            0 :    logic wr_mcounteren_r;
-     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277            0 :    logic wr_mseccfg_r;
-     278            4 :    logic [2:0] mseccfg_ns;
+     275              :    logic wr_mcounteren_r;
+     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277              :    logic wr_mseccfg_r;
+     278              :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,9 +389,9 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286            0 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288            1 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290            0 :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -402,10 +402,10 @@
      298            0 :    logic [15:2] dcsr_ns, dcsr;
      299            0 :    logic [5:0] mip_ns, mip;
      300            0 :    logic [5:0] mie_ns, mie;
-     301           30 :    logic [31:0] mcyclel_ns, mcyclel;
+     301            6 :    logic [31:0] mcyclel_ns, mcyclel;
      302            0 :    logic [31:0] mcycleh_ns, mcycleh;
-     303            4 :    logic [31:0] minstretl_ns, minstretl;
-     304            0 :    logic [31:0] minstreth_ns, minstreth;
+     303            0 :    logic [31:0] minstretl_ns, minstretl;
+     304            0 :    logic [31:0] minstreth_ns, minstreth;
      305            0 :    logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;
      306            0 :    logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;
      307            0 :    logic [31:0] mscratch;
@@ -428,8 +428,8 @@
      324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
      325            4 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
      326            0 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
-     327         4304 :    logic i0_valid_wb;
-     328         4304 :    logic tlu_i0_commit_cmt;
+     327          976 :    logic i0_valid_wb;
+     328          976 :    logic tlu_i0_commit_cmt;
      329            0 :    logic [31:1] vectored_path, interrupt_path;
      330            0 :    logic [16:0] dicawics_ns, dicawics;
      331            0 :    logic        wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
@@ -444,22 +444,22 @@
      340            0 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
      341            0 :    logic synchronous_flush_r;
      342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
-     343          124 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
-     344           30 :    logic [31:0] mcyclel_inc;
+     343           28 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
+     344            6 :    logic [31:0] mcyclel_inc;
      345            0 :    logic [31:0] mcycleh_inc;
      346              : 
-     347           20 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
+     347            4 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
      348              : 
-     349            4 :    logic [31:0] minstretl_inc, minstretl_read;
-     350            0 :    logic [31:0] minstreth_inc, minstreth_read;
+     349            0 :    logic [31:0] minstretl_inc, minstretl_read;
+     350            0 :    logic [31:0] minstreth_inc, minstreth_read;
      351            2 :    logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;
-     352           42 :    logic valid_csr;
+     352           12 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355          560 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355          176 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
      357            0 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
-     358         4304 :    logic i0_trigger_eval_r;
+     358          976 :    logic i0_trigger_eval_r;
      359              : 
      360            0 :    logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
      361            4 :    logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
@@ -506,17 +506,17 @@
      402            8 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405        66208 :    logic csr_wr_clk;
+     405        14760 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
-     407          660 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
+     407          228 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
      409            0 :    logic lsu_single_ecc_error_r;
      410            0 :    logic [31:0] lsu_error_pkt_addr_r;
      411            2 :    logic mcyclel_cout_in;
-     412         4304 :    logic i0_valid_no_ebreak_ecall_r;
-     413         4304 :    logic minstret_enable_f;
+     412          976 :    logic i0_valid_no_ebreak_ecall_r;
+     413          976 :    logic minstret_enable_f;
      414            4 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
-     415         4304 :    logic pc0_valid_r;
+     415          976 :    logic pc0_valid_r;
      416            4 :    logic [15:0] mfdc_int, mfdc_ns;
      417            4 :    logic [31:0] mrac_in;
      418            4 :    logic [31:27] csr_sat;
@@ -535,13 +535,13 @@
      431            0 :    logic            mhpmc5h_wr_en0, mhpmc5h_wr_en;
      432            0 :    logic            mhpmc6h_wr_en0, mhpmc6h_wr_en;
      433            0 :    logic [63:0]     mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;
-     434           10 :    logic perfcnt_halted_d1, zero_event_r;
+     434            4 :    logic perfcnt_halted_d1, zero_event_r;
      435            0 :    logic [3:0] perfcnt_during_sleep;
      436            0 :    logic [9:0] event_r;
      437              : 
-     438         1132 :    el2_inst_pkt_t pmu_i0_itype_qual;
+     438          244 :    el2_inst_pkt_t pmu_i0_itype_qual;
      439              : 
-     440           18 :    logic dec_csr_wen_r_mod;
+     440            8 :    logic dec_csr_wen_r_mod;
      441              : 
      442            4 :    logic flush_clkvalid;
      443            0 :    logic sel_fir_addr;
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483            0 :    logic  csr_acc_r;    // CSR access error
-     484           15 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         1143 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483              :    logic  csr_acc_r;    // CSR access error
+     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994            0 :    logic csr_wr_acc_r;
-     995            0 :    logic csr_rd_acc_r;
+     994              :    logic csr_wr_acc_r;
+     995              :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568            0 :    logic  pmp_any_region_locked;
+    1568              :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
@@ -2828,11 +2828,11 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727        66208 :    input logic clk,
-    2728        66208 :    input logic free_l2clk,
-    2729        66208 :    input logic csr_wr_clk,
+    2727        14760 :    input logic clk,
+    2728        14760 :    input logic free_l2clk,
+    2729        14760 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
-    2731           18 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
+    2731            8 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
     2732            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
     2733            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
     2734              : 
@@ -2859,12 +2859,12 @@
     2755              :    localparam MITCTL_ENABLE_HALTED      = 1;
     2756              :    localparam MITCTL_ENABLE_PAUSED      = 2;
     2757              : 
-    2758           30 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
+    2758            6 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
     2759            0 :    logic [2:0] mitctl0_ns, mitctl0;
     2760            0 :    logic [3:0] mitctl1_ns, mitctl1;
     2761            0 :    logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
     2762            2 :    logic mitcnt0_inc_ok, mitcnt1_inc_ok;
-    2763          124 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
+    2763           28 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
     2764            0 :  logic mit0_match_ns;
     2765            0 :  logic mit1_match_ns;
     2766            0 :  logic mitctl0_0_b_ns;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_trigger.sv.html
index b299897a9dc..2bea51b77a0 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dma_ctrl.sv.html
index 7eba344aa38..42e9b670e9a 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29        66208 :    input logic         clk,
-      30        66208 :    input logic         free_clk,
+      29        14760 :    input logic         clk,
+      30        14760 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -173,8 +173,8 @@
       69            0 :    output logic        dma_active,         // DMA is busy
       70            0 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
       71            0 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
-      72         1422 :    input logic         dccm_ready, // dccm ready to accept DMA request
-      73          343 :    input logic         iccm_ready, // iccm ready to accept DMA request
+      72          462 :    input logic         dccm_ready, // dccm ready to accept DMA request
+      73           68 :    input logic         iccm_ready, // iccm ready to accept DMA request
       74            2 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
       75              : 
       76              :    // PMU signals
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185        66208 :    logic                    dma_buffer_c1_clk;
-     186        66208 :    logic                    dma_free_clk;
+     185        14760 :    logic                    dma_buffer_c1_clk;
+     186        14760 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu.sv.html
index 3290e4ce3db..6376149d3b3 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,46 +124,46 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        66208 :    input logic          clk,                                           // Top level clock
+      23        14760 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
-      27         4304 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
-      28         4304 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
+      27          976 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
+      28          976 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
       29            0 :    input logic  [31:0]  dbg_cmd_wrdata,                                // Debug data   to primary I0 RS1
       30            0 :    input el2_alu_pkt_t i0_ap,                                         // DEC alu {valid,predecodes}
       31              : 
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
-      34          232 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35          554 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
-      36          122 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
+      34           12 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
+      35           10 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      36           20 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
       39            0 :    input logic  [31:0]  lsu_result_m,                                  // Load result M-stage
-      40           14 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
-      41         3562 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
-      42         1556 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
-      43           12 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
-      44           18 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45          324 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
-      46           18 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
-      47          238 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
-      48         3113 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49         1167 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
-      50          244 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
+      40            0 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
+      41          924 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
+      42          244 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
+      43            8 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
+      44            8 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
+      45           16 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      46           16 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
+      47            8 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
+      48          530 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
+      49          246 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      50           20 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51           10 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
-      52           40 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      54           24 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55           41 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      54            4 :    input logic          dec_csr_ren_d,                                 // CSR read select
+      55            0 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57         3081 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57          532 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
       59            0 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
       61              : 
-      62          238 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
+      62           16 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
       63              : 
       64            4 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
       65            0 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
@@ -173,37 +173,37 @@
       69            0 :    input logic [31:2]  dec_tlu_meihap,                                 // External stall mux data
       70              : 
       71              : 
-      72          140 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
-      73            6 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
+      72          240 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
+      73            0 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
       74              : 
-      75          345 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
-      76          112 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
+      75           70 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
+      76            4 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
       77              : 
-      78          110 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
+      78           16 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
       79            2 :    output logic [31:1]  exu_i0_pc_x,                                   // Primary PC  result to DEC
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            2 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83          576 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83          172 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
-      86           26 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87          746 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
-      88          314 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
-      89         1268 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90          122 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
-      91          258 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
+      86            4 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
+      87          208 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      88           64 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
+      89          268 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
+      90            2 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      91            8 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
-      93            2 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
-      94          206 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95          122 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      96          108 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      93            0 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
+      94           20 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
+      95            2 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      96            4 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
-     100          314 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101          706 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102          930 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     100           64 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
+     101          232 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102          242 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105            0 :    output logic [31:0]  exu_div_result,                                // Divide result
@@ -214,49 +214,49 @@
      110              : 
      111              : 
      112            4 :    logic [31:0]                i0_rs1_bypass_data_d;
-     113            4 :    logic [31:0]                i0_rs2_bypass_data_d;
-     114          196 :    logic                       i0_rs1_bypass_en_d;
-     115           32 :    logic                       i0_rs2_bypass_en_d;
-     116           12 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
-     117           12 :    logic [31:0]                muldiv_rs1_d;
-     118          238 :    logic [31:1]                pred_correct_npc_r;
-     119          718 :    logic                       i0_pred_correct_upper_r;
+     113            0 :    logic [31:0]                i0_rs2_bypass_data_d;
+     114            4 :    logic                       i0_rs1_bypass_en_d;
+     115            0 :    logic                       i0_rs2_bypass_en_d;
+     116            8 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
+     117            8 :    logic [31:0]                muldiv_rs1_d;
+     118           16 :    logic [31:1]                pred_correct_npc_r;
+     119          180 :    logic                       i0_pred_correct_upper_r;
      120            2 :    logic [31:1]                i0_flush_path_upper_r;
-     121           24 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
-     122         4304 :    logic                       x_ctl_en,  r_ctl_en;
+     121            4 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
+     122          976 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124          122 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125          122 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126          713 :    logic                       i0_taken_d;
-     127          712 :    logic                       i0_taken_x;
-     128          746 :    logic                       i0_valid_d;
-     129          746 :    logic                       i0_valid_x;
-     130          122 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124            2 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125            2 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126          234 :    logic                       i0_taken_d;
+     127          232 :    logic                       i0_taken_x;
+     128          208 :    logic                       i0_valid_d;
+     129          208 :    logic                       i0_valid_x;
+     130            2 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
-     132            2 :    el2_predict_pkt_t          final_predict_mp;
-     133          232 :    el2_predict_pkt_t          i0_predict_newp_d;
+     132            0 :    el2_predict_pkt_t          final_predict_mp;
+     133           12 :    el2_predict_pkt_t          i0_predict_newp_d;
      134              : 
      135            0 :    logic                       flush_in_d;
-     136          110 :    logic [31:0]                alu_result_x;
+     136           16 :    logic [31:0]                alu_result_x;
      137              : 
      138            0 :    logic                       mul_valid_x;
      139            0 :    logic [31:0]                mul_result_x;
      140              : 
-     141          118 :    el2_predict_pkt_t          i0_pp_r;
+     141            8 :    el2_predict_pkt_t          i0_pp_r;
      142              : 
-     143          341 :    logic                       i0_flush_upper_d;
+     143           66 :    logic                       i0_flush_upper_d;
      144           10 :    logic [31:1]                i0_flush_path_d;
-     145          232 :    el2_predict_pkt_t          i0_predict_p_d;
-     146          718 :    logic                       i0_pred_correct_upper_d;
+     145           12 :    el2_predict_pkt_t          i0_predict_p_d;
+     146          180 :    logic                       i0_pred_correct_upper_d;
      147              : 
-     148          340 :    logic                       i0_flush_upper_x;
+     148           64 :    logic                       i0_flush_upper_x;
      149            2 :    logic [31:1]                i0_flush_path_x;
-     150          118 :    el2_predict_pkt_t          i0_predict_p_x;
-     151          718 :    logic                       i0_pred_correct_upper_x;
-     152         1166 :    logic                       i0_branch_x;
+     150            8 :    el2_predict_pkt_t          i0_predict_p_x;
+     151          180 :    logic                       i0_pred_correct_upper_x;
+     152          244 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
-     155          110 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
+     155            8 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
      156              : 
      157              : 
      158              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_alu_ctl.sv.html
index 8aa8663c0a9..dfc17e07b7f 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,52 +124,52 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        66208 :    input  logic                  clk,                // Top level clock
+      23        14760 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
-      27          340 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
+      27           64 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
       28            4 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
-      29         4305 :    input  logic                  enable,             // Clock enable
-      30         3113 :    input  logic                  valid_in,           // Valid
+      29          978 :    input  logic                  enable,             // Clock enable
+      30          530 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
-      32           24 :    input  logic                  csr_ren_in,         // CSR select
-      33           41 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34           12 :    input  logic signed [31:0]    a_in,               // A operand
-      35          348 :    input  logic        [31:0]    b_in,               // B operand
+      32            4 :    input  logic                  csr_ren_in,         // CSR select
+      33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34            8 :    input  logic signed [31:0]    a_in,               // A operand
+      35           24 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
-      37          232 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
-      38          238 :    input  logic        [12:1]    brimm_in,           // Branch offset
+      37           12 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
+      38            8 :    input  logic        [12:1]    brimm_in,           // Branch offset
       39              : 
       40              : 
-      41          110 :    output logic        [31:0]    result_ff,          // final result
-      42          341 :    output logic                  flush_upper_out,    // Branch flush
-      43          345 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
+      41           16 :    output logic        [31:0]    result_ff,          // final result
+      42           66 :    output logic                  flush_upper_out,    // Branch flush
+      43           70 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
       44           10 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            2 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46          718 :    output logic                  pred_correct_out,   // NPC control
-      47          232 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
+      46          180 :    output logic                  pred_correct_out,   // NPC control
+      47           12 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
       50              : 
-      51           12 :    logic               [31:0]    zba_a_in;
-      52          130 :    logic               [31:0]    aout;
-      53          120 :    logic                         cout,ov,neg;
+      51            8 :    logic               [31:0]    zba_a_in;
+      52           24 :    logic               [31:0]    aout;
+      53            4 :    logic                         cout,ov,neg;
       54            0 :    logic               [31:0]    lout;
-      55           12 :    logic               [31:0]    sout;
-      56          112 :    logic                         sel_shift;
-      57         2685 :    logic                         sel_adder;
+      55            8 :    logic               [31:0]    sout;
+      56            0 :    logic                         sel_shift;
+      57          494 :    logic                         sel_adder;
       58            0 :    logic                         slt_one;
-      59          713 :    logic                         actual_taken;
+      59          234 :    logic                         actual_taken;
       60           10 :    logic               [31:1]    pcout;
-      61          271 :    logic                         cond_mispredict;
-      62           62 :    logic                         target_mispredict;
-      63         2770 :    logic                         eq, ne, lt, ge;
-      64          216 :    logic                         any_jal;
-      65          651 :    logic               [1:0]     newhist;
-      66          216 :    logic                         sel_pc;
-      67           12 :    logic               [31:0]    csr_write_data;
-      68          122 :    logic               [31:0]    result;
+      61           66 :    logic                         cond_mispredict;
+      62            8 :    logic                         target_mispredict;
+      63          736 :    logic                         eq, ne, lt, ge;
+      64           20 :    logic                         any_jal;
+      65           68 :    logic               [1:0]     newhist;
+      66           20 :    logic                         sel_pc;
+      67            8 :    logic               [31:0]    csr_write_data;
+      68           24 :    logic               [31:0]    result;
       69              : 
       70              : 
       71              : 
@@ -348,7 +348,7 @@
      244              :                                 ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |
      245              :                                 ( {32{~ap_zba   }} &  a_in[31:0]       );
      246              : 
-     247         1263 :    logic        [31:0]    bm;
+     247          250 :    logic        [31:0]    bm;
      248              : 
      249              :    assign bm[31:0]            = ( ap.sub )  ?  ~b_in[31:0]  :  b_in[31:0];
      250              : 
@@ -383,8 +383,8 @@
      279              : 
      280            0 :    logic        [5:0]     shift_amount;
      281            2 :    logic        [31:0]    shift_mask;
-     282          214 :    logic        [62:0]    shift_extend;
-     283          210 :    logic        [62:0]    shift_long;
+     282           12 :    logic        [62:0]    shift_extend;
+     283           12 :    logic        [62:0]    shift_long;
      284              : 
      285              : 
      286              :    assign shift_amount[5:0]            = ( { 6{ap.sll}}   & (6'd32 - {1'b0,b_in[4:0]}) ) |   // [5] unused
@@ -416,7 +416,7 @@
      312              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CLZ,CTZ      * * * * * * * * * * * * * * * * * *
      313              : 
      314            0 :    logic                  bitmanip_clz_ctz_sel;
-     315           12 :    logic        [31:0]    bitmanip_a_reverse_ff;
+     315            8 :    logic        [31:0]    bitmanip_a_reverse_ff;
      316            0 :    logic        [31:0]    bitmanip_lzd_in;
      317            2 :    logic        [5:0]     bitmanip_dw_lzd_enc;
      318            0 :    logic        [5:0]     bitmanip_clz_ctz_result;
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342      1140288 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343      1140288 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342       645184 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343       645184 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
@@ -460,7 +460,7 @@
      356              : 
      357              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CPOP         * * * * * * * * * * * * * * * * * *
      358              : 
-     359            6 :    logic        [5:0]     bitmanip_cpop;
+     359            8 :    logic        [5:0]     bitmanip_cpop;
      360            0 :    logic        [5:0]     bitmanip_cpop_result;
      361              : 
      362              : 
@@ -499,7 +499,7 @@
      395              : 
      396              :    assign bitmanip_minmax_sel          =  ap_min | ap_max;
      397              : 
-     398         2772 :    logic                  bitmanip_minmax_sel_a;
+     398          738 :    logic                  bitmanip_minmax_sel_a;
      399              : 
      400              :    assign bitmanip_minmax_sel_a        =  ge  ^ ap_min;
      401              : 
@@ -557,7 +557,7 @@
      453              : 
      454              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  ZBSET, ZBCLR, ZBINV  * * * * * * * * * * * * * *
      455              : 
-     456           22 :    logic        [31:0]    bitmanip_sb_1hot;
+     456            4 :    logic        [31:0]    bitmanip_sb_1hot;
      457            0 :    logic        [31:0]    bitmanip_sb_data;
      458              : 
      459              :    assign bitmanip_sb_1hot[31:0]       = ( 32'h00000001 << b_in[4:0] );
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_div_ctl.sv.html
index f715c0ef9be..57cbf2bf2de 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,13 +124,13 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        66208 :    input logic           clk,                       // Top level clock
+      23        14760 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
       27            0 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
-      28           12 :    input logic  [31:0]   dividend,                  // Numerator
-      29          348 :    input logic  [31:0]   divisor,                   // Denominator
+      28            8 :    input logic  [31:0]   dividend,                  // Numerator
+      29           24 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
@@ -1414,16 +1414,16 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313        66208 :    input  logic            clk,                       // Top level clock
+    1313        14760 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
     1317            0 :    input  logic            cancel,                    // Flush pipeline
     1318            0 :    input  logic            valid_in,
-    1319          552 :    input  logic            signed_in,
+    1319          218 :    input  logic            signed_in,
     1320            0 :    input  logic            rem_in,
-    1321           12 :    input  logic [31:0]     dividend_in,
-    1322          348 :    input  logic [31:0]     divisor_in,
+    1321            8 :    input  logic [31:0]     dividend_in,
+    1322           24 :    input  logic [31:0]     divisor_in,
     1323              : 
     1324            0 :    output logic            valid_out,
     1325            0 :    output logic [31:0]     data_out
@@ -1446,7 +1446,7 @@
     1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
     1344            0 :    logic                   b_enable, b_twos_comp;
-    1345          348 :    logic        [32:0]     b_in;
+    1345           24 :    logic        [32:0]     b_in;
     1346            0 :    logic        [37:0]     b_ff;
     1347              : 
     1348            0 :    logic        [31:0]     q_in, q_ff;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_mul_ctl.sv.html
index 7f526530b10..7c22bf1dcf6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23        66208 :    input logic          clk,              // Top level clock
+      23        14760 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209      1140288 :              if (bcompress_test_bit_d)
+     209       645184 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236      1140288 :              if (bdecompress_test_bit_d)
+     236       645184 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu.sv.html
index 31ed3486716..a89f30dd69c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,18 +129,18 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28        66208 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29        66208 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30        66208 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28        14760 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        14760 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        14760 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
-      33         4305 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
+      33          978 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
       34              : 
-      35          345 :    input logic exu_flush_final, // flush, includes upper and lower
-      36         4304 :    input logic dec_tlu_i0_commit_cmt , // committed i0
+      35           70 :    input logic exu_flush_final, // flush, includes upper and lower
+      36          976 :    input logic dec_tlu_i0_commit_cmt , // committed i0
       37            0 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
       38            0 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
-      39          112 :    input logic [31:1] exu_flush_path_final, // flush fetch address
+      39            4 :    input logic [31:1] exu_flush_path_final, // flush fetch address
       40              : 
       41            0 :    input logic [31:0]  dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
       42            0 :    input logic         dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
@@ -172,10 +172,10 @@
       68            0 :    output logic                            ifu_axi_bready,
       69              : 
       70              :    // AXI Read Channels
-      71         4336 :    output logic                            ifu_axi_arvalid,
-      72         4336 :    input  logic                            ifu_axi_arready,
-      73         2620 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      74         1684 :    output logic [31:0]                     ifu_axi_araddr,
+      71          988 :    output logic                            ifu_axi_arvalid,
+      72          988 :    input  logic                            ifu_axi_arready,
+      73          512 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      74           20 :    output logic [31:0]                     ifu_axi_araddr,
       75            2 :    output logic [3:0]                      ifu_axi_arregion,
       76            0 :    output logic [7:0]                      ifu_axi_arlen,
       77            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -185,10 +185,10 @@
       81            2 :    output logic [2:0]                      ifu_axi_arprot,
       82            0 :    output logic [3:0]                      ifu_axi_arqos,
       83              : 
-      84         8669 :    input  logic                            ifu_axi_rvalid,
+      84         1974 :    input  logic                            ifu_axi_rvalid,
       85            2 :    output logic                            ifu_axi_rready,
-      86         1120 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-      87          576 :    input  logic [63:0]                     ifu_axi_rdata,
+      86          446 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+      87           16 :    input  logic [63:0]                     ifu_axi_rdata,
       88            0 :    input  logic [1:0]                      ifu_axi_rresp,
       89              : 
       90            2 :    input  logic                      ifu_bus_clk_en,
@@ -206,10 +206,10 @@
      102            0 :    output logic                      iccm_dma_rvalid,
      103            0 :    output logic [63:0]               iccm_dma_rdata,
      104            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     105          343 :    output logic                      iccm_ready,
+     105           68 :    output logic                      iccm_ready,
      106              : 
-     107         4305 :    output logic       ifu_pmu_instr_aligned,
-     108          272 :    output logic       ifu_pmu_fetch_stall,
+     107          978 :    output logic       ifu_pmu_instr_aligned,
+     108           58 :    output logic       ifu_pmu_fetch_stall,
      109            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
      110              : 
      111              : //   I$ & ITAG Ports
@@ -217,8 +217,8 @@
      113            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      114            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      115              : 
-     116          150 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     117          962 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     116           16 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     117           44 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      118            0 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      119            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
      120            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
@@ -227,8 +227,8 @@
      123              : 
      124            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
      125            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     126          962 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     127         3842 :    output logic                      ic_sel_premux_data, // Select the premux data.
+     126           44 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     127          970 :    output logic                      ic_sel_premux_data, // Select the premux data.
      128              : 
      129            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      130            0 :    output logic                      ic_debug_rd_en,     // Icache debug rd
@@ -244,7 +244,7 @@
      140              : 
      141              : 
      142              :    // ICCM ports
-     143           26 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
+     143            4 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
      144            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
      145            0 :    output logic                      iccm_rden,          // ICCM read enable.
      146            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
@@ -259,46 +259,46 @@
      155            0 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
      156              : 
      157              : // Perf counter sigs
-     158         4336 :    output logic       ifu_pmu_ic_miss, // ic miss
+     158          988 :    output logic       ifu_pmu_ic_miss, // ic miss
      159            0 :    output logic       ifu_pmu_ic_hit, // ic hit
      160            0 :    output logic       ifu_pmu_bus_error, // iside bus error
      161            0 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
-     162         4336 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
+     162          988 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
      163              : 
      164              : 
      165            0 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
      166            0 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
      167              : 
-     168         4305 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
+     168          978 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
      169            0 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
      170            0 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
-     172          132 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
+     172           12 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173           10 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174         2237 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174          482 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
-     176         4336 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
+     176          988 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
-     178           62 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
-     179          122 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180          554 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     178           12 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
+     179           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
+     180           10 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
-     184            2 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
-     185          206 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186          122 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-     187          108 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+     184            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+     185           20 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
+     186            2 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     187            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
-     190          258 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191          122 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-     192           26 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+     190            8 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
+     191            2 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     192            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
      195            4 :    input dec_tlu_flush_lower_wb,
      196              : 
-     197          704 :    output logic [15:0] ifu_i0_cinst,
+     197          232 :    output logic [15:0] ifu_i0_cinst,
      198              : 
      199            2 :     output logic [31:1] ifu_pmp_addr,
      200            0 :     input  logic        ifu_pmp_error,
@@ -315,12 +315,12 @@
      211              :    localparam TAGWIDTH = 2 ;
      212              :    localparam IDWIDTH  = 2 ;
      213              : 
-     214          256 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
+     214          208 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
      215            2 :    logic [31:1]            ifc_fetch_addr_f;
      216            2 :    logic [31:1]            ifc_fetch_addr_bf;
      217              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
      218              : 
-     219         3820 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
+     219          596 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
      220            2 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
      221              : 
      222            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
@@ -329,33 +329,33 @@
      225              :    assign ifu_ic_error_start = ic_error_start;
      226              : 
      227              : 
-     228         1848 :    logic        ic_write_stall;
+     228          488 :    logic        ic_write_stall;
      229            0 :    logic        ic_dma_active;
-     230          347 :    logic        ifc_dma_access_ok;
+     230           72 :    logic        ifc_dma_access_ok;
      231            0 :    logic [1:0]  ic_access_fault_f;
      232            0 :    logic [1:0]  ic_access_fault_type_f;
-     233         4342 :    logic        ifu_ic_mb_empty;
+     233          996 :    logic        ifu_ic_mb_empty;
      234              : 
-     235         4328 :    logic ic_hit_f;
+     235          980 :    logic ic_hit_f;
      236              : 
-     237          546 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238          716 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
-     239          136 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240          440 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
-     241          380 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
-     242          306 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243          340 :    logic [11:0] ifu_bp_poffset_f; // predicted target
-     244           16 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
-     245          170 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
-     246          418 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247          122 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     237          208 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
+     238          352 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     239            0 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
+     240          354 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     241            8 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
+     242            8 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
+     243          352 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     244            0 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
+     245            0 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
+     246            0 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
+     247            2 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
-     251         3820 :    logic [1:0]   ic_fetch_val_f;
-     252         1026 :    logic [31:0] ic_data_f;
-     253         1026 :    logic [31:0] ifu_fetch_data_f;
-     254         2154 :    logic ifc_fetch_req_f;
+     251          596 :    logic [1:0]   ic_fetch_val_f;
+     252           44 :    logic [31:0] ic_data_f;
+     253           44 :    logic [31:0] ifu_fetch_data_f;
+     254          662 :    logic ifc_fetch_req_f;
      255            0 :    logic ifc_fetch_req_f_raw;
      256            0 :    logic iccm_dma_rd_ecc_double_err;
      257            0 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
@@ -369,7 +369,7 @@
      265              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
      266              : 
      267            2 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
-     268         2154 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
+     268          662 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
      269            2 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
      270            0 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
      271            0 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_aln_ctl.sv.html
index 48d2ed580a8..2584c605ff0 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30        66208 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31        66208 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        14760 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        14760 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -141,166 +141,166 @@
       37            0 :    input logic [1:0]                              ic_access_fault_f,        // Instruction access fault for the current fetch.
       38            0 :    input logic [1:0]                              ic_access_fault_type_f,   // Instruction access fault types
       39              : 
-      40          345 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
+      40           70 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
       41              : 
-      42         4305 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
+      42          978 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
       43              : 
-      44         1026 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
+      44           44 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
       45              : 
-      46         3820 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
+      46          596 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
       47            2 :    input logic [31:1]                             ifu_fetch_pc,             // starting pc of fetch
       48              : 
       49              : 
       50              : 
-      51         4305 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
+      51          978 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
       52            0 :    output logic                                   ifu_i0_icaf,              // Instruction 0 has access fault
       53            0 :    output logic [1:0]                             ifu_i0_icaf_type,         // Instruction 0 access fault type
       54            0 :    output logic                                   ifu_i0_icaf_second,       // Instruction 0 has access fault on second 2B of 4B inst
       55              : 
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
-      57          132 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
+      57           12 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58           10 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59         2237 :    output logic                                   ifu_i0_pc4,
+      59          482 :    output logic                                   ifu_i0_pc4,
       60              : 
-      61         3178 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62          256 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      61          480 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
+      62          208 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65          122 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
-      66          136 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67          340 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      65            2 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      66            0 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
+      67          352 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
-      70          306 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
-      71          380 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
-      72          170 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
-      73          546 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
-      74          418 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
-      75           16 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
+      70            8 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
+      71            8 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
+      72            0 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
+      73          208 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
+      74            0 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
+      75            0 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
       76              : 
       77              : 
-      78           62 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
-      79          122 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80          554 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      78           12 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
+      79           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
+      80           10 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
       84              : 
-      85         4305 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
+      85          978 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
       86              : 
-      87          704 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
+      87          232 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
       88              :    );
       89              : 
       90              : 
       91              : 
-      92         4328 :    logic                                          ifvalid;
+      92          980 :    logic                                          ifvalid;
       93            0 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
       94            0 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
       95              : 
       96            0 :    logic [1:0]                                    f2val_in, f2val;
-      97          861 :    logic [1:0]                                    f1val_in, f1val;
-      98         2958 :    logic [1:0]                                    f0val_in, f0val;
+      97           30 :    logic [1:0]                                    f1val_in, f1val;
+      98          564 :    logic [1:0]                                    f0val_in, f0val;
       99            0 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
-     101          613 :    logic [31:0]                                   aligndata;
-     102         2237 :    logic                                          first4B, first2B;
+     101           50 :    logic [31:0]                                   aligndata;
+     102          482 :    logic                                          first4B, first2B;
      103              : 
-     104          128 :    logic [31:0]                                   uncompress0;
-     105         4305 :    logic                                          i0_shift;
-     106         1783 :    logic                                          shift_2B, shift_4B;
-     107         1125 :    logic                                          f1_shift_2B;
-     108          861 :    logic                                          f2_valid, sf1_valid, sf0_valid;
+     104            4 :    logic [31:0]                                   uncompress0;
+     105          978 :    logic                                          i0_shift;
+     106          494 :    logic                                          shift_2B, shift_4B;
+     107          238 :    logic                                          f1_shift_2B;
+     108           30 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
-     110          613 :    logic [31:0]                                   ifirst;
-     111         3201 :    logic [1:0]                                    alignval;
-     112         1298 :    logic [31:1]                                   firstpc, secondpc;
+     110           50 :    logic [31:0]                                   ifirst;
+     111          738 :    logic [1:0]                                    alignval;
+     112           16 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114          136 :    logic [11:0]                                   f1poffset;
-     115          332 :    logic [11:0]                                   f0poffset;
-     116          146 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117          450 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
-     118          329 :    logic [1:0]                                    f1hist1;
-     119          630 :    logic [1:0]                                    f0hist1;
-     120          299 :    logic [1:0]                                    f1hist0;
-     121          514 :    logic [1:0]                                    f0hist0;
+     114            0 :    logic [11:0]                                   f1poffset;
+     115          348 :    logic [11:0]                                   f0poffset;
+     116            2 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117            6 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     118            4 :    logic [1:0]                                    f1hist1;
+     119            4 :    logic [1:0]                                    f0hist1;
+     120            4 :    logic [1:0]                                    f1hist0;
+     121            0 :    logic [1:0]                                    f0hist0;
      122              : 
-     123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
+     123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
      124              : 
      125            0 :    logic [1:0]                                    f1ictype;
      126            0 :    logic [1:0]                                    f0ictype;
      127              : 
-     128          152 :    logic [1:0]                                    f1pc4;
-     129          356 :    logic [1:0]                                    f0pc4;
+     128            0 :    logic [1:0]                                    f1pc4;
+     129            0 :    logic [1:0]                                    f0pc4;
      130              : 
-     131            0 :    logic [1:0]                                    f1ret;
-     132           14 :    logic [1:0]                                    f0ret;
-     133          112 :    logic [1:0]                                    f1way;
-     134          388 :    logic [1:0]                                    f0way;
+     131            0 :    logic [1:0]                                    f1ret;
+     132            0 :    logic [1:0]                                    f0ret;
+     133            0 :    logic [1:0]                                    f1way;
+     134          208 :    logic [1:0]                                    f0way;
      135              : 
-     136          213 :    logic [1:0]                                    f1brend;
-     137          368 :    logic [1:0]                                    f0brend;
+     136            0 :    logic [1:0]                                    f1brend;
+     137            0 :    logic [1:0]                                    f0brend;
      138              : 
-     139          284 :    logic [1:0]                                    alignbrend;
-     140          358 :    logic [1:0]                                    alignpc4;
+     139            0 :    logic [1:0]                                    alignbrend;
+     140            0 :    logic [1:0]                                    alignpc4;
      141              : 
-     142           22 :    logic [1:0]                                    alignret;
-     143          336 :    logic [1:0]                                    alignway;
-     144          422 :    logic [1:0]                                    alignhist1;
-     145          344 :    logic [1:0]                                    alignhist0;
-     146         1423 :    logic [1:1]                                    alignfromf1;
-     147          575 :    logic                                          i0_ends_f1;
+     142            0 :    logic [1:0]                                    alignret;
+     143            8 :    logic [1:0]                                    alignway;
+     144            4 :    logic [1:0]                                    alignhist1;
+     145            0 :    logic [1:0]                                    alignhist0;
+     146          438 :    logic [1:1]                                    alignfromf1;
+     147          226 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
-     150          112 :    logic [31:1]                                   f1prett;
-     151          156 :    logic [31:1]                                   f0prett;
-     152            0 :    logic [1:0]                                    f1dbecc;
+     150            0 :    logic [31:1]                                   f1prett;
+     151            0 :    logic [31:1]                                   f0prett;
+     152            0 :    logic [1:0]                                    f1dbecc;
      153            0 :    logic [1:0]                                    f0dbecc;
      154            0 :    logic [1:0]                                    f1icaf;
      155            0 :    logic [1:0]                                    f0icaf;
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159          358 :    logic                                          i0_brp_pc4;
+     159            0 :    logic                                          i0_brp_pc4;
      160              : 
-     161          118 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
+     161           16 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165         1433 :    logic [1:0]                                    wrptr, wrptr_in;
-     166         1245 :    logic [1:0]                                    rdptr, rdptr_in;
-     167         1342 :    logic [2:0]                                    qwen;
-     168          128 :    logic [31:0]                                   q2,q1,q0;
-     169          829 :    logic                                          q2off_in, q2off;
-     170          893 :    logic                                          q1off_in, q1off;
-     171          940 :    logic                                          q0off_in, q0off;
-     172         2643 :    logic                                          f0_shift_2B;
+     165          312 :    logic [1:0]                                    wrptr, wrptr_in;
+     166          220 :    logic [1:0]                                    rdptr, rdptr_in;
+     167          308 :    logic [2:0]                                    qwen;
+     168            4 :    logic [31:0]                                   q2,q1,q0;
+     169          210 :    logic                                          q2off_in, q2off;
+     170          234 :    logic                                          q1off_in, q1off;
+     171          272 :    logic                                          q0off_in, q0off;
+     172          722 :    logic                                          f0_shift_2B;
      173              : 
-     174          788 :    logic [31:0]                                   q0eff;
-     175          748 :    logic [31:0]                                   q0final;
-     176         2273 :    logic                                          q0ptr;
-     177         2273 :    logic [1:0]                                    q0sel;
+     174           44 :    logic [31:0]                                   q0eff;
+     175           36 :    logic [31:0]                                   q0final;
+     176          698 :    logic                                          q0ptr;
+     177          698 :    logic [1:0]                                    q0sel;
      178              : 
-     179          526 :    logic [31:0]                                   q1eff;
-     180          513 :    logic [15:0]                                   q1final;
-     181         1164 :    logic                                          q1ptr;
-     182         1164 :    logic [1:0]                                    q1sel;
+     179           20 :    logic [31:0]                                   q1eff;
+     180           22 :    logic [15:0]                                   q1final;
+     181          244 :    logic                                          q1ptr;
+     182          244 :    logic [1:0]                                    q1sel;
      183              : 
-     184         1245 :    logic [2:0]                                    qren;
+     184          220 :    logic [2:0]                                    qren;
      185              : 
-     186          264 :    logic                                          consume_fb1, consume_fb0;
+     186          208 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
      190              :    localparam                                     BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
-     191           73 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
-     192           24 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
-     193           14 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
+     191            0 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
+     192            0 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
+     193            0 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
      194              : 
      195              :    localparam                                     MHI   = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
-     198           67 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199          411 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     198            2 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
+     199            6 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201            0 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_bp_ctl.sv.html
index 113ac93fc9e..fda4ce350eb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,17 +135,17 @@
       31              :  )
       32              :   (
       33              : 
-      34        66208 :    input logic clk,
+      34        14760 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
-      37         4328 :    input logic ic_hit_f,      // Icache hit, enables F address capture
+      37          980 :    input logic ic_hit_f,      // Icache hit, enables F address capture
       38              : 
       39            2 :    input logic [31:1] ifc_fetch_addr_f, // look up btb address
-      40         2154 :    input logic ifc_fetch_req_f,  // F1 valid
+      40          662 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
-      42          258 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43          122 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-      44           26 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+      42            8 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
+      43            2 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      44            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
       47              : 
@@ -154,28 +154,28 @@
       50              : 
       51            0 :    input logic dec_tlu_bpred_disable, // disable all branch prediction
       52              : 
-      53            2 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+      53            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
-      55          206 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56          122 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      57          108 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      55           20 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
+      56            2 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      57            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
-      60          345 :    input logic exu_flush_final, // all flushes
+      60           70 :    input logic exu_flush_final, // all flushes
       61              : 
-      62          716 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
-      63          136 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64          440 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      62          352 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      63            0 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      64          354 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66          122 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66            2 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
-      68          546 :    output logic [1:0] ifu_bp_way_f, // way
-      69           16 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
-      70          380 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
-      71          306 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
-      72          170 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
-      73          418 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74          340 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      68          208 :    output logic [1:0] ifu_bp_way_f, // way
+      69            0 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
+      70            8 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
+      71            8 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
+      72            0 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
+      73            0 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
+      74          352 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -205,77 +205,77 @@
      101              :    localparam BHT_NO_ADDR_MATCH  = ( pt.BHT_ARRAY_DEPTH <= 16 );
      102              : 
      103              : 
-     104          100 :    logic exu_mp_valid_write;
-     105          306 :    logic exu_mp_ataken;
-     106          320 :    logic exu_mp_valid; // conditional branch mispredict
-     107          166 :    logic exu_mp_boffset; // branch offsett
-     108           96 :    logic exu_mp_pc4; // branch is a 4B inst
-     109           46 :    logic exu_mp_call; // branch is a call inst
-     110           62 :    logic exu_mp_ret; // branch is a ret inst
-     111           14 :    logic exu_mp_ja; // branch is a jump always
-     112           86 :    logic [1:0] exu_mp_hist; // new history
-     113           94 :    logic [11:0] exu_mp_tgt; // target offset
-     114          108 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115          560 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116          576 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
-     117           26 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
+     104           28 :    logic exu_mp_valid_write;
+     105           60 :    logic exu_mp_ataken;
+     106           64 :    logic exu_mp_valid; // conditional branch mispredict
+     107           12 :    logic exu_mp_boffset; // branch offsett
+     108            4 :    logic exu_mp_pc4; // branch is a 4B inst
+     109            8 :    logic exu_mp_call; // branch is a call inst
+     110            8 :    logic exu_mp_ret; // branch is a ret inst
+     111            4 :    logic exu_mp_ja; // branch is a jump always
+     112           64 :    logic [1:0] exu_mp_hist; // new history
+     113            8 :    logic [11:0] exu_mp_tgt; // target offset
+     114            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
+     115          176 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116          172 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     117            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120          122 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120            2 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122            0 :    logic use_mp_way, use_mp_way_p1;
      123            0 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
-     124           36 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
+     124            0 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127          340 :    logic [11:0]       btb_rd_tgt_f;
-     128          108 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
-     129          675 :    logic [1:1]        bp_total_branch_offset_f;
+     127          352 :    logic [11:0]       btb_rd_tgt_f;
+     128            0 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
+     129          390 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
      131            2 :    logic [31:1]       bp_btb_target_adder_f;
      132            2 :    logic [31:1]       bp_rs_call_target_f;
-     133           37 :    logic              rs_push, rs_pop, rs_hold;
-     134           26 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
+     133            2 :    logic              rs_push, rs_pop, rs_hold;
+     134            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
      135            0 :    logic [pt.BTB_BTAG_SIZE-1:0] btb_wr_tag, fetch_rd_tag_f, fetch_rd_tag_p1_f;
-     136           56 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
-     137            2 :    logic               btb_wr_en_way0, btb_wr_en_way1;
+     136            4 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
+     137            0 :    logic               btb_wr_en_way0, btb_wr_en_way1;
      138              : 
      139              : 
-     140          320 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
-     141           26 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
+     140           64 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
+     141            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
      142            0 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144            0 :    logic  branch_error_bank_conflict_f;
-     145          122 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145            2 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146            0 :    logic [1:0] num_valids;
      147            0 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
      148            0 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
      149            0 :                         mp_wrindex_dec, mp_wrlru_b0;
-     150          666 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
+     150          208 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
      151            0 :    logic  tag_match_way0_f, tag_match_way1_f;
-     152          262 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
-     153           84 :    logic [1:0] bht_valid_f, bht_force_taken_f;
+     152            0 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
+     153            0 :    logic [1:0] bht_valid_f, bht_force_taken_f;
      154              : 
-     155            0 :    logic leak_one_f, leak_one_f_d1;
+     155            0 :    logic leak_one_f, leak_one_f_d1;
      156              : 
      157              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way0_out ;
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161          250 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     161          212 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
      162            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
-     164          210 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
+     164          208 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
      165            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
      166              : 
-     167           90 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
+     167            0 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169          716 :    logic                                         final_h;
-     170           38 :    logic                                         btb_fg_crossing_f;
-     171          142 :    logic                                         middle_of_bank;
+     169          352 :    logic                                         final_h;
+     170            0 :    logic                                         btb_fg_crossing_f;
+     171            8 :    logic                                         middle_of_bank;
      172              : 
      173              : 
-     174          306 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
+     174            8 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
      175            0 :    logic                                         branch_error_bank_conflict_p1_f;
      176            0 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
      177              : 
@@ -283,17 +283,17 @@
      179            2 :    logic [31:2] fetch_addr_p1_f;
      180              : 
      181              : 
-     182            6 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
-     183          416 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
+     182            8 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
+     183          208 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185          102 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
-     187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
+     187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
-     190          518 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191          318 :     logic [1:0]                                  bht_bank1_rd_data_f;
-     192          546 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
+     190          180 :     logic [1:0]                                  bht_bank0_rd_data_f;
+     191            0 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     192          184 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
      195              :    assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict
@@ -348,7 +348,7 @@
      244              :    // set on leak one, hold until next flush without leak one
      245              :    assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
      246              : 
-     247          344 : logic exu_flush_final_d1;
+     247           68 : logic exu_flush_final_d1;
      248              : 
      249              :  if(!pt.BTB_FULLYA) begin : genblock1
      250              :    assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
@@ -461,8 +461,8 @@
      357              : 
      358              :  end // if (!pt.BTB_FULLYA)
      359              :    // Detect end of cache line and mask as needed
-     360          388 :    logic eoc_near;
-     361          250 :    logic eoc_mask;
+     360          216 :    logic eoc_near;
+     361          210 :    logic eoc_mask;
      362              :    assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];
      363              :    assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));
      364              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372          284 :    logic [16:1] btb_sel_data_f;
+     372          352 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -484,7 +484,7 @@
      380              :                                     ({16{btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]) );
      381              : 
      382              : 
-     383           16 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
+     383            0 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
      384              : 
      385              :    // a valid taken target needs to kill the next fetch as we compute the target address
      386              :    assign ifu_bp_hit_taken_f = |(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f & ~leak_one_f_d1 & ~dec_tlu_bpred_disable;
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460          122 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460            2 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500          561 : logic [1:0] bloc_f;
-     501          535 : logic use_fa_plus;
+     500          388 : logic [1:0] bloc_f;
+     501          212 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -719,8 +719,8 @@
      615              :                                                 exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
-     618           86 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619           70 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     618           64 :    logic [1:0] bht_wr_data0, bht_wr_data2;
+     619            0 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -732,9 +732,9 @@
      628              : 
      629              : 
      630              : 
-     631          125 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
+     631            6 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
      632              : 
-     633          125 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
+     633            6 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
      634              :    el2_btb_ghr_hash #(.pt(pt)) mpghrhs  (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      635              :    el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      636              :    el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676        28550 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676        16134 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678        28550 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679        28550 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678        16134 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679        16134 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684        28550 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684        16134 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686        28550 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687        28550 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686        16134 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687        16134 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -933,8 +933,8 @@
      829              : 
      830              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0]      bht_bank_wr_data ;
      831              :    logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0]                bht_bank_rd_data_out ;
-     832           26 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
-     833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
+     832            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
+     833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
      834              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0]           bht_bank_sel   ;
      835              : 
      836              :    for ( i=0; i<2; i++) begin : BANKS
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877        28550 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878        28550 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879        28550 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877        16134 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878        16134 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879        16134 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881        28550 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882        28550 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881        16134 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882        16134 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_compress_ctl.sv.html
index 7ef1ade653b..5cac93b1980 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,14 +127,14 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26          410 :    input  logic [15:0] din,        // 16-bit   compressed instruction
-      27          128 :    output logic [31:0] dout        // 32-bit uncompressed instruction
+      26           36 :    input  logic [15:0] din,        // 16-bit   compressed instruction
+      27            4 :    output logic [31:0] dout        // 32-bit uncompressed instruction
       28              :    );
       29              : 
       30              : 
-      31         1784 :    logic               legal;
+      31          496 :    logic               legal;
       32              : 
-      33          410 :    logic [15:0]  i;
+      33           36 :    logic [15:0]  i;
       34              : 
       35            2 :    logic [31:0]  o,l1,l2,l3;
       36              : 
@@ -144,27 +144,27 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43         1098 :    logic rdrd;
-      44          652 :    logic rdrs1;
-      45          626 :    logic rs2rs2;
-      46           76 :    logic rdprd;
-      47          378 :    logic rdprs1;
-      48           24 :    logic rs2prs2;
-      49         1766 :    logic rs2prd;
-      50         1786 :    logic uimm9_2;
-      51           40 :    logic ulwimm6_2;
-      52          130 :    logic ulwspimm7_2;
-      53           84 :    logic rdeq2;
-      54           64 :    logic rdeq1;
-      55         1472 :    logic rs1eq2;
-      56          320 :    logic sbroffset8_1;
-      57           84 :    logic simm9_4;
-      58          586 :    logic simm5_0;
-      59          132 :    logic sjaloffset11_1;
-      60           16 :    logic sluimm17_12;
-      61           92 :    logic uimm5_0;
-      62            0 :    logic uswimm6_2;
-      63          232 :    logic uswspimm7_2;
+      43          252 :    logic rdrd;
+      44          224 :    logic rdrs1;
+      45           20 :    logic rs2rs2;
+      46            4 :    logic rdprd;
+      47          224 :    logic rdprs1;
+      48            4 :    logic rs2prs2;
+      49          498 :    logic rs2prd;
+      50          498 :    logic uimm9_2;
+      51            0 :    logic ulwimm6_2;
+      52           12 :    logic ulwspimm7_2;
+      53            4 :    logic rdeq2;
+      54            8 :    logic rdeq1;
+      55          482 :    logic rs1eq2;
+      56          220 :    logic sbroffset8_1;
+      57            4 :    logic simm9_4;
+      58          236 :    logic simm5_0;
+      59           12 :    logic sjaloffset11_1;
+      60            0 :    logic sluimm17_12;
+      61            0 :    logic uimm5_0;
+      62            0 :    logic uswimm6_2;
+      63           12 :    logic uswspimm7_2;
       64              : 
       65              : 
       66              : 
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115          696 :    logic [5:0] simm5d;
-     116          696 :    logic [9:2] uimm9d;
+     115          220 :    logic [5:0] simm5d;
+     116          220 :    logic [9:2] uimm9d;
      117              : 
-     118          696 :    logic [9:4] simm9d;
-     119          696 :    logic [6:2] ulwimm6d;
-     120          696 :    logic [7:2] ulwspimm7d;
-     121          696 :    logic [5:0] uimm5d;
-     122          696 :    logic [20:1] sjald;
+     118          220 :    logic [9:4] simm9d;
+     119          220 :    logic [6:2] ulwimm6d;
+     120          220 :    logic [7:2] ulwspimm7d;
+     121          220 :    logic [5:0] uimm5d;
+     122          220 :    logic [20:1] sjald;
      123              : 
-     124          696 :    logic [31:12] sluimmd;
+     124          220 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,9 +272,9 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171          696 :    logic [8:1]   sbr8d;
-     172          696 :    logic [6:2]   uswimm6d;
-     173          806 :    logic [7:2]   uswspimm7d;
+     171          220 :    logic [8:1]   sbr8d;
+     172          220 :    logic [6:2]   uswimm6d;
+     173          220 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
      176              :    assign sbr8d[8:1] =   { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ic_mem.sv.html
index b5e508f5d25..a084eb94b64 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26        66208 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27        66208 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26        14760 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27        14760 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -141,11 +141,11 @@
       37            0 :       input logic                                   ic_debug_wr_en,     // Icache debug wr
       38            0 :       input logic                                   ic_debug_tag_array, // Debug tag array
       39            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_debug_way,       // Debug way. Rd or Wr.
-      40          962 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-      41         3842 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
+      40           44 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+      41          970 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
       42              : 
-      43          150 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
-      44          962 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      43           16 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
+      44           44 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       45            0 :       output logic [70:0]                           ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       46            0 :       output logic [25:0]                           ictag_debug_rd_data,// Debug icache tag.
       47            0 :       input logic  [70:0]                           ic_debug_wr_data,   // Debug wr cache.
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91        66208 :       input logic clk,
-      92        66208 :       input logic active_clk,
+      91        14760 :       input logic clk,
+      92        14760 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -201,8 +201,8 @@
       97            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en,
       98            0 :       input logic                          ic_rd_en,           // Read enable
       99              : 
-     100          150 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
-     101          962 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     100           16 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
+     101           44 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      102            0 :       input  logic [70:0]                             ic_debug_wr_data,   // Debug wr cache.
      103            0 :       output logic [70:0]                             ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      104            0 :       output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
@@ -212,8 +212,8 @@
      108            0 :       input logic                            ic_debug_wr_en,      // Icache debug wr
      109            0 :       input logic                            ic_debug_tag_array,  // Debug tag array
      110            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way,        // Debug way. Rd or Wr.
-     111          962 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-     112         3842 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
+     111           44 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+     112          970 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
      113              : 
      114            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
      115            0 :       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
@@ -221,7 +221,7 @@
      117              : 
      118              :       ) ;
      119              : 
-     120          341 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
+     120          212 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
      121            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_wren;    //bank x ways
      122            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_rden;    //bank x ways
      123              : 
@@ -231,9 +231,9 @@
      127            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                ic_debug_sel_sb;
      128              : 
      129              :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0]                  wb_dout ;       //  ways x bank
-     130          150 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
+     130           16 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
      131              :    logic [pt.ICACHE_NUM_WAYS-1:0] [141:0]                                         wb_dout_way_pre;
-     132          962 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
+     132           44 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
      133            0 :    logic [141:0]                                                                  wb_dout_ecc;
      134              : 
      135            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                bank_check_en;
@@ -245,11 +245,11 @@
      141            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en;    // debug wr_way
      142            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en_ff; // debug wr_way
      143            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_wr_way_en;    // debug wr_way
-     144           26 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
+     144            4 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
      145              : 
-     146           26 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
+     146            4 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
      147              : 
-     148           32 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
+     148            4 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
      149            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_rd_hit_q;
      150              : 
      151              : 
@@ -278,7 +278,7 @@
      174              : 
      175              : 
      176            2 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr;
-     177           26 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
+     177            4 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
      178              : 
      179            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_up;
      180            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only_up;
@@ -296,7 +296,7 @@
      192              :    assign  ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      193              :    assign  ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      194              : 
-     195          450 :    logic end_of_cache_line;
+     195          224 :    logic end_of_cache_line;
      196              :    assign end_of_cache_line = (pt.ICACHE_LN_SZ==7'h40) ? (&ic_rw_addr_q[5:4]) : ic_rw_addr_q[4];
      197            2 :    always_comb begin : clkens
      198            2 :       ic_bank_way_clken  = '0;
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803        66208 :       input logic                                                   clk,
-     804        66208 :       input logic                                                   active_clk,
+     803        14760 :       input logic                                                   clk,
+     804        14760 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
@@ -945,7 +945,7 @@
      841            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en ;
      842            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en_ff ;
      843              : 
-     844           26 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
+     844            4 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
      845            2 :    logic [31:pt.ICACHE_TAG_LO]                                     ic_rw_addr_ff;
      846            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_rden_q;          // way
      847            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_wren;          // way
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_iccm_mem.sv.html
index 5f3218b372d..928e3492486 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,14 +129,14 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28        66208 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29        66208 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28        14760 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29        14760 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
       33            0 :    input logic                                        iccm_wren,                           // ICCM write enable
       34            0 :    input logic                                        iccm_rden,                           // ICCM read enable
-      35           26 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
+      35            4 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
       36            0 :    input logic                                        iccm_buf_correct_ecc,                // ICCM is doing a single bit error correct cycle
       37            0 :    input logic                                        iccm_correction_state,               // ICCM under a correction - This is needed to guard replacements when hit
       38            0 :    input logic [2:0]                                  iccm_wr_size,                        // ICCM write size
@@ -154,13 +154,13 @@
       50            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                wren_bank;
       51            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
       52            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
-      53           26 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
+      53            4 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
       54              : 
       55            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
-      57           28 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58         1115 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
-      59          341 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
+      57            4 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
+      58          248 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      59          212 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
       60            0 :    logic             [63:0]              iccm_rd_data_pre;
       61            0 :    logic             [63:0]              iccm_data;
       62            0 :    logic [1:0]                           addr_incr;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html
index a1c6e426e55..dac59cdbf0d 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,27 +130,27 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29        66208 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30        66208 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        14760 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        14760 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
       34              : 
-      35         4328 :    input logic ic_hit_f,      // Icache hit
-      36         4342 :    input logic ifu_ic_mb_empty, // Miss buffer empty
+      35          980 :    input logic ic_hit_f,      // Icache hit
+      36          996 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
-      38         3178 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39          256 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      38          480 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
+      39          208 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
       41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
-      42          345 :    input logic exu_flush_final, // FLush
-      43          112 :    input logic [31:1] exu_flush_path_final, // Flush path
+      42           70 :    input logic exu_flush_final, // FLush
+      43            4 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45          716 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
-      46          136 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      45          352 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      46            0 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
-      48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
-      49         1848 :    input logic ic_write_stall, // IC is writing, stop fetching
+      48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
+      49          488 :    input logic ic_write_stall, // IC is writing, stop fetching
       50            0 :    input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
       51              : 
       52            0 :    input logic [31:0]  dec_tlu_mrac_ff ,   // side_effect and cacheable for each region
@@ -158,34 +158,34 @@
       54            2 :    output logic [31:1] ifc_fetch_addr_f, // fetch addr F
       55            2 :    output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
       56              : 
-      57         2154 :    output logic  ifc_fetch_req_f,  // fetch request valid F
+      57          662 :    output logic  ifc_fetch_req_f,  // fetch request valid F
       58              : 
-      59          272 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
+      59           58 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
       60              : 
       61            2 :    output logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. BF stage
-      62         2154 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
+      62          662 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
       63            2 :    output logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. BF stage
       64            0 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       65            0 :    output logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       66              : 
-      67          347 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
+      67           72 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
       68              : 
       69              : 
       70              :    );
       71              : 
       72            2 :    logic [31:1]  fetch_addr_bf;
       73            2 :    logic [31:1]  fetch_addr_next;
-      74          304 :    logic [3:0]   fb_write_f, fb_write_ns;
+      74          172 :    logic [3:0]   fb_write_f, fb_write_ns;
       75              : 
-      76          304 :    logic     fb_full_f_ns, fb_full_f;
+      76          172 :    logic     fb_full_f_ns, fb_full_f;
       77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
-      78         3838 :    logic     sel_last_addr_bf, sel_next_addr_bf;
-      79         6247 :    logic     miss_f, miss_a;
+      78          804 :    logic     sel_last_addr_bf, sel_next_addr_bf;
+      79         1476 :    logic     miss_f, miss_a;
       80            0 :    logic     flush_fb, dma_iccm_stall_any_f;
       81            4 :    logic     mb_empty_mod, goto_idle, leave_idle;
-      82         2146 :    logic     fetch_bf_en;
-      83          370 :    logic         line_wrap;
-      84          343 :    logic         fetch_addr_next_1;
+      82          666 :    logic     fetch_bf_en;
+      83          212 :    logic         line_wrap;
+      84          212 :    logic         fetch_addr_next_1;
       85              : 
       86              :    // FSM assignment
       87              :     typedef enum logic [1:0] { IDLE  = 2'b00 ,
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_mem_ctl.sv.html
index cd7e40405fa..a45f9bd38f7 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,40 +131,40 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30        66208 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31        66208 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32        66208 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30        14760 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        14760 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32        14760 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
-      35          345 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
+      35           70 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
       36            4 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
       37            0 :    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
-      38         4304 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
+      38          976 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
       39            0 :    input logic                       dec_tlu_force_halt,            // force halt.
       40              : 
       41            2 :    input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
       42            2 :    input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
-      43         2154 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
+      43          662 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
       44            2 :    input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
       45            0 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
-      47          347 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
+      47           72 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49          716 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49          352 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51          440 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51          354 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
-      53         4336 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
-      54         4342 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
+      53          988 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
+      54          996 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
       55            0 :    output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
-      56         1848 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
+      56          488 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
       57              : 
       58              : /// PMU signals
-      59         4336 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
+      59          988 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
       60            0 :    output logic                      ifu_pmu_ic_hit,                // IC hit event
       61            0 :    output logic                      ifu_pmu_bus_error,             // Bus error event
       62            0 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
-      63         4336 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
+      63          988 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
       64              : 
       65              :   //-------------------------- IFU AXI signals--------------------------
       66              :    // AXI Write Channels
@@ -188,10 +188,10 @@
       84            0 :    output logic                            ifu_axi_bready,
       85              : 
       86              :    // AXI Read Channels
-      87         4336 :    output logic                            ifu_axi_arvalid,
-      88         4336 :    input  logic                            ifu_axi_arready,
-      89         2620 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      90         1684 :    output logic [31:0]                     ifu_axi_araddr,
+      87          988 :    output logic                            ifu_axi_arvalid,
+      88          988 :    input  logic                            ifu_axi_arready,
+      89          512 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      90           20 :    output logic [31:0]                     ifu_axi_araddr,
       91            2 :    output logic [3:0]                      ifu_axi_arregion,
       92            0 :    output logic [7:0]                      ifu_axi_arlen,
       93            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -201,10 +201,10 @@
       97            2 :    output logic [2:0]                      ifu_axi_arprot,
       98            0 :    output logic [3:0]                      ifu_axi_arqos,
       99              : 
-     100         8669 :    input  logic                            ifu_axi_rvalid,
+     100         1974 :    input  logic                            ifu_axi_rvalid,
      101            2 :    output logic                            ifu_axi_rready,
-     102         1120 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     103          576 :    input  logic [63:0]                     ifu_axi_rdata,
+     102          446 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     103           16 :    input  logic [63:0]                     ifu_axi_rdata,
      104            0 :    input  logic [1:0]                      ifu_axi_rresp,
      105              : 
      106            2 :     input  logic                     ifu_bus_clk_en,
@@ -221,7 +221,7 @@
      117            0 :    output logic                      iccm_dma_rvalid,   //   Data read from iccm is valid
      118            0 :    output logic [63:0]               iccm_dma_rdata,    //   dma data read from iccm
      119            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     120          343 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
+     120           68 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
      121              : 
      122              : 
      123              : //   I$ & ITAG Ports
@@ -229,8 +229,8 @@
      125            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      126            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      127              : 
-     128          150 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
-     129          962 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     128           16 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
+     129           44 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      130            0 :    input  logic [70:0]               ic_debug_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      131            0 :    input  logic [25:0]               ictag_debug_rd_data,  // Debug icache tag.
      132            0 :    output logic [70:0]               ic_debug_wr_data,     // Debug wr cache.
@@ -253,7 +253,7 @@
      149            0 :    input  logic                      ic_tag_perr,        // Icache Tag parity error
      150              : 
      151              :    // ICCM ports
-     152           26 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
+     152            4 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
      153            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
      154            0 :    output logic                      iccm_rden,          // ICCM read enable.
      155            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
@@ -261,9 +261,9 @@
      157              : 
      158            0 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
      159            0 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
-     160         3820 :    input  logic [1:0]                ifu_fetch_val,
+     160          596 :    input  logic [1:0]                ifu_fetch_val,
      161              :    // IFU control signals
-     162         4328 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
+     162          980 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
      163            0 :    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
      164            0 :    output logic [1:0]                ic_access_fault_type_f, // Access fault types
      165            0 :    output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
@@ -274,10 +274,10 @@
      170              : 
      171            0 :    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
      172            0 :    output logic                      iccm_dma_sb_error,      // Single Bit ECC error from a DMA access
-     173         3820 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
-     174         1026 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
-     175          962 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
-     176         3842 :    output logic                      ic_sel_premux_data,     // Select premux data.
+     173          596 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
+     174           44 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
+     175           44 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
+     176          970 :    output logic                      ic_sel_premux_data,     // Select premux data.
      177              : 
      178              : /////  Debug
      179            0 :    input  el2_cache_debug_pkt_t     dec_tlu_ic_diag_pkt ,       // Icache/tag debug read/write packet
@@ -304,8 +304,8 @@
      200              : 
      201              : 
      202              : 
-     203         8669 :    logic           bus_ifu_wr_en     ;
-     204         8667 :    logic           bus_ifu_wr_en_ff  ;
+     203         1974 :    logic           bus_ifu_wr_en     ;
+     204         1972 :    logic           bus_ifu_wr_en_ff  ;
      205            0 :    logic           bus_ifu_wr_en_ff_q  ;
      206            0 :    logic           bus_ifu_wr_en_ff_wo_err  ;
      207            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     bus_ic_wr_en ;
@@ -333,36 +333,36 @@
      229            0 :    logic           scnd_miss_index_match ;
      230              : 
      231              : 
-     232          343 :    logic           ifc_dma_access_q_ok;
+     232           68 :    logic           ifc_dma_access_q_ok;
      233            0 :    logic           ifc_iccm_access_f ;
      234            0 :    logic           ifc_region_acc_fault_f;
      235            0 :    logic           ifc_region_acc_fault_final_f;
      236            0 :    logic  [1:0]    ifc_bus_acc_fault_f;
-     237         4336 :    logic           ic_act_miss_f;
+     237          988 :    logic           ic_act_miss_f;
      238            0 :    logic           ic_miss_under_miss_f;
-     239          220 :    logic           ic_ignore_2nd_miss_f;
+     239           56 :    logic           ic_ignore_2nd_miss_f;
      240            0 :    logic           ic_act_hit_f;
-     241         4334 :    logic           miss_pending;
+     241          986 :    logic           miss_pending;
      242            2 :    logic [31:1]    imb_in , imb_ff  ;
      243            2 :    logic [31:pt.ICACHE_BEAT_ADDR_HI+1]    miss_addr_in , miss_addr  ;
-     244          670 :    logic           miss_wrap_f ;
-     245          344 :    logic           flush_final_f;
-     246         2469 :    logic           ifc_fetch_req_f;
-     247         2154 :    logic           ifc_fetch_req_f_raw;
-     248         4328 :    logic           fetch_req_f_qual   ;
-     249         2154 :    logic           ifc_fetch_req_qual_bf ;
+     244          436 :    logic           miss_wrap_f ;
+     245           68 :    logic           flush_final_f;
+     246          724 :    logic           ifc_fetch_req_f;
+     247          662 :    logic           ifc_fetch_req_f_raw;
+     248          980 :    logic           fetch_req_f_qual   ;
+     249          662 :    logic           ifc_fetch_req_qual_bf ;
      250            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     replace_way_mb_any;
-     251         4332 :    logic           last_beat;
-     252         6226 :    logic           reset_beat_cnt  ;
-     253         1913 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
-     254         3872 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
+     251          984 :    logic           last_beat;
+     252         1480 :    logic           reset_beat_cnt  ;
+     253          480 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
+     254          564 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
      255            2 :    logic [31:1]    ifu_fetch_addr_int_f ;
      256            2 :    logic [31:1]    ifu_ic_rw_int_addr ;
-     257         4335 :    logic           crit_wd_byp_ok_ff ;
-     258         4327 :    logic           ic_crit_wd_rdy_new_ff;
-     259          504 :    logic   [79:0]  ic_byp_data_only_pre_new;
-     260          426 :    logic   [79:0]  ic_byp_data_only_new;
-     261         4328 :    logic           ic_byp_hit_f ;
+     257          988 :    logic           crit_wd_byp_ok_ff ;
+     258          978 :    logic           ic_crit_wd_rdy_new_ff;
+     259           20 :    logic   [79:0]  ic_byp_data_only_pre_new;
+     260           16 :    logic   [79:0]  ic_byp_data_only_new;
+     261          980 :    logic           ic_byp_hit_f ;
      262            2 :    logic           ic_valid ;
      263            2 :    logic           ic_valid_ff;
      264            0 :    logic           reset_all_tags;
@@ -380,94 +380,94 @@
      276              : 
      277            0 :    logic           reset_ic_in ;
      278            0 :    logic           reset_ic_ff ;
-     279          341 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
+     279          212 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
      280            2 :    logic [31:1]    ifu_status_wr_addr;
      281            0 :    logic           sel_mb_addr ;
      282            0 :    logic           sel_mb_addr_ff ;
      283            0 :    logic           sel_mb_status_addr ;
-     284          962 :    logic [63:0]    ic_final_data;
+     284           44 :    logic [63:0]    ic_final_data;
      285              : 
      286            0 :    logic [pt.ICACHE_STATUS_BITS-1:0]                              way_status_new_ff ;
      287            0 :    logic                                    way_status_wr_en_ff ;
      288            0 :    logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0]        way_status_out ;
      289            0 :    logic [1:0]                              ic_debug_way_enc;
      290              : 
-     291         1120 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
+     291          446 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
      292              : 
-     293         2469 :    logic         fetch_req_icache_f;
+     293          724 :    logic         fetch_req_icache_f;
      294            0 :    logic         fetch_req_iccm_f;
      295            0 :    logic         ic_iccm_hit_f;
      296            2 :    logic         fetch_uncacheable_ff;
      297            0 :    logic         way_status_wr_en;
-     298         3842 :    logic         sel_byp_data;
-     299         3844 :    logic         sel_ic_data;
+     298          970 :    logic         sel_byp_data;
+     299          972 :    logic         sel_ic_data;
      300            0 :    logic         sel_iccm_data;
      301            0 :    logic         ic_rd_parity_final_err;
-     302         4336 :    logic         ic_act_miss_f_delayed;
+     302          988 :    logic         ic_act_miss_f_delayed;
      303            0 :    logic         bus_ifu_wr_data_error;
      304            0 :    logic         bus_ifu_wr_data_error_ff;
      305            0 :    logic         way_status_wr_en_w_debug;
      306            0 :    logic         ic_debug_tag_val_rd_out;
-     307         4336 :    logic         ifu_pmu_ic_miss_in;
+     307          988 :    logic         ifu_pmu_ic_miss_in;
      308            0 :    logic         ifu_pmu_ic_hit_in;
      309            0 :    logic         ifu_pmu_bus_error_in;
-     310         4336 :    logic         ifu_pmu_bus_trxn_in;
+     310          988 :    logic         ifu_pmu_bus_trxn_in;
      311            0 :    logic         ifu_pmu_bus_busy_in;
      312            0 :    logic         ic_debug_ict_array_sel_in;
      313            0 :    logic         ic_debug_ict_array_sel_ff;
      314            0 :    logic         debug_data_clken;
-     315         4332 :    logic         last_data_recieved_in ;
-     316         4332 :    logic         last_data_recieved_ff ;
+     315          984 :    logic         last_data_recieved_in ;
+     316          984 :    logic         last_data_recieved_ff ;
      317              : 
-     318         8669 :    logic                          ifu_bus_rvalid           ;
-     319         8667 :    logic                          ifu_bus_rvalid_ff        ;
-     320         8667 :    logic                          ifu_bus_rvalid_unq_ff    ;
-     321         4336 :    logic                          ifu_bus_arready_unq       ;
-     322         4335 :    logic                          ifu_bus_arready_unq_ff    ;
-     323         4336 :    logic                          ifu_bus_arvalid           ;
-     324         4336 :    logic                          ifu_bus_arvalid_ff        ;
-     325         4336 :    logic                          ifu_bus_arready           ;
-     326         4335 :    logic                          ifu_bus_arready_ff        ;
-     327          576 :    logic [63:0]                   ifu_bus_rdata_ff        ;
+     318         1974 :    logic                          ifu_bus_rvalid           ;
+     319         1972 :    logic                          ifu_bus_rvalid_ff        ;
+     320         1972 :    logic                          ifu_bus_rvalid_unq_ff    ;
+     321          988 :    logic                          ifu_bus_arready_unq       ;
+     322          988 :    logic                          ifu_bus_arready_unq_ff    ;
+     323          988 :    logic                          ifu_bus_arvalid           ;
+     324          988 :    logic                          ifu_bus_arvalid_ff        ;
+     325          988 :    logic                          ifu_bus_arready           ;
+     326          988 :    logic                          ifu_bus_arready_ff        ;
+     327           16 :    logic [63:0]                   ifu_bus_rdata_ff        ;
      328            0 :    logic [1:0]                    ifu_bus_rresp_ff          ;
-     329         8669 :    logic                          ifu_bus_rsp_valid ;
+     329         1974 :    logic                          ifu_bus_rsp_valid ;
      330            2 :    logic                          ifu_bus_rsp_ready ;
-     331         1120 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
-     332          576 :    logic [63:0]                   ifu_bus_rsp_rdata;
+     331          446 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
+     332           16 :    logic [63:0]                   ifu_bus_rsp_rdata;
      333            0 :    logic [1:0]                    ifu_bus_rsp_opc;
      334              : 
-     335          860 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
+     335           40 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
      336            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    wr_data_c1_clk;
-     337          859 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
-     338          859 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
+     337           38 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
+     338           38 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
      339            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error_in;
      340            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error;
-     341          341 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
-     342          534 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
+     341          212 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
+     342          226 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
      343            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_1;
-     344          330 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
-     345          330 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
+     344           14 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
+     345           14 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
      346            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_1;
-     347         6145 :    logic          miss_buff_hit_unq_f ;
+     347         1254 :    logic          miss_buff_hit_unq_f ;
      348            0 :    logic          stream_hit_f ;
      349            0 :    logic          stream_miss_f ;
      350            0 :    logic          stream_eol_f ;
-     351         4328 :    logic          crit_byp_hit_f ;
-     352         1120 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
+     351          980 :    logic          crit_byp_hit_f ;
+     352          446 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
      353              :    logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;
-     354          648 :    logic [63:0] ic_miss_buff_half;
+     354           24 :    logic [63:0] ic_miss_buff_half;
      355            0 :    logic        scnd_miss_req, scnd_miss_req_q;
      356            0 :    logic        scnd_miss_req_in;
      357              : 
      358              : 
      359            0 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_ff;
-     360           30 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
+     360            4 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
      361            0 :    logic [38:0]                         iccm_ecc_corr_data_ff;
      362            0 :    logic                                iccm_ecc_write_status     ;
      363            0 :    logic                                iccm_rd_ecc_single_err_ff   ;
      364            0 :    logic                                iccm_error_start;     // start the error fsm
      365            0 :    logic                                perr_state_en;
-     366         9715 :    logic                                miss_state_en;
+     366         2390 :    logic                                miss_state_en;
      367              : 
      368            0 :    logic        busclk;
      369            0 :    logic        busclk_force;
@@ -475,46 +475,46 @@
      371            2 :    logic        bus_ifu_bus_clk_en_ff;
      372            2 :    logic        bus_ifu_bus_clk_en ;
      373              : 
-     374         4336 :    logic        ifc_bus_ic_req_ff_in;
-     375         4336 :    logic        ifu_bus_cmd_valid ;
-     376         4336 :    logic        ifu_bus_cmd_ready ;
+     374          988 :    logic        ifc_bus_ic_req_ff_in;
+     375          988 :    logic        ifu_bus_cmd_valid ;
+     376          988 :    logic        ifu_bus_cmd_ready ;
      377              : 
-     378         4335 :    logic        bus_inc_data_beat_cnt     ;
-     379         6226 :    logic        bus_reset_data_beat_cnt   ;
-     380        10563 :    logic        bus_hold_data_beat_cnt    ;
+     378          988 :    logic        bus_inc_data_beat_cnt     ;
+     379         1480 :    logic        bus_reset_data_beat_cnt   ;
+     380         2470 :    logic        bus_hold_data_beat_cnt    ;
      381              : 
-     382         4336 :    logic        bus_inc_cmd_beat_cnt     ;
+     382          988 :    logic        bus_inc_cmd_beat_cnt     ;
      383            0 :    logic        bus_reset_cmd_beat_cnt_0   ;
-     384         4336 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
-     385         4338 :    logic        bus_hold_cmd_beat_cnt    ;
+     384          988 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
+     385          990 :    logic        bus_hold_cmd_beat_cnt    ;
      386              : 
      387            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_data_beat_count  ;
      388            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_data_beat_count      ;
      389              : 
-     390         4336 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
-     391         4336 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
+     390          988 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
+     391          988 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
      392              : 
      393              : 
-     394         1913 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
-     395         1913 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
+     394          480 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
+     395          480 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
      396              : 
      397              : 
-     398         4336 :    logic        bus_cmd_sent           ;
-     399         4333 :    logic        bus_last_data_beat     ;
+     398          988 :    logic        bus_cmd_sent           ;
+     399          986 :    logic        bus_last_data_beat     ;
      400              : 
      401              : 
      402            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren            ;
      403              : 
      404            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren_last       ;
      405            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       wren_reset_miss      ;
-     406          347 :    logic        ifc_dma_access_ok_d;
-     407          346 :    logic        ifc_dma_access_ok_prev;
+     406           72 :    logic        ifc_dma_access_ok_d;
+     407           70 :    logic        ifc_dma_access_ok_prev;
      408              : 
-     409         4336 :    logic   bus_cmd_req_in ;
-     410         4336 :    logic   bus_cmd_req_hold ;
+     409          988 :    logic   bus_cmd_req_in ;
+     410          988 :    logic   bus_cmd_req_hold ;
      411              : 
-     412         2118 :    logic   second_half_available ;
-     413         2118 :    logic   write_ic_16_bytes ;
+     412          496 :    logic   second_half_available ;
+     413          496 :    logic   write_ic_16_bytes ;
      414              : 
      415            0 :    logic   ifc_region_acc_fault_final_bf;
      416            0 :    logic   ifc_region_acc_fault_memory_bf;
@@ -523,21 +523,21 @@
      419              : 
      420            0 :    logic   iccm_correct_ecc;
      421            0 :    logic   dma_sb_err_state, dma_sb_err_state_ff;
-     422         2633 :    logic   two_byte_instr;
+     422          742 :    logic   two_byte_instr;
      423              : 
      424              :    typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;
-     425            6 :    miss_state_t miss_state, miss_nxtstate;
+     425            8 :    miss_state_t miss_state, miss_nxtstate;
      426              : 
      427              :    typedef enum logic [1:0] {ERR_STOP_IDLE=2'b00, ERR_FETCH1=2'b01 , ERR_FETCH2=2'b10 , ERR_STOP_FETCH=2'b11} err_stop_state_t;
      428            0 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
      429            0 :    logic   err_stop_state_en ;
      430            0 :    logic   err_stop_fetch ;
      431              : 
-     432         4327 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
+     432          978 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434          490 :    logic   ifu_bp_hit_taken_q_f;
-     435         8669 :    logic   ifu_bus_rvalid_unq;
-     436         4336 :    logic   bus_cmd_beat_en;
+     434          176 :    logic   ifu_bp_hit_taken_q_f;
+     435         1974 :    logic   ifu_bus_rvalid_unq;
+     436          988 :    logic   bus_cmd_beat_en;
      437              : 
      438              : 
      439              : // ---- Clock gating section -----
@@ -587,21 +587,21 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486         5502 :          IDLE: begin : idle
-     487         5502 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488         5502 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486         3129 :          IDLE: begin : idle
+     487         3129 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488         3129 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490        16590 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491        16590 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492        16590 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493        16590 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494        16590 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495        16590 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496        16590 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497        16590 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498        16590 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499        16590 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500        16590 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490         9287 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491         9287 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492         9287 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493         9287 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494         9287 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495         9287 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496         9287 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497         9287 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498         9287 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499         9287 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500         9287 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,24 +611,24 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510         6258 :          MISS_WAIT: begin : miss_wait
-     511         6258 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512         6258 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510         3596 :          MISS_WAIT: begin : miss_wait
+     511         3596 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512         3596 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514          192 :          HIT_U_MISS: begin : hit_u_miss
-     515          192 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516          192 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517          192 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514          110 :          HIT_U_MISS: begin : hit_u_miss
+     515          110 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516          110 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517          110 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
      521            0 :                                     exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;
      522            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      523              :          end
-     524            8 :          STALL_SCND_MISS: begin : stall_scnd_miss
-     525            8 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
-     526            8 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
-     527            8 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
+     524           12 :          STALL_SCND_MISS: begin : stall_scnd_miss
+     525           12 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
+     526           12 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
+     527           12 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      528              :          end
      529            0 :          default: begin : def_case
      530            0 :                   miss_nxtstate   = IDLE;
@@ -638,7 +638,7 @@
      534              :    end
      535              :    rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en),   .*);
      536              : 
-     537         4334 :   logic    sel_hold_imb     ;
+     537          986 :   logic    sel_hold_imb     ;
      538              : 
      539              :    assign miss_pending       =  (miss_state != IDLE) ;
      540              :    assign crit_wd_byp_ok_ff  =  (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
@@ -902,7 +902,7 @@
      798              : /////////////////////////////////////////////////////////////////////////////////////
      799              : //  Create full buffer...                                                          //
      800              : /////////////////////////////////////////////////////////////////////////////////////
-     801          576 :      logic [63:0]       ic_miss_buff_data_in;
+     801           16 :      logic [63:0]       ic_miss_buff_data_in;
      802              :      assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
      803              : 
      804              :      for (genvar i=0; i<pt.ICACHE_NUM_BEATS; i++) begin :  wr_flop
@@ -939,10 +939,10 @@
      835              : /////////////////////////////////////////////////////////////////////////////////////
      836              : // New bypass ready                                                                //
      837              : /////////////////////////////////////////////////////////////////////////////////////
-     838          329 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
-     839          304 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
-     840         4333 :    logic   bypass_data_ready_in;
-     841         4328 :    logic   ic_crit_wd_rdy_new_in;
+     838          212 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
+     839           10 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
+     840          986 :    logic   bypass_data_ready_in;
+     841          980 :    logic   ic_crit_wd_rdy_new_in;
      842              : 
      843              :    assign bypass_index[pt.ICACHE_BEAT_ADDR_HI:1] = imb_ff[pt.ICACHE_BEAT_ADDR_HI:1] ;
      844              :    assign bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3] = bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] + 1 ;
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945        28550 :       ERR_IDLE: begin : err_idle
-     946        28550 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947        28550 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948        28550 :         perr_sb_write_status = perr_state_en;
+     945        16134 :       ERR_IDLE: begin : err_idle
+     946        16134 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947        16134 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948        16134 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990        28550 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991        28550 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992        28550 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990        16134 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991        16134 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992        16134 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1469,7 +1469,7 @@
     1365              :                               ((miss_state == CRIT_BYP_OK) &  miss_state_en &  (miss_nxtstate == MISS_WAIT))  ))  |
     1366              :                              ( ifc_fetch_req_bf & exu_flush_final  & ~ifc_fetch_uncacheable_bf & ~ifc_iccm_access_bf )     ;
     1367              : 
-    1368         4517 : logic   ic_real_rd_wp_unused;
+    1368         1038 : logic   ic_real_rd_wp_unused;
     1369              : assign  ic_real_rd_wp_unused  =  (ifc_fetch_req_bf &  ~ifc_iccm_access_bf  &  ~ifc_region_acc_fault_final_bf & ~dec_tlu_fence_i_wb & ~stream_miss_f & ~ic_act_miss_f &
     1370              :                             ~(((miss_state == STREAM) & ~miss_state_en) |
     1371              :                               ((miss_state == CRIT_BYP_OK) & ~miss_state_en & ~(miss_nxtstate == MISS_WAIT)) |
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446        28550 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447        28550 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446        16134 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447        16134 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509        28550 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510        28550 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511        57100 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509        16134 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510        16134 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511        32268 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lib.sv.html
index 33633aa176a..ea1876eda05 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35         1800 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
-      36         1800 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
+      35           48 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
+      36           48 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
       37              :                         );
       38              : 
       39              : 
@@ -158,9 +158,9 @@
       54              : #(
       55              : `include "el2_param.vh"
       56              :  )(
-      57          240 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58          572 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59          560 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      57           16 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
+      58           26 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59           42 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu.sv.html
index efdb6f9b8c3..c7533808998 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -147,12 +147,12 @@
       43            0 :    input logic                             dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
       44            0 :    input logic                             dec_tlu_core_ecc_disable,          // disable the generation of the ecc
       45              : 
-      46          140 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
-      47            6 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
-      48           52 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
+      46          240 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
+      47            0 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
+      48            0 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
       49              : 
-      50          402 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
-      51         1420 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
+      50           24 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
+      51          460 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
       52            0 :    input logic [31:0]                      dec_tlu_mrac_ff,       // CSR for memory region control
       53              : 
       54            0 :    output logic [31:0]                     lsu_result_m,          // lsu load data
@@ -160,8 +160,8 @@
       56            0 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
       57            0 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
       58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
-      59          969 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
-      60          967 :    output logic                            lsu_active,            // Used to turn off top level clk
+      59          236 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
+      60          234 :    output logic                            lsu_active,            // Used to turn off top level clk
       61              : 
       62            0 :    output logic [31:1]                     lsu_fir_addr,        // fast interrupt address
       63            0 :    output logic [1:0]                      lsu_fir_error,       // Error during fast interrupt lookup
@@ -170,22 +170,22 @@
       66            0 :    output el2_lsu_error_pkt_t             lsu_error_pkt_r,               // lsu exception packet
       67            0 :    output logic                            lsu_imprecise_error_load_any,  // bus load imprecise error
       68            0 :    output logic                            lsu_imprecise_error_store_any, // bus store imprecise error
-      69          111 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
+      69          220 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
       70              : 
       71              :    // Non-blocking loads
-      72          660 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
-      73          202 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
+      72          228 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
+      73           20 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
       74            0 :    output logic                               lsu_nonblock_load_inv_r,        // invalidate signal for the cam entry for non block loads
-      75          202 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
-      76          718 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
+      75           20 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
+      76          232 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
       77            0 :    output logic                               lsu_nonblock_load_data_error,   // non block load has an error
-      78           36 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
-      79           14 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
+      78            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
+      79            0 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
       80              : 
-      81          660 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
-      82          760 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
+      81          228 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
+      82          232 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
       83            0 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
-      84         1548 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
+      84          468 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
       85            0 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
       86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
       87            0 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
@@ -199,8 +199,8 @@
       95            0 :    output logic                            dccm_rden,       // DCCM read enable
       96            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo, // DCCM write address low bank
       97            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi, // DCCM write address hi bank
-      98          140 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
-      99          140 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
+      98          240 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
+      99          240 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
      100            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo, // DCCM write data for lo bank
      101            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi, // DCCM write data for hi bank
      102              : 
@@ -211,16 +211,16 @@
      107            0 :    output logic                            picm_wren,    // PIC memory write enable
      108            0 :    output logic                            picm_rden,    // PIC memory read enable
      109            0 :    output logic                            picm_mken,    // Need to read the mask for stores to determine which bits to write/forward
-     110          121 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
-     111          121 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
-     112            6 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
-     113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
+     110          240 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
+     111          240 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
+     112            0 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
+     113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
      114              : 
      115              :    // AXI Write Channels
-     116          888 :    output logic                            lsu_axi_awvalid,
-     117         1549 :    input  logic                            lsu_axi_awready,
+     116          240 :    output logic                            lsu_axi_awvalid,
+     117          468 :    input  logic                            lsu_axi_awready,
      118            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     119          111 :    output logic [31:0]                     lsu_axi_awaddr,
+     119          220 :    output logic [31:0]                     lsu_axi_awaddr,
      120            2 :    output logic [3:0]                      lsu_axi_awregion,
      121            0 :    output logic [7:0]                      lsu_axi_awlen,
      122            0 :    output logic [2:0]                      lsu_axi_awsize,
@@ -230,22 +230,22 @@
      126            0 :    output logic [2:0]                      lsu_axi_awprot,
      127            0 :    output logic [3:0]                      lsu_axi_awqos,
      128              : 
-     129          888 :    output logic                            lsu_axi_wvalid,
-     130         1549 :    input  logic                            lsu_axi_wready,
+     129          240 :    output logic                            lsu_axi_wvalid,
+     130          468 :    input  logic                            lsu_axi_wready,
      131            0 :    output logic [63:0]                     lsu_axi_wdata,
-     132          148 :    output logic [7:0]                      lsu_axi_wstrb,
+     132            8 :    output logic [7:0]                      lsu_axi_wstrb,
      133            2 :    output logic                            lsu_axi_wlast,
      134              : 
-     135          886 :    input  logic                            lsu_axi_bvalid,
+     135          236 :    input  logic                            lsu_axi_bvalid,
      136            2 :    output logic                            lsu_axi_bready,
      137            0 :    input  logic [1:0]                      lsu_axi_bresp,
      138            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      139              : 
      140              :    // AXI Read Channels
-     141          660 :    output logic                            lsu_axi_arvalid,
-     142         1549 :    input  logic                            lsu_axi_arready,
+     141          228 :    output logic                            lsu_axi_arvalid,
+     142          468 :    input  logic                            lsu_axi_arready,
      143            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     144          111 :    output logic [31:0]                     lsu_axi_araddr,
+     144          220 :    output logic [31:0]                     lsu_axi_araddr,
      145            2 :    output logic [3:0]                      lsu_axi_arregion,
      146            0 :    output logic [7:0]                      lsu_axi_arlen,
      147            0 :    output logic [2:0]                      lsu_axi_arsize,
@@ -255,10 +255,10 @@
      151            0 :    output logic [2:0]                      lsu_axi_arprot,
      152            0 :    output logic [3:0]                      lsu_axi_arqos,
      153              : 
-     154          718 :    input  logic                            lsu_axi_rvalid,
+     154          232 :    input  logic                            lsu_axi_rvalid,
      155            2 :    output logic                            lsu_axi_rready,
      156            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     157           34 :    input  logic [63:0]                     lsu_axi_rdata,
+     157            8 :    input  logic [63:0]                     lsu_axi_rdata,
      158            0 :    input  logic [1:0]                      lsu_axi_rresp,
      159            2 :    input  logic                            lsu_axi_rlast,
      160              : 
@@ -276,33 +276,33 @@
      172            0 :    output logic                            dccm_dma_ecc_error,  // DMA load had ecc error
      173            0 :    output logic [2:0]                      dccm_dma_rtag,       // DMA request tag
      174            0 :    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
-     175         1422 :    output logic                            dccm_ready,          // lsu ready for DMA access
+     175          462 :    output logic                            dccm_ready,          // lsu ready for DMA access
      176              : 
      177              :    // DCCM ECC status
      178            0 :    output logic                            lsu_dccm_rd_ecc_single_err,
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182        66208 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183        66208 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182        14760 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183        14760 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
-     186          140 :     output logic [31:0] lsu_pmp_addr_start,
-     187          140 :     output logic [31:0] lsu_pmp_addr_end,
-     188          190 :     input  logic        lsu_pmp_error_start,
-     189          190 :     input  logic        lsu_pmp_error_end,
-     190          760 :     output logic        lsu_pmp_we,
-     191          660 :     output logic        lsu_pmp_re
+     186          240 :     output logic [31:0] lsu_pmp_addr_start,
+     187          240 :     output logic [31:0] lsu_pmp_addr_end,
+     188            0 :     input  logic        lsu_pmp_error_start,
+     189            0 :     input  logic        lsu_pmp_error_end,
+     190          232 :     output logic        lsu_pmp_we,
+     191          228 :     output logic        lsu_pmp_re
      192              : 
      193              :    );
      194              : 
      195            0 :    logic        lsu_dccm_rden_m;
      196            0 :    logic        lsu_dccm_rden_r;
-     197            6 :    logic [31:0] store_data_m;
-     198            6 :    logic [31:0] store_data_r;
-     199            6 :    logic [31:0] store_data_hi_r, store_data_lo_r;
-     200            6 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
-     201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
+     197            0 :    logic [31:0] store_data_m;
+     198            0 :    logic [31:0] store_data_r;
+     199            0 :    logic [31:0] store_data_hi_r, store_data_lo_r;
+     200            0 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
+     201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
      202            0 :    logic [31:0] sec_data_lo_r, sec_data_hi_r;
      203              : 
      204            0 :    logic [31:0] lsu_ld_data_m;
@@ -324,12 +324,12 @@
      220              : 
      221            0 :    logic [31:0] picm_mask_data_m;
      222              : 
-     223          140 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
-     224          140 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
+     223          240 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
+     224          240 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
      225              :   assign lsu_pmp_addr_start = lsu_addr_d;
      226              :   assign lsu_pmp_addr_end   = end_addr_d;
      227              : 
-     228          394 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
+     228           24 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
      229            0 :    logic        lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
      230              :   assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
      231              :   assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
@@ -338,7 +338,7 @@
      234            0 :    logic        store_stbuf_reqvld_r;
      235            0 :    logic        ldst_stbuf_reqvld_r;
      236              : 
-     237         1420 :    logic        lsu_commit_r;
+     237          460 :    logic        lsu_commit_r;
      238            0 :    logic        lsu_exc_m;
      239              : 
      240            0 :    logic        addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
@@ -365,11 +365,11 @@
      261            0 :    logic        lsu_stbuf_full_any;
      262              : 
      263              :     // Bus signals
-     264         1420 :    logic        lsu_busreq_r;
-     265          840 :    logic        lsu_bus_buffer_pend_any;
-     266         1281 :    logic        lsu_bus_buffer_empty_any;
+     264          460 :    logic        lsu_busreq_r;
+     265          232 :    logic        lsu_bus_buffer_pend_any;
+     266          456 :    logic        lsu_bus_buffer_empty_any;
      267            0 :    logic        lsu_bus_buffer_full_any;
-     268         1420 :    logic        lsu_busreq_m;
+     268          460 :    logic        lsu_busreq_m;
      269            0 :    logic [31:0] bus_read_data_m;
      270              : 
      271            0 :    logic        flush_m_up, flush_r;
@@ -381,16 +381,16 @@
      277            0 :    logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
      278              : 
      279              :    // Clocks
-     280         1009 :    logic        lsu_busm_clken;
-     281         2180 :    logic        lsu_bus_obuf_c1_clken;
-     282        66208 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283        66208 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284        66208 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     280          234 :    logic        lsu_busm_clken;
+     281          692 :    logic        lsu_bus_obuf_c1_clken;
+     282        14760 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283        14760 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284        14760 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286        66208 :    logic        lsu_stbuf_c1_clk;
-     287        66208 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286        14760 :    logic        lsu_stbuf_c1_clk;
+     287        14760 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289        66208 :    logic        lsu_free_c2_clk;
+     289        14760 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_addrcheck.sv.html
index a3acdcdb690..fabbb02a898 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,16 +131,16 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30        66208 :    input logic          lsu_c2_m_clk,              // clock
+      30        14760 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
-      33          140 :    input logic [31:0]   start_addr_d,              // start address for lsu
-      34          140 :    input logic [31:0]   end_addr_d,                // end address for lsu
-      35          394 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
+      33          240 :    input logic [31:0]   start_addr_d,              // start address for lsu
+      34          240 :    input logic [31:0]   end_addr_d,                // end address for lsu
+      35           24 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
       36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
-      37          476 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
+      37          220 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
       38              : 
-      39          140 :    input logic [31:0]   rs1_d,                     // address rs operand
+      39          240 :    input logic [31:0]   rs1_d,                     // address rs operand
       40              : 
       41            0 :    output logic         is_sideeffects_m,          // is sideffects space
       42            0 :    output logic         addr_in_dccm_d,            // address in dccm
@@ -154,10 +154,10 @@
       50            0 :    output logic         fir_dccm_access_error_d,   // Fast interrupt dccm access error
       51            0 :    output logic         fir_nondccm_access_error_d,// Fast interrupt dccm access error
       52              : 
-      53          190 :     input logic lsu_pmp_error_start,
-      54          190 :     input logic lsu_pmp_error_end,
+      53            0 :     input logic lsu_pmp_error_start,
+      54            0 :     input logic lsu_pmp_error_end,
       55              : 
-      56            0 :    input  logic         scan_mode                  // Scan mode
+      56            0 :    input  logic         scan_mode                  // Scan mode
       57              : );
       58              : 
       59              : 
@@ -167,7 +167,7 @@
       63            0 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
       64            0 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
       65            0 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
-      66          476 :    logic [4:0]  csr_idx;
+      66          220 :    logic [4:0]  csr_idx;
       67            0 :    logic        addr_in_iccm;
       68            0 :    logic        start_addr_dccm_or_pic;
       69            0 :    logic        base_reg_dccm_or_pic;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_buffer.sv.html
index 64c09e672d6..4443c10dc5e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31        66208 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        14760 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -142,34 +142,34 @@
       38            0 :    input logic                          dec_tlu_force_halt,
       39              : 
       40              :    // various clocks needed for the bus reads and writes
-      41         2180 :    input logic                          lsu_bus_obuf_c1_clken,
-      42         1009 :    input logic                          lsu_busm_clken,
-      43        66208 :    input logic                          lsu_c2_r_clk,
-      44        66208 :    input logic                          lsu_bus_ibuf_c1_clk,
+      41          692 :    input logic                          lsu_bus_obuf_c1_clken,
+      42          234 :    input logic                          lsu_busm_clken,
+      43        14760 :    input logic                          lsu_c2_r_clk,
+      44        14760 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46        66208 :    input logic                          lsu_bus_buf_c1_clk,
-      47        66208 :    input logic                          lsu_free_c2_clk,
+      46        14760 :    input logic                          lsu_bus_buf_c1_clk,
+      47        14760 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
-      51         1420 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
-      52          394 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
-      53          394 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
+      51          460 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
+      52           24 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
+      53           24 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
       54              : 
-      55          140 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
-      56          140 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
-      57          140 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
-      58          140 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
-      59            6 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
+      55          240 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
+      56          240 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
+      57          240 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
+      58          240 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
+      59            0 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
       60              : 
-      61          198 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
-      62          118 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
-      63         1420 :    input logic                          lsu_busreq_m,                   // bus request is in m
-      64         1420 :    output logic                         lsu_busreq_r,                   // bus request is in r
+      61           16 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
+      62           16 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
+      63          460 :    input logic                          lsu_busreq_m,                   // bus request is in m
+      64          460 :    output logic                         lsu_busreq_r,                   // bus request is in r
       65            0 :    input logic                          ld_full_hit_m,                  // load can get all its byte from a write buffer entry
       66            4 :    input logic                          flush_m_up,                     // flush
       67            0 :    input logic                          flush_r,                        // flush
-      68         1420 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
+      68          460 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
       69            0 :    input logic                          is_sideeffects_r,               // lsu attribute is side_effects
       70            0 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
       71            0 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
@@ -177,38 +177,38 @@
       73              : 
       74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
       75              : 
-      76          840 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
+      76          232 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
       77            0 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
-      78         1281 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
+      78          456 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
       79              : 
       80            0 :    output logic [3:0]                   ld_byte_hit_buf_lo, ld_byte_hit_buf_hi,    // Byte enables for forwarding data
       81            0 :    output logic [31:0]                  ld_fwddata_buf_lo, ld_fwddata_buf_hi,      // load forwarding data
       82              : 
       83            0 :    output logic                         lsu_imprecise_error_load_any,     // imprecise load bus error
       84            0 :    output logic                         lsu_imprecise_error_store_any,    // imprecise store bus error
-      85          111 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
+      85          220 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
       86              : 
       87              :    // Non-blocking loads
-      88          660 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
-      89          202 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
+      88          228 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
+      89           20 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
       90            0 :    output logic                               lsu_nonblock_load_inv_r,       // invalidate signal for the cam entry for non block loads
-      91          202 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
-      92          718 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
+      91           20 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
+      92          232 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
       93            0 :    output logic                               lsu_nonblock_load_data_error,  // non block load has an error
-      94           36 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
-      95           14 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
+      94            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
+      95            0 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
       96              : 
       97              :    // PMU events
-      98         1548 :    output logic                         lsu_pmu_bus_trxn,
+      98          468 :    output logic                         lsu_pmu_bus_trxn,
       99            0 :    output logic                         lsu_pmu_bus_misaligned,
      100            0 :    output logic                         lsu_pmu_bus_error,
      101            0 :    output logic                         lsu_pmu_bus_busy,
      102              : 
      103              :    // AXI Write Channels
-     104          888 :    output logic                            lsu_axi_awvalid,
-     105         1549 :    input  logic                            lsu_axi_awready,
+     104          240 :    output logic                            lsu_axi_awvalid,
+     105          468 :    input  logic                            lsu_axi_awready,
      106            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     107          111 :    output logic [31:0]                     lsu_axi_awaddr,
+     107          220 :    output logic [31:0]                     lsu_axi_awaddr,
      108            2 :    output logic [3:0]                      lsu_axi_awregion,
      109            0 :    output logic [7:0]                      lsu_axi_awlen,
      110            0 :    output logic [2:0]                      lsu_axi_awsize,
@@ -218,22 +218,22 @@
      114            0 :    output logic [2:0]                      lsu_axi_awprot,
      115            0 :    output logic [3:0]                      lsu_axi_awqos,
      116              : 
-     117          888 :    output logic                            lsu_axi_wvalid,
-     118         1549 :    input  logic                            lsu_axi_wready,
+     117          240 :    output logic                            lsu_axi_wvalid,
+     118          468 :    input  logic                            lsu_axi_wready,
      119            0 :    output logic [63:0]                     lsu_axi_wdata,
-     120          148 :    output logic [7:0]                      lsu_axi_wstrb,
+     120            8 :    output logic [7:0]                      lsu_axi_wstrb,
      121            2 :    output logic                            lsu_axi_wlast,
      122              : 
-     123          886 :    input  logic                            lsu_axi_bvalid,
+     123          236 :    input  logic                            lsu_axi_bvalid,
      124            2 :    output logic                            lsu_axi_bready,
      125            0 :    input  logic [1:0]                      lsu_axi_bresp,
      126            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      127              : 
      128              :    // AXI Read Channels
-     129          660 :    output logic                            lsu_axi_arvalid,
-     130         1549 :    input  logic                            lsu_axi_arready,
+     129          228 :    output logic                            lsu_axi_arvalid,
+     130          468 :    input  logic                            lsu_axi_arready,
      131            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     132          111 :    output logic [31:0]                     lsu_axi_araddr,
+     132          220 :    output logic [31:0]                     lsu_axi_araddr,
      133            2 :    output logic [3:0]                      lsu_axi_arregion,
      134            0 :    output logic [7:0]                      lsu_axi_arlen,
      135            0 :    output logic [2:0]                      lsu_axi_arsize,
@@ -243,10 +243,10 @@
      139            0 :    output logic [2:0]                      lsu_axi_arprot,
      140            0 :    output logic [3:0]                      lsu_axi_arqos,
      141              : 
-     142          718 :    input  logic                            lsu_axi_rvalid,
+     142          232 :    input  logic                            lsu_axi_rvalid,
      143            2 :    output logic                            lsu_axi_rready,
      144            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     145           34 :    input  logic [63:0]                     lsu_axi_rdata,
+     145            8 :    input  logic [63:0]                     lsu_axi_rdata,
      146            0 :    input  logic [1:0]                      lsu_axi_rresp,
      147              : 
      148            2 :    input logic                             lsu_bus_clk_en,
@@ -264,7 +264,7 @@
      160              :    localparam TIMER_MAX = TIMER - 1;  // Maximum value of timer
      161              :    localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);
      162              : 
-     163          325 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
+     163           76 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
      164            0 :    logic [DEPTH-1:0]                    ld_addr_hitvec_lo, ld_addr_hitvec_hi;
      165            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvec_lo, ld_byte_hitvec_hi;
      166            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;
@@ -273,37 +273,37 @@
      169            0 :    logic [3:0]                          ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;
      170              : 
      171            2 :    logic [3:0]                          ldst_byteen_r;
-     172          325 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
-     173            6 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
-     174            2 :    logic                                is_aligned_r;                   // Aligned load/store
+     172           76 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
+     173            0 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
+     174            2 :    logic                                is_aligned_r;                   // Aligned load/store
      175            2 :    logic                                ldst_samedw_r;
      176              : 
-     177          660 :    logic                                lsu_nonblock_load_valid_r;
-     178           48 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
-     179          194 :    logic [1:0]                          lsu_nonblock_addr_offset;
-     180           78 :    logic [1:0]                          lsu_nonblock_sz;
-     181          410 :    logic                                lsu_nonblock_unsign;
-     182          718 :    logic                                lsu_nonblock_load_data_ready;
+     177          228 :    logic                                lsu_nonblock_load_valid_r;
+     178           68 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
+     179          104 :    logic [1:0]                          lsu_nonblock_addr_offset;
+     180            8 :    logic [1:0]                          lsu_nonblock_sz;
+     181          216 :    logic                                lsu_nonblock_unsign;
+     182          232 :    logic                                lsu_nonblock_load_data_ready;
      183              : 
      184            0 :    logic [DEPTH-1:0]                    CmdPtr0Dec, CmdPtr1Dec;
      185            0 :    logic [DEPTH-1:0]                    RspPtrDec;
      186            0 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
      187            0 :    logic [DEPTH_LOG2-1:0]               RspPtr;
-     188          202 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
-     189          414 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
+     188           20 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
+     189          228 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
      190            0 :    logic                                found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;
      191            0 :    logic [3:0]                          buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;
-     192           12 :    logic                                any_done_wait_state;
+     192            4 :    logic                                any_done_wait_state;
      193            0 :    logic                                bus_sideeffect_pend;
      194            2 :    logic                                bus_coalescing_disable;
      195              : 
-     196           92 :    logic                                bus_addr_match_pending;
-     197         1548 :    logic                                bus_cmd_sent, bus_cmd_ready;
-     198          888 :    logic                                bus_wcmd_sent, bus_wdata_sent;
-     199          718 :    logic                                bus_rsp_read, bus_rsp_write;
+     196            4 :    logic                                bus_addr_match_pending;
+     197          468 :    logic                                bus_cmd_sent, bus_cmd_ready;
+     198          240 :    logic                                bus_wcmd_sent, bus_wdata_sent;
+     199          232 :    logic                                bus_rsp_read, bus_rsp_write;
      200            0 :    logic [pt.LSU_BUS_TAG-1:0]           bus_rsp_read_tag, bus_rsp_write_tag;
      201            0 :    logic                                bus_rsp_read_error, bus_rsp_write_error;
-     202           34 :    logic [63:0]                         bus_rsp_rdata;
+     202            8 :    logic [63:0]                         bus_rsp_rdata;
      203              : 
      204              :    // Bus buffer signals
      205            0 :    state_t [DEPTH-1:0]                  buf_state;
@@ -333,21 +333,21 @@
      229            0 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
      230            0 :    logic   [DEPTH-1:0]                  buf_dual_in;
      231            2 :    logic   [DEPTH-1:0]                  buf_samedw_in;
-     232          118 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
+     232           16 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
      233            0 :    logic   [DEPTH-1:0]                  buf_sideeffect_in;
-     234          490 :    logic   [DEPTH-1:0]                  buf_unsign_in;
-     235          402 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
-     236          760 :    logic   [DEPTH-1:0]                  buf_write_in;
+     234          216 :    logic   [DEPTH-1:0]                  buf_unsign_in;
+     235           24 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
+     236          232 :    logic   [DEPTH-1:0]                  buf_write_in;
      237            0 :    logic   [DEPTH-1:0]                  buf_wr_en;
      238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
-     239          414 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
+     239          228 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
      240            0 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
      241            0 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
      242            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
-     243          325 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
-     244          140 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
-     245            6 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
-     246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
+     243           76 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
+     244          240 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
+     245            0 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
+     246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
      247            0 :    logic   [DEPTH-1:0]                  buf_data_en;
      248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
      249            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_ageQ;
@@ -356,69 +356,69 @@
      252            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspageQ;
      253              : 
      254              :    // Input buffer signals
-     255          760 :    logic                               ibuf_valid;
+     255          232 :    logic                               ibuf_valid;
      256            0 :    logic                               ibuf_dual;
      257            2 :    logic                               ibuf_samedw;
      258            0 :    logic                               ibuf_nomerge;
-     259           40 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
-     260           40 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
-     261            0 :    logic                               ibuf_sideeffect;
+     259            0 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
+     260            0 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
+     261            0 :    logic                               ibuf_sideeffect;
      262            0 :    logic                               ibuf_unsign;
      263            2 :    logic                               ibuf_write;
-     264           24 :    logic [1:0]                         ibuf_sz;
-     265           12 :    logic [3:0]                         ibuf_byteen;
-     266           44 :    logic [31:0]                        ibuf_addr;
-     267            6 :    logic [31:0]                        ibuf_data;
-     268          762 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
+     264            4 :    logic [1:0]                         ibuf_sz;
+     265            2 :    logic [3:0]                         ibuf_byteen;
+     266            4 :    logic [31:0]                        ibuf_addr;
+     267            0 :    logic [31:0]                        ibuf_data;
+     268          234 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
      269              : 
-     270          788 :    logic                               ibuf_byp;
-     271          760 :    logic                               ibuf_wr_en;
-     272          760 :    logic                               ibuf_rst;
+     270          236 :    logic                               ibuf_byp;
+     271          232 :    logic                               ibuf_wr_en;
+     272          232 :    logic                               ibuf_rst;
      273            0 :    logic                               ibuf_force_drain;
-     274          760 :    logic                               ibuf_drain_vld;
+     274          232 :    logic                               ibuf_drain_vld;
      275            0 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
-     276          202 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
-     277          202 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
-     278          402 :    logic [1:0]                         ibuf_sz_in;
-     279          140 :    logic [31:0]                        ibuf_addr_in;
-     280          325 :    logic [3:0]                         ibuf_byteen_in;
-     281            6 :    logic [31:0]                        ibuf_data_in;
-     282          762 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
-     283           12 :    logic [3:0]                         ibuf_byteen_out;
-     284            6 :    logic [31:0]                        ibuf_data_out;
-     285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
+     276           20 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
+     277           20 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
+     278           24 :    logic [1:0]                         ibuf_sz_in;
+     279          240 :    logic [31:0]                        ibuf_addr_in;
+     280           76 :    logic [3:0]                         ibuf_byteen_in;
+     281            0 :    logic [31:0]                        ibuf_data_in;
+     282          234 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
+     283            2 :    logic [3:0]                         ibuf_byteen_out;
+     284            0 :    logic [31:0]                        ibuf_data_out;
+     285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
      286              : 
      287              :    // Output buffer signals
-     288         1548 :    logic                               obuf_valid;
-     289          426 :    logic                               obuf_write;
-     290           12 :    logic                               obuf_nosend;
-     291          660 :    logic                               obuf_rdrsp_pend;
+     288          468 :    logic                               obuf_valid;
+     289          222 :    logic                               obuf_write;
+     290            4 :    logic                               obuf_nosend;
+     291          228 :    logic                               obuf_rdrsp_pend;
      292            0 :    logic                               obuf_sideeffect;
-     293          111 :    logic [31:0]                        obuf_addr;
+     293          220 :    logic [31:0]                        obuf_addr;
      294            0 :    logic [63:0]                        obuf_data;
-     295           78 :    logic [1:0]                         obuf_sz;
-     296          288 :    logic [7:0]                         obuf_byteen;
+     295            8 :    logic [1:0]                         obuf_sz;
+     296           40 :    logic [7:0]                         obuf_byteen;
      297            0 :    logic                               obuf_merge;
      298            0 :    logic                               obuf_cmd_done, obuf_data_done;
      299            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0;
      300            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1;
      301            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag;
      302              : 
-     303          708 :    logic                               ibuf_buf_byp;
+     303          236 :    logic                               ibuf_buf_byp;
      304            0 :    logic                               obuf_force_wr_en;
      305            0 :    logic                               obuf_wr_wait;
-     306         1548 :    logic                               obuf_wr_en, obuf_wr_enQ;
-     307         1548 :    logic                               obuf_rst;
-     308          426 :    logic                               obuf_write_in;
-     309          400 :    logic                               obuf_nosend_in;
+     306          468 :    logic                               obuf_wr_en, obuf_wr_enQ;
+     307          468 :    logic                               obuf_rst;
+     308          222 :    logic                               obuf_write_in;
+     309           12 :    logic                               obuf_nosend_in;
      310            2 :    logic                               obuf_rdrsp_pend_en;
-     311          660 :    logic                               obuf_rdrsp_pend_in;
+     311          228 :    logic                               obuf_rdrsp_pend_in;
      312            0 :    logic                               obuf_sideeffect_in;
      313            2 :    logic                               obuf_aligned_in;
-     314          111 :    logic [31:0]                        obuf_addr_in;
-     315            1 :    logic [63:0]                        obuf_data_in;
-     316           78 :    logic [1:0]                         obuf_sz_in;
-     317          308 :    logic [7:0]                         obuf_byteen_in;
+     314          220 :    logic [31:0]                        obuf_addr_in;
+     315            0 :    logic [63:0]                        obuf_data_in;
+     316            8 :    logic [1:0]                         obuf_sz_in;
+     317           40 :    logic [7:0]                         obuf_byteen_in;
      318            0 :    logic                               obuf_merge_in;
      319            0 :    logic                               obuf_cmd_done_in, obuf_data_done_in;
      320            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0_in;
@@ -427,33 +427,33 @@
      323              : 
      324            0 :    logic                               obuf_merge_en;
      325            0 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
-     326          158 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
-     327            1 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
+     326            4 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
+     327            0 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
      328              : 
-     329          888 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
-     330          888 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
-     331          660 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
+     329          240 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
+     330          240 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
+     331          228 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
      332            2 :    logic                               lsu_axi_bvalid_q, lsu_axi_bready_q;
      333            2 :    logic                               lsu_axi_rvalid_q, lsu_axi_rready_q;
      334            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_axi_bid_q, lsu_axi_rid_q;
      335            0 :    logic [1:0]                         lsu_axi_bresp_q, lsu_axi_rresp_q;
      336            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_imprecise_error_store_tag;
-     337           34 :    logic [63:0]                        lsu_axi_rdata_q;
+     337            8 :    logic [63:0]                        lsu_axi_rdata_q;
      338              : 
      339              :    //------------------------------------------------------------------------------
      340              :    // Load forwarding logic start
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344        96618 :    function automatic logic [2:0] f_Enc8to3;
+     344        54826 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348        96618 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349        96618 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350        96618 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348        54826 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349        54826 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350        54826 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352        96618 :       return Enc_value[2:0];
+     352        54826 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -758,51 +758,51 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657       107240 :             IDLE: begin
-     658       107240 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659       107240 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660       107240 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661       107240 :                      buf_wr_en[i]    = buf_state_en[i];
-     662       107240 :                      buf_data_en[i]  = buf_state_en[i];
-     663       107240 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664       107240 :                      buf_cmd_state_bus_en[i]  = '0;
+     657        60465 :             IDLE: begin
+     658        60465 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659        60465 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660        60465 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661        60465 :                      buf_wr_en[i]    = buf_state_en[i];
+     662        60465 :                      buf_data_en[i]  = buf_state_en[i];
+     663        60465 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664        60465 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         2104 :             CMD: begin
-     672         2104 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         2104 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         2104 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         2104 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         2104 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         2104 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         2104 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         2104 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         2104 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         2104 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671         1229 :             CMD: begin
+     672         1229 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673         1229 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674         1229 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675         1229 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676         1229 :                      buf_ldfwd_in[i]          = 1'b1;
+     677         1229 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678         1229 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679         1229 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680         1229 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681         1229 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683         4234 :             RESP: begin
-     684         4234 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685         4234 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686         4234 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687         4234 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688         4234 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689         4234 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690         4234 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691         4234 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692         4234 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693         4234 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694         4234 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695         4234 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683         2471 :             RESP: begin
+     684         2471 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685         2471 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686         2471 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687         2471 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688         2471 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689         2471 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690         2471 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691         2471 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692         2471 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693         2471 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694         2471 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695         2471 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697         4234 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698         4234 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699         4234 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700         4234 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701         4234 :                      buf_cmd_state_bus_en[i]  = '0;
+     697         2471 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698         2471 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699         2471 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700         2471 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701         2471 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
      703            0 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
      704            0 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
@@ -811,18 +811,18 @@
      707            0 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
      708            0 :                      buf_cmd_state_bus_en[i]  = '0;
      709              :             end
-     710           10 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
-     711           10 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
-     712           10 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
-     713           10 :                       buf_cmd_state_bus_en[i]  = '0;
+     710            6 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
+     711            6 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
+     712            6 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
+     713            6 :                       buf_cmd_state_bus_en[i]  = '0;
      714              :             end
-     715          612 :             DONE: begin
-     716          612 :                      buf_nxtstate[i]           = IDLE;
-     717          612 :                      buf_rst[i]                = 1'b1;
-     718          612 :                      buf_state_en[i]           = 1'b1;
-     719          612 :                      buf_ldfwd_in[i]           = 1'b0;
-     720          612 :                      buf_ldfwd_en[i]           = buf_state_en[i];
-     721          612 :                      buf_cmd_state_bus_en[i]  = '0;
+     715          365 :             DONE: begin
+     716          365 :                      buf_nxtstate[i]           = IDLE;
+     717          365 :                      buf_rst[i]                = 1'b1;
+     718          365 :                      buf_state_en[i]           = 1'b1;
+     719          365 :                      buf_ldfwd_in[i]           = 1'b0;
+     720          365 :                      buf_ldfwd_en[i]           = buf_state_en[i];
+     721          365 :                      buf_cmd_state_bus_en[i]  = '0;
      722              :             end
      723            0 :             default : begin
      724            0 :                      buf_nxtstate[i]          = IDLE;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_intf.sv.html
index e68b2f13646..70e028e5a75 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30        66208 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        14760 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -140,71 +140,71 @@
       36            0 :    input logic                          dec_tlu_sideeffect_posted_disable,  // disable the posted sideeffect load store to the bus
       37              : 
       38              :    // various clocks needed for the bus reads and writes
-      39         2180 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
-      40         1009 :    input logic                          lsu_busm_clken,                     // bus clock enable
+      39          692 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
+      40          234 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42        66208 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43        66208 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44        66208 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42        14760 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43        14760 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44        14760 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46        66208 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47        66208 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48        66208 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46        14760 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47        14760 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48        14760 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
-      51         1420 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
-      52         1420 :    input logic                          lsu_busreq_m,                      // bus request is in m
+      51          460 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
+      52          460 :    input logic                          lsu_busreq_m,                      // bus request is in m
       53              : 
-      54          394 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
-      55          394 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
+      54           24 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
+      55           24 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
       56              : 
-      57          140 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
-      58          140 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
+      57          240 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
+      58          240 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
       59              : 
-      60          140 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
-      61          140 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
+      60          240 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
+      61          240 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
       62              : 
-      63            6 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
-      64            0 :    input logic                          dec_tlu_force_halt,
+      63            0 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
+      64            0 :    input logic                          dec_tlu_force_halt,
       65              : 
-      66         1420 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
+      66          460 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
       67            0 :    input logic                          is_sideeffects_m,                  // lsu attribute is side_effects
       68            4 :    input logic                          flush_m_up,                        // flush
       69            0 :    input logic                          flush_r,                           // flush
       70            0 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71              : 
-      72         1420 :    output logic                         lsu_busreq_r,                      // bus request is in r
-      73          840 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      72          460 :    output logic                         lsu_busreq_r,                      // bus request is in r
+      73          232 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
       74            0 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
-      75         1281 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
+      75          456 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
       76            0 :    output logic [31:0]                  bus_read_data_m,                   // the bus return data
       77              : 
       78              : 
       79            0 :    output logic                         lsu_imprecise_error_load_any,      // imprecise load bus error
       80            0 :    output logic                         lsu_imprecise_error_store_any,     // imprecise store bus error
-      81          111 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
+      81          220 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
       82              : 
       83              :    // Non-blocking loads
-      84          660 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
-      85          202 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
+      84          228 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
+      85           20 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
       86            0 :    output logic                               lsu_nonblock_load_inv_r,     // invalidate signal for the cam entry for non block loads
-      87          202 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
-      88          718 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
+      87           20 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
+      88          232 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
       89            0 :    output logic                               lsu_nonblock_load_data_error,// non block load has an error
-      90           36 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
-      91           14 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
+      90            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
+      91            0 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
       92              : 
       93              :    // PMU events
-      94         1548 :    output logic                         lsu_pmu_bus_trxn,
+      94          468 :    output logic                         lsu_pmu_bus_trxn,
       95            0 :    output logic                         lsu_pmu_bus_misaligned,
       96            0 :    output logic                         lsu_pmu_bus_error,
       97            0 :    output logic                         lsu_pmu_bus_busy,
       98              : 
       99              :    // AXI Write Channels
-     100          888 :    output logic                        lsu_axi_awvalid,
-     101         1549 :    input  logic                        lsu_axi_awready,
+     100          240 :    output logic                        lsu_axi_awvalid,
+     101          468 :    input  logic                        lsu_axi_awready,
      102            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_awid,
-     103          111 :    output logic [31:0]                 lsu_axi_awaddr,
+     103          220 :    output logic [31:0]                 lsu_axi_awaddr,
      104            2 :    output logic [3:0]                  lsu_axi_awregion,
      105            0 :    output logic [7:0]                  lsu_axi_awlen,
      106            0 :    output logic [2:0]                  lsu_axi_awsize,
@@ -214,22 +214,22 @@
      110            0 :    output logic [2:0]                  lsu_axi_awprot,
      111            0 :    output logic [3:0]                  lsu_axi_awqos,
      112              : 
-     113          888 :    output logic                        lsu_axi_wvalid,
-     114         1549 :    input  logic                        lsu_axi_wready,
+     113          240 :    output logic                        lsu_axi_wvalid,
+     114          468 :    input  logic                        lsu_axi_wready,
      115            0 :    output logic [63:0]                 lsu_axi_wdata,
-     116          148 :    output logic [7:0]                  lsu_axi_wstrb,
+     116            8 :    output logic [7:0]                  lsu_axi_wstrb,
      117            2 :    output logic                        lsu_axi_wlast,
      118              : 
-     119          886 :    input  logic                        lsu_axi_bvalid,
+     119          236 :    input  logic                        lsu_axi_bvalid,
      120            2 :    output logic                        lsu_axi_bready,
      121            0 :    input  logic [1:0]                  lsu_axi_bresp,
      122            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_bid,
      123              : 
      124              :    // AXI Read Channels
-     125          660 :    output logic                        lsu_axi_arvalid,
-     126         1549 :    input  logic                        lsu_axi_arready,
+     125          228 :    output logic                        lsu_axi_arvalid,
+     126          468 :    input  logic                        lsu_axi_arready,
      127            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_arid,
-     128          111 :    output logic [31:0]                 lsu_axi_araddr,
+     128          220 :    output logic [31:0]                 lsu_axi_araddr,
      129            2 :    output logic [3:0]                  lsu_axi_arregion,
      130            0 :    output logic [7:0]                  lsu_axi_arlen,
      131            0 :    output logic [2:0]                  lsu_axi_arsize,
@@ -239,10 +239,10 @@
      135            0 :    output logic [2:0]                  lsu_axi_arprot,
      136            0 :    output logic [3:0]                  lsu_axi_arqos,
      137              : 
-     138          718 :    input  logic                        lsu_axi_rvalid,
+     138          232 :    input  logic                        lsu_axi_rvalid,
      139            2 :    output logic                        lsu_axi_rready,
      140            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_rid,
-     141           34 :    input  logic [63:0]                 lsu_axi_rdata,
+     141            8 :    input  logic [63:0]                 lsu_axi_rdata,
      142            0 :    input  logic [1:0]                  lsu_axi_rresp,
      143              : 
      144            2 :    input logic                         lsu_bus_clk_en
@@ -256,16 +256,16 @@
      152            2 :    logic [3:0]        ldst_byteen_m, ldst_byteen_r;
      153            0 :    logic [7:0]        ldst_byteen_ext_m, ldst_byteen_ext_r;
      154            0 :    logic [3:0]        ldst_byteen_hi_m, ldst_byteen_hi_r;
-     155          325 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
+     155           76 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
      156            0 :    logic              is_sideeffects_r;
      157              : 
-     158           18 :    logic [63:0]       store_data_ext_r;
-     159            0 :    logic [31:0]       store_data_hi_r;
-     160            6 :    logic [31:0]       store_data_lo_r;
+     158            0 :    logic [63:0]       store_data_ext_r;
+     159            0 :    logic [31:0]       store_data_hi_r;
+     160            0 :    logic [31:0]       store_data_lo_r;
      161              : 
-     162         1514 :    logic              addr_match_dw_lo_r_m;
-     163         1422 :    logic              addr_match_word_lo_r_m;
-     164          118 :    logic              no_word_merge_r, no_dword_merge_r;
+     162          466 :    logic              addr_match_dw_lo_r_m;
+     163          462 :    logic              addr_match_word_lo_r_m;
+     164           16 :    logic              no_word_merge_r, no_dword_merge_r;
      165              : 
      166            0 :    logic              ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
      167            0 :    logic [3:0]        ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_clkdomain.sv.html
index b25afcdb46d..60d7cc3333b 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31        66208 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32        66208 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31        14760 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32        14760 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -144,52 +144,52 @@
       40              : 
       41            0 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
       42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
-      43         1420 :    input logic      lsu_busreq_r,                      // busreq in r
-      44          840 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      45         1281 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
+      43          460 :    input logic      lsu_busreq_r,                      // busreq in r
+      44          232 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      45          456 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
       46            2 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
       47              : 
       48            2 :    input logic      lsu_bus_clk_en,                    // bus clock enable
       49              : 
-      50          402 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
-      51          394 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
-      52          394 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
-      53          394 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
+      50           24 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
+      51           24 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
+      52           24 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
+      53           24 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
       54              : 
       55              :    // Outputs
-      56         2180 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
-      57         1009 :    output logic     lsu_busm_clken,                    // bus clock enable
+      56          692 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
+      57          234 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59        66208 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60        66208 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59        14760 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60        14760 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62        66208 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63        66208 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62        14760 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63        14760 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65        66208 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66        66208 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65        14760 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66        14760 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68        66208 :    output logic     lsu_stbuf_c1_clk,
+      68        14760 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70        66208 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71        66208 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70        14760 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71        14760 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74        66208 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74        14760 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
       78              : 
-      79         1420 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
-      80         1420 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
-      81         1420 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
-      82          760 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
+      79          460 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
+      80          460 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
+      81          460 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
+      82          232 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
       83              : 
       84              : 
       85            0 :    logic lsu_stbuf_c1_clken;
-      86         1009 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
+      86          234 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
       87              : 
-      88          927 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
+      88          230 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
       89              : 
       90              :    //-------------------------------------------------------------------------------------------
       91              :    // Clock Enable logic
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html
index ef8c0a8229e..a8cae1ba448 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,37 +136,37 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35        66208 :    input logic                             lsu_c2_m_clk,            // clocks
-      36        66208 :    input logic                             lsu_c2_r_clk,            // clocks
-      37        66208 :    input logic                             lsu_c1_r_clk,            // clocks
-      38        66208 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39        66208 :    input logic                             lsu_free_c2_clk,         // clocks
+      35        14760 :    input logic                             lsu_c2_m_clk,            // clocks
+      36        14760 :    input logic                             lsu_c2_r_clk,            // clocks
+      37        14760 :    input logic                             lsu_c1_r_clk,            // clocks
+      38        14760 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39        14760 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41        66208 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41        14760 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
-      45          394 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
-      46          394 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
-      47          394 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
+      45           24 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
+      46           24 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
+      47           24 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
       48            0 :    input logic                             addr_in_dccm_d,          // address maps to dccm
       49            0 :    input logic                             addr_in_pic_d,           // address maps to pic
       50            0 :    input logic                             addr_in_pic_m,           // address maps to pic
       51            0 :    input logic                             addr_in_dccm_m, addr_in_dccm_r,   // address in dccm per pipe stage
       52            0 :    input logic                             addr_in_pic_r,                    // address in pic  per pipe stage
       53            0 :    input logic                             lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
-      54         1420 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
+      54          460 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
       55            0 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
       56              : 
       57              :    // lsu address down the pipe
-      58          140 :    input logic [31:0]                      lsu_addr_d,
-      59          140 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
-      60          140 :    input logic [31:0]                      lsu_addr_r,
+      58          240 :    input logic [31:0]                      lsu_addr_d,
+      59          240 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
+      60          240 :    input logic [31:0]                      lsu_addr_r,
       61              : 
       62              :    // lsu address down the pipe - needed to check unaligned
-      63          140 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
-      64          140 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
-      65          140 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
+      63          240 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
+      64          240 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
+      65          240 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
       66              : 
       67              : 
       68            0 :    input logic                             stbuf_reqvld_any,        // write enable
@@ -206,8 +206,8 @@
      102            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_hi_m,           // corrected dccm data
      103            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_lo_m,           // corrected dccm data
      104              : 
-     105            6 :    input logic [31:0]                      store_data_m,            // Store data M-stage
-     106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
+     105            0 :    input logic [31:0]                      store_data_m,            // Store data M-stage
+     106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
      107            0 :    input logic                             dma_pic_wen,             // Perform PIC writes
      108            0 :    input logic [2:0]                       dma_mem_tag_m,           // DMA Buffer entry number M-stage
      109            0 :    input logic [31:0]                      dma_mem_addr,            // DMA request address
@@ -218,11 +218,11 @@
      114            0 :    input logic [pt.DCCM_ECC_WIDTH-1:0]     dma_dccm_wdata_ecc_lo,   // ECC bits for the DMA wdata
      115              : 
      116            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_hi_r,
-     117            6 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
-     118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
-     119            6 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
-     120            6 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
-     121            0 :    output logic                            ld_single_ecc_error_r,
+     117            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
+     118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
+     119            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
+     120            0 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
+     121            0 :    output logic                            ld_single_ecc_error_r,
      122            0 :    output logic                            ld_single_ecc_error_r_ff,
      123              : 
      124            0 :    output logic [31:0]                     picm_mask_data_m,        // pic data to stbuf
@@ -240,8 +240,8 @@
      136            0 :    output logic                            dccm_rden,               // dccm interface -- write
      137            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo,         // dccm interface -- wr addr for lo bank
      138            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi,         // dccm interface -- wr addr for hi bank
-     139          140 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
-     140          140 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
+     139          240 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
+     140          240 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
      141            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,         // dccm write data for lo bank
      142            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,         // dccm write data for hi bank
      143              : 
@@ -252,10 +252,10 @@
      148            0 :    output logic                            picm_wren,               // write to pic
      149            0 :    output logic                            picm_rden,               // read to pick
      150            0 :    output logic                            picm_mken,               // write to pic need a mask
-     151          121 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
-     152          121 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
-     153            6 :    output logic [31:0]                     picm_wr_data,            // write data
-     154            0 :    input logic [31:0]                      picm_rd_data,            // read data
+     151          240 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
+     152          240 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
+     153            0 :    output logic [31:0]                     picm_wr_data,            // write data
+     154            0 :    input logic [31:0]                      picm_rd_data,            // read data
      155              : 
      156            0 :    input logic                             scan_mode                // scan mode
      157              : );
@@ -277,7 +277,7 @@
      173            0 :    logic                           kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
      174              : 
      175              :     // byte_en flowing down
-     176          232 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
+     176           12 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
      177            0 :    logic [7:0]                     store_byteen_ext_m, store_byteen_ext_r;
      178              : 
      179              :    if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_mem.sv.html
index bad804c6b6e..a78b0654794 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35        66208 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36        66208 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35        14760 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        14760 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
@@ -145,8 +145,8 @@
       41            0 :    input logic         dccm_rden,                                       // read enable
       42            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,                     // write address
       43            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,                     // write address
-      44          140 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
-      45          140 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
+      44          240 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
+      45          240 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
       46            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,              // write data
       47            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,              // write data
       48              :    el2_mem_if.veer_dccm                   dccm_mem_export,              // RAM repositioned in testbench and connected by this interface
@@ -164,7 +164,7 @@
       60              : 
       61            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        wren_bank;
       62            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        rden_bank;
-      63          140 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
+      63          240 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
       64            0 :    logic [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+DCCM_WIDTH_BITS)]           rd_addr_even, rd_addr_odd;
       65            0 :    logic                                                                rd_unaligned, wr_unaligned;
       66            0 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0]              dccm_bank_dout;
@@ -172,8 +172,8 @@
       68              : 
       69            0 :    logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0]               wr_data_bank;
       70              : 
-      71          594 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
-      72          594 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
+      71          124 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
+      72          124 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
       73              : 
       74            0 :    logic [pt.DCCM_NUM_BANKS-1:0]            dccm_clken;
       75              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_ecc.sv.html
index a5ced5f1f29..123e23412fb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,22 +135,22 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34        66208 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35        66208 :    input logic                           lsu_c2_r_clk,       // clock
+      34        14760 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        14760 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
       39              : 
-      40          394 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
-      41          394 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
+      40           24 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
+      41           24 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
       42            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  stbuf_data_any,
       43              : 
       44            0 :    input logic                           dec_tlu_core_ecc_disable,  // disables the ecc computation and error flagging
       45              : 
       46            0 :    input logic                           lsu_dccm_rden_r,          // dccm rden
       47            0 :    input logic                           addr_in_dccm_r,           // address in dccm
-      48          140 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
-      49          140 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
+      48          240 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
+      49          240 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
       50            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r,          // data from the dccm
       51            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r,          // data from the dccm
       52            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_r,       // data from the dccm + ecc
@@ -164,8 +164,8 @@
       60            0 :    input logic                           ld_single_ecc_error_r_ff,  // ld has a single ecc error
       61            0 :    input logic                           lsu_dccm_rden_m,           // dccm rden
       62            0 :    input logic                           addr_in_dccm_m,            // address in dccm
-      63          140 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
-      64          140 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
+      63          240 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
+      64          240 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
       65            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m,           // raw data from mem
       66            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m,           // raw data from mem
       67            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_m,        // ecc read out from mem
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html
index ca299f28da3..cb4f4023840 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35        66208 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        14760 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38        66208 :    input logic                lsu_c1_m_clk,
-      39        66208 :    input logic                lsu_c1_r_clk,
-      40        66208 :    input logic                lsu_c2_m_clk,
-      41        66208 :    input logic                lsu_c2_r_clk,
-      42        66208 :    input logic                lsu_store_c1_m_clk,
+      38        14760 :    input logic                lsu_c1_m_clk,
+      39        14760 :    input logic                lsu_c1_r_clk,
+      40        14760 :    input logic                lsu_c2_m_clk,
+      41        14760 :    input logic                lsu_c2_r_clk,
+      42        14760 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
@@ -160,32 +160,32 @@
       56            0 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
       57            0 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
       58              : 
-      59          140 :    input logic [31:0]         exu_lsu_rs1_d,             // address
-      60            6 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
+      59          240 :    input logic [31:0]         exu_lsu_rs1_d,             // address
+      60            0 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
       61              : 
-      62          402 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
-      63         1420 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
-      64           52 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
+      62           24 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
+      63          460 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
+      64            0 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
       65              : 
-      66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
+      66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
       67            0 :    input  logic [31:0]        bus_read_data_m,           // the bus return data
       68            0 :    output logic [31:0]        lsu_result_m,              // lsu load data
       69            0 :    output logic [31:0]        lsu_result_corr_r,         // This is the ECC corrected data going to RF
       70              :    // lsu address down the pipe
-      71          140 :    output logic [31:0]        lsu_addr_d,
-      72          140 :    output logic [31:0]        lsu_addr_m,
-      73          140 :    output logic [31:0]        lsu_addr_r,
+      71          240 :    output logic [31:0]        lsu_addr_d,
+      72          240 :    output logic [31:0]        lsu_addr_m,
+      73          240 :    output logic [31:0]        lsu_addr_r,
       74              :    // lsu address down the pipe - needed to check unaligned
-      75          140 :    output logic [31:0]        end_addr_d,
-      76          140 :    output logic [31:0]        end_addr_m,
-      77          140 :    output logic [31:0]        end_addr_r,
+      75          240 :    output logic [31:0]        end_addr_d,
+      76          240 :    output logic [31:0]        end_addr_m,
+      77          240 :    output logic [31:0]        end_addr_r,
       78              :    // store data down the pipe
-      79            6 :    output logic [31:0]        store_data_m,
+      79            0 :    output logic [31:0]        store_data_m,
       80              : 
-      81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
+      81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
       82            0 :    output logic                lsu_exc_m,                // Access or misaligned fault
       83            0 :    output logic                is_sideeffects_m,         // is sideffects space
-      84         1420 :    output logic                lsu_commit_r,             // lsu instruction in r commits
+      84          460 :    output logic                lsu_commit_r,             // lsu instruction in r commits
       85            0 :    output logic                lsu_single_ecc_error_incr,// LSU inc SB error counter
       86            0 :    output el2_lsu_error_pkt_t lsu_error_pkt_r,          // lsu exception packet
       87              : 
@@ -211,26 +211,26 @@
      107            0 :    input logic [63:0]         dma_mem_wdata,
      108              : 
      109              :    // Store buffer related signals
-     110          394 :    output el2_lsu_pkt_t      lsu_pkt_d,
-     111          394 :    output el2_lsu_pkt_t      lsu_pkt_m,
-     112          394 :    output el2_lsu_pkt_t      lsu_pkt_r,
+     110           24 :    output el2_lsu_pkt_t      lsu_pkt_d,
+     111           24 :    output el2_lsu_pkt_t      lsu_pkt_m,
+     112           24 :    output el2_lsu_pkt_t      lsu_pkt_r,
      113              : 
-     114          190 :     input logic lsu_pmp_error_start,
-     115          190 :     input logic lsu_pmp_error_end,
+     114            0 :     input logic lsu_pmp_error_start,
+     115            0 :     input logic lsu_pmp_error_end,
      116              : 
-     117            0 :    input  logic               scan_mode                  // Scan mode
+     117            0 :    input  logic               scan_mode                  // Scan mode
      118              : 
      119              :    );
      120              : 
      121            0 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
-     122          140 :    logic [31:0]        full_addr_d;
-     123          140 :    logic [31:0]        full_end_addr_d;
-     124          140 :    logic [31:0]        lsu_rs1_d;
-     125           52 :    logic [11:0]        lsu_offset_d;
-     126          140 :    logic [31:0]        rs1_d;
-     127           52 :    logic [11:0]        offset_d;
-     128           52 :    logic [12:0]        end_addr_offset_d;
-     129            0 :    logic [2:0]         addr_offset_d;
+     122          240 :    logic [31:0]        full_addr_d;
+     123          240 :    logic [31:0]        full_end_addr_d;
+     124          240 :    logic [31:0]        lsu_rs1_d;
+     125            0 :    logic [11:0]        lsu_offset_d;
+     126          240 :    logic [31:0]        rs1_d;
+     127            0 :    logic [11:0]        offset_d;
+     128            0 :    logic [12:0]        end_addr_offset_d;
+     129            0 :    logic [2:0]         addr_offset_d;
      130              : 
      131            0 :    logic [63:0]        dma_mem_wdata_shifted;
      132            2 :    logic               addr_external_d;
@@ -242,12 +242,12 @@
      138            0 :    logic               fir_dccm_access_error_m, fir_nondccm_access_error_m;
      139              : 
      140            0 :    logic [3:0]         exc_mscause_d, exc_mscause_m;
-     141          140 :    logic [31:0]        rs1_d_raw;
-     142            6 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
-     143            0 :    logic [31:0]        bus_read_data_r;
+     141          240 :    logic [31:0]        rs1_d_raw;
+     142            0 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
+     143            0 :    logic [31:0]        bus_read_data_r;
      144              : 
      145            0 :    el2_lsu_pkt_t           dma_pkt_d;
-     146          394 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
+     146           24 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
      147            0 :    el2_lsu_error_pkt_t     lsu_error_pkt_m;
      148              : 
      149              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_stbuf.sv.html
index e1542b6119a..3c29627e88c 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,23 +137,23 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36        66208 :    input logic                           clk,                         // core clock
+      36        14760 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39        66208 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40        66208 :    input logic                           lsu_free_c2_clk,             // free clk
+      39        14760 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40        14760 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
-      44         1420 :    input logic                           lsu_commit_r,                // lsu commits
-      45         1420 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
+      44          460 :    input logic                           lsu_commit_r,                // lsu commits
+      45          460 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
       46            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_hi_r,             // merged data from the dccm for stores. This is used for fwding
-      47            6 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
-      48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
-      49            6 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
+      47            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
+      48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
+      49            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
       50              : 
       51              :    // Store Buffer output
-      52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
+      52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
       53            0 :    output logic                          stbuf_reqvld_flushed_any,    // Top entry is flushed
       54            0 :    output logic [pt.LSU_SB_BITS-1:0]     stbuf_addr_any,              // address
       55            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any,              // stbuf data
@@ -163,13 +163,13 @@
       59            2 :    output logic                          lsu_stbuf_empty_any,         // stbuf is empty
       60            0 :    output logic                          ldst_stbuf_reqvld_r,         // needed for clocking
       61              : 
-      62          140 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
-      63          140 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
-      64          140 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
+      62          240 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
+      63          240 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
+      64          240 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
       65              : 
-      66          140 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
-      67          140 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
-      68          140 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
+      66          240 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
+      67          240 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
+      68          240 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
       69              : 
       70            0 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71            0 :    input logic                           addr_in_dccm_m,              // address is in dccm
@@ -177,8 +177,8 @@
       73              : 
       74              :    // Forwarding signals
       75            0 :    input logic                           lsu_cmpen_m,                 // needed for forwarding stbuf - load
-      76          394 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
-      77          394 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
+      76           24 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
+      77           24 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
       78              : 
       79            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m,          // stbuf data
       80            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m,          // stbuf data
@@ -206,13 +206,13 @@
      102            0 :    logic [DEPTH-1:0]                     stbuf_wr_en;
      103            0 :    logic [DEPTH-1:0]                     stbuf_dma_kill_en;
      104            0 :    logic [DEPTH-1:0]                     stbuf_reset;
-     105          140 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
+     105          240 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
      106            0 :    logic [DEPTH-1:0][DATA_WIDTH-1:0]     stbuf_datain;
      107            0 :    logic [DEPTH-1:0][BYTE_WIDTH-1:0]     stbuf_byteenin;
      108              : 
      109            0 :    logic [7:0]             store_byteen_ext_r;
      110            0 :    logic [BYTE_WIDTH-1:0]  store_byteen_hi_r;
-     111          240 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
+     111           12 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
      112              : 
      113            0 :    logic                   WrPtrEn, RdPtrEn;
      114            0 :    logic [DEPTH_LOG2-1:0]  WrPtr, RdPtr;
@@ -225,7 +225,7 @@
      121            0 :    logic [3:0]             stbuf_numvld_any, stbuf_specvld_any;
      122            0 :    logic [1:0]             stbuf_specvld_m, stbuf_specvld_r;
      123              : 
-     124          140 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
+     124          240 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
      125              : 
      126              :    // variables to detect matching from the store queue
      127            0 :    logic [DEPTH-1:0]                 stbuf_match_hi, stbuf_match_lo;
@@ -241,7 +241,7 @@
      137            0 :    logic [BYTE_WIDTH-1:0]  ld_byte_hit_hi, ld_byte_rhit_hi;
      138              : 
      139            0 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_hi_r;
-     140          325 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
+     140           76 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
      141              :    // byte_en flowing down
      142            0 :    logic [7:0]             ldst_byteen_r;
      143            0 :    logic [7:0]             ldst_byteen_ext_r;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_trigger.sv.html
index 07086465d97..c82878b5132 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,11 +132,11 @@
       28              : `include "el2_param.vh"
       29              :  )(
       30            0 :    input el2_trigger_pkt_t [3:0] trigger_pkt_any,            // trigger packet from dec
-      31          394 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
-      32          140 :    input logic [31:0]             lsu_addr_m,                 // address
-      33            6 :    input logic [31:0]             store_data_m,               // store data
+      31           24 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
+      32          240 :    input logic [31:0]             lsu_addr_m,                 // address
+      33            0 :    input logic [31:0]             store_data_m,               // store data
       34              : 
-      35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
+      35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
       36              : );
       37              : 
       38            0 :    logic               trigger_enable;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem.sv.html
index 27b47497094..3f8a1387fc6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25        66208 :    input logic         clk,
+      25        14760 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -137,8 +137,8 @@
       33            0 :    input logic         dccm_rden,
       34            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,
       35            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,
-      36          140 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
-      37          140 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
+      36          240 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
+      37          240 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
       38            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
       39            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
       40              : 
@@ -147,7 +147,7 @@
       43            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
       44              : 
       45              :    //ICCM ports
-      46           26 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
+      46            4 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
       47            0 :    input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
       48            0 :    input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
       49            0 :    input logic         iccm_wren,
@@ -164,12 +164,12 @@
       60            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
       61            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
       62            0 :    input  logic         ic_rd_en,
-      63          962 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-      64         3842 :    input  logic         ic_sel_premux_data, // Premux data sel
+      63           44 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+      64          970 :    input  logic         ic_sel_premux_data, // Premux data sel
       65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
       66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
       67              : 
-      68          150 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+      68           16 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
       69            0 :    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
       70            0 :    output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       71            0 :    input  logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -178,7 +178,7 @@
       74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
       75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
       76              : 
-      77          962 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      77           44 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
       79              : 
       80              : 
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92        66208 :    logic active_clk;
+      92        14760 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem_if.sv.html
index 80253f17d1b..652f6518e5e 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,14 +130,14 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29        96804 :   logic                                                               clk;
+      29        22308 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
       33              :   // ICCM
       34            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
       35            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_wren_bank;
-      36           78 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
+      36           12 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
       37              : 
       38            0 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_wr_data;
       39            0 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
@@ -149,7 +149,7 @@
       45              :   // DCCM
       46            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_clken;
       47            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
-      48          420 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
+      48          720 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
       49            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
       50            0 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
       51            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pic_ctrl.sv.html
index e2379cd1c69..5272b96afcd 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,16 +131,16 @@
       27              :  )
       28              :                   (
       29              : 
-      30        66208 :                      input  logic                   clk,                  // Core clock
-      31        66208 :                      input  logic                   free_clk,             // free clock
+      30        14760 :                      input  logic                   clk,                  // Core clock
+      31        14760 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
       35            0 :                      input  logic [pt.PIC_TOTAL_INT_PLUS1-1:0]   extintsrc_req,  // Interrupt requests
-      36          121 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
-      37          121 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
-      38            6 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
-      39            0 :                      input  logic                   picm_wren,            // Write enable to the register
+      36          240 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
+      37          240 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
+      38            0 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
+      39            0 :                      input  logic                   picm_wren,            // Write enable to the register
       40            0 :                      input  logic                   picm_rden,            // Read enable for the register
       41            0 :                      input  logic                   picm_mken,            // Read the Mask for the register
       42            0 :                      input  logic [3:0]             meicurpl,             // Current Priority Level
@@ -185,11 +185,11 @@
       81              : 
       82            0 : logic  raddr_config_pic_match ;
       83            0 : logic  raddr_intenable_base_match;
-      84          946 : logic  raddr_intpriority_base_match;
+      84          242 : logic  raddr_intpriority_base_match;
       85            0 : logic  raddr_config_gw_base_match ;
       86              : 
       87            0 : logic  waddr_config_pic_match ;
-      88          946 : logic  waddr_intpriority_base_match;
+      88          242 : logic  waddr_intpriority_base_match;
       89            0 : logic  waddr_intenable_base_match;
       90            0 : logic  waddr_config_gw_base_match ;
       91            0 : logic  addr_clear_gw_base_match ;
@@ -228,16 +228,16 @@
      124            0 : logic                                        intpriord;
      125            0 : logic                                        config_reg_we ;
      126            0 : logic                                        config_reg_re ;
-     127          216 : logic                                        config_reg_in ;
+     127          100 : logic                                        config_reg_in ;
      128            0 : logic                                        prithresh_reg_write , prithresh_reg_read;
      129            0 : logic                                        intpriority_reg_read ;
      130            0 : logic                                        intenable_reg_read   ;
      131            0 : logic                                        gw_config_reg_read   ;
      132            0 : logic                                        picm_wren_ff , picm_rden_ff ;
-     133          121 : logic [31:0]                                 picm_raddr_ff;
-     134          121 : logic [31:0]                                 picm_waddr_ff;
-     135            6 : logic [31:0]                                 picm_wr_data_ff;
-     136            0 : logic [3:0]                                  mask;
+     133          240 : logic [31:0]                                 picm_raddr_ff;
+     134          240 : logic [31:0]                                 picm_waddr_ff;
+     135            0 : logic [31:0]                                 picm_wr_data_ff;
+     136            0 : logic [3:0]                                  mask;
      137            0 : logic                                        picm_mken_ff;
      138            0 : logic [ID_BITS-1:0]                          claimid_in ;
      139            0 : logic [INTPRIORITY_BITS-1:0]                 pl_in ;
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155        66208 :    logic                                     pic_raddr_c1_clk;
-     156        66208 :    logic                                     pic_data_c1_clk;
-     157        66208 :    logic                                     pic_pri_c1_clk;
-     158        66208 :    logic                                     pic_int_c1_clk;
-     159        66208 :    logic                                     gw_config_c1_clk;
+     155        14760 :    logic                                     pic_raddr_c1_clk;
+     156        14760 :    logic                                     pic_data_c1_clk;
+     157        14760 :    logic                                     pic_pri_c1_clk;
+     158        14760 :    logic                                     pic_int_c1_clk;
+     159        14760 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500       913600 :               if (intenable_reg_re[i]) begin
+     500       516288 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503       913600 :               if (intpriority_reg_re[i]) begin
+     503       516288 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506       913600 :               if (gw_config_reg_re[i]) begin
+     506       516288 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -627,7 +627,7 @@
      523              : 
      524              : assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0] ;
      525              : 
-     526          140 : logic [14:0] address;
+     526          240 : logic [14:0] address;
      527              : 
      528              : assign address[14:0] = picm_raddr_ff[14:0];
      529              : 
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562      1000308 :                              input logic rawclk,
+     562       230516 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pmp.sv.html
index f7d12fd097b..4f969b434fb 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,29 +127,29 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26        66208 :     input logic clk,       // Top level clock
+      26        14760 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35            0 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36            2 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36              :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
-      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
+      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
       40              :     input logic             [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],
       41              : 
-      42          140 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
+      42          240 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
       43            0 :     input  el2_pmp_type_pkt_t        pmp_chan_type[PMP_CHANNELS],
-      44          190 :     output logic                     pmp_chan_err [PMP_CHANNELS]
+      44            0 :     output logic                     pmp_chan_err [PMP_CHANNELS]
       45              : );
       46              : 
       47              :   logic [                33:0]                     csr_pmp_addr_i          [pt.PMP_ENTRIES];
-      48          140 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
+      48          240 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
       49              : 
       50              :   logic [                33:0]                     region_start_addr       [pt.PMP_ENTRIES];
       51              :   logic [33:PMP_GRANULARITY+2]                     region_addr_mask        [pt.PMP_ENTRIES];
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60            1 :   logic any_region_enabled;
+      60              :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133      1710432 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133       967776 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139      1710432 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139       967776 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            3 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       109734 :       if (!matched && match_all[r]) begin
-     170       109734 :         access_fail = ~final_perm_check[r];
-     171       109734 :         matched = 1'b1;
+     169        62370 :       if (!matched && match_all[r]) begin
+     170        62370 :         access_fail = ~final_perm_check[r];
+     171        62370 :         matched = 1'b1;
      172              :       end
      173              :     end
      174            6 :     return access_fail;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223            2 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -348,12 +348,12 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247      1285074 :           OFF:     region_match_all[c][r] = 1'b0;
+     247       726354 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250        85326 :           TOR: begin
-     251        85326 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252        85326 :                                      region_match_lt[c][r];
+     250        48078 :           TOR: begin
+     251        48078 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252        48078 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer.sv.html
index 5da31fc5f40..42199ae88be 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29        66208 :    input logic                  clk,
+      29        14760 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
@@ -138,12 +138,12 @@
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37        66208 :    output logic                 active_l2clk,
-      38        66208 :    output logic                 free_l2clk,
+      37        14760 :    output logic                 active_l2clk,
+      38        14760 :    output logic                 free_l2clk,
       39              : 
-      40          471 :    output logic [31:0] trace_rv_i_insn_ip,
+      40            8 :    output logic [31:0] trace_rv_i_insn_ip,
       41            2 :    output logic [31:0] trace_rv_i_address_ip,
-      42         4304 :    output logic   trace_rv_i_valid_ip,
+      42          976 :    output logic   trace_rv_i_valid_ip,
       43            0 :    output logic   trace_rv_i_exception_ip,
       44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
       45            0 :    output logic   trace_rv_i_interrupt_ip,
@@ -182,8 +182,8 @@
       78            0 :    output logic                          dccm_rden,
       79            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_lo,
       80            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_hi,
-      81          140 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
-      82          140 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
+      81          240 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
+      82          240 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
       83            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
       84            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_hi,
       85              : 
@@ -191,7 +191,7 @@
       87            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_hi,
       88              : 
       89              :    // ICCM ports
-      90           26 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
+      90            4 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
       91            0 :    output logic                  iccm_wren,
       92            0 :    output logic                  iccm_rden,
       93            0 :    output logic [2:0]            iccm_wr_size,
@@ -208,16 +208,16 @@
      104            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_wr_en,
      105            0 :    output logic                  ic_rd_en,
      106              : 
-     107          150 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     108          962 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     107           16 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     108           44 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      109            0 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      112              : 
      113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
      114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     115          962 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     116         3842 :    output logic                      ic_sel_premux_data, // Select premux data
+     115           44 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     116          970 :    output logic                      ic_sel_premux_data, // Select premux data
      117              : 
      118              : 
      119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -233,10 +233,10 @@
      129              : 
      130              :    //-------------------------- LSU AXI signals--------------------------
      131              :    // AXI Write Channels
-     132          888 :    output logic                            lsu_axi_awvalid,
+     132          240 :    output logic                            lsu_axi_awvalid,
      133            0 :    input  logic                            lsu_axi_awready,
      134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     135          111 :    output logic [31:0]                     lsu_axi_awaddr,
+     135          220 :    output logic [31:0]                     lsu_axi_awaddr,
      136            2 :    output logic [3:0]                      lsu_axi_awregion,
      137            0 :    output logic [7:0]                      lsu_axi_awlen,
      138            0 :    output logic [2:0]                      lsu_axi_awsize,
@@ -246,10 +246,10 @@
      142            0 :    output logic [2:0]                      lsu_axi_awprot,
      143            0 :    output logic [3:0]                      lsu_axi_awqos,
      144              : 
-     145          888 :    output logic                            lsu_axi_wvalid,
+     145          240 :    output logic                            lsu_axi_wvalid,
      146            0 :    input  logic                            lsu_axi_wready,
      147            0 :    output logic [63:0]                     lsu_axi_wdata,
-     148          148 :    output logic [7:0]                      lsu_axi_wstrb,
+     148            8 :    output logic [7:0]                      lsu_axi_wstrb,
      149            2 :    output logic                            lsu_axi_wlast,
      150              : 
      151            0 :    input  logic                            lsu_axi_bvalid,
@@ -258,10 +258,10 @@
      154            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      155              : 
      156              :    // AXI Read Channels
-     157          660 :    output logic                            lsu_axi_arvalid,
+     157          228 :    output logic                            lsu_axi_arvalid,
      158            0 :    input  logic                            lsu_axi_arready,
      159            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     160          111 :    output logic [31:0]                     lsu_axi_araddr,
+     160          220 :    output logic [31:0]                     lsu_axi_araddr,
      161            2 :    output logic [3:0]                      lsu_axi_arregion,
      162            0 :    output logic [7:0]                      lsu_axi_arlen,
      163            0 :    output logic [2:0]                      lsu_axi_arsize,
@@ -305,10 +305,10 @@
      201            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      202              : 
      203              :    // AXI Read Channels
-     204         4336 :    output logic                            ifu_axi_arvalid,
+     204          988 :    output logic                            ifu_axi_arvalid,
      205            0 :    input  logic                            ifu_axi_arready,
-     206         2620 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-     207         1684 :    output logic [31:0]                     ifu_axi_araddr,
+     206          512 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     207           20 :    output logic [31:0]                     ifu_axi_araddr,
      208            2 :    output logic [3:0]                      ifu_axi_arregion,
      209            0 :    output logic [7:0]                      ifu_axi_arlen,
      210            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -419,24 +419,24 @@
      315            0 :    output logic                  hmastlock,
      316            0 :    output logic [3:0]            hprot,
      317            0 :    output logic [2:0]            hsize,
-     318         4336 :    output logic [1:0]            htrans,
+     318          988 :    output logic [1:0]            htrans,
      319            0 :    output logic                  hwrite,
      320              : 
-     321          576 :    input  logic [63:0]           hrdata,
+     321           16 :    input  logic [63:0]           hrdata,
      322            2 :    input  logic                  hready,
      323            0 :    input  logic                  hresp,
      324              : 
      325              :    // LSU AHB Master
-     326          111 :    output logic [31:0]          lsu_haddr,
+     326          220 :    output logic [31:0]          lsu_haddr,
      327            0 :    output logic [2:0]           lsu_hburst,
      328            0 :    output logic                 lsu_hmastlock,
      329            0 :    output logic [3:0]           lsu_hprot,
      330            0 :    output logic [2:0]           lsu_hsize,
-     331         1548 :    output logic [1:0]           lsu_htrans,
-     332          426 :    output logic                 lsu_hwrite,
-     333           25 :    output logic [63:0]          lsu_hwdata,
+     331          468 :    output logic [1:0]           lsu_htrans,
+     332          222 :    output logic                 lsu_hwrite,
+     333           48 :    output logic [63:0]          lsu_hwdata,
      334              : 
-     335           34 :    input  logic [63:0]          lsu_hrdata,
+     335            8 :    input  logic [63:0]          lsu_hrdata,
      336            2 :    input  logic                 lsu_hready,
      337            0 :    input  logic                 lsu_hresp,
      338              : 
@@ -496,12 +496,12 @@
      392              : 
      393              : 
      394              : 
-     395          386 :    logic [63:0]                  hwdata_nc;
+     395           12 :    logic [63:0]                  hwdata_nc;
      396              :    //----------------------------------------------------------------------
      397              :    //
      398              :    //----------------------------------------------------------------------
      399              : 
-     400         4305 :    logic                         ifu_pmu_instr_aligned;
+     400          978 :    logic                         ifu_pmu_instr_aligned;
      401            0 :    logic                         ifu_ic_error_start;
      402            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
      403            0 :    logic                         ifu_iccm_rd_ecc_single_err;
@@ -509,55 +509,55 @@
      405            0 :    logic                         lsu_dccm_rd_ecc_single_err;
      406            0 :    logic                         lsu_dccm_rd_ecc_double_err;
      407              : 
-     408         1549 :    logic                         lsu_axi_awready_ahb;
-     409         1549 :    logic                         lsu_axi_wready_ahb;
-     410          886 :    logic                         lsu_axi_bvalid_ahb;
+     408          468 :    logic                         lsu_axi_awready_ahb;
+     409          468 :    logic                         lsu_axi_wready_ahb;
+     410          236 :    logic                         lsu_axi_bvalid_ahb;
      411            0 :    logic                         lsu_axi_bready_ahb;
      412            0 :    logic [1:0]                   lsu_axi_bresp_ahb;
      413            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
-     414         1549 :    logic                         lsu_axi_arready_ahb;
-     415          718 :    logic                         lsu_axi_rvalid_ahb;
+     414          468 :    logic                         lsu_axi_arready_ahb;
+     415          232 :    logic                         lsu_axi_rvalid_ahb;
      416            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
-     417           34 :    logic [63:0]                  lsu_axi_rdata_ahb;
+     417            8 :    logic [63:0]                  lsu_axi_rdata_ahb;
      418            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
      419            2 :    logic                         lsu_axi_rlast_ahb;
      420              : 
-     421         1549 :    logic                         lsu_axi_awready_int;
-     422         1549 :    logic                         lsu_axi_wready_int;
-     423          886 :    logic                         lsu_axi_bvalid_int;
+     421          468 :    logic                         lsu_axi_awready_int;
+     422          468 :    logic                         lsu_axi_wready_int;
+     423          236 :    logic                         lsu_axi_bvalid_int;
      424            0 :    logic                         lsu_axi_bready_int;
      425            0 :    logic [1:0]                   lsu_axi_bresp_int;
      426            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
-     427         1549 :    logic                         lsu_axi_arready_int;
-     428          718 :    logic                         lsu_axi_rvalid_int;
+     427          468 :    logic                         lsu_axi_arready_int;
+     428          232 :    logic                         lsu_axi_rvalid_int;
      429            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
-     430           34 :    logic [63:0]                  lsu_axi_rdata_int;
+     430            8 :    logic [63:0]                  lsu_axi_rdata_int;
      431            0 :    logic [1:0]                   lsu_axi_rresp_int;
      432            2 :    logic                         lsu_axi_rlast_int;
      433              : 
-     434         4336 :    logic                         ifu_axi_awready_ahb;
-     435         4336 :    logic                         ifu_axi_wready_ahb;
+     434          988 :    logic                         ifu_axi_awready_ahb;
+     435          988 :    logic                         ifu_axi_wready_ahb;
      436            0 :    logic                         ifu_axi_bvalid_ahb;
      437            0 :    logic                         ifu_axi_bready_ahb;
      438            0 :    logic [1:0]                   ifu_axi_bresp_ahb;
-     439         1120 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
-     440         4336 :    logic                         ifu_axi_arready_ahb;
-     441         8669 :    logic                         ifu_axi_rvalid_ahb;
-     442         1120 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
-     443          576 :    logic [63:0]                  ifu_axi_rdata_ahb;
+     439          446 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
+     440          988 :    logic                         ifu_axi_arready_ahb;
+     441         1974 :    logic                         ifu_axi_rvalid_ahb;
+     442          446 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
+     443           16 :    logic [63:0]                  ifu_axi_rdata_ahb;
      444            0 :    logic [1:0]                   ifu_axi_rresp_ahb;
      445            2 :    logic                         ifu_axi_rlast_ahb;
      446              : 
-     447         4336 :    logic                         ifu_axi_awready_int;
-     448         4336 :    logic                         ifu_axi_wready_int;
+     447          988 :    logic                         ifu_axi_awready_int;
+     448          988 :    logic                         ifu_axi_wready_int;
      449            0 :    logic                         ifu_axi_bvalid_int;
      450            0 :    logic                         ifu_axi_bready_int;
      451            0 :    logic [1:0]                   ifu_axi_bresp_int;
-     452         1120 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
-     453         4336 :    logic                         ifu_axi_arready_int;
-     454         8669 :    logic                         ifu_axi_rvalid_int;
-     455         1120 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
-     456          576 :    logic [63:0]                  ifu_axi_rdata_int;
+     452          446 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
+     453          988 :    logic                         ifu_axi_arready_int;
+     454         1974 :    logic                         ifu_axi_rvalid_int;
+     455          446 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
+     456           16 :    logic [63:0]                  ifu_axi_rdata_int;
      457            0 :    logic [1:0]                   ifu_axi_rresp_int;
      458            2 :    logic                         ifu_axi_rlast_int;
      459              : 
@@ -636,13 +636,13 @@
      532            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
      533              : 
      534              : 
-     535         3562 :    logic         dec_i0_rs1_en_d;
-     536         1556 :    logic         dec_i0_rs2_en_d;
-     537           12 :    logic  [31:0] gpr_i0_rs1_d;
-     538           18 :    logic  [31:0] gpr_i0_rs2_d;
+     535          924 :    logic         dec_i0_rs1_en_d;
+     536          244 :    logic         dec_i0_rs2_en_d;
+     537            8 :    logic  [31:0] gpr_i0_rs1_d;
+     538            8 :    logic  [31:0] gpr_i0_rs2_d;
      539              : 
-     540           18 :    logic [31:0] dec_i0_result_r;
-     541          110 :    logic [31:0] exu_i0_result_x;
+     540           16 :    logic [31:0] dec_i0_result_r;
+     541           16 :    logic [31:0] exu_i0_result_x;
      542            2 :    logic [31:1] exu_i0_pc_x;
      543            2 :    logic [31:1] exu_npc_r;
      544              : 
@@ -653,70 +653,70 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552          324 :    logic [31:0] dec_i0_immed_d;
-     553          238 :    logic [12:1] dec_i0_br_immed_d;
-     554          244 :    logic         dec_i0_select_pc_d;
+     552           16 :    logic [31:0] dec_i0_immed_d;
+     553            8 :    logic [12:1] dec_i0_br_immed_d;
+     554           20 :    logic         dec_i0_select_pc_d;
      555              : 
      556           10 :    logic [31:1] dec_i0_pc_d;
-     557           40 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
-     558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
+     557            0 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
+     558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
-     560         3113 :    logic         dec_i0_alu_decode_d;
-     561         1167 :    logic         dec_i0_branch_d;
+     560          530 :    logic         dec_i0_alu_decode_d;
+     561          246 :    logic         dec_i0_branch_d;
      562              : 
-     563         4336 :    logic         ifu_miss_state_idle;
+     563          988 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
      565            0 :    logic         dec_tlu_flush_leak_one_r;
      566            0 :    logic         dec_tlu_flush_err_r;
-     567         4305 :    logic         ifu_i0_valid;
-     568          132 :    logic [31:0]  ifu_i0_instr;
+     567          978 :    logic         ifu_i0_valid;
+     568           12 :    logic [31:0]  ifu_i0_instr;
      569           10 :    logic [31:1]  ifu_i0_pc;
      570              : 
-     571          345 :    logic        exu_flush_final;
+     571           70 :    logic        exu_flush_final;
      572              : 
-     573          112 :    logic [31:1] exu_flush_path_final;
+     573            4 :    logic [31:1] exu_flush_path_final;
      574              : 
-     575          140 :    logic [31:0] exu_lsu_rs1_d;
-     576            6 :    logic [31:0] exu_lsu_rs2_d;
+     575          240 :    logic [31:0] exu_lsu_rs1_d;
+     576            0 :    logic [31:0] exu_lsu_rs2_d;
      577              : 
      578              : 
-     579          402 :    el2_lsu_pkt_t    lsu_p;
-     580         3081 :    logic             dec_qual_lsu_d;
+     579           24 :    el2_lsu_pkt_t    lsu_p;
+     580          532 :    logic             dec_qual_lsu_d;
      581              : 
-     582         1420 :    logic        dec_lsu_valid_raw_d;
-     583           52 :    logic [11:0] dec_lsu_offset_d;
+     582          460 :    logic        dec_lsu_valid_raw_d;
+     583            0 :    logic [11:0] dec_lsu_offset_d;
      584              : 
-     585            0 :    logic [31:0]  lsu_result_m;
+     585            0 :    logic [31:0]  lsu_result_m;
      586            0 :    logic [31:0]  lsu_result_corr_r;     // This is the ECC corrected data going to RF
      587            0 :    logic         lsu_single_ecc_error_incr;     // Increment the ecc counter
      588            0 :    el2_lsu_error_pkt_t lsu_error_pkt_r;
      589            0 :    logic         lsu_imprecise_error_load_any;
      590            0 :    logic         lsu_imprecise_error_store_any;
-     591          111 :    logic [31:0]  lsu_imprecise_error_addr_any;
+     591          220 :    logic [31:0]  lsu_imprecise_error_addr_any;
      592            0 :    logic         lsu_load_stall_any;       // This is for blocking loads
      593            0 :    logic         lsu_store_stall_any;      // This is for blocking stores
-     594          969 :    logic         lsu_idle_any;             // doesn't include DMA
-     595          967 :    logic         lsu_active;               // lsu is active. used for clock
+     594          236 :    logic         lsu_idle_any;             // doesn't include DMA
+     595          234 :    logic         lsu_active;               // lsu is active. used for clock
      596              : 
      597              : 
      598            0 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
      599            0 :    logic [1:0]   lsu_fir_error;       // Error during fast interrupt lookup
      600              : 
      601              :    // Non-blocking loads
-     602          660 :    logic                                 lsu_nonblock_load_valid_m;
-     603          202 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
+     602          228 :    logic                                 lsu_nonblock_load_valid_m;
+     603           20 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
      604            0 :    logic                                 lsu_nonblock_load_inv_r;
-     605          202 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
-     606          718 :    logic                                 lsu_nonblock_load_data_valid;
-     607           36 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
-     608           14 :    logic [31:0]                          lsu_nonblock_load_data;
+     605           20 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
+     606          232 :    logic                                 lsu_nonblock_load_data_valid;
+     607            0 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
+     608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
-     610           24 :    logic        dec_csr_ren_d;
-     611           41 :    logic [31:0] dec_csr_rddata_d;
+     610            4 :    logic        dec_csr_ren_d;
+     611            0 :    logic [31:0] dec_csr_rddata_d;
      612              : 
-     613            0 :    logic [31:0] exu_csr_rs1_x;
+     613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
-     615         4304 :    logic        dec_tlu_i0_commit_cmt;
+     615          976 :    logic        dec_tlu_i0_commit_cmt;
      616            4 :    logic        dec_tlu_flush_lower_r;
      617            4 :    logic        dec_tlu_flush_lower_wb;
      618            0 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
@@ -725,7 +725,7 @@
      621            0 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624         2237 :    logic        ifu_i0_pc4;
+     624          482 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
@@ -735,30 +735,30 @@
      631            0 :    logic [31:0] exu_div_result;
      632            0 :    logic exu_div_wren;
      633              : 
-     634         4305 :    logic dec_i0_decode_d;
+     634          978 :    logic dec_i0_decode_d;
      635              : 
      636              : 
-     637          238 :    logic [31:1] pred_correct_npc_x;
+     637           16 :    logic [31:1] pred_correct_npc_x;
      638              : 
-     639          258 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
+     639            8 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
      640              : 
-     641            2 :    el2_predict_pkt_t  exu_mp_pkt;
-     642          206 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643          122 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
-     644          108 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
+     641            0 :    el2_predict_pkt_t  exu_mp_pkt;
+     642           20 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
+     643            2 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     644            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647          122 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648          576 :    logic [1:0]  exu_i0_br_hist_r;
+     647            2 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648          172 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651          746 :    logic        exu_i0_br_valid_r;
-     652          314 :    logic        exu_i0_br_mp_r;
-     653         1268 :    logic        exu_i0_br_middle_r;
+     651          208 :    logic        exu_i0_br_valid_r;
+     652           64 :    logic        exu_i0_br_mp_r;
+     653          268 :    logic        exu_i0_br_middle_r;
      654              : 
-     655          258 :    logic        exu_i0_br_way_r;
+     655            8 :    logic        exu_i0_br_way_r;
      656              : 
-     657           26 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
+     657            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
      658              : 
      659            0 :    logic        dma_dccm_req;
      660            0 :    logic        dma_iccm_req;
@@ -779,8 +779,8 @@
      675              : 
      676            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
      677            0 :    logic        dma_iccm_stall_any;       // Stall the fetch
-     678         1422 :    logic        dccm_ready;
-     679          343 :    logic        iccm_ready;
+     678          462 :    logic        dccm_ready;
+     679           68 :    logic        iccm_ready;
      680              : 
      681            0 :    logic        dma_pmu_dccm_read;
      682            0 :    logic        dma_pmu_dccm_write;
@@ -795,29 +795,29 @@
      691            0 :    logic        ifu_i0_dbecc;
      692            0 :    logic        iccm_dma_sb_error;
      693              : 
-     694           62 :    el2_br_pkt_t i0_brp;
-     695          122 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696          554 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     694           12 :    el2_br_pkt_t i0_brp;
+     695           20 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
+     696           10 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697            0 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
      700            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
      701              : 
      702              : 
-     703          232 :    el2_predict_pkt_t dec_i0_predict_p_d;
+     703           12 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705          554 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
-     706          122 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
+     705           10 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     706           20 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707            0 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
      709              :    // PIC ports
      710            0 :    logic                  picm_wren;
      711            0 :    logic                  picm_rden;
      712            0 :    logic                  picm_mken;
-     713          121 :    logic [31:0]           picm_rdaddr;
-     714          121 :    logic [31:0]           picm_wraddr;
-     715            6 :    logic [31:0]           picm_wr_data;
-     716            0 :    logic [31:0]           picm_rd_data;
+     713          240 :    logic [31:0]           picm_rdaddr;
+     714          240 :    logic [31:0]           picm_wraddr;
+     715            0 :    logic [31:0]           picm_wr_data;
+     716            0 :    logic [31:0]           picm_rd_data;
      717              : 
      718              :    // feature disable from mfdc
      719            0 :    logic  dec_tlu_external_ldfwd_disable; // disable external load forwarding
@@ -843,18 +843,18 @@
      739              :   // PMP Signals
      740            0 :   el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
      741              :   logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
-     742          140 :   logic [31:0]            pmp_chan_addr [3];
+     742          240 :   logic [31:0]            pmp_chan_addr [3];
      743            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
-     744          190 :   logic                   pmp_chan_err  [3];
+     744            0 :   logic                   pmp_chan_err  [3];
      745              : 
-     746            2 :   logic [31:1] ifu_pmp_addr;
+     746            2 :   logic [31:1] ifu_pmp_addr;
      747            0 :   logic        ifu_pmp_error;
-     748          140 :   logic [31:0] lsu_pmp_addr_start;
-     749          190 :   logic        lsu_pmp_error_start;
-     750          140 :   logic [31:0] lsu_pmp_addr_end;
-     751          190 :   logic        lsu_pmp_error_end;
-     752          760 :   logic        lsu_pmp_we;
-     753          660 :   logic        lsu_pmp_re;
+     748          240 :   logic [31:0] lsu_pmp_addr_start;
+     749            0 :   logic        lsu_pmp_error_start;
+     750          240 :   logic [31:0] lsu_pmp_addr_end;
+     751            0 :   logic        lsu_pmp_error_end;
+     752          232 :   logic        lsu_pmp_we;
+     753          228 :   logic        lsu_pmp_re;
      754              : 
      755              :    // -----------------------DEBUG  START -------------------------------
      756              : 
@@ -870,7 +870,7 @@
      766              : 
      767            0 :    logic                   core_dbg_cmd_done;         // Final muxed cmd done to debug
      768            0 :    logic                   core_dbg_cmd_fail;         // Final muxed cmd done to debug
-     769           18 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
+     769           16 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
      770              : 
      771            0 :    logic                   dma_dbg_cmd_done;          // Abstarct memory command sent to dma is done
      772            0 :    logic                   dma_dbg_cmd_fail;          // Abstarct memory command sent to dma failed
@@ -879,7 +879,7 @@
      775            0 :    logic                   dbg_dma_bubble;            // Debug needs a bubble to send a valid
      776            0 :    logic                   dma_dbg_ready;             // DMA is ready to accept debug request
      777              : 
-     778           18 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
+     778           16 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
      779            0 :    logic                   dec_dbg_cmd_done;          // This will be treated like a valid signal
      780            0 :    logic                   dec_dbg_cmd_fail;          // Abstract command failed
      781            0 :    logic                   dec_tlu_mpc_halted_only;   // Only halted due to MPC
@@ -889,43 +889,43 @@
      785            0 :    logic                   dec_debug_wdata_rs1_d;
      786            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
      787              : 
-     788         4304 :    logic [1:0]             dec_data_en;
-     789         4304 :    logic [1:0]             dec_ctl_en;
+     788          976 :    logic [1:0]             dec_data_en;
+     789          976 :    logic [1:0]             dec_ctl_en;
      790              : 
      791              :    // PMU Signals
-     792          314 :    logic                   exu_pmu_i0_br_misp;
-     793          706 :    logic                   exu_pmu_i0_br_ataken;
-     794          930 :    logic                   exu_pmu_i0_pc4;
+     792           64 :    logic                   exu_pmu_i0_br_misp;
+     793          232 :    logic                   exu_pmu_i0_br_ataken;
+     794          242 :    logic                   exu_pmu_i0_pc4;
      795              : 
-     796          660 :    logic                   lsu_pmu_load_external_m;
-     797          760 :    logic                   lsu_pmu_store_external_m;
+     796          228 :    logic                   lsu_pmu_load_external_m;
+     797          232 :    logic                   lsu_pmu_store_external_m;
      798            0 :    logic                   lsu_pmu_misaligned_m;
-     799         1548 :    logic                   lsu_pmu_bus_trxn;
+     799          468 :    logic                   lsu_pmu_bus_trxn;
      800            0 :    logic                   lsu_pmu_bus_misaligned;
      801            0 :    logic                   lsu_pmu_bus_error;
      802            0 :    logic                   lsu_pmu_bus_busy;
      803              : 
-     804          272 :    logic                   ifu_pmu_fetch_stall;
-     805         4336 :    logic                   ifu_pmu_ic_miss;
+     804           58 :    logic                   ifu_pmu_fetch_stall;
+     805          988 :    logic                   ifu_pmu_ic_miss;
      806            0 :    logic                   ifu_pmu_ic_hit;
      807            0 :    logic                   ifu_pmu_bus_error;
      808            0 :    logic                   ifu_pmu_bus_busy;
-     809         4336 :    logic                   ifu_pmu_bus_trxn;
+     809          988 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812        66208 :    logic                   free_clk;
-     813        66208 :    logic                   active_clk;
+     812        14760 :    logic                   free_clk;
+     813        14760 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
      817              : 
-     818          704 :    logic [15:0]            ifu_i0_cinst;
+     818          232 :    logic [15:0]            ifu_i0_cinst;
      819              : 
      820              : // fast interrupt
      821            0 :    logic [31:2]            dec_tlu_meihap;
      822            0 :    logic                   dec_extint_stall;
      823              : 
-     824         4304 :    el2_trace_pkt_t  trace_rv_trace_pkt;
+     824          976 :    el2_trace_pkt_t  trace_rv_trace_pkt;
      825              : 
      826              : 
      827            0 :    logic                   lsu_fastint_stall_any;
@@ -941,7 +941,7 @@
      837            0 :    logic        pause_state;
      838            0 :    logic        halt_state;
      839              : 
-     840         1280 :    logic        dec_tlu_core_empty;
+     840          268 :    logic        dec_tlu_core_empty;
      841              : 
      842              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
      843              : 
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890            0 :    logic priv_mode;
+     890              :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892            2 :    logic priv_mode_eff;
+     892              :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894            0 :    logic priv_mode_ns;
+     894              :    logic priv_mode_ns;
      895              : 
-     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer_wrapper.sv.html
index 674305f1fdf..b3d000fa237 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30        66208 :    input logic                             clk,
+      30        14760 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
@@ -140,9 +140,9 @@
       36            0 :    input logic [31:1]                      jtag_id,
       37              : 
       38              : 
-      39          471 :    output logic [31:0]                     trace_rv_i_insn_ip,
+      39            8 :    output logic [31:0]                     trace_rv_i_insn_ip,
       40            2 :    output logic [31:0]                     trace_rv_i_address_ip,
-      41         4304 :    output logic                            trace_rv_i_valid_ip,
+      41          976 :    output logic                            trace_rv_i_valid_ip,
       42            0 :    output logic                            trace_rv_i_exception_ip,
       43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
       44            0 :    output logic                            trace_rv_i_interrupt_ip,
@@ -339,24 +339,24 @@
      235            0 :    output logic                            hmastlock,
      236            0 :    output logic [3:0]                      hprot,
      237            0 :    output logic [2:0]                      hsize,
-     238         4336 :    output logic [1:0]                      htrans,
+     238          988 :    output logic [1:0]                      htrans,
      239            0 :    output logic                            hwrite,
      240              : 
-     241          576 :    input logic [63:0]                      hrdata,
+     241           16 :    input logic [63:0]                      hrdata,
      242            2 :    input logic                             hready,
      243            0 :    input logic                             hresp,
      244              : 
      245              :    // LSU AHB Master
-     246          111 :    output logic [31:0]                     lsu_haddr,
+     246          220 :    output logic [31:0]                     lsu_haddr,
      247            0 :    output logic [2:0]                      lsu_hburst,
      248            0 :    output logic                            lsu_hmastlock,
      249            0 :    output logic [3:0]                      lsu_hprot,
      250            0 :    output logic [2:0]                      lsu_hsize,
-     251         1548 :    output logic [1:0]                      lsu_htrans,
-     252          426 :    output logic                            lsu_hwrite,
-     253           25 :    output logic [63:0]                     lsu_hwdata,
+     251          468 :    output logic [1:0]                      lsu_htrans,
+     252          222 :    output logic                            lsu_hwrite,
+     253           48 :    output logic [63:0]                     lsu_hwdata,
      254              : 
-     255           34 :    input logic [63:0]                      lsu_hrdata,
+     255            8 :    input logic [63:0]                      lsu_hrdata,
      256            2 :    input logic                             lsu_hready,
      257            0 :    input logic                             lsu_hresp,
      258              :    // Debug Syster Bus AHB
@@ -454,16 +454,16 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353        66208 :    logic                             active_l2clk;
-     354        66208 :    logic                             free_l2clk;
+     353        14760 :    logic                             active_l2clk;
+     354        14760 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
      358            0 :    logic         dccm_rden;
      359            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo;
      360            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi;
-     361          140 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
-     362          140 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
+     361          240 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
+     362          240 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
      363            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
      364            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi;
      365              : 
@@ -490,19 +490,19 @@
      386            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way;   // Debug way. Rd or Wr.
      387              : 
      388            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
-     389          150 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
-     390          962 :    logic [63:0]  ic_rd_data;
+     389           16 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
+     390           44 :    logic [63:0]  ic_rd_data;
      391            0 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      392            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
      393              : 
      394            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
      395            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
      396              : 
-     397          962 :    logic [63:0]  ic_premux_data;
-     398         3842 :    logic         ic_sel_premux_data;
+     397           44 :    logic [63:0]  ic_premux_data;
+     398          970 :    logic         ic_sel_premux_data;
      399              : 
      400              :    // ICCM ports
-     401           26 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
+     401            4 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
      402            0 :    logic           iccm_wren;
      403            0 :    logic           iccm_rden;
      404            0 :    logic [2:0]     iccm_wr_size;
@@ -610,10 +610,10 @@
      506              : 
      507              : 
      508              : `ifdef RV_BUILD_AHB_LITE
-     509          888 :    wire                            lsu_axi_awvalid;
+     509          240 :    wire                            lsu_axi_awvalid;
      510            0 :    wire                            lsu_axi_awready;
      511            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid;
-     512          111 :    wire [31:0]                     lsu_axi_awaddr;
+     512          220 :    wire [31:0]                     lsu_axi_awaddr;
      513            2 :    wire [3:0]                      lsu_axi_awregion;
      514            0 :    wire [7:0]                      lsu_axi_awlen;
      515            0 :    wire [2:0]                      lsu_axi_awsize;
@@ -624,10 +624,10 @@
      520            0 :    wire [3:0]                      lsu_axi_awqos;
      521              : 
      522              : 
-     523          888 :    wire                            lsu_axi_wvalid;
+     523          240 :    wire                            lsu_axi_wvalid;
      524            0 :    wire                            lsu_axi_wready;
      525            0 :    wire [63:0]                     lsu_axi_wdata;
-     526          148 :    wire [7:0]                      lsu_axi_wstrb;
+     526            8 :    wire [7:0]                      lsu_axi_wstrb;
      527            2 :    wire                            lsu_axi_wlast;
      528              : 
      529            0 :    wire                            lsu_axi_bvalid;
@@ -636,10 +636,10 @@
      532            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid;
      533              : 
      534              :    // AXI Read Channels
-     535          660 :    wire                            lsu_axi_arvalid;
+     535          228 :    wire                            lsu_axi_arvalid;
      536            0 :    wire                            lsu_axi_arready;
      537            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid;
-     538          111 :    wire [31:0]                     lsu_axi_araddr;
+     538          220 :    wire [31:0]                     lsu_axi_araddr;
      539            2 :    wire [3:0]                      lsu_axi_arregion;
      540            0 :    wire [7:0]                      lsu_axi_arlen;
      541            0 :    wire [2:0]                      lsu_axi_arsize;
@@ -694,10 +694,10 @@
      590            0 :    wire [pt.IFU_BUS_TAG-1:0]      ifu_axi_bid;
      591              : 
      592              :    // AXI Read Channels
-     593         4336 :    wire                            ifu_axi_arvalid;
+     593          988 :    wire                            ifu_axi_arvalid;
      594            0 :    wire                            ifu_axi_arready;
-     595         2620 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
-     596         1684 :    wire [31:0]                     ifu_axi_araddr;
+     595          512 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
+     596           20 :    wire [31:0]                     ifu_axi_araddr;
      597            2 :    wire [3:0]                      ifu_axi_arregion;
      598            0 :    wire [7:0]                      ifu_axi_arlen;
      599            0 :    wire [2:0]                      ifu_axi_arsize;
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_mem_lib.sv.html
index d0f19096fc0..09f1f6321e6 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111       456768 : `EL2_RAM(4096, 39)
+     111       258112 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175       114192 : `EL2_RAM_BE(512, 142)
+     175        64528 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208        57096 : `EL2_RAM_BE(128, 52)
+     208        32264 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_rvjtag_tap.v.html
index b3ac8a66d19..aefdd920efe 100644
--- a/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_csr_mstatus/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index.html b/html/main/coverage_dashboard/all_ahb_dhry/index.html
index cf41f91f0ff..6324d1ee60c 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        42.3%
+    
+        42.5%
     
     
-        2269
+        2259
     
     
-        5364
+        5317
     
 
       
@@ -80,13 +80,13 @@
         Branch
     
     
-        61.1%
+        61.0%
     
     
-        653
+        652
     
     
-        1069
+        1068
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
             
                 
-                    27.7%
+                    27.8%
                 
             
 
             
-                353
+                352
                 /
-                1275
+                1265
             
         
             
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.1%
+                    51.4%
                 
             
 
             
-                37
+                36
                 /
-                71
+                70
             
         
     
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.3%
+                    40.5%
                 
             
 
             
-                406
+                400
                 /
-                1007
+                987
             
         
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    60.3%
+                    59.7%
                 
             
 
             
-                208
+                206
                 /
                 345
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.9%
+                    8.3%
                 
             
 
             
-                8
+                7
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design.html
index 9739521d05b..a3c4e3df004 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -59,13 +59,13 @@
         Toggle
     
     
-        27.7%
+        27.8%
     
     
-        353
+        352
     
     
-        1275
+        1265
     
 
       
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        52.1%
+    
+        51.4%
     
     
-        37
+        36
     
     
-        71
+        70
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    35.0%
+                    50.0%
                 
             
 
             
                 7
                 /
-                20
+                14
             
         
             
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.4%
+                    39.2%
                 
             
 
             
-                21
+                20
                 /
-                52
+                51
             
         
     
@@ -411,7 +411,7 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
@@ -423,9 +423,9 @@
             
 
             
-                210
+                209
                 /
-                631
+                627
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dbg.html
index b8744a672f4..4bd0b7bc6c5 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dec.html
index 97ef4daa6b5..618922bd7f9 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        40.3%
+    
+        40.5%
     
     
-        406
+        400
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    42.0%
+                    42.3%
                 
             
 
             
-                108
+                107
                 /
-                257
+                253
             
         
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    61.8%
+                    61.5%
                 
             
 
             
-                170
+                169
                 /
                 275
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.2%
+                    21.9%
                 
             
 
             
                 7
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
             
                 
-                    24.3%
+                    24.2%
                 
             
 
             
-                91
+                87
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dmi.html
index 7a3107af9cd..f3ce9302eab 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_exu.html
index 7339d155105..ec9acd1124e 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_exu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        60.3%
+    
+        59.7%
     
     
-        208
+        206
     
     
         345
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    82.0%
+                    81.0%
                 
             
 
             
-                82
+                81
                 /
                 100
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    51.1%
+                    50.0%
                 
             
 
             
-                45
+                44
                 /
                 88
             
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_ifu.html
index 5d16e1dff0c..0b0bdeedded 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_include.html
index b2698b24409..13973880b0d 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        7.9%
+    
+        8.3%
     
     
-        8
+        7
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.9%
+                    8.3%
                 
             
 
             
-                8
+                7
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lib.html
index 6103ee83811..bdcd4243d7a 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lsu.html
index 5084803b3be..f0fe9ffa129 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_ahb_to_axi4.sv.html
index ae29531051b..946ff6f2f99 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_axi4_to_ahb.sv.html
index d88b2fab241..4c6caa31bf1 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_beh_lib.sv.html
index 9717c836b1e..2b377c3c505 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_jtag_to_core_sync.v.html
index 4aa85ed7423..7728db05e2f 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_mux.v.html
index 42bc1aec44e..2c4f641a34d 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_wrapper.v.html
index d7e99d2e215..332ddf6717a 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dbg.sv.html
index c641d04b3d9..a4a3205ce7f 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec.sv.html
index d5bc9352e3d..a7ad635eac4 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        42.0%
+    
+        42.3%
     
     
-        108
+        107
     
     
-        257
+        253
     
 
             
@@ -354,9 +354,9 @@
      250         4328 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252           16 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253          696 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253            0 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
-     255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+     255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256            4 :     output logic dec_tlu_flush_lower_wb,
      257            0 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
      258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295            0 :     output logic priv_mode,
-     296            0 :     output logic priv_mode_eff,
-     297            0 :     output logic priv_mode_ns,
+     295              :     output logic priv_mode,
+     296              :     output logic priv_mode_eff,
+     297              :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300            0 :     output el2_mseccfg_pkt_t mseccfg,
+     300              :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_csr_equ_m.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_csr_equ_m.svh.html
rename to html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_csr_equ_m.svh.html
index c08523425fc..0a5ad0139c5 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    axi_dhry
+                    ahb_dhry
                 
                 
                 
@@ -107,12 +107,12 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           11 : logic csr_mstatus;
-       7            2 : logic csr_mtvec;
+       6           26 : logic csr_mstatus;
+       7            4 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
-      10            4 : logic csr_mcyclel;
-      11            8 : logic csr_mcycleh;
+      10            8 : logic csr_mcyclel;
+      11           16 : logic csr_mcycleh;
       12            0 : logic csr_minstretl;
       13            0 : logic csr_minstreth;
       14            0 : logic csr_mscratch;
@@ -120,7 +120,7 @@
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            2 : logic csr_mrac;
+      19            4 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -184,7 +184,7 @@
       80            0 : logic csr_pmpaddr48;
       81            0 : logic valid_only;
       82            0 : logic presync;
-      83            7 : logic postsync;
+      83           18 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370           10 : logic legal;
+     370           24 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_decode_ctl.sv.html
index e40839046e3..ddec64f91f7 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_decode_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        61.8%
+    
+        61.5%
     
     
-        170
+        169
     
     
         275
@@ -192,8 +192,8 @@
       88              : 
       89       291478 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91          696 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92           24 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92           24 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_gpr_ctl.sv.html
index 4b64a680b57..42dc33613d4 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_ib_ctl.sv.html
index 9fabb89e8ee..d5ed2b7d19f 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_pmp_ctl.sv.html
index 527ea967a23..b1e39ec961f 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.2%
+    
+        21.9%
     
     
         7
     
     
-        33
+        32
     
 
             
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52            0 :    input el2_mseccfg_pkt_t mseccfg,
+      52              :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_tlu_ctl.sv.html
index bfcda81161a..3d81c6101e8 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -59,13 +59,13 @@
         Toggle
     
     
-        24.3%
+        24.2%
     
     
-        91
+        87
     
     
-        375
+        360
     
 
             
@@ -284,8 +284,8 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183          696 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184           24 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183            0 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184           24 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186       152534 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243            0 :    output logic  priv_mode,
-     244            0 :    output logic  priv_mode_eff,
-     245            0 :    output logic  priv_mode_ns,
+     243              :    output logic  priv_mode,
+     244              :    output logic  priv_mode_eff,
+     245              :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248            0 :    output logic [2:0] mseccfg,
+     248              :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275            0 :    logic wr_mcounteren_r;
-     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277            0 :    logic wr_mseccfg_r;
-     278            2 :    logic [2:0] mseccfg_ns;
+     275              :    logic wr_mcounteren_r;
+     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277              :    logic wr_mseccfg_r;
+     278              :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,7 +389,7 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286            0 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
      290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483            0 :    logic  csr_acc_r;    // CSR access error
-     484            5 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485       101241 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483              :    logic  csr_acc_r;    // CSR access error
+     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994            0 :    logic csr_wr_acc_r;
-     995            0 :    logic csr_rd_acc_r;
+     994              :    logic csr_wr_acc_r;
+     995              :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568            0 :    logic  pmp_any_region_locked;
+    1568              :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_trigger.sv.html
index b975e1a6ac4..1509ae49c88 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dma_ctrl.sv.html
index 6a56193e355..4f4c8936ecb 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu.sv.html
index cbe5568af88..f605bbde393 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        82.0%
+    
+        81.0%
     
     
-        82
+        81
     
     
         100
@@ -156,9 +156,9 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54           16 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55          696 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55            0 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57       259918 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57       259918 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
       59          252 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_alu_ctl.sv.html
index 996cede6f9d..0f5cebb7ea1 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_alu_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        51.1%
+    
+        50.0%
     
     
-        45
+        44
     
     
         88
@@ -134,8 +134,8 @@
       30       268340 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32           16 :    input  logic                  csr_ren_in,         // CSR select
-      33          696 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34           24 :    input  logic signed [31:0]    a_in,               // A operand
+      33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34           24 :    input  logic signed [31:0]    a_in,               // A operand
       35        34372 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
       37        38176 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_div_ctl.sv.html
index bfb089b4bca..f06d7f801f5 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_mul_ctl.sv.html
index 3a3994aa24e..4a4cf1de822 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu.sv.html
index 029d79aebb8..aa60adb583d 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_aln_ctl.sv.html
index 8d5cacf01c0..2f97237b443 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_bp_ctl.sv.html
index b5dca9fbfa6..ab6651764eb 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_compress_ctl.sv.html
index f3aaddf5d9a..ce850d460a5 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ic_mem.sv.html
index 45000dd5d44..5db102d02af 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_iccm_mem.sv.html
index 3eccf9e2aa3..fd9bbeaf5d0 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ifc_ctl.sv.html
index 78ead347e21..e13781ef4a4 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_mem_ctl.sv.html
index 2f5cf07fca6..bd38f20962b 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lib.sv.html
index a959a94f47c..5b5660f62de 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu.sv.html
index 0a7cd191531..452a8a0bf02 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_addrcheck.sv.html
index 6f128c58d3d..99d43995ad6 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_buffer.sv.html
index c7fd254f73b..b4fec274636 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_intf.sv.html
index fbfa7a7f863..846e8b2c990 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_clkdomain.sv.html
index ce953ec1aad..6baa41a2301 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_ctl.sv.html
index e00dda69841..46d08c88e15 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_mem.sv.html
index 94dbfcd9b99..058a169c651 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_ecc.sv.html
index b51bbeb12ee..e4926b4c938 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_lsc_ctl.sv.html
index 883c7327f62..3ddd750499e 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_stbuf.sv.html
index ce799cae20e..0b50d601566 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_trigger.sv.html
index 327515a9602..ea883f00765 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem.sv.html
index 45c50f727fa..89ec3113688 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem_if.sv.html
index 144a9603615..7f0d8c81341 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pic_ctrl.sv.html
index 90aec3cef2d..3602c4d3f5f 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pmp.sv.html
index 0141ad4b799..1aedbe1290c 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        35.0%
+    
+        50.0%
     
     
         7
     
     
-        20
+        14
     
 
             
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        40.4%
+    
+        39.2%
     
     
-        21
+        20
     
     
-        52
+        51
     
 
             
@@ -132,12 +132,12 @@
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35            0 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36            0 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36              :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
       39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60            0 :   logic any_region_enabled;
+      60              :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -177,7 +177,7 @@
       73              :   //                                             \--> pmp_chan_err
       74              : 
       75              :   // A wrapper function in which it is decided which form of permission check function gets called
-      76           96 :   function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,
+      76           96 :   function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,
       77              :                                               el2_pmp_cfg_pkt_t csr_pmp_cfg,
       78              :                                               el2_pmp_type_pkt_t req_type,
       79              :                                               logic priv_mode,
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            3 :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223            0 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -332,7 +332,7 @@
      228              :   end
      229              : `endif
      230              : 
-     231            0 :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
+     231            0 :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
      232              :     assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]};  // addr. widening: 32-bit -> 34-bit
      233            0 :     for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
      234              :       // Comparators are sized according to granularity
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer.sv.html
index f233cc032cd..50db68d26a3 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -62,10 +62,10 @@
         33.3%
     
     
-        210
+        209
     
     
-        631
+        627
     
 
             
@@ -712,9 +712,9 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610           16 :    logic        dec_csr_ren_d;
-     611          696 :    logic [31:0] dec_csr_rddata_d;
+     611            0 :    logic [31:0] dec_csr_rddata_d;
      612              : 
-     613            0 :    logic [31:0] exu_csr_rs1_x;
+     613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
      615        42906 :    logic        dec_tlu_i0_commit_cmt;
      616            4 :    logic        dec_tlu_flush_lower_r;
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890            0 :    logic priv_mode;
+     890              :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892            0 :    logic priv_mode_eff;
+     892              :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894            0 :    logic priv_mode_ns;
+     894              :    logic priv_mode_ns;
      895              : 
-     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer_wrapper.sv.html
index 8c6414929ab..2c776783bb0 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_dhry/index_mem_lib.sv.html
index 3e03ee31967..4f469cd8d93 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_dhry/index_rvjtag_tap.v.html
index ff3398b00d9..a1a8dfc0b8d 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_dhry/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index.html b/html/main/coverage_dashboard/all_ahb_ecc/index.html
index 41f9487c56a..b4ea0a76aef 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design.html
index 6b68f8b7357..38894ebc4c6 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dbg.html
index e07a1e0eeab..f5a66a491d2 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dec.html
index 3809db1c675..c5ba8c2c990 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dmi.html
index 698160f68b0..c92450c83ee 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_exu.html
index 2e4c1f483e2..3db75751ef0 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_ifu.html
index 7a99a8544f3..7be2ab5e7fc 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_include.html
index 90bf5c7055e..c0977ee829e 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lib.html
index f090871731e..7bc37c56fdd 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lsu.html
index 97382cd7bef..7fe1cb7d740 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_ahb_to_axi4.sv.html
index 225aa7a5ff8..b431bab7f8c 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_axi4_to_ahb.sv.html
index 40d62bca842..fa1122f74d8 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_beh_lib.sv.html
index eb354433832..bf553281d63 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_jtag_to_core_sync.v.html
index f9448420daf..9447f923e87 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_mux.v.html
index 080f99c2747..35a1e0bc25d 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_wrapper.v.html
index fab1a4b08bf..0a4301c7160 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dbg.sv.html
index bc69484c79d..719bf5d09fd 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec.sv.html
index 0bbab663923..fe4d68bc361 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -354,9 +354,9 @@
      250         1256 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252           44 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253            0 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253            2 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
-     255           16 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+     255           16 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256           16 :     output logic dec_tlu_flush_lower_wb,
      257            4 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
      258            4 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295              :     output logic priv_mode,
-     296              :     output logic priv_mode_eff,
-     297              :     output logic priv_mode_ns,
+     295            0 :     output logic priv_mode,
+     296            0 :     output logic priv_mode_eff,
+     297            0 :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300              :     output el2_mseccfg_pkt_t mseccfg,
+     300            0 :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_csr_equ_m.svh.html
index a288530fc99..96b7336abbc 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -107,8 +107,8 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           64 : logic csr_mstatus;
-       7            8 : logic csr_mtvec;
+       6           32 : logic csr_mstatus;
+       7            4 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
       10            0 : logic csr_mcyclel;
@@ -117,10 +117,10 @@
       13            0 : logic csr_minstreth;
       14            0 : logic csr_mscratch;
       15            0 : logic csr_mepc;
-      16           16 : logic csr_mcause;
-      17           16 : logic csr_mscause;
+      16            8 : logic csr_mcause;
+      17            8 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19           10 : logic csr_mrac;
+      19            5 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -130,7 +130,7 @@
       26            0 : logic csr_meicidpl;
       27            0 : logic csr_dcsr;
       28            0 : logic csr_mcgc;
-      29           36 : logic csr_mfdc;
+      29           18 : logic csr_mfdc;
       30            0 : logic csr_dpc;
       31            0 : logic csr_mtsel;
       32            0 : logic csr_mtdata1;
@@ -168,8 +168,8 @@
       64            0 : logic csr_meicpct;
       65            0 : logic csr_mdeau;
       66            0 : logic csr_micect;
-      67            4 : logic csr_miccmect;
-      68            8 : logic csr_mdccmect;
+      67            2 : logic csr_miccmect;
+      68            4 : logic csr_mdccmect;
       69            0 : logic csr_mfdht;
       70            0 : logic csr_mfdhs;
       71            0 : logic csr_dicawics;
@@ -183,8 +183,8 @@
       79            0 : logic csr_pmpaddr32;
       80            0 : logic csr_pmpaddr48;
       81            0 : logic valid_only;
-      82           36 : logic presync;
-      83           22 : logic postsync;
+      82           18 : logic presync;
+      83           11 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370           62 : logic legal;
+     370           31 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_decode_ctl.sv.html
index d5ae49ee277..5b674b2756a 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,8 +192,8 @@
       88              : 
       89         8846 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92           62 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91            2 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92           62 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_gpr_ctl.sv.html
index d79a9046296..69c022c93c5 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_ib_ctl.sv.html
index 050e7208a81..4ae44c99fcf 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_pmp_ctl.sv.html
index 7f606170f0e..db9ea8edeb1 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52              :    input el2_mseccfg_pkt_t mseccfg,
+      52            0 :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_tlu_ctl.sv.html
index 46cf91ba738..8db5010003c 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -284,8 +284,8 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183            0 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184           62 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183            2 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184           62 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186         3268 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243              :    output logic  priv_mode,
-     244              :    output logic  priv_mode_eff,
-     245              :    output logic  priv_mode_ns,
+     243            0 :    output logic  priv_mode,
+     244            0 :    output logic  priv_mode_eff,
+     245            0 :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248              :    output logic [2:0] mseccfg,
+     248            0 :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275              :    logic wr_mcounteren_r;
-     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277              :    logic wr_mseccfg_r;
-     278              :    logic [2:0] mseccfg_ns;
+     275            0 :    logic wr_mcounteren_r;
+     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277            0 :    logic wr_mseccfg_r;
+     278            4 :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,9 +389,9 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286            4 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290            0 :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483              :    logic  csr_acc_r;    // CSR access error
-     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483            0 :    logic  csr_acc_r;    // CSR access error
+     484           21 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485         4608 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994              :    logic csr_wr_acc_r;
-     995              :    logic csr_rd_acc_r;
+     994            0 :    logic csr_wr_acc_r;
+     995            0 :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568              :    logic  pmp_any_region_locked;
+    1568            0 :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_trigger.sv.html
index 44236169d54..23bc0355fdd 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dma_ctrl.sv.html
index 96e45d2253d..3a5ac6f71a7 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu.sv.html
index 5ad46e066ec..955a28696a1 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,9 +156,9 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54           44 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55            0 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55            2 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57         9616 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57         9616 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
       59            8 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_alu_ctl.sv.html
index 9aa693b9e47..93048c78016 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,8 +134,8 @@
       30         9678 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32           44 :    input  logic                  csr_ren_in,         // CSR select
-      33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34          398 :    input  logic signed [31:0]    a_in,               // A operand
+      33            2 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34          398 :    input  logic signed [31:0]    a_in,               // A operand
       35         2280 :    input  logic        [31:0]    b_in,               // B operand
       36            8 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
       37            8 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_div_ctl.sv.html
index ed5797ebe18..deddbcecb63 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_mul_ctl.sv.html
index 508e111a3a9..b1f617f9174 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu.sv.html
index 7fe7cb5d730..afe5e62259e 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_aln_ctl.sv.html
index fc2a97a77fa..978596ae214 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_bp_ctl.sv.html
index 8668dcd1122..cf4f7afade6 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_compress_ctl.sv.html
index 76e2ff2cda5..1d26f1da899 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ic_mem.sv.html
index a85d2ca2a11..b1f9a765564 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_iccm_mem.sv.html
index 5bac7ba3651..68465926e9b 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ifc_ctl.sv.html
index a36fe32fcb4..b7d28dc0b22 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_mem_ctl.sv.html
index e190e87a11f..5f50e5e0b96 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lib.sv.html
index 38f809f4b8d..8d0420c801f 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu.sv.html
index fefed0bb6a8..a7a5a646363 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_addrcheck.sv.html
index e09a6a47739..ffe6a3918f0 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_buffer.sv.html
index 65be090ab3e..3c08e31db8d 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_intf.sv.html
index e40949c54c1..ef1209cf689 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_clkdomain.sv.html
index 6022719015b..df6fa0a4bef 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_ctl.sv.html
index 78f18c59ebd..9c998601df5 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_mem.sv.html
index 608860504b5..9450c08a75d 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_ecc.sv.html
index a0261a6aad5..9a3b115a836 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_lsc_ctl.sv.html
index 5ab0abcd001..c20874d548e 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_stbuf.sv.html
index 8214a359d1c..1e091dd6d74 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_trigger.sv.html
index cf6e5828843..2262443c53e 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem.sv.html
index 70d29bc3e33..2306b88fa36 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem_if.sv.html
index 94cc9286805..a1d5d124c7b 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pic_ctrl.sv.html
index 71efab7d088..f4942678475 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pmp.sv.html
index 4adc5d6f4a4..cb372e6df87 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,12 +132,12 @@
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36              :     input logic priv_mode_eff,  // operating effective privilege mode
+      35            0 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36            0 :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
       39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60              :   logic any_region_enabled;
+      60            0 :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -177,7 +177,7 @@
       73              :   //                                             \--> pmp_chan_err
       74              : 
       75              :   // A wrapper function in which it is decided which form of permission check function gets called
-      76           96 :   function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,
+      76           96 :   function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,
       77              :                                               el2_pmp_cfg_pkt_t csr_pmp_cfg,
       78              :                                               el2_pmp_type_pkt_t req_type,
       79              :                                               logic priv_mode,
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            6 :     logic access_fail = 1'b0;
+     161            3 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223            0 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -332,7 +332,7 @@
      228              :   end
      229              : `endif
      230              : 
-     231            0 :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
+     231            0 :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
      232              :     assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]};  // addr. widening: 32-bit -> 34-bit
      233            0 :     for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
      234              :       // Comparators are sized according to granularity
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer.sv.html
index 2dd3ffb08b0..77fd028ec8c 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -712,9 +712,9 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610           44 :    logic        dec_csr_ren_d;
-     611            0 :    logic [31:0] dec_csr_rddata_d;
+     611            2 :    logic [31:0] dec_csr_rddata_d;
      612              : 
-     613            0 :    logic [31:0] exu_csr_rs1_x;
+     613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
      615         1946 :    logic        dec_tlu_i0_commit_cmt;
      616           16 :    logic        dec_tlu_flush_lower_r;
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890              :    logic priv_mode;
+     890            0 :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892              :    logic priv_mode_eff;
+     892            0 :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894              :    logic priv_mode_ns;
+     894            0 :    logic priv_mode_ns;
      895              : 
-     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer_wrapper.sv.html
index 739c062129d..d7c1df9f31b 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_ecc/index_mem_lib.sv.html
index 4e35a51ae5d..e4741e11ae8 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_ecc/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_ecc/index_rvjtag_tap.v.html
index 26a7a2e6d08..51fe5d584e0 100644
--- a/html/main/coverage_dashboard/all_ahb_ecc/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_ecc/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index.html b/html/main/coverage_dashboard/all_ahb_hello_world/index.html
index 703ef4e1106..4df74908d8f 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -59,13 +59,13 @@
         Toggle
     
     
-        28.5%
+        28.6%
     
     
-        1531
+        1521
     
     
-        5364
+        5317
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
             
                 
-                    21.8%
+                    21.9%
                 
             
 
             
-                278
+                277
                 /
-                1275
+                1265
             
         
             
@@ -275,7 +275,7 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
@@ -287,9 +287,9 @@
             
 
             
-                324
+                318
                 /
-                1007
+                987
             
         
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    25.5%
+                    24.9%
                 
             
 
             
-                88
+                86
                 /
                 345
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    8.9%
+                    9.5%
                 
             
 
             
-                9
+                8
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design.html
index bff09b0e806..f9b3e92f335 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -59,13 +59,13 @@
         Toggle
     
     
-        21.8%
+        21.9%
     
     
-        278
+        277
     
     
-        1275
+        1265
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    25.0%
+                    35.7%
                 
             
 
             
                 5
                 /
-                20
+                14
             
         
             
@@ -411,7 +411,7 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
@@ -423,9 +423,9 @@
             
 
             
-                169
+                168
                 /
-                631
+                627
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dbg.html
index 390259fc845..e76153a2efa 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dec.html
index 096c9ae7642..cac9870e2da 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -62,10 +62,10 @@
         32.2%
     
     
-        324
+        318
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    33.1%
+                    33.2%
                 
             
 
             
-                85
+                84
                 /
-                257
+                253
             
         
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    46.9%
+                    46.5%
                 
             
 
             
-                129
+                128
                 /
                 275
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.2%
+                    21.9%
                 
             
 
             
                 7
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    22.7%
+                    22.5%
                 
             
 
             
-                85
+                81
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dmi.html
index 4e364f8ebb9..5bd81f218dc 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_exu.html
index a308e93ab14..a4e7c3e120a 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_exu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        25.5%
+    
+        24.9%
     
     
-        88
+        86
     
     
         345
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.0%
+                    49.0%
                 
             
 
             
-                50
+                49
                 /
                 100
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    27.3%
+                    26.1%
                 
             
 
             
-                24
+                23
                 /
                 88
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_ifu.html
index 2fbc3bb1283..8681ee69e66 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_include.html
index cab328cb602..dc41d673c2d 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        8.9%
+    
+        9.5%
     
     
-        9
+        8
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    8.9%
+                    9.5%
                 
             
 
             
-                9
+                8
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lib.html
index c2d8bf89423..6bae1ee34ae 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lsu.html
index 653acc13d9e..b3a65fe5385 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_ahb_to_axi4.sv.html
index 9974096bdbe..d33ad02331e 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_axi4_to_ahb.sv.html
index 69b273bc899..9743052fcf0 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_beh_lib.sv.html
index 7cf757862b0..cb41affab57 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_jtag_to_core_sync.v.html
index 37c5a5c6aba..9ba732dc184 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_mux.v.html
index d369d639afe..a2396238c73 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_wrapper.v.html
index 8e263a801a0..d94ff254c59 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dbg.sv.html
index e9d5fca482d..76527f0db3b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec.sv.html
index f08d71aa500..d61ba4c97ac 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        33.1%
+    
+        33.2%
     
     
-        85
+        84
     
     
-        257
+        253
     
 
             
@@ -354,7 +354,7 @@
      250            0 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            0 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253           16 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253           11 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255           20 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256           20 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_csr_equ_m.svh.html
similarity index 98%
rename from html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html
rename to html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_csr_equ_m.svh.html
index 053639f1a76..847c4ab2c8c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_csr_equ_m.svh.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        8.3%
+    
+        9.5%
     
     
-        7
+        8
     
     
         84
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    ahb_hello_world_iccm
+                    ahb_hello_world
                 
                 
                 
@@ -107,20 +107,20 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6            7 : logic csr_mstatus;
-       7            2 : logic csr_mtvec;
+       6           16 : logic csr_mstatus;
+       7            4 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
       10            0 : logic csr_mcyclel;
       11            0 : logic csr_mcycleh;
-      12            0 : logic csr_minstretl;
-      13            0 : logic csr_minstreth;
-      14            0 : logic csr_mscratch;
+      12            2 : logic csr_minstretl;
+      13            2 : logic csr_minstreth;
+      14            0 : logic csr_mscratch;
       15            0 : logic csr_mepc;
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            2 : logic csr_mrac;
+      19            4 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -183,8 +183,8 @@
       79            0 : logic csr_pmpaddr32;
       80            0 : logic csr_pmpaddr48;
       81            0 : logic valid_only;
-      82            2 : logic presync;
-      83            1 : logic postsync;
+      82            6 : logic presync;
+      83            6 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370            6 : logic legal;
+     370           14 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_decode_ctl.sv.html
index f7e26b845e9..7ad2e37de96 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_decode_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        46.9%
+    
+        46.5%
     
     
-        129
+        128
     
     
         275
@@ -192,7 +192,7 @@
       88              : 
       89         1002 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91           16 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91           11 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           44 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_gpr_ctl.sv.html
index 0786738796d..499685d37fc 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_ib_ctl.sv.html
index 6fc55fee425..984229432bb 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_pmp_ctl.sv.html
index 06129cd450d..1be67777045 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.2%
+    
+        21.9%
     
     
         7
     
     
-        33
+        32
     
 
             
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_tlu_ctl.sv.html
index f420f458cf9..21ee50a9577 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        22.7%
+    
+        22.5%
     
     
-        85
+        81
     
     
-        375
+        360
     
 
             
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183           16 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183           11 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           44 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186            0 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -379,7 +379,7 @@
      275            0 :    logic wr_mcounteren_r;
      276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277            0 :    logic wr_mseccfg_r;
-     278           12 :    logic [2:0] mseccfg_ns;
+     278           10 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484           43 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         6696 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484           34 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485         5034 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_trigger.sv.html
index 00187a76bb4..d733b7e30a4 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dma_ctrl.sv.html
index 772c23cde39..f2974408737 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu.sv.html
index aecad3693dc..56dbc9edc63 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.0%
+    
+        49.0%
     
     
-        50
+        49
     
     
         100
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53          368 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            0 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55           16 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55           11 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57         6820 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_alu_ctl.sv.html
index ce656bab741..70aacd8946a 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_alu_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        27.3%
+    
+        26.1%
     
     
-        24
+        23
     
     
         88
@@ -134,7 +134,7 @@
       30         6818 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            0 :    input  logic                  csr_ren_in,         // CSR select
-      33           16 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33           11 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34            0 :    input  logic signed [31:0]    a_in,               // A operand
       35           16 :    input  logic        [31:0]    b_in,               // B operand
       36            0 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_div_ctl.sv.html
index ad95cc616b3..caa8dae7d95 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_mul_ctl.sv.html
index 93d76122653..f50e277d8c7 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu.sv.html
index 9fea5abc07b..0afbf49902b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_aln_ctl.sv.html
index 556666485c2..bfe4f5ab0f0 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_bp_ctl.sv.html
index 5f59029fc83..7ab12f725c2 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_compress_ctl.sv.html
index 9a690686d19..50b2e4661f3 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ic_mem.sv.html
index 9ce6af3b240..750f851da50 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_iccm_mem.sv.html
index 6963e4a7ad1..23210f1ccb9 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ifc_ctl.sv.html
index 86a392e4ff3..429cf8de121 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_mem_ctl.sv.html
index edb1da47e02..e52960fae00 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lib.sv.html
index 9c8f67aa06e..8dee20da49d 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu.sv.html
index 92596da114f..0bd695651b1 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_addrcheck.sv.html
index adc877d523a..9658356dfea 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_buffer.sv.html
index 955803a573d..28f29ab683f 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_intf.sv.html
index cd7d33a6b17..55d4f0103cb 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_clkdomain.sv.html
index e1219823343..80627714d94 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_ctl.sv.html
index c79d8e8b1ef..588e32be79a 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_mem.sv.html
index baf07eb3dfd..c2ec48465e9 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_ecc.sv.html
index 25b58335050..f99084d268b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_lsc_ctl.sv.html
index 8ba2cb92b81..bf8fbf4ad70 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_stbuf.sv.html
index d55f4a14e0c..b7c83a732f2 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_trigger.sv.html
index 2dea8b42b0e..15fb3c8d200 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem.sv.html
index e2d8bf8d0e6..62da420bb5b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem_if.sv.html
index def50522577..79b34b9f4d0 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pic_ctrl.sv.html
index 9805c44d2ee..9b10d480116 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pmp.sv.html
index eb6ae4070c8..fa26f445b30 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        25.0%
+    
+        35.7%
     
     
         5
     
     
-        20
+        14
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154           18 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155           18 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            9 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            9 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            9 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164           18 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer.sv.html
index d5eddf926dc..be4fbed801b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -62,10 +62,10 @@
         26.8%
     
     
-        169
+        168
     
     
-        631
+        627
     
 
             
@@ -712,7 +712,7 @@
      608            4 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            0 :    logic        dec_csr_ren_d;
-     611           16 :    logic [31:0] dec_csr_rddata_d;
+     611           11 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer_wrapper.sv.html
index 6f9392d53f1..99208c57401 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_mem_lib.sv.html
index 32f13bb4d18..cedc8ed5f42 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_hello_world/index_rvjtag_tap.v.html
index 9cba46284b7..2908aeed9b5 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index.html
index 282bf99169f..26d767a79c8 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -80,13 +80,13 @@
         Branch
     
     
-        60.1%
+        60.0%
     
     
-        642
+        641
     
     
-        1069
+        1068
     
 
       
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.1%
+                    51.4%
                 
             
 
             
-                37
+                36
                 /
-                71
+                70
             
         
     
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design.html
index 423ec1871cd..00e8c54b316 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        52.1%
+    
+        51.4%
     
     
-        37
+        36
     
     
-        71
+        70
     
 
       
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.4%
+                    39.2%
                 
             
 
             
-                21
+                20
                 /
-                52
+                51
             
         
     
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html
index 656336d7f69..3ba80b238a9 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html
index e6bb2880f05..7900cff3d7c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html
index a00be60425a..52bead53c42 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html
index 61e2373a8f5..753debf6e65 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html
index 1b2d41f63be..d738115eaaf 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html
index 53466b4bca6..5953adc7c71 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html
index 633638f679b..ee7934428c8 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html
index 50afd7fdc13..65d7b3596a1 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_ahb_to_axi4.sv.html
index 339f72a3e7f..ec5be767040 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_axi4_to_ahb.sv.html
index 05c2b87e9be..84156867632 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_beh_lib.sv.html
index 262b3e07cef..b9ddff7b46e 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html
index 592e284c1a6..d91c6c6dc38 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_mux.v.html
index 36aa361e58e..42e6f949e16 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_wrapper.v.html
index 6467c08631b..b58c1ff04d3 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dbg.sv.html
index e4244d91afd..b4406d16fff 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec.sv.html
index 711d788957d..85b520ee355 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html
index d620427a93d..84e61b4f988 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_decode_ctl.sv.html
index 84d1fa325ac..a8b6310de0c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html
index 0ba087c7a0c..d50136bfc2f 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_ib_ctl.sv.html
index def353b7606..b10aa1ffe90 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html
index e18dd173377..415a5ce32fa 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html
index c5c22d033a5..eccae5ce7d5 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_trigger.sv.html
index 989153df2ab..92862ebd79c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dma_ctrl.sv.html
index 86a8b23cd58..4c9761f4e7b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu.sv.html
index 8b08583d57f..a83f99315a5 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_alu_ctl.sv.html
index 2a84979a3ff..aa6d6bd6505 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_div_ctl.sv.html
index 872bedb5c44..e7f6a78217b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_mul_ctl.sv.html
index a88af3e7016..19270daeada 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu.sv.html
index b2e8e43602c..d393596a357 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html
index af402a4b4aa..318b52d9cee 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html
index d088114f080..fa2530e6912 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html
index 39f7239c2e5..ee5de94464c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ic_mem.sv.html
index 5076a922fd9..542d1f90d07 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html
index f0dd79e928d..97218114112 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html
index 264a2f5939d..2747657f860 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html
index 2b4e0f6af14..c17bca6c372 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lib.sv.html
index 6ebf0f7d4cd..a475413dd6c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu.sv.html
index 4b002360810..f9a71ddf4b8 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_addrcheck.sv.html
index 1e9e88a332d..9781e622065 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html
index 99351146ed1..0ac4dac9733 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_intf.sv.html
index 068df801ac6..389162d3a5b 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_clkdomain.sv.html
index f23860598f2..564bd799e91 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html
index 334fb8b2bc6..4526508fa50 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html
index ee263d5d453..07c0dae889f 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_ecc.sv.html
index d42f57b6924..99c5ee61d71 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html
index 5a786bc032f..bb3efd15f6c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_stbuf.sv.html
index 4a7de5199aa..27dd4158d1c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_trigger.sv.html
index 100d4bbb5fd..8556424ef27 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem.sv.html
index cb8ec00c620..4d2827cddcc 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem_if.sv.html
index 0e70e85ac47..3ebc3f24b00 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pic_ctrl.sv.html
index b936f9f67cb..41561b960e3 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pmp.sv.html
index f35e3ce989f..f63d495e367 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        40.4%
+    
+        39.2%
     
     
-        21
+        20
     
     
-        52
+        51
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            3 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer.sv.html
index aef5de3a52a..606b3d01617 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer_wrapper.sv.html
index d114b52d3cc..b7eca8fc369 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_mem_lib.sv.html
index d0764968bff..62939adc8ff 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_rvjtag_tap.v.html
index dee9eec84f0..8b3e12b9782 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_dccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index.html
index d4a64c1e288..4408ccef572 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        32.1%
+    
+        31.9%
     
     
-        1705
+        1709
     
     
-        5317
+        5364
     
 
       
@@ -80,13 +80,13 @@
         Branch
     
     
-        61.3%
+        61.2%
     
     
-        655
+        654
     
     
-        1069
+        1068
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
             
                 
-                    23.3%
+                    23.1%
                 
             
 
             
                 295
                 /
-                1265
+                1275
             
         
             
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.1%
+                    51.4%
                 
             
 
             
-                37
+                36
                 /
-                71
+                70
             
         
     
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    35.5%
+                    35.1%
                 
             
 
             
-                350
+                353
                 /
-                987
+                1007
             
         
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    8.3%
+                    7.9%
                 
             
 
             
-                7
+                8
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design.html
index ab11d3f175e..1339a907972 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -59,13 +59,13 @@
         Toggle
     
     
-        23.3%
+        23.1%
     
     
         295
     
     
-        1265
+        1275
     
 
       
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        52.1%
+    
+        51.4%
     
     
-        37
+        36
     
     
-        71
+        70
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    35.7%
+                    25.0%
                 
             
 
             
                 5
                 /
-                14
+                20
             
         
             
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.4%
+                    39.2%
                 
             
 
             
-                21
+                20
                 /
-                52
+                51
             
         
     
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.5%
+                    28.4%
                 
             
 
             
                 179
                 /
-                627
+                631
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html
index 745d09c99e8..0f14243788c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html
index 8a98f389626..8e713cb32f9 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        35.5%
+    
+        35.1%
     
     
-        350
+        353
     
     
-        987
+        1007
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    36.4%
+                    35.8%
                 
             
 
             
                 92
                 /
-                253
+                257
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.1%
+                    27.3%
                 
             
 
             
                 9
                 /
-                32
+                33
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
             
                 
-                    23.9%
+                    23.7%
                 
             
 
             
-                86
+                89
                 /
-                360
+                375
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html
index 58e2f402fdf..94d6e0b45b5 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html
index f79f32418b1..8d8c12e010c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html
index d4955906fdf..c9f019d16cc 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html
index 7794bbb7b25..4c30dac13f1 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        8.3%
+    
+        7.9%
     
     
-        7
+        8
     
     
-        84
+        101
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_m.svh
+            
+                el2_dec_csr_equ_mu.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    8.3%
+                    7.9%
                 
             
 
             
-                7
+                8
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html
index e52843fd418..de8d01d33e2 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html
index e3948c1909a..b6118dd8e66 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_ahb_to_axi4.sv.html
index a94d028b79b..c4995258504 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_axi4_to_ahb.sv.html
index 140e732c0da..458c4dcb559 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_beh_lib.sv.html
index 3b4529255e4..7c447abfe3a 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html
index 9e6881c4d87..f7636610c04 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_mux.v.html
index 93b1579896d..d150bb843af 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_wrapper.v.html
index 26d9aedd6af..b3005ce0c33 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dbg.sv.html
index 5c414216e86..5362361c2de 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec.sv.html
index d1e7d2705b5..832527e4316 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        36.4%
+    
+        35.8%
     
     
         92
     
     
-        253
+        257
     
 
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_csr_equ_mu.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_csr_equ_mu.svh.html
rename to html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_csr_equ_mu.svh.html
index 4831aa04131..443aa8d8085 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_csr_equ_mu.svh.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        8.9%
+    
+        7.9%
     
     
-        9
+        8
     
     
         101
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    ahb_hello_world
+                    ahb_hello_world_iccm
                 
                 
                 
@@ -107,20 +107,20 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           43 : logic csr_mstatus;
-       7           10 : logic csr_mtvec;
+       6            7 : logic csr_mstatus;
+       7            2 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
       10            0 : logic csr_mcyclel;
       11            0 : logic csr_mcycleh;
-      12            8 : logic csr_minstretl;
-      13            8 : logic csr_minstreth;
-      14            0 : logic csr_mscratch;
+      12            0 : logic csr_minstretl;
+      13            0 : logic csr_minstreth;
+      14            0 : logic csr_mscratch;
       15            0 : logic csr_mepc;
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19           10 : logic csr_mrac;
+      19            2 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -185,7 +185,7 @@
       81            0 : logic csr_pmpaddr16;
       82            0 : logic csr_pmpaddr32;
       83            0 : logic csr_pmpaddr48;
-      84           43 : logic csr_cyclel;
+      84            7 : logic csr_cyclel;
       85            0 : logic csr_cycleh;
       86            0 : logic csr_instretl;
       87            0 : logic csr_instreth;
@@ -200,8 +200,8 @@
       96            0 : logic csr_mseccfgl;
       97            0 : logic csr_mseccfgh;
       98            0 : logic valid_only;
-      99           18 : logic presync;
-     100           21 : logic postsync;
+      99            2 : logic presync;
+     100            1 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444           38 : logic legal;
+     444            6 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_decode_ctl.sv.html
index 51e4f486841..3abd259b67d 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html
index 9fa751e0535..3e5649d2850 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_ib_ctl.sv.html
index a33ef38a217..9fad3817ca8 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html
index 5475ea7e1d9..a80e3162d6d 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.1%
+    
+        27.3%
     
     
         9
     
     
-        32
+        33
     
 
             
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html
index 442f1a2d935..c606fa2da44 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -59,13 +59,13 @@
         Toggle
     
     
-        23.9%
+        23.7%
     
     
-        86
+        89
     
     
-        360
+        375
     
 
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_trigger.sv.html
index 12c8b711dd8..475c1bc5a6e 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dma_ctrl.sv.html
index 1dfdb6ce8dd..a5144ec3611 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu.sv.html
index 60c6e86052d..54158aed469 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_alu_ctl.sv.html
index b0627d99490..e3624aebd17 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_div_ctl.sv.html
index 8b28abe55a4..2b885dbe488 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_mul_ctl.sv.html
index ee435342eda..32bcecf06b6 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu.sv.html
index ed804a2c915..33e447f3035 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html
index e8d0d8c3988..2c720089297 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html
index db1074df7f4..5b25d34bd98 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html
index 8ef87d66c47..8204381fda3 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ic_mem.sv.html
index 94e928d41ed..a3aba35ceca 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html
index 5a54078e3a0..eaed73b138a 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html
index 09043be032a..658ac386d6f 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html
index 27373c88c08..a10a2fcef61 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lib.sv.html
index e08cf534048..6f43c869dd0 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu.sv.html
index 301cc51c064..9e41da262db 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_addrcheck.sv.html
index ecce4a833a9..5edb446ec0c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html
index 4deafcf7e2c..0a0e2e27fc1 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_intf.sv.html
index 9f93bc3a4a7..01761e0ff1d 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_clkdomain.sv.html
index 5dd04e4d913..807b6bbe396 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html
index 5f33709d4cb..31ea576ac95 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html
index 4112c3177ca..4ca4c030b60 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_ecc.sv.html
index 9c65d5fd6b0..3d2800c9b4c 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html
index fd04d492003..e42ca1e8e05 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_stbuf.sv.html
index d78bcefe2ec..a6151fbcbb6 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_trigger.sv.html
index 865e6b9f4cb..0b5dae099d6 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem.sv.html
index 7e5a3e079a8..a447318923f 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem_if.sv.html
index 260b867feac..a71706d3ff6 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pic_ctrl.sv.html
index 47448ba328c..14bcd337234 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pmp.sv.html
index 3c51724e7fe..226858bab48 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        35.7%
+    
+        25.0%
     
     
         5
     
     
-        14
+        20
     
 
             
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        40.4%
+    
+        39.2%
     
     
-        21
+        20
     
     
-        52
+        51
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer.sv.html
index 74329aeb31c..fa4a52d8e22 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.5%
+    
+        28.4%
     
     
         179
     
     
-        627
+        631
     
 
             
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer_wrapper.sv.html
index ae938a00576..d9f38af65d0 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_mem_lib.sv.html
index f9b1b4edc11..3c43c3dadbf 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_rvjtag_tap.v.html
index b7467d729a5..1fb7058f574 100644
--- a/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_hello_world_iccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index.html b/html/main/coverage_dashboard/all_ahb_insns/index.html
index 352a0f4a481..cd22a5e64bf 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        39.3%
+    
+        32.7%
     
     
-        2108
+        1740
     
     
-        5364
+        5317
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.2%
+                    23.9%
                 
             
 
             
-                360
+                302
                 /
-                1275
+                1265
             
         
             
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.4%
+                    38.9%
                 
             
 
             
-                457
+                384
                 /
-                1007
+                987
             
         
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    41.7%
+                    38.0%
                 
             
 
             
-                144
+                131
                 /
                 345
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.3%
+                    47.5%
                 
             
 
             
-                530
+                482
                 /
                 1014
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    9.9%
+                    8.3%
                 
             
 
             
-                10
+                7
                 /
-                101
+                84
             
         
             
@@ -615,19 +615,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    31.4%
+                    29.1%
                 
             
 
             
-                109
+                101
                 /
                 347
             
@@ -683,19 +683,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.9%
+                    29.8%
                 
             
 
             
-                471
+                306
                 /
                 1027
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design.html
index 4fd74b299a2..991bc7e6400 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        28.2%
+    
+        23.9%
     
     
-        360
+        302
     
     
-        1275
+        1265
     
 
       
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    22.9%
+                    18.8%
                 
             
 
             
-                11
+                9
                 /
                 48
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    24.1%
+                    17.6%
                 
             
 
             
-                26
+                19
                 /
                 108
             
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    60.0%
+                    35.7%
                 
             
 
             
-                12
+                5
                 /
-                20
+                14
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    35.3%
+                    30.1%
                 
             
 
             
-                223
+                189
                 /
-                631
+                627
             
         
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    22.9%
+                    20.3%
                 
             
 
             
-                70
+                62
                 /
                 306
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dbg.html
index 94e77b88847..cb22afb5059 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dec.html
index f23489c267e..6daf2408d1d 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        45.4%
+    
+        38.9%
     
     
-        457
+        384
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    47.1%
+                    39.9%
                 
             
 
             
-                121
+                101
                 /
-                257
+                253
             
         
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    64.0%
+                    56.0%
                 
             
 
             
-                176
+                154
                 /
                 275
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    72.2%
+                    61.1%
                 
             
 
             
-                13
+                11
                 /
                 18
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    42.4%
+                    43.8%
                 
             
 
             
                 14
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    30.9%
+                    24.2%
                 
             
 
             
-                116
+                87
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dmi.html
index 2b0ca94649e..b9c09747ce7 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_exu.html
index bef511b40d5..ec1437b806a 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_exu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        41.7%
+    
+        38.0%
     
     
-        144
+        131
     
     
         345
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    78.0%
+                    69.0%
                 
             
 
             
-                78
+                69
                 /
                 100
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    53.4%
+                    48.9%
                 
             
 
             
-                47
+                43
                 /
                 88
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_ifu.html
index 7373bfe0cad..d63a008d733 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        52.3%
+    
+        47.5%
     
     
-        530
+        482
     
     
         1014
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    44.2%
+                    41.9%
                 
             
 
             
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                 /
                 172
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    76.0%
+                    64.0%
                 
             
 
             
-                95
+                80
                 /
                 125
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    82.7%
+                    65.5%
                 
             
 
             
-                91
+                72
                 /
                 110
             
@@ -343,19 +343,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    97.4%
+                    81.6%
                 
             
 
             
-                37
+                31
                 /
                 38
             
@@ -547,19 +547,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    78.6%
+                    71.4%
                 
             
 
             
-                33
+                30
                 /
                 42
             
@@ -615,19 +615,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.0%
+                    44.7%
                 
             
 
             
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+                157
                 /
                 351
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_include.html
index e807334363e..56444b5d8a6 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        9.9%
+    
+        8.3%
     
     
-        10
+        7
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    9.9%
+                    8.3%
                 
             
 
             
-                10
+                7
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lib.html
index d03716b426f..7398dea0155 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lib.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        31.4%
+    
+        29.1%
     
     
-        109
+        101
     
     
         347
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    53.7%
+                    48.5%
                 
             
 
             
-                73
+                66
                 /
                 136
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    20.0%
+                    13.3%
                 
             
 
             
-                3
+                2
                 /
                 15
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lsu.html
index dd66af8cc78..0777d650abe 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        45.9%
+    
+        29.8%
     
     
-        471
+        306
     
     
         1027
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    42.4%
+                    26.8%
                 
             
 
             
-                84
+                53
                 /
                 198
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    24.0%
+                    14.0%
                 
             
 
             
-                12
+                7
                 /
                 50
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    64.5%
+                    44.5%
                 
             
 
             
-                165
+                114
                 /
                 256
             
@@ -343,19 +343,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    57.4%
+                    42.6%
                 
             
 
             
-                66
+                49
                 /
                 115
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    25.0%
+                    10.7%
                 
             
 
             
-                28
+                12
                 /
                 112
             
@@ -547,19 +547,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    30.8%
+                    19.2%
                 
             
 
             
-                8
+                5
                 /
                 26
             
@@ -615,19 +615,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    15.3%
+                    8.5%
                 
             
 
             
-                9
+                5
                 /
                 59
             
@@ -683,19 +683,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.6%
+                    21.2%
                 
             
 
             
-                43
+                18
                 /
                 85
             
@@ -751,19 +751,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.9%
+                    14.5%
                 
             
 
             
-                22
+                11
                 /
                 76
             
@@ -819,19 +819,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.0%
+                    20.0%
                 
             
 
             
-                4
+                2
                 /
                 10
             
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_ahb_to_axi4.sv.html
index 36cbf1612ad..b74f07dc790 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : )
       29              : //   ,TAG  = 1)
       30              : (
-      31       404408 :    input                   clk,
+      31        15288 :    input                   clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -242,9 +242,9 @@
      138            2 :       buf_read_error_in = 1'b0;              // signal indicating that an error came back with the read from the core
      139            2 :       cmdbuf_wr_en      = 1'b0;              // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
      140            2 :       case (buf_state)
-     141        96198 :          IDLE: begin  // No commands recieved
-     142        96198 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
-     143        96198 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
+     141        49950 :          IDLE: begin  // No commands recieved
+     142        49950 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
+     143        49950 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
      144              :           end
      145            0 :          WR: begin // Write command recieved last cycle
      146            0 :                   buf_nxtstate      = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite  ? WR : RD;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_axi4_to_ahb.sv.html
index b2a02e37a3b..2ea2a1aeeb2 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : `include "el2_param.vh"
       28              : ,parameter TAG  = 1) (
       29              : 
-      30       384792 :    input                   clk,
-      31       384792 :    input                   free_clk,
+      30        14808 :    input                   clk,
+      31        14808 :    input                   free_clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -389,18 +389,18 @@
      285            2 :       rd_bypass_idle   = 1'b0;
      286              : 
      287            2 :       case (buf_state)
-     288        96198 :          IDLE: begin
-     289        96198 :                   master_ready   = 1'b1;
-     290        96198 :                   buf_write_in = (master_opc[2:1] == 2'b01);
-     291        96198 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
-     292        96198 :                   buf_state_en = master_valid & master_ready;
-     293        96198 :                   buf_wr_en    = buf_state_en;
-     294        96198 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
-     295        96198 :                   buf_cmd_byte_ptr_en   = buf_state_en;
-     296        96198 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
-     297        96198 :                   bypass_en       = buf_state_en;
-     298        96198 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
-     299        96198 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
+     288        49950 :          IDLE: begin
+     289        49950 :                   master_ready   = 1'b1;
+     290        49950 :                   buf_write_in = (master_opc[2:1] == 2'b01);
+     291        49950 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
+     292        49950 :                   buf_state_en = master_valid & master_ready;
+     293        49950 :                   buf_wr_en    = buf_state_en;
+     294        49950 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
+     295        49950 :                   buf_cmd_byte_ptr_en   = buf_state_en;
+     296        49950 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
+     297        49950 :                   bypass_en       = buf_state_en;
+     298        49950 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
+     299        49950 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
      300              :           end
      301            0 :          CMD_RD: begin
      302            0 :                   buf_nxtstate    = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_beh_lib.sv.html
index 1a77727adae..3fcd3a603df 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_beh_lib.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        53.7%
+    
+        48.5%
     
     
-        73
+        66
     
     
         136
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22       384792 :      input logic           clk,
+      22        14808 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38        96196 :    always_ff @(posedge clk or negedge rst_l) begin
+      38        49948 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42        96186 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42        49938 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52            0 :      input logic             en,
-      53       384792 :      input logic           clk,
+      53        14808 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -171,10 +171,10 @@
       67              : // rvdff with en and clear
       68              : module rvdffsc #( parameter WIDTH=1, SHORT=0 )
       69              :    (
-      70          804 :      input logic [WIDTH-1:0] din,
+      70            8 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73      1617632 :      input logic           clk,
+      73        61152 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -192,13 +192,13 @@
       88              : // _fpga versions
       89              : module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
       90              :    (
-      91        15114 :      input logic [WIDTH-1:0] din,
+      91          464 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94       404408 :      input logic           rawclk,
+      94        15288 :      input logic           rawclk,
       95            2 :      input logic           rst_l,
       96              : 
-      97        15114 :      output logic [WIDTH-1:0] dout
+      97          462 :      output logic [WIDTH-1:0] dout
       98              :      );
       99              : 
      100              : if (SHORT == 1) begin : genblock
@@ -220,7 +220,7 @@
      116            0 :      input logic             en,
      117            0 :      input logic           clk,
      118            6 :      input logic           clken,
-     119       789200 :      input logic           rawclk,
+     119        30096 :      input logic           rawclk,
      120            6 :      input logic           rst_l,
      121              : 
      122            0 :      output logic [WIDTH-1:0] dout
@@ -243,14 +243,14 @@
      139              : module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
      140              :    (
      141           26 :      input logic [WIDTH-1:0] din,
-     142        63988 :      input logic             en,
+     142         2796 :      input logic             en,
      143            0 :      input logic             clear,
-     144        62406 :      input logic             clk,
+     144         5092 :      input logic             clk,
      145            6 :      input logic             clken,
-     146       789200 :      input logic             rawclk,
+     146        30096 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
-     149         4340 :      output logic [WIDTH-1:0] dout
+     149          274 :      output logic [WIDTH-1:0] dout
      150              :      );
      151              : 
      152            0 :    logic [WIDTH-1:0]          din_new;
@@ -269,9 +269,9 @@
      165              : 
      166              : module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
      167              :    (
-     168          768 :      input  logic [WIDTH-1:0] din,
-     169            0 :      input  logic           en,
-     170       384792 :      input  logic           clk,
+     168            0 :      input  logic [WIDTH-1:0] din,
+     169            0 :      input  logic           en,
+     170        14808 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -309,12 +309,12 @@
      205              : 
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
-     208          698 :      input  logic [WIDTH-1:0] din,
-     209      2308752 :      input  logic             clk,
+     208           32 :      input  logic [WIDTH-1:0] din,
+     209        88848 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
-     211       192740 :      input  logic             en,
+     211         7388 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
-     213          698 :      output logic [WIDTH-1:0] dout
+     213           32 :      output logic [WIDTH-1:0] dout
      214              :      );
      215              : 
      216              : 
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            0 :      input  logic [WIDTH-1:0] din,
-     242       384792 :      input  logic             clk,
+     242        14808 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -397,12 +397,12 @@
      293              : // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
-     296          212 :      input  logic [WIDTH-1:0] din,
-     297       404408 :      input  logic             clk,
+     296          184 :      input  logic [WIDTH-1:0] din,
+     297        15288 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
-     299        25696 :      input  logic             en,
+     299          992 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
-     301          212 :      output logic [WIDTH-1:0] dout
+     301          184 :      output logic [WIDTH-1:0] dout
      302              :      );
      303              : 
      304              :    localparam integer RIGHT = 31;
@@ -440,16 +440,16 @@
      336              : 
      337              : module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
      338              :    (
-     339          108 :      input  logic [WIDTH-1:0] din,
+     339            8 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341       404408 :      input  logic           clk,
+     341        15288 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
-     344          108 :      output logic [WIDTH-1:0] dout
+     344            8 :      output logic [WIDTH-1:0] dout
      345              :      );
      346              : 
      347            0 :    logic                      l1clk;
-     348            4 :    logic                      en;
+     348           42 :    logic                      en;
      349              : 
      350              : 
      351              : 
@@ -519,7 +519,7 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418       404408 :      input  logic                 clk,
+     418        15288 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
      420            0 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434      5964276 :      input  logic                 rawclk,
+     434       229524 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -551,17 +551,17 @@
      447              : 
      448              : module rvlsadder
      449              :   (
-     450          124 :     input logic [31:0] rs1,
-     451          484 :     input logic [11:0] offset,
+     450            0 :     input logic [31:0] rs1,
+     451            0 :     input logic [11:0] offset,
      452              : 
-     453          128 :     output logic [31:0] dout
+     453            0 :     output logic [31:0] dout
      454              :     );
      455              : 
-     456          484 :    logic                cout;
-     457          484 :    logic                sign;
+     456            0 :    logic                cout;
+     457            0 :    logic                sign;
      458              : 
-     459         2780 :    logic [31:12]        rs1_inc;
-     460         2058 :    logic [31:12]        rs1_dec;
+     459          264 :    logic [31:12]        rs1_inc;
+     460           18 :    logic [31:12]        rs1_dec;
      461              : 
      462              :    assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
      463              : 
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480           16 :     input [31:1] pc,
-     481         8740 :     input [12:1] offset,
+     481          502 :     input [12:1] offset,
      482              : 
-     483          698 :     output [31:1] dout
+     483           32 :     output [31:1] dout
      484              :     );
      485              : 
-     486         8680 :    logic          cout;
-     487         9270 :    logic          sign;
+     486          498 :    logic          cout;
+     487          530 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -700,8 +700,8 @@
      596              : // Check if the S_ADDR <= addr < E_ADDR
      597              : module rvrangecheck  #(CCM_SADR = 32'h0,
      598              :                        CCM_SIZE  = 128) (
-     599          256 :    input  logic [31:0]   addr,                             // Address to be checked for range
-     600            0 :    output logic          in_range,                            // S_ADDR <= start_addr < E_ADDR
+     599            0 :    input  logic [31:0]   addr,                             // Address to be checked for range
+     600            0 :    output logic          in_range,                            // S_ADDR <= start_addr < E_ADDR
      601            0 :    output logic          in_region
      602              : );
      603              : 
@@ -804,8 +804,8 @@
      700              : endmodule // rvecc_decode
      701              : 
      702              : module rvecc_encode_64  (
-     703         4704 :                       input [63:0] din,
-     704        14984 :                       output [6:0] ecc_out
+     703           40 :                       input [63:0] din,
+     704          124 :                       output [6:0] ecc_out
      705              :                       );
      706              :   assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
      707              : 
@@ -896,10 +896,10 @@
      792              : 
      793              : module rvoclkhdr
      794              :   (
-     795       111386 :    input  logic en,
-     796     10919016 :    input  logic clk,
+     795         5810 :    input  logic en,
+     796       412776 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798     10919016 :    output logic l1clk
+     798       412776 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_insns/index_dmi_jtag_to_core_sync.v.html
index 017e6903c58..0fef7e1bc6e 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32       404408 : input       clk,        // Core clock
+      32        15288 : input       clk,        // Core clock
       33              : 
       34            0 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35            0 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49        96196 : always @ ( posedge clk or negedge rst_n) begin
+      49        49948 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54        96192 :     else begin
-      55        96192 :         rden <= {rden[1:0], rd_en};
-      56        96192 :         wren <= {wren[1:0], wr_en};
+      54        49944 :     else begin
+      55        49944 :         rden <= {rden[1:0], rd_en};
+      56        49944 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_insns/index_dmi_mux.v.html
index 7965f1e9e09..2469eeec6cc 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_insns/index_dmi_wrapper.v.html
index ea4055fea2b..ac0248bd1a2 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36       404408 :   input              core_clk,            // Core clock                  
+      36        15288 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38            0 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39            0 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dbg.sv.html
index 572a0f6778a..a421aa47c9d 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110       404408 :    input logic                         clk,
-     111       404408 :    input logic                         free_clk,
+     110        15288 :    input logic                         clk,
+     111        15288 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254            0 :    logic              dbg_free_clken;
-     255       404408 :    logic              dbg_free_clk;
+     255        15288 :    logic              dbg_free_clk;
      256              : 
      257            0 :    logic              sb_free_clken;
-     258       404408 :    logic              sb_free_clk;
+     258        15288 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474        96198 :             IDLE: begin
-     475        96198 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476        96198 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477        96198 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474        49950 :             IDLE: begin
+     475        49950 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476        49950 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477        49950 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604        96198 :             SBIDLE: begin
-     605        96198 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606        96198 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607        96198 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608        96198 :                      sbcs_sbbusy_din        = 1'b1;
-     609        96198 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610        96198 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604        49950 :             SBIDLE: begin
+     605        49950 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606        49950 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607        49950 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608        49950 :                      sbcs_sbbusy_din        = 1'b1;
+     609        49950 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610        49950 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec.sv.html
index bcff3a145e3..f474d676395 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        47.1%
+    
+        39.9%
     
     
-        121
+        101
     
     
-        257
+        253
     
 
             
@@ -136,19 +136,19 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35       404408 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36       404408 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37       404408 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38       404408 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35        15288 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        15288 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37        15288 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38        15288 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
       42            0 :     output logic dec_extint_stall,  // Stall on external interrupt
       43              : 
-      44        25728 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
+      44          998 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
       45            0 :     output logic dec_pause_state_cg, // to top for active state clock gating
       46              : 
-      47         7392 :     output logic dec_tlu_core_empty,
+      47          144 :     output logic dec_tlu_core_empty,
       48              : 
       49            2 :     input logic        rst_l,   // reset, active low
       50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
@@ -174,27 +174,27 @@
       70            2 :     output logic mpc_debug_run_ack,   // Run ack
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
-      73         1032 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74         4000 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
-      75         5370 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
+      73          104 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
+      74          276 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      75          298 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
-      78         3944 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
-      79         1424 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
+      78          268 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
+      79          252 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
       80            0 :     input logic lsu_nonblock_load_inv_r,  // invalidate request for nonblock load r
-      81         1424 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
-      82         4032 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
+      81          252 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
+      82          268 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
       83            0 :     input logic lsu_nonblock_load_data_error,  // nonblock load bus error
-      84           36 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
-      85           16 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
+      84            0 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
+      85            0 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
       86              : 
-      87         8288 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
-      88           12 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
-      89            0 :     input logic lsu_pmu_bus_error,         // D side bus error
-      90           32 :     input logic lsu_pmu_bus_busy,          // D side bus busy
-      91           12 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
-      92         3944 :     input logic lsu_pmu_load_external_m,   // D side bus load
-      93         3968 :     input logic lsu_pmu_store_external_m,  // D side bus store
+      87          544 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
+      88            0 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
+      89            0 :     input logic lsu_pmu_bus_error,         // D side bus error
+      90            0 :     input logic lsu_pmu_bus_busy,          // D side bus busy
+      91            0 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
+      92          268 :     input logic lsu_pmu_load_external_m,   // D side bus load
+      93          272 :     input logic lsu_pmu_store_external_m,  // D side bus store
       94            0 :     input logic dma_pmu_dccm_read,         // DMA DCCM read
       95            0 :     input logic dma_pmu_dccm_write,        // DMA DCCM write
       96            0 :     input logic dma_pmu_any_read,          // DMA read
@@ -203,13 +203,13 @@
       99            0 :     input logic [31:1] lsu_fir_addr,  // Fast int address
      100            0 :     input logic [ 1:0] lsu_fir_error, // Fast int lookup error
      101              : 
-     102        25728 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
-     103          950 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
-     104        26024 :     input logic ifu_pmu_ic_miss,        // icache miss
+     102          998 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
+     103           42 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
+     104          996 :     input logic ifu_pmu_ic_miss,        // icache miss
      105            0 :     input logic ifu_pmu_ic_hit,         // icache hit
      106            0 :     input logic ifu_pmu_bus_error,      // Instruction side bus error
      107            0 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
-     108        26024 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
+     108          996 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
      109              : 
      110            0 :     input logic ifu_ic_error_start,         // IC single bit error
      111            0 :     input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
@@ -228,11 +228,11 @@
      124            0 :     input logic ifu_i0_icaf_second,  // i0 has access fault on second 2B of 4B inst
      125            0 :     input logic ifu_i0_dbecc,        // icache/iccm double-bit error
      126              : 
-     127         6290 :     input logic lsu_idle_any,  // lsu idle for halting
+     127          280 :     input logic lsu_idle_any,  // lsu idle for halting
      128              : 
-     129          124 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
-     130          544 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
-     131         8682 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
+     129           20 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
+     130           20 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
+     131           30 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
      132            0 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
      133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
      134              : 
@@ -241,9 +241,9 @@
      137              : 
      138            0 :     input logic        lsu_imprecise_error_load_any,   // LSU imprecise load bus error
      139            0 :     input logic        lsu_imprecise_error_store_any,  // LSU imprecise store bus error
-     140            2 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
+     140            0 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
      141              : 
-     142            0 :     input logic [31:0] exu_div_result,  // final div result
+     142            0 :     input logic [31:0] exu_div_result,  // final div result
      143            0 :     input logic        exu_div_wren,    // Divide write enable to GPR
      144              : 
      145            0 :     input logic [31:0] exu_csr_rs1_x,  // rs1 for csr instruction
@@ -251,24 +251,24 @@
      147            0 :     input logic [31:0] lsu_result_m,      // load result
      148            0 :     input logic [31:0] lsu_result_corr_r, // load result - corrected load data
      149              : 
-     150            8 :     input logic lsu_load_stall_any,   // This is for blocking loads
-     151            8 :     input logic lsu_store_stall_any,  // This is for blocking stores
-     152            0 :     input logic dma_dccm_stall_any,   // stall any load/store at decode, pmu event
+     150            0 :     input logic lsu_load_stall_any,   // This is for blocking loads
+     151            0 :     input logic lsu_store_stall_any,  // This is for blocking stores
+     152            0 :     input logic dma_dccm_stall_any,   // stall any load/store at decode, pmu event
      153            0 :     input logic dma_iccm_stall_any,   // iccm stalled, pmu event
      154              : 
      155            0 :     input logic iccm_dma_sb_error,  // ICCM DMA single bit error
      156              : 
-     157         1240 :     input logic exu_flush_final,  // slot0 flush
+     157          110 :     input logic exu_flush_final,  // slot0 flush
      158              : 
      159            2 :     input logic [31:1] exu_npc_r,  // next PC
      160              : 
-     161          688 :     input logic [31:0] exu_i0_result_x,  // alu result x
+     161           16 :     input logic [31:0] exu_i0_result_x,  // alu result x
      162              : 
      163              : 
-     164        25052 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
-     165          540 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
+     164          754 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
+     165           16 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166           10 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167        13532 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167          350 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            2 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
@@ -290,7 +290,7 @@
      186              :     // Debug start
      187            0 :     input logic dbg_halt_req,        // DM requests a halt
      188            0 :     input logic dbg_resume_req,      // DM requests a resume
-     189        26024 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
+     189          996 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
      190              : 
      191            0 :     output logic        dec_tlu_dbg_halted,        // Core is halted and ready for debug command
      192            0 :     output logic        dec_tlu_debug_mode,        // Core is in debug mode
@@ -313,81 +313,81 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212         3756 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212          184 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215         5692 :     input  logic       exu_i0_br_valid_r,        // valid
-     216         1032 :     input  logic       exu_i0_br_mp_r,           // mispredict
-     217         7436 :     input  logic       exu_i0_br_middle_r,       // middle of bank
+     215          252 :     input  logic       exu_i0_br_valid_r,        // valid
+     216          104 :     input  logic       exu_i0_br_mp_r,           // mispredict
+     217          312 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
      219              :     // branch info from pipe1 for errors or counter updates
      220              : 
-     221         2712 :     input logic exu_i0_br_way_r,  // way hit or repl
+     221           12 :     input logic exu_i0_br_way_r,  // way hit or repl
      222              : 
-     223        21740 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
-     224        11480 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
-     225           12 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
+     223          680 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
+     224          280 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
+     225            8 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
      226            4 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228         1380 :     output logic [31:0] dec_i0_immed_d,    // immediate data
-     229          920 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
+     228           20 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     229            8 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
-     233        18816 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234         8364 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     233          474 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
+     234          534 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
-     236          760 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
+     236           28 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
      238           10 :     output logic [31:1] dec_i0_pc_d,             // pc's at decode
-     239          648 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
+     239          244 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
      240            0 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
      241              : 
      242           12 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
      243              : 
-     244         1432 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
-     245        18878 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
+     244           16 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
+     245          712 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
      246            0 :     output el2_mul_pkt_t mul_p,           // mul packet
      247            0 :     output el2_div_pkt_t div_p,           // div packet
      248            0 :     output logic         dec_div_cancel,  // cancel divide operation
      249              : 
-     250          484 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
+     250            0 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
-     252          148 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253            4 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     252            4 :     output logic        dec_csr_ren_d,    // CSR read enable
+     253            0 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
-     255           64 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
-     256           64 :     output logic dec_tlu_flush_lower_wb,
-     257           12 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
-     258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
+     255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+     256            4 :     output logic dec_tlu_flush_lower_wb,
+     257            0 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
+     258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      259            0 :     output logic dec_tlu_fence_i_r,  // flush is a fence_i rfnpc, flush icache
      260              : 
-     261          506 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
+     261           24 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
      262              : 
-     263         2712 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
+     263           12 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
      264              : 
      265            0 :     output logic dec_tlu_perfcnt0,  // toggles when slot0 perf counter 0 has an event inc
      266            0 :     output logic dec_tlu_perfcnt1,  // toggles when slot0 perf counter 1 has an event inc
      267            0 :     output logic dec_tlu_perfcnt2,  // toggles when slot0 perf counter 2 has an event inc
      268            0 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
      269              : 
-     270          424 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
-     271         8682 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
-     272          544 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
+     270           20 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
+     271           30 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
+     272           20 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
      273            0 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
      274              : 
      275            0 :     output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index,  // Fully associt btb error index
      276              : 
-     277         7856 :     output logic dec_lsu_valid_raw_d,
+     277          540 :     output logic dec_lsu_valid_raw_d,
      278              : 
      279            0 :     output logic [31:0] dec_tlu_mrac_ff,  // CSR for memory region control
      280              : 
-     281        25728 :     output logic [1:0] dec_data_en,  // clock-gate control logic
-     282        25696 :     output logic [1:0] dec_ctl_en,
+     281          996 :     output logic [1:0] dec_data_en,  // clock-gate control logic
+     282          992 :     output logic [1:0] dec_ctl_en,
      283              : 
-     284         3180 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
+     284          206 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
      285              : 
-     286            4 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
+     286          996 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
      287              : 
      288              :     // PMP signals
      289            0 :     output el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295           18 :     output logic priv_mode,
-     296           18 :     output logic priv_mode_eff,
-     297           18 :     output logic priv_mode_ns,
+     295              :     output logic priv_mode,
+     296              :     output logic priv_mode_eff,
+     297              :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300            0 :     output el2_mseccfg_pkt_t mseccfg,
+     300              :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
@@ -423,7 +423,7 @@
      319            0 :     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
      320            0 :     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
      321              : 
-     322        25728 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+     322          996 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
      323            0 :     input  logic scan_mode               // Flop scan mode control
      324              : 
      325              : );
@@ -432,44 +432,44 @@
      328            0 :   logic dec_tlu_dec_clk_override;  // to and from dec blocks
      329            0 :   logic clk_override;
      330              : 
-     331        25052 :   logic dec_ib0_valid_d;
+     331          754 :   logic dec_ib0_valid_d;
      332              : 
-     333        25728 :   logic dec_pmu_instr_decoded;
-     334          832 :   logic dec_pmu_decode_stall;
+     333          998 :   logic dec_pmu_instr_decoded;
+     334          244 :   logic dec_pmu_decode_stall;
      335            0 :   logic dec_pmu_presync_stall;
-     336           68 :   logic dec_pmu_postsync_stall;
+     336            0 :   logic dec_pmu_postsync_stall;
      337              : 
-     338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
+     338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
-     340         7684 :   logic [4:0] dec_i0_rs1_d;
-     341         7564 :   logic [4:0] dec_i0_rs2_d;
+     340           16 :   logic [4:0] dec_i0_rs1_d;
+     341           40 :   logic [4:0] dec_i0_rs2_d;
      342              : 
-     343          540 :   logic [31:0] dec_i0_instr_d;
+     343           16 :   logic [31:0] dec_i0_instr_d;
      344              : 
      345            0 :   logic dec_tlu_trace_disable;
      346            0 :   logic dec_tlu_pipelining_disable;
      347              : 
      348              : 
-     349         8272 :   logic [4:0] dec_i0_waddr_r;
-     350        13152 :   logic dec_i0_wen_r;
+     349          256 :   logic [4:0] dec_i0_waddr_r;
+     350          372 :   logic dec_i0_wen_r;
      351           12 :   logic [31:0] dec_i0_wdata_r;
-     352           48 :   logic dec_csr_wen_r;  // csr write enable at wb
-     353         5796 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
-     354            4 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
+     352           12 :   logic dec_csr_wen_r;  // csr write enable at wb
+     353           36 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
+     354            8 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
      355            4 :   logic [31:0] dec_csr_wrdata_r;  // csr write data at wb
      356              : 
-     357            4 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
-     358          196 :   logic dec_csr_legal_d;  // csr indicates legal operation
+     357            8 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
+     358           16 :   logic dec_csr_legal_d;  // csr indicates legal operation
      359              : 
-     360           48 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
-     361          196 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
-     362            4 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
+     360           12 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
+     361           16 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
+     362            0 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
      363              : 
-     364           12 :   el2_trap_pkt_t dec_tlu_packet_r;
+     364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366        13532 :   logic dec_i0_pc4_d;
+     366          350 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
-     368          128 :   logic dec_tlu_postsync_d;
+     368            4 :   logic dec_tlu_postsync_d;
      369            0 :   logic dec_tlu_debug_stall;
      370              : 
      371            0 :   logic [31:0] dec_illegal_inst;
@@ -480,18 +480,18 @@
      376            0 :   logic dec_i0_icaf_second_d;
      377            0 :   logic [3:0] dec_i0_trigger_match_d;
      378            0 :   logic dec_debug_fence_d;
-     379         4032 :   logic dec_nonblock_load_wen;
-     380          532 :   logic [4:0] dec_nonblock_load_waddr;
-     381            0 :   logic dec_tlu_flush_pause_r;
-     382          124 :   el2_br_pkt_t dec_i0_brp;
-     383          544 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
-     384         8682 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
+     379          268 :   logic dec_nonblock_load_wen;
+     380            0 :   logic [4:0] dec_nonblock_load_waddr;
+     381            0 :   logic dec_tlu_flush_pause_r;
+     382           20 :   el2_br_pkt_t dec_i0_brp;
+     383           20 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
+     384           30 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
      385            0 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
      386            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
      387              : 
      388            2 :   logic [31:1] dec_tlu_i0_pc_r;
      389            0 :   logic dec_tlu_i0_kill_writeb_wb;
-     390        25728 :   logic dec_tlu_i0_valid_r;
+     390          996 :   logic dec_tlu_i0_valid_r;
      391              : 
      392            0 :   logic dec_pause_state;
      393              : 
@@ -499,14 +499,14 @@
      395              : 
      396            0 :   logic dec_tlu_flush_extint;  // Fast ext int started
      397              : 
-     398         2908 :   logic [31:0] dec_i0_inst_wb;
+     398           12 :   logic [31:0] dec_i0_inst_wb;
      399            2 :   logic [31:1] dec_i0_pc_wb;
-     400        25716 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
+     400          996 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
      401            0 :   logic [ 4:0] dec_tlu_exc_cause_wb1;
-     402            4 :   logic [31:0] dec_tlu_mtval_wb1;
-     403           28 :   logic        dec_tlu_i0_exc_valid_wb1;
+     402            0 :   logic [31:0] dec_tlu_mtval_wb1;
+     403            0 :   logic        dec_tlu_i0_exc_valid_wb1;
      404              : 
-     405            0 :   logic [ 4:0] div_waddr_wb;
+     405            0 :   logic [ 4:0] div_waddr_wb;
      406            0 :   logic        dec_div_active;
      407              : 
      408            0 :   logic        dec_debug_valid_d;
diff --git a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_csr_equ_m.svh.html
similarity index 98%
rename from html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_csr_equ_m.svh.html
rename to html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_csr_equ_m.svh.html
index bea1f947180..b854bd07243 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_csr_equ_m.svh.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        7.1%
+    
+        8.3%
     
     
-        6
+        7
     
     
         84
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    ahb_cmark
+                    ahb_insns
                 
                 
                 
@@ -102,17 +102,17 @@
 
 
            Line data    Source code

 
-       1            0 : logic csr_misa;
-       2            0 : logic csr_mvendorid;
+       1            4 : logic csr_misa;
+       2            0 : logic csr_mvendorid;
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           27 : logic csr_mstatus;
-       7            6 : logic csr_mtvec;
+       6           18 : logic csr_mstatus;
+       7            4 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
-      10           12 : logic csr_mcyclel;
-      11            0 : logic csr_mcycleh;
+      10            0 : logic csr_mcyclel;
+      11            0 : logic csr_mcycleh;
       12            0 : logic csr_minstretl;
       13            0 : logic csr_minstreth;
       14            0 : logic csr_mscratch;
@@ -120,8 +120,8 @@
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            6 : logic csr_mrac;
-      20            0 : logic csr_dmst;
+      19            0 : logic csr_mrac;
+      20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
       23            0 : logic csr_meivt;
@@ -177,14 +177,14 @@
       73            0 : logic csr_dicad0;
       74            0 : logic csr_dicad1;
       75            0 : logic csr_dicago;
-      76            0 : logic csr_pmpcfg;
-      77            0 : logic csr_pmpaddr0;
-      78            0 : logic csr_pmpaddr16;
+      76            4 : logic csr_pmpcfg;
+      77            4 : logic csr_pmpaddr0;
+      78            0 : logic csr_pmpaddr16;
       79            0 : logic csr_pmpaddr32;
       80            0 : logic csr_pmpaddr48;
       81            0 : logic valid_only;
       82            0 : logic presync;
-      83           15 : logic postsync;
+      83           14 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370           24 : logic legal;
+     370           16 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_csr_equ_mu.svh.html
deleted file mode 100644
index 86e11499d2f..00000000000
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_csr_equ_mu.svh.html
+++ /dev/null
@@ -1,666 +0,0 @@
-
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-        Full
-        coverage report
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-        
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-            
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-                    Project
-                    Full
-                    coverage report
-                

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-        
Current view:
-                    Cores-VeeR-EL2—Cores-VeeR-EL2—design—include—el2_dec_csr_equ_mu.svh
-                CoverageHitTotal
Test Date:
-                    19-09-2024
-                
-        Toggle
-    
-        9.9%
-    
-        10
-    
-        101
-    
Test:
-                    ahb_insns
-                
-        Branch
-    
-        0.0%
-    
-        0
-    
-        0
-    

-    

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-
            Line data    Source code

-
-       1            4 : logic csr_misa;
-       2            0 : logic csr_mvendorid;
-       3            0 : logic csr_marchid;
-       4            0 : logic csr_mimpid;
-       5            0 : logic csr_mhartid;
-       6          162 : logic csr_mstatus;
-       7            4 : logic csr_mtvec;
-       8            0 : logic csr_mip;
-       9            0 : logic csr_mie;
-      10            0 : logic csr_mcyclel;
-      11            0 : logic csr_mcycleh;
-      12            0 : logic csr_minstretl;
-      13            0 : logic csr_minstreth;
-      14            0 : logic csr_mscratch;
-      15           88 : logic csr_mepc;
-      16           56 : logic csr_mcause;
-      17            0 : logic csr_mscause;
-      18            0 : logic csr_mtval;
-      19            0 : logic csr_mrac;
-      20            0 : logic csr_dmst;
-      21            0 : logic csr_mdseac;
-      22            0 : logic csr_meihap;
-      23            0 : logic csr_meivt;
-      24            0 : logic csr_meipt;
-      25            0 : logic csr_meicurpl;
-      26            0 : logic csr_meicidpl;
-      27            0 : logic csr_dcsr;
-      28            0 : logic csr_mcgc;
-      29            0 : logic csr_mfdc;
-      30            0 : logic csr_dpc;
-      31            0 : logic csr_mtsel;
-      32            0 : logic csr_mtdata1;
-      33            0 : logic csr_mtdata2;
-      34            0 : logic csr_mhpmc3;
-      35            0 : logic csr_mhpmc4;
-      36            0 : logic csr_mhpmc5;
-      37            0 : logic csr_mhpmc6;
-      38            0 : logic csr_mhpmc3h;
-      39            0 : logic csr_mhpmc4h;
-      40            0 : logic csr_mhpmc5h;
-      41            0 : logic csr_mhpmc6h;
-      42            0 : logic csr_mhpme3;
-      43            0 : logic csr_mhpme4;
-      44            0 : logic csr_mhpme5;
-      45            0 : logic csr_mhpme6;
-      46            0 : logic csr_mcounteren;
-      47            0 : logic csr_mcountinhibit;
-      48            0 : logic csr_mitctl0;
-      49            0 : logic csr_mitctl1;
-      50            0 : logic csr_mitb0;
-      51            0 : logic csr_mitb1;
-      52            0 : logic csr_mitcnt0;
-      53            0 : logic csr_mitcnt1;
-      54            0 : logic csr_perfva;
-      55            0 : logic csr_perfvb;
-      56            0 : logic csr_perfvc;
-      57            0 : logic csr_perfvd;
-      58            0 : logic csr_perfve;
-      59            0 : logic csr_perfvf;
-      60            0 : logic csr_perfvg;
-      61            0 : logic csr_perfvh;
-      62            0 : logic csr_perfvi;
-      63            0 : logic csr_mpmc;
-      64            0 : logic csr_mcpc;
-      65            0 : logic csr_meicpct;
-      66            0 : logic csr_mdeau;
-      67            0 : logic csr_micect;
-      68            0 : logic csr_miccmect;
-      69            0 : logic csr_mdccmect;
-      70            0 : logic csr_mfdht;
-      71            0 : logic csr_mfdhs;
-      72            0 : logic csr_dicawics;
-      73            0 : logic csr_dicad0h;
-      74            0 : logic csr_dicad0;
-      75            0 : logic csr_dicad1;
-      76            0 : logic csr_dicago;
-      77            0 : logic csr_menvcfg;
-      78            0 : logic csr_menvcfgh;
-      79            4 : logic csr_pmpcfg;
-      80            4 : logic csr_pmpaddr0;
-      81            0 : logic csr_pmpaddr16;
-      82            0 : logic csr_pmpaddr32;
-      83            0 : logic csr_pmpaddr48;
-      84          198 : logic csr_cyclel;
-      85            0 : logic csr_cycleh;
-      86            0 : logic csr_instretl;
-      87            0 : logic csr_instreth;
-      88            0 : logic csr_hpmc3;
-      89            0 : logic csr_hpmc4;
-      90            0 : logic csr_hpmc5;
-      91            0 : logic csr_hpmc6;
-      92            0 : logic csr_hpmc3h;
-      93            0 : logic csr_hpmc4h;
-      94            0 : logic csr_hpmc5h;
-      95            0 : logic csr_hpmc6h;
-      96            0 : logic csr_mseccfgl;
-      97            0 : logic csr_mseccfgh;
-      98            0 : logic valid_only;
-      99            0 : logic presync;
-     100           70 : logic postsync;
-     101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     103              : 
-     104              : assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     105              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     106              : 
-     107              : assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     108              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     109              : 
-     110              : assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]
-     111              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     112              : 
-     113              : assign csr_mhartid = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     114              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]);
-     115              : 
-     116              : assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     117              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
-     118              :     &!dec_csr_rdaddr_d[0]);
-     119              : 
-     120              : assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     121              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     122              : 
-     123              : assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
-     124              :     &!dec_csr_rdaddr_d[0]);
-     125              : 
-     126              : assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     127              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     128              : 
-     129              : assign csr_mcyclel = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     130              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     131              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     132              : 
-     133              : assign csr_mcycleh = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     134              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     135              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     136              : 
-     137              : assign csr_minstretl = (dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     138              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     139              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     140              : 
-     141              : assign csr_minstreth = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     142              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     143              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     144              : 
-     145              : assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     146              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     147              : 
-     148              : assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     149              :     &dec_csr_rdaddr_d[0]);
-     150              : 
-     151              : assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     152              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     153              : 
-     154              : assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     155              :     &dec_csr_rdaddr_d[2]);
-     156              : 
-     157              : assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[2]
-     158              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     159              : 
-     160              : assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     161              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     162              :     &!dec_csr_rdaddr_d[1]);
-     163              : 
-     164              : assign csr_dmst = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
-     165              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     166              : 
-     167              : assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     168              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
-     169              : 
-     170              : assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     171              :     &dec_csr_rdaddr_d[3]);
-     172              : 
-     173              : assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     174              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     175              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     176              : 
-     177              : assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     178              :     &dec_csr_rdaddr_d[0]);
-     179              : 
-     180              : assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     181              :     &dec_csr_rdaddr_d[2]);
-     182              : 
-     183              : assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     184              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     185              : 
-     186              : assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     187              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);
-     188              : 
-     189              : assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     190              :     &!dec_csr_rdaddr_d[0]);
-     191              : 
-     192              : assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     193              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     194              : 
-     195              : assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     196              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
-     197              : 
-     198              : assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     199              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     200              : 
-     201              : assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     202              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
-     203              : 
-     204              : assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     205              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);
-     206              : 
-     207              : assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     208              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     209              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     210              : 
-     211              : assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     212              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     213              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     214              : 
-     215              : assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     216              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     217              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     218              : 
-     219              : assign csr_mhpmc6 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     220              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     221              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     222              : 
-     223              : assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     224              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     225              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     226              : 
-     227              : assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     228              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     229              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     230              : 
-     231              : assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     232              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     233              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     234              : 
-     235              : assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     236              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     237              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     238              : 
-     239              : assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     240              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     241              :     &dec_csr_rdaddr_d[0]);
-     242              : 
-     243              : assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     244              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     245              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     246              : 
-     247              : assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     248              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
-     249              :     &dec_csr_rdaddr_d[0]);
-     250              : 
-     251              : assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     252              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
-     253              :     &!dec_csr_rdaddr_d[0]);
-     254              : 
-     255              : assign csr_mcounteren = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     256              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     257              : 
-     258              : assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     259              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     260              :     &!dec_csr_rdaddr_d[0]);
-     261              : 
-     262              : assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     263              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
-     264              :     &!dec_csr_rdaddr_d[0]);
-     265              : 
-     266              : assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     267              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     268              :     &dec_csr_rdaddr_d[0]);
-     269              : 
-     270              : assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
-     271              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     272              : 
-     273              : assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
-     274              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     275              : 
-     276              : assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     277              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
-     278              :     &!dec_csr_rdaddr_d[0]);
-     279              : 
-     280              : assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]
-     281              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     282              : 
-     283              : assign csr_perfva  = 1'b0;
-     284              : 
-     285              : assign csr_perfvb  = 1'b0;
-     286              : 
-     287              : assign csr_perfvc  = 1'b0;
-     288              : 
-     289              : assign csr_perfvd  = 1'b0;
-     290              : 
-     291              : assign csr_perfve  = 1'b0;
-     292              : 
-     293              : assign csr_perfvf  = 1'b0;
-     294              : 
-     295              : assign csr_perfvg  = 1'b0;
-     296              : 
-     297              : assign csr_perfvh  = 1'b0;
-     298              : 
-     299              : assign csr_perfvi  = 1'b0;
-     300              : 
-     301              : assign csr_mpmc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     302              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     303              :     &dec_csr_rdaddr_d[1]);
-     304              : 
-     305              : assign csr_mcpc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
-     306              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     307              : 
-     308              : assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     309              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     310              : 
-     311              : assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     312              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
-     313              : 
-     314              : assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     315              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     316              : 
-     317              : assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     318              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
-     319              : 
-     320              : assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     321              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     322              : 
-     323              : assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     324              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     325              : 
-     326              : assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
-     327              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     328              : 
-     329              : assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     330              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     331              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     332              : 
-     333              : assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     334              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     335              : 
-     336              : assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
-     337              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     338              : 
-     339              : assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     340              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     341              : 
-     342              : assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     343              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     344              : 
-     345              : assign csr_menvcfg = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     346              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]);
-     347              : 
-     348              : assign csr_menvcfgh = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     349              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
-     350              : 
-     351              : assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     352              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
-     353              : 
-     354              : assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     355              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
-     356              : 
-     357              : assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     358              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
-     359              : 
-     360              : assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     361              :     &dec_csr_rdaddr_d[4]);
-     362              : 
-     363              : assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     364              :     &!dec_csr_rdaddr_d[4]);
-     365              : 
-     366              : assign csr_cyclel = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     367              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     368              : 
-     369              : assign csr_cycleh = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     370              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     371              : 
-     372              : assign csr_instretl = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     373              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     374              : 
-     375              : assign csr_instreth = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     376              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     377              : 
-     378              : assign csr_hpmc3 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     379              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     380              : 
-     381              : assign csr_hpmc4 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     382              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     383              : 
-     384              : assign csr_hpmc5 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     385              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     386              : 
-     387              : assign csr_hpmc6 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     388              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     389              : 
-     390              : assign csr_hpmc3h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     391              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     392              : 
-     393              : assign csr_hpmc4h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     394              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     395              : 
-     396              : assign csr_hpmc5h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     397              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     398              : 
-     399              : assign csr_hpmc6h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     400              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     401              : 
-     402              : assign csr_mseccfgl = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     403              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]);
-     404              : 
-     405              : assign csr_mseccfgh = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     406              :     &dec_csr_rdaddr_d[4]);
-     407              : 
-     408              : assign valid_only = (!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     409              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (
-     410              :     !dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
-     411              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
-     412              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[7]
-     413              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
-     414              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
-     415              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]);
-     416              : 
-     417              : assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     418              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
-     419              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     420              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
-     421              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
-     422              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     423              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
-     424              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
-     425              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
-     426              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
-     427              :     dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     428              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     429              : 
-     430              : assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     431              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     432              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]
-     433              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
-     434              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     435              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
-     436              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
-     437              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]
-     438              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
-     439              :     dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[4]
-     440              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
-     441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     442              :     &dec_csr_rdaddr_d[0]);
-     443              : 
-     444          196 : logic legal;
-     445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     448              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
-     449              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     450              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     451              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     452              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     453              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     454              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     455              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     456              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     457              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     458              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     459              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     460              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     461              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     462              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]
-     463              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     464              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
-     465              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     466              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     467              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
-     468              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     469              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (
-     470              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     471              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
-     472              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     473              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     474              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     475              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
-     476              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     477              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (
-     478              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]
-     479              :     &!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     480              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     481              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     482              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     483              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     484              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     485              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     486              :     &!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     487              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     488              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
-     489              :     &dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]
-     490              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     491              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     492              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     493              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     494              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
-     495              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     496              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     497              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
-     498              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     499              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     500              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (
-     501              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     502              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     503              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     504              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
-     505              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     506              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     507              :     &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
-     508              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
-     509              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     510              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     511              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     512              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     513              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     514              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     515              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     516              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
-     517              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     518              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     519              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
-     520              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     521              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     522              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
-     523              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     524              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     525              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[9]
-     526              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     527              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
-     528              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     529              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     530              :     &!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     531              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     532              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     533              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     534              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
-     535              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     536              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     537              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
-     538              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     539              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     540              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
-     541              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     542              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     543              :     &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     544              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     545              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]
-     546              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     547              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
-     548              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     549              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     550              :     &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     551              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     552              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]
-     553              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     554              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);
-     555              : 
-        

-

-
-
-
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_decode_ctl.sv.html
index 67c7c225f96..5b6d74171b0 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_decode_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        64.0%
+    
+        56.0%
     
     
-        176
+        154
     
     
         275
@@ -133,29 +133,29 @@
       29              : 
       30            0 :    output logic dec_extint_stall,            // Stall from external interrupt
       31              : 
-      32         3180 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
-      33         2908 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
+      32          206 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
+      33           12 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
       34            2 :    output logic [31:1] dec_i0_pc_wb,         // 31b pc at wb+1 for trace encoder
       35              : 
       36              : 
-      37         3944 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
-      38         1424 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
+      37          268 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
+      38          252 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
       39            0 :    input logic                                lsu_nonblock_load_inv_r,         // invalidate request for nonblock load r
-      40         1424 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
-      41         4032 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
+      40          252 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
+      41          268 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
       42            0 :    input logic                                lsu_nonblock_load_data_error,    // nonblock load bus error
-      43           36 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
+      43            0 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
       44              : 
       45              : 
-      46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
+      46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
       47              : 
       48            0 :    input logic dec_tlu_wr_pause_r,                    // pause instruction at r
       49            0 :    input logic dec_tlu_pipelining_disable,            // pipeline disable - presync, i0 decode only
       50              : 
       51            0 :    input logic [3:0]  lsu_trigger_match_m,            // lsu trigger matches
       52              : 
-      53           12 :    input logic lsu_pmu_misaligned_m,                  // perf mon: load/store misalign
-      54            0 :    input logic dec_tlu_debug_stall,                   // debug stall decode
+      53            0 :    input logic lsu_pmu_misaligned_m,                  // perf mon: load/store misalign
+      54            0 :    input logic dec_tlu_debug_stall,                   // debug stall decode
       55            0 :    input logic dec_tlu_flush_leak_one_r,              // leak1 instruction
       56              : 
       57            0 :    input logic dec_debug_fence_d,                     // debug fence instruction
@@ -168,87 +168,87 @@
       64              : 
       65            0 :    input logic dec_i0_dbecc_d,                        // icache/iccm double-bit error
       66              : 
-      67          124 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
-      68          544 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69         8682 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      67           20 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
+      68           20 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      69           30 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
-      73         6290 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
+      73          280 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
       74              : 
-      75            8 :    input logic lsu_load_stall_any,                    // stall any load at decode
-      76            8 :    input logic lsu_store_stall_any,                   // stall any store at decode
-      77            0 :    input logic dma_dccm_stall_any,                    // stall any load/store at decode
+      75            0 :    input logic lsu_load_stall_any,                    // stall any load at decode
+      76            0 :    input logic lsu_store_stall_any,                   // stall any store at decode
+      77            0 :    input logic dma_dccm_stall_any,                    // stall any load/store at decode
       78              : 
       79            0 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
       80              : 
       81            0 :    input logic dec_tlu_i0_kill_writeb_wb,             // I0 is flushed, don't writeback any results to arch state
-      82           64 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
+      82            4 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
       83            0 :    input logic dec_tlu_i0_kill_writeb_r,              // I0 is flushed, don't writeback any results to arch state
-      84           64 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
+      84            4 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
       85            0 :    input logic dec_tlu_flush_pause_r,                 // don't clear pause state on initial lower flush
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
-      87          128 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
+      87            4 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89        13532 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89          350 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91            4 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92          196 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
       96            0 :    input logic [31:0] lsu_result_m,                   // load result
       97            0 :    input logic [31:0] lsu_result_corr_r,              // load result - corrected data for writing gpr's, not for bypassing
       98              : 
-      99         1240 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
+      99          110 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
      100              : 
      101            2 :    input logic [31:1] exu_i0_pc_x,                    // pcs at e1
      102              : 
-     103          540 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
+     103           16 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
      104              : 
-     105        25052 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
+     105          754 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
      106              : 
-     107          688 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
+     107           16 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109       404408 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110       404408 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111       404408 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109        15288 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110        15288 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111        15288 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
      115              : 
      116              : 
      117              : 
-     118        21740 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
-     119        11480 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
+     118          680 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
+     119          280 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
-     121         7684 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122         7564 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     121           16 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
+     122           40 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124         1380 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124           20 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
-     127          920 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
+     127            8 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
      128              : 
      129            0 :    output el2_alu_pkt_t i0_ap,                       // alu packets
      130              : 
-     131        25728 :    output logic        dec_i0_decode_d,               // i0 decode
+     131          998 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
-     133        18816 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134         8364 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     133          474 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
+     134          534 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
-     136         8272 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137        13152 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     136          256 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
+     137          372 :    output logic        dec_i0_wen_r,                  // i0 write enable
      138           12 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
-     140          760 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
+     140           28 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
      141              : 
-     142          648 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
+     142          244 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
      143            0 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
      144           12 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
      145              : 
-     146         1432 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
-     147        18878 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
+     146           16 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
+     147          712 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
      148              : 
      149            0 :    output el2_mul_pkt_t    mul_p,                    // multiply packet
      150              : 
@@ -256,46 +256,46 @@
      152            0 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
      153            0 :    output logic             dec_div_cancel,           // cancel the divide operation
      154              : 
-     155         7856 :    output logic        dec_lsu_valid_raw_d,
-     156          484 :    output logic [11:0] dec_lsu_offset_d,
+     155          540 :    output logic        dec_lsu_valid_raw_d,
+     156            0 :    output logic [11:0] dec_lsu_offset_d,
      157              : 
-     158          148 :    output logic        dec_csr_ren_d,                 // valid csr decode
-     159           48 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
-     160          196 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
-     161            4 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
-     162           48 :    output logic        dec_csr_wen_r,                 // csr write enable at r
-     163         5796 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
-     164            4 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
+     158            4 :    output logic        dec_csr_ren_d,                 // valid csr decode
+     159           12 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
+     160           16 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
+     161            8 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
+     162           12 :    output logic        dec_csr_wen_r,                 // csr write enable at r
+     163           36 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
+     164            8 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
      165            4 :    output logic [31:0] dec_csr_wrdata_r,              // csr write data at r
-     166            4 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
+     166            0 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
      167              : 
-     168        25728 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
+     168          996 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
      169              : 
-     170           12 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
+     170            0 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
      171              : 
-     172            2 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
+     172            2 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
      173              : 
      174            0 :    output logic [31:0] dec_illegal_inst,              // illegal inst
-     175          506 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
+     175           24 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
-     177          424 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178         8682 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
-     179          544 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
+     177           20 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
+     178           30 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     179           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      183              : 
-     184        25728 :    output logic [1:0] dec_data_en,                    // clock-gating logic
-     185        25696 :    output logic [1:0] dec_ctl_en,
+     184          996 :    output logic [1:0] dec_data_en,                    // clock-gating logic
+     185          992 :    output logic [1:0] dec_ctl_en,
      186              : 
-     187        25728 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
-     188          832 :    output logic       dec_pmu_decode_stall,           // decode is stalled
+     187          998 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
+     188          244 :    output logic       dec_pmu_decode_stall,           // decode is stalled
      189            0 :    output logic       dec_pmu_presync_stall,          // decode has presync stall
-     190           68 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
+     190            0 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
      191              : 
-     192         4032 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
-     193          532 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
-     194            0 :    output logic       dec_pause_state,                // core in pause state
+     192          268 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
+     193            0 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
+     194            0 :    output logic       dec_pause_state,                // core in pause state
      195            0 :    output logic       dec_pause_state_cg,             // pause state for clock-gating
      196              : 
      197            0 :    output logic       dec_div_active,                 // non-block divide is active
@@ -308,27 +308,27 @@
      204              : 
      205            0 :    el2_dec_pkt_t           i0_dp_raw, i0_dp;
      206              : 
-     207          540 :    logic [31:0]        i0;
-     208        25052 :    logic               i0_valid_d;
+     207           16 :    logic [31:0]        i0;
+     208          754 :    logic               i0_valid_d;
      209              : 
      210           12 :    logic [31:0]        i0_result_r;
      211              : 
-     212          112 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
+     212            0 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
      213              : 
-     214          540 :    logic               i0_jalimm20;
-     215          552 :    logic               i0_uiimm20;
+     214           16 :    logic               i0_jalimm20;
+     215           32 :    logic               i0_uiimm20;
      216              : 
-     217         7856 :    logic               lsu_decode_d;
-     218         1380 :    logic [31:0]        i0_immed_d;
+     217          540 :    logic               lsu_decode_d;
+     218           20 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
-     220         1364 :    logic               i0_postsync;
+     220          240 :    logic               i0_postsync;
      221              : 
-     222          188 :    logic               postsync_stall;
-     223          188 :    logic               ps_stall;
+     222            4 :    logic               postsync_stall;
+     223            4 :    logic               ps_stall;
      224              : 
-     225        25696 :    logic               prior_inflight, prior_inflight_wb;
+     225          992 :    logic               prior_inflight, prior_inflight_wb;
      226              : 
-     227           48 :    logic               csr_clr_d, csr_set_d, csr_write_d;
+     227           12 :    logic               csr_clr_d, csr_set_d, csr_write_d;
      228              : 
      229            0 :    logic               csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
      230            0 :    logic [31:0]        csr_mask_x;
@@ -339,9 +339,9 @@
      235              : 
      236            0 :    logic [4:0]         csrimm_x;
      237              : 
-     238            4 :    logic [31:0]        csr_rddata_x;
+     238            0 :    logic [31:0]        csr_rddata_x;
      239              : 
-     240            0 :    logic               mul_decode_d;
+     240            0 :    logic               mul_decode_d;
      241            0 :    logic               div_decode_d;
      242            0 :    logic               div_e1_to_r;
      243            0 :    logic               div_flush;
@@ -351,49 +351,49 @@
      247            0 :    logic               i0_div_prior_div_stall;
      248            0 :    logic               nonblock_div_cancel;
      249              : 
-     250        23976 :    logic               i0_legal;
-     251            8 :    logic               shift_illegal;
-     252            8 :    logic               illegal_inst_en;
-     253            8 :    logic               illegal_lockout_in, illegal_lockout;
-     254        25720 :    logic               i0_legal_decode_d;
-     255          952 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
+     250          518 :    logic               i0_legal;
+     251            0 :    logic               shift_illegal;
+     252            0 :    logic               illegal_inst_en;
+     253            0 :    logic               illegal_lockout_in, illegal_lockout;
+     254          998 :    logic               i0_legal_decode_d;
+     255          248 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
-     257         4768 :    logic [12:1]        last_br_immed_d;
-     258          648 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
+     257          180 :    logic [12:1]        last_br_immed_d;
+     258          244 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
      261            0 :    logic               i0_div_decode_d;
      262            0 :    logic               i0_load_block_d;
      263            0 :    logic [1:0]         i0_rs1_depth_d, i0_rs2_depth_d;
      264              : 
-     265            8 :    logic               i0_load_stall_d;
-     266            0 :    logic               i0_store_stall_d;
+     265            0 :    logic               i0_load_stall_d;
+     266            0 :    logic               i0_store_stall_d;
      267              : 
-     268         3460 :    logic               i0_predict_nt, i0_predict_t;
+     268          114 :    logic               i0_predict_nt, i0_predict_t;
      269              : 
-     270         1064 :    logic               i0_notbr_error, i0_br_toffset_error;
+     270          176 :    logic               i0_notbr_error, i0_br_toffset_error;
      271            0 :    logic               i0_ret_error;
-     272         1176 :    logic               i0_br_error;
-     273         1176 :    logic               i0_br_error_all;
-     274         5840 :    logic [11:0]        i0_br_offset;
+     272          236 :    logic               i0_br_error;
+     273          236 :    logic               i0_br_error_all;
+     274          270 :    logic [11:0]        i0_br_offset;
      275              : 
-     276         2936 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
-     277        22626 :    logic               i0_pcall_12b_offset;
-     278          140 :    logic               i0_pcall_raw;
-     279          144 :    logic               i0_pcall_case;
-     280          140 :    logic               i0_pcall;
+     276           16 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
+     277          720 :    logic               i0_pcall_12b_offset;
+     278           12 :    logic               i0_pcall_raw;
+     279           16 :    logic               i0_pcall_case;
+     280           12 :    logic               i0_pcall;
      281              : 
-     282          400 :    logic               i0_pja_raw;
-     283          420 :    logic               i0_pja_case;
-     284          400 :    logic               i0_pja;
+     282            4 :    logic               i0_pja_raw;
+     283            8 :    logic               i0_pja_case;
+     284            4 :    logic               i0_pja;
      285              : 
-     286          136 :    logic               i0_pret_case;
-     287          136 :    logic               i0_pret_raw, i0_pret;
+     286           12 :    logic               i0_pret_case;
+     287           12 :    logic               i0_pret_raw, i0_pret;
      288              : 
-     289          112 :    logic               i0_jal;                                // jal's that are not predicted
+     289            0 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292         7076 :    logic               i0_predict_br;
+     292          298 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301        13532 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301          350 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303        16704 :    logic               i0_rd_en_d;
+     303          636 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -412,43 +412,43 @@
      308            0 :    logic               leak1_i1_stall_in, leak1_i1_stall;
      309            0 :    logic               leak1_mode;
      310              : 
-     311           48 :    logic               i0_csr_write_only_d;
+     311           12 :    logic               i0_csr_write_only_d;
      312              : 
-     313        25696 :    logic               prior_inflight_x, prior_inflight_eff;
-     314          196 :    logic               any_csr_d;
+     313          992 :    logic               prior_inflight_x, prior_inflight_eff;
+     314           16 :    logic               any_csr_d;
      315              : 
-     316           48 :    logic               prior_csr_write;
+     316           12 :    logic               prior_csr_write;
      317              : 
-     318        25728 :    logic [3:0]        i0_pipe_en;
-     319        25696 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
-     320        25728 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
+     318          996 :    logic [3:0]        i0_pipe_en;
+     319          992 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
+     320          996 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
      321              : 
      322            0 :    logic              debug_fence_i;
      323            0 :    logic              debug_fence;
      324              : 
-     325           48 :    logic              i0_csr_write;
+     325           12 :    logic              i0_csr_write;
      326            0 :    logic              presync_stall;
      327              : 
      328            0 :    logic              i0_instr_error;
      329            0 :    logic              i0_icaf_d;
      330              : 
-     331           64 :    logic              clear_pause;
+     331            4 :    logic              clear_pause;
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335         6868 :    logic              i0_brp_valid;
-     336         3104 :    logic              nonblock_load_cancel;
-     337         6290 :    logic              lsu_idle;
-     338           12 :    logic              lsu_pmu_misaligned_r;
-     339          148 :    logic              csr_ren_qual_d;
-     340          148 :    logic              csr_read_x;
-     341          960 :    logic              i0_block_d;
-     342          952 :    logic              i0_block_raw_d;  // This is use to create the raw valid
-     343          188 :    logic              ps_stall_in;
-     344         1060 :    logic [31:0]       i0_result_x;
+     335          488 :    logic              i0_brp_valid;
+     336           16 :    logic              nonblock_load_cancel;
+     337          280 :    logic              lsu_idle;
+     338            0 :    logic              lsu_pmu_misaligned_r;
+     339            4 :    logic              csr_ren_qual_d;
+     340            4 :    logic              csr_read_x;
+     341          248 :    logic              i0_block_d;
+     342          248 :    logic              i0_block_raw_d;  // This is use to create the raw valid
+     343            4 :    logic              ps_stall_in;
+     344           16 :    logic [31:0]       i0_result_x;
      345              : 
-     346         3944 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
-     347         3944 :    el2_dest_pkt_t         x_d_in, r_d_in;
+     346          256 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
+     347          256 :    el2_dest_pkt_t         x_d_in, r_d_in;
      348              : 
      349            0 :    el2_trap_pkt_t         d_t, x_t, x_t_in, r_t_in, r_t;
      350              : 
@@ -456,16 +456,16 @@
      352              : 
      353            2 :    logic [31:1]       dec_i0_pc_r;
      354              : 
-     355           48 :    logic csr_read, csr_write;
-     356          112 :    logic i0_br_unpred;
+     355            4 :    logic csr_read, csr_write;
+     356            0 :    logic i0_br_unpred;
      357              : 
-     358         3944 :    logic nonblock_load_valid_m_delay;
-     359        16700 :    logic i0_wen_r;
+     358          268 :    logic nonblock_load_valid_m_delay;
+     359          636 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
      363              : 
-     364         1240 :    logic flush_final_r;
+     364          108 :    logic flush_final_r;
      365              : 
      366            2 :    logic bitmanip_zbb_legal;
      367            2 :    logic bitmanip_zbs_legal;
@@ -489,24 +489,24 @@
      385              :    localparam NBLOAD_TAG_MSB  = pt.LSU_NUM_NBLOAD_WIDTH-1;
      386              : 
      387              : 
-     388         4032 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
-     389           36 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
-     390            0 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
+     388          268 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
+     389            0 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
+     390            0 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
      391              : 
-     392           36 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
-     393            0 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
+     392            0 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
+     393            0 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
      394              : 
      395            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
      396            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
      397            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
      398              : 
-     399          568 :    logic [4:0] nonblock_load_rd;
-     400          764 :    logic i0_nonblock_load_stall;
-     401          648 :    logic i0_nonblock_boundary_stall;
+     399            0 :    logic [4:0] nonblock_load_rd;
+     400          244 :    logic i0_nonblock_load_stall;
+     401          244 :    logic i0_nonblock_boundary_stall;
      402              : 
      403            0 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
      404              : 
-     405         3944 :    logic i0_load_kill_wen_r;
+     405          268 :    logic i0_load_kill_wen_r;
      406              : 
      407            2 :    logic found;
      408              : 
@@ -517,24 +517,24 @@
      413           12 :    logic [31:0] i0_result_r_raw;
      414           12 :    logic [31:0] i0_result_corr_r;
      415              : 
-     416         4374 :    logic [12:1] last_br_immed_x;
+     416          180 :    logic [12:1] last_br_immed_x;
      417              : 
-     418         3292 :    logic [31:0]        i0_inst_d;
-     419         2908 :    logic [31:0]        i0_inst_x;
-     420         2908 :    logic [31:0]        i0_inst_r;
-     421         2908 :    logic [31:0]        i0_inst_wb_in;
-     422         2908 :    logic [31:0]        i0_inst_wb;
+     418           12 :    logic [31:0]        i0_inst_d;
+     419           12 :    logic [31:0]        i0_inst_x;
+     420           12 :    logic [31:0]        i0_inst_r;
+     421           12 :    logic [31:0]        i0_inst_wb_in;
+     422           12 :    logic [31:0]        i0_inst_wb;
      423              : 
      424            2 :    logic [31:1]        i0_pc_wb;
      425              : 
-     426        25728 :    logic               i0_wb_en;
+     426          996 :    logic               i0_wb_en;
      427              : 
      428            2 :    logic               trace_enable;
      429              : 
      430            0 :    logic               debug_valid_x;
      431              : 
-     432         7240 :    el2_inst_pkt_t i0_itype;
-     433         7564 :    el2_reg_pkt_t i0r;
+     432          298 :    el2_inst_pkt_t i0_itype;
+     433           16 :    el2_reg_pkt_t i0r;
      434              : 
      435              : 
      436              :    rvdffie  #(8) misc1ff (.*,
@@ -631,14 +631,14 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530         3076 :       if (i0_br_error_all | i0_instr_error) begin
-     531         3076 :          i0_dp          =   '0;
-     532         3076 :          i0_dp.alu      = 1'b1;
-     533         3076 :          i0_dp.rs1      = 1'b1;
-     534         3076 :          i0_dp.rs2      = 1'b1;
-     535         3076 :          i0_dp.lor      = 1'b1;
-     536         3076 :          i0_dp.legal    = 1'b1;
-     537         3076 :          i0_dp.postsync = 1'b1;
+     530         1774 :       if (i0_br_error_all | i0_instr_error) begin
+     531         1774 :          i0_dp          =   '0;
+     532         1774 :          i0_dp.alu      = 1'b1;
+     533         1774 :          i0_dp.rs1      = 1'b1;
+     534         1774 :          i0_dp.rs2      = 1'b1;
+     535         1774 :          i0_dp.lor      = 1'b1;
+     536         1774 :          i0_dp.legal    = 1'b1;
+     537         1774 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -709,16 +709,16 @@
      605            2 :       found = 0;
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
-     608        14436 :             if (~cam[i].valid) begin
-     609        89966 :                cam_wen[i] = cam_write;
-     610        89966 :                found = 1'b1;
+     608         7750 :             if (~cam[i].valid) begin
+     609        46574 :                cam_wen[i] = cam_write;
+     610        46574 :                found = 1'b1;
      611              :             end
-     612        14436 :             else begin
-     613        14436 :                cam_wen[i] = 0;
+     612         7750 :             else begin
+     613         7750 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617       362394 :             cam_wen[i] = 0;
+     617       189162 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,28 +756,28 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655         2122 :          if (cam_data_reset_val[i])
-     656         2122 :            cam[i].valid = 1'b0;
+     655         1129 :          if (cam_data_reset_val[i])
+     656         1129 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
      659              : 
-     660         6366 :          if (cam_wen[i]) begin
-     661         6366 :             cam_in[i].valid    = 1'b1;
-     662         6366 :             cam_in[i].wb       = 1'b0;
-     663         6366 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
-     664         6366 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
+     660         3387 :          if (cam_wen[i]) begin
+     661         3387 :             cam_in[i].valid    = 1'b1;
+     662         3387 :             cam_in[i].wb       = 1'b0;
+     663         3387 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
+     664         3387 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666          148 :          else if ( (cam_inv_reset_val[i]) |
+     666           76 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
-     668          148 :            cam_in[i].valid = 1'b0;
+     668           76 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670       476678 :            cam_in[i] = cam[i];
+     670       248753 :            cam_in[i] = cam[i];
      671              : 
-     672         6366 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
-     673         6366 :            cam_in[i].wb = 1'b1;
+     672         3387 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     673         3387 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676       384792 :          if (dec_tlu_force_halt)
+     676       199800 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746        18998 :       if (i0_legal_decode_d) begin
-     747        18998 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748         2622 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749         2638 :          if (i0_dp.store)                i0_itype = STORE;
-     750         8536 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751        18998 :          if (i0_dp.zbb | i0_dp.zbs |
+     746         9940 :       if (i0_legal_decode_d) begin
+     747         9940 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748         1383 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749         1388 :          if (i0_dp.store)                i0_itype = STORE;
+     750         4359 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751         9940 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756          102 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757           24 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758        18998 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759            4 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760            4 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761        18998 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762        18998 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763           22 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764         4256 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765          790 :          if (i0_dp.jal)                  i0_itype = JAL;
+     756           52 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757           15 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758         9940 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759          443 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760          443 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761         9940 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762         9940 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763          452 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764         2318 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765          410 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862        96198 :       if (dec_extint_stall) begin
+     862        49950 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868        96198 :       else begin
-     869        96198 :          lsu_p.valid = lsu_decode_d;
+     868        49950 :       else begin
+     869        49950 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871        96198 :          lsu_p.load                         =  i0_dp.load ;
-     872        96198 :          lsu_p.store                        =  i0_dp.store;
-     873        96198 :          lsu_p.by                           =  i0_dp.by   ;
-     874        96198 :          lsu_p.half                         =  i0_dp.half ;
-     875        96198 :          lsu_p.word                         =  i0_dp.word ;
-     876        96198 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871        49950 :          lsu_p.load                         =  i0_dp.load ;
+     872        49950 :          lsu_p.store                        =  i0_dp.store;
+     873        49950 :          lsu_p.by                           =  i0_dp.by   ;
+     874        49950 :          lsu_p.half                         =  i0_dp.half ;
+     875        49950 :          lsu_p.word                         =  i0_dp.word ;
+     876        49950 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878        96198 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879        96198 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880        96198 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878        49950 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879        49950 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880        49950 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882        96198 :          lsu_p.unsign  =  i0_dp.unsign;
+     882        49950 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1380,7 +1380,7 @@
     1276            2 :       r_t_in.i0trigger[3:0]              = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
     1277            2 :       r_t_in.pmu_lsu_misaligned          = lsu_pmu_misaligned_r;   // only valid if a load/store is valid in DC3 stage
     1278              : 
-    1279           32 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
+    1279           17 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
     1280              : 
     1281              :    end
     1282              : 
@@ -1614,11 +1614,11 @@
     1510              : module el2_dec_dec_ctl
     1511              :   import el2_pkg::*;
     1512              : (
-    1513          540 :     input logic [31:0] inst,
+    1513           16 :     input logic [31:0] inst,
     1514            0 :     output el2_dec_pkt_t out
     1515              : );
     1516              : 
-    1517          540 :   logic [31:0] i;
+    1517           16 :   logic [31:0] i;
     1518              : 
     1519              :   assign i[31:0] = inst[31:0];
     1520              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_gpr_ctl.sv.html
index dd610776766..eabae928073 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_gpr_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        72.2%
+    
+        61.1%
     
     
-        13
+        11
     
     
         18
@@ -122,25 +122,25 @@
       18              : #(
       19              :    `include "el2_param.vh"
       20              :  )  (
-      21         7684 :     input logic [4:0]  raddr0,       // logical read addresses
-      22         7564 :     input logic [4:0]  raddr1,
+      21           16 :     input logic [4:0]  raddr0,       // logical read addresses
+      22           40 :     input logic [4:0]  raddr1,
       23              : 
-      24        13152 :     input logic        wen0,         // write enable
-      25         8272 :     input logic [4:0]  waddr0,       // write address
+      24          372 :     input logic        wen0,         // write enable
+      25          256 :     input logic [4:0]  waddr0,       // write address
       26           12 :     input logic [31:0] wd0,          // write data
       27              : 
-      28         4032 :     input logic        wen1,         // write enable
-      29          532 :     input logic [4:0]  waddr1,       // write address
-      30           16 :     input logic [31:0] wd1,          // write data
+      28          268 :     input logic        wen1,         // write enable
+      29            0 :     input logic [4:0]  waddr1,       // write address
+      30            0 :     input logic [31:0] wd1,          // write data
       31              : 
-      32            0 :     input logic        wen2,         // write enable
+      32            0 :     input logic        wen2,         // write enable
       33            0 :     input logic [4:0]  waddr2,       // write address
       34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36       404408 :     input logic        clk,
+      36        15288 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
-      39           12 :     output logic [31:0] rd0,         // read data
+      39            8 :     output logic [31:0] rd0,         // read data
       40            4 :     output logic [31:0] rd1,
       41              : 
       42            0 :     input  logic        scan_mode
@@ -149,7 +149,7 @@
       45              :    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
       46              :    logic [31:1] [31:0] gpr_in;
       47            0 :    logic [31:1] w0v,w1v,w2v;
-      48           56 :    logic [31:1] gpr_wr_en;
+      48            4 :    logic [31:1] gpr_wr_en;
       49              : 
       50              :    // GPR Write Enables
       51              :    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_ib_ctl.sv.html
index a99a09f2fc0..90328656278 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,36 +129,36 @@
       25            0 :    input logic [1:0]           dbg_cmd_type,                       // dbg type
       26            0 :    input logic [31:0]          dbg_cmd_addr,                       // expand to 31:0
       27              : 
-      28          124 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
-      29          544 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30         8682 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      28           20 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
+      29           20 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
+      30           30 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34        13532 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
-      35        25052 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
+      34          350 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      35          754 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
       38              : 
       39            0 :    input logic   ifu_i0_icaf_second,                               // i0 has access fault on second 2B of 4B inst
       40            0 :    input logic   ifu_i0_dbecc,                                     // i0 double-bit error
-      41          540 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
+      41           16 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
       42           10 :    input logic [31:1]  ifu_i0_pc,                                  // i0 pc from the aligner
       43              : 
       44              : 
-      45        25052 :    output logic dec_ib0_valid_d,                                   // ib0 valid
+      45          754 :    output logic dec_ib0_valid_d,                                   // ib0 valid
       46            0 :    output logic dec_debug_valid_d,                                 // Debug read or write at D-stage
       47              : 
       48              : 
-      49          540 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
+      49           16 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
       50              : 
       51           10 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53        13532 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53          350 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
-      55          124 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
-      56          544 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57         8682 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      55           20 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
+      56           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      57           30 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
@@ -185,7 +185,7 @@
       81            0 :    logic         debug_read_csr;
       82            0 :    logic         debug_write_csr;
       83              : 
-      84          520 :    logic [34:0]  ifu_i0_pcdata, pc0;
+      84           12 :    logic [34:0]  ifu_i0_pcdata, pc0;
       85              : 
       86              :    assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
       87              :                                   ifu_i0_pc[31:1], ifu_i0_pc4 };
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_pmp_ctl.sv.html
index f9d5e67546b..3eaed4929cd 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        42.4%
+    
+        43.8%
     
     
         14
     
     
-        33
+        32
     
 
             
@@ -133,14 +133,14 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32       404408 :    input logic clk,
-      33       404408 :    input logic free_l2clk,
-      34       404408 :    input logic csr_wr_clk,
+      32        15288 :    input logic clk,
+      33        15288 :    input logic free_l2clk,
+      34        15288 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
-      36           48 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
-      37            4 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
+      36           12 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+      37            8 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
       38            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
-      39            4 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
+      39            8 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
       40              : 
       41            4 :    input logic csr_pmpcfg,
       42            4 :    input logic csr_pmpaddr0,
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52            0 :    input el2_mseccfg_pkt_t mseccfg,
+      52              :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_tlu_ctl.sv.html
index 7395fc038d5..db1223c2325 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        30.9%
+    
+        24.2%
     
     
-        116
+        87
     
     
-        375
+        360
     
 
             
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32       404408 :    input logic clk,
-      33       404408 :    input logic free_clk,
-      34       404408 :    input logic free_l2clk,
+      32        15288 :    input logic clk,
+      33        15288 :    input logic free_clk,
+      34        15288 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
@@ -149,29 +149,29 @@
       45              : 
       46              : 
       47              :    // perf counter inputs
-      48        25728 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
-      49          950 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
-      50        26024 :    input logic       ifu_pmu_ic_miss, // icache miss
+      48          998 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
+      49           42 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
+      50          996 :    input logic       ifu_pmu_ic_miss, // icache miss
       51            0 :    input logic       ifu_pmu_ic_hit, // icache hit
       52            0 :    input logic       ifu_pmu_bus_error, // Instruction side bus error
       53            0 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
-      54        26024 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
-      55        25728 :    input logic       dec_pmu_instr_decoded, // decoded instructions
-      56          832 :    input logic       dec_pmu_decode_stall, // decode stall
+      54          996 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
+      55          998 :    input logic       dec_pmu_instr_decoded, // decoded instructions
+      56          244 :    input logic       dec_pmu_decode_stall, // decode stall
       57            0 :    input logic       dec_pmu_presync_stall, // decode stall due to presync'd inst
-      58           68 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
-      59            8 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
-      60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
+      58            0 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
+      59            0 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
+      60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
-      62         1032 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63         4000 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64         5370 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
-      65         8288 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
-      66           12 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
-      67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
-      68           32 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
-      69         3944 :    input logic       lsu_pmu_load_external_m, // D side bus load
-      70         3968 :    input logic       lsu_pmu_store_external_m, // D side bus store
+      62          104 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
+      63          276 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64          298 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      65          544 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
+      66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
+      67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
+      68            0 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
+      69          268 :    input logic       lsu_pmu_load_external_m, // D side bus load
+      70          272 :    input logic       lsu_pmu_store_external_m, // D side bus store
       71            0 :    input logic       dma_pmu_dccm_read,          // DMA DCCM read
       72            0 :    input logic       dma_pmu_dccm_write,         // DMA DCCM write
       73            0 :    input logic       dma_pmu_any_read,           // DMA read
@@ -188,43 +188,43 @@
       84            0 :    input logic dec_pause_state, // Pause counter not zero
       85            0 :    input logic         lsu_imprecise_error_store_any,      // store bus error
       86            0 :    input logic         lsu_imprecise_error_load_any,      // store bus error
-      87            2 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
+      87            0 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
       88              : 
-      89           48 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
-      90          196 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
-      91            4 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
+      89           12 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
+      90           16 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
+      91            8 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
       92              : 
-      93           48 :    input logic        dec_csr_wen_r,      // csr write enable at wb
-      94         5796 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
-      95            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+      93           12 :    input logic        dec_csr_wen_r,      // csr write enable at wb
+      94           36 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
+      95            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
       96            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       97              : 
-      98            4 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
+      98            0 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
       99              : 
-     100        25728 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
+     100          996 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
      101              : 
      102            2 :    input logic [31:1] exu_npc_r, // for NPC tracking
      103              : 
      104            2 :    input logic [31:1] dec_tlu_i0_pc_r, // for PC/NPC tracking
      105              : 
-     106           12 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
+     106            0 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
      107              : 
-     108            0 :    input logic [31:0] dec_illegal_inst, // For mtval
-     109        25728 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
+     108            0 :    input logic [31:0] dec_illegal_inst, // For mtval
+     109          998 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112         3756 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112          184 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115         5692 :    input logic        exu_i0_br_valid_r, // valid
-     116         1032 :    input logic        exu_i0_br_mp_r, // mispredict
-     117         7436 :    input logic        exu_i0_br_middle_r, // middle of bank
+     115          252 :    input logic        exu_i0_br_valid_r, // valid
+     116          104 :    input logic        exu_i0_br_mp_r, // mispredict
+     117          312 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
      119              :    // branch info from pipe1 for errors or counter updates
      120              : 
-     121         2712 :    input logic             exu_i0_br_way_r, // way hit or repl
+     121           12 :    input logic             exu_i0_br_way_r, // way hit or repl
      122              : 
-     123         7392 :    output logic dec_tlu_core_empty,  // core is empty
+     123          144 :    output logic dec_tlu_core_empty,  // core is empty
      124              :    // Debug start
      125            0 :    output logic dec_dbg_cmd_done, // abstract command done
      126            0 :    output logic dec_dbg_cmd_fail, // abstract command failed
@@ -243,8 +243,8 @@
      139              : 
      140            0 :    input  logic dbg_halt_req, // DM requests a halt
      141            0 :    input  logic dbg_resume_req, // DM requests a resume
-     142        26024 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
-     143         6290 :    input  logic lsu_idle_any, // lsu is idle
+     142          996 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
+     143          280 :    input  logic lsu_idle_any, // lsu is idle
      144            0 :    input  logic dec_div_active, // oop div is active
      145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
      146              : 
@@ -284,24 +284,24 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183            4 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184          196 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183            0 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
-     186         2712 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
+     186           12 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
      188            0 :    output logic dec_tlu_i0_kill_writeb_wb,    // I0 is flushed, don't writeback any results to arch state
-     189           64 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
-     190        25728 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
+     189            4 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
+     190          996 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
      191              : 
      192            0 :    output logic dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
-     193           64 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
-     194           12 :    output logic [31:1] dec_tlu_flush_path_r, // flush pc
-     195            0 :    output logic dec_tlu_fence_i_r,           // flush is a fence_i rfnpc, flush icache
+     193            4 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
+     194            0 :    output logic [31:1] dec_tlu_flush_path_r, // flush pc
+     195            0 :    output logic dec_tlu_fence_i_r,           // flush is a fence_i rfnpc, flush icache
      196            0 :    output logic dec_tlu_wr_pause_r,           // CSR write to pause reg is at R.
      197            0 :    output logic dec_tlu_flush_pause_r,        // Flush is due to pause
      198              : 
      199            0 :    output logic dec_tlu_presync_d,            // CSR read needs to be presync'd
-     200          128 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
+     200            4 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
      201              : 
      202              : 
      203            0 :    output logic [31:0] dec_tlu_mrac_ff,        // CSR for memory region control
@@ -313,14 +313,14 @@
      209            0 :    output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc
      210            0 :    output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
      211              : 
-     212           28 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
-     213        25716 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
+     212            0 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
+     213          996 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
      214            0 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
      215            0 :    output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
-     216            4 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
+     216            0 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
      217              : 
      218              :    // feature disable from mfdc
-     219            0 :    output logic  dec_tlu_external_ldfwd_disable, // disable external load forwarding
+     219            0 :    output logic  dec_tlu_external_ldfwd_disable, // disable external load forwarding
      220            0 :    output logic  dec_tlu_sideeffect_posted_disable,  // disable posted stores to side-effect address
      221            0 :    output logic  dec_tlu_core_ecc_disable, // disable core ECC
      222            0 :    output logic  dec_tlu_bpred_disable,           // disable branch prediction
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243           18 :    output logic  priv_mode,
-     244           18 :    output logic  priv_mode_eff,
-     245           18 :    output logic  priv_mode_ns,
+     243              :    output logic  priv_mode,
+     244              :    output logic  priv_mode_eff,
+     245              :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248            0 :    output logic [2:0] mseccfg,
+     248              :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275            0 :    logic wr_mcounteren_r;
-     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277            0 :    logic wr_mseccfg_r;
-     278            8 :    logic [2:0] mseccfg_ns;
+     275              :    logic wr_mcounteren_r;
+     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277              :    logic wr_mseccfg_r;
+     278              :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,23 +389,23 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286            0 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
      294            0 :    logic        force_halt;
      295            0 :    logic [5:0]  mfdht, mfdht_ns;
-     296           18 :    logic mstatus_mie_ns;
-     297            0 :    logic [30:0] mtvec_ns, mtvec;
+     296            0 :    logic mstatus_mie_ns;
+     297            0 :    logic [30:0] mtvec_ns, mtvec;
      298            0 :    logic [15:2] dcsr_ns, dcsr;
      299            0 :    logic [5:0] mip_ns, mip;
      300            0 :    logic [5:0] mie_ns, mie;
-     301          186 :    logic [31:0] mcyclel_ns, mcyclel;
+     301            6 :    logic [31:0] mcyclel_ns, mcyclel;
      302            0 :    logic [31:0] mcycleh_ns, mcycleh;
-     303           30 :    logic [31:0] minstretl_ns, minstretl;
-     304            0 :    logic [31:0] minstreth_ns, minstreth;
+     303            0 :    logic [31:0] minstretl_ns, minstretl;
+     304            0 :    logic [31:0] minstreth_ns, minstreth;
      305            0 :    logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;
      306            0 :    logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;
      307            0 :    logic [31:0] mscratch;
@@ -420,16 +420,16 @@
      316            0 :    logic [3:0] meipt_ns, meipt;
      317            0 :    logic [31:0] mdseac;
      318            0 :    logic mdseac_locked_ns, mdseac_locked_f, mdseac_en, nmi_lsu_detected;
-     319            2 :    logic [31:1] mepc_ns, mepc;
-     320            0 :    logic [31:1] dpc_ns, dpc;
+     319            0 :    logic [31:1] mepc_ns, mepc;
+     320            0 :    logic [31:1] dpc_ns, dpc;
      321            0 :    logic [31:0] mcause_ns, mcause;
      322            0 :    logic [3:0] mscause_ns, mscause, mscause_type;
-     323            4 :    logic [31:0] mtval_ns, mtval;
-     324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
-     325           64 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
-     326            2 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
-     327        25716 :    logic i0_valid_wb;
-     328        25728 :    logic tlu_i0_commit_cmt;
+     323            0 :    logic [31:0] mtval_ns, mtval;
+     324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
+     325            4 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
+     326            0 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
+     327          996 :    logic i0_valid_wb;
+     328          996 :    logic tlu_i0_commit_cmt;
      329            0 :    logic [31:1] vectored_path, interrupt_path;
      330            0 :    logic [16:0] dicawics_ns, dicawics;
      331            0 :    logic        wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
@@ -441,25 +441,25 @@
      337            0 :                 ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r;
      338            0 :    logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready,
      339            0 :          take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible;
-     340           28 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
-     341           28 :    logic synchronous_flush_r;
-     342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
-     343          748 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
-     344          186 :    logic [31:0] mcyclel_inc;
+     340            0 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
+     341            0 :    logic synchronous_flush_r;
+     342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
+     343           28 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
+     344            6 :    logic [31:0] mcyclel_inc;
      345            0 :    logic [31:0] mcycleh_inc;
      346              : 
-     347          120 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
+     347            4 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
      348              : 
-     349           30 :    logic [31:0] minstretl_inc, minstretl_read;
-     350            0 :    logic [31:0] minstreth_inc, minstreth_read;
+     349            0 :    logic [31:0] minstretl_inc, minstretl_read;
+     350            0 :    logic [31:0] minstreth_inc, minstreth_read;
      351            2 :    logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;
-     352          196 :    logic valid_csr;
+     352           16 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355         5116 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355          184 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
-     357           60 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
-     358        25728 :    logic i0_trigger_eval_r;
+     357            0 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
+     358          996 :    logic i0_trigger_eval_r;
      359              : 
      360            0 :    logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
      361            4 :    logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
@@ -506,19 +506,19 @@
      402            8 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405       404408 :    logic csr_wr_clk;
+     405        15288 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
-     407         3944 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
+     407          268 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
      409            0 :    logic lsu_single_ecc_error_r;
      410            0 :    logic [31:0] lsu_error_pkt_addr_r;
      411            2 :    logic mcyclel_cout_in;
-     412        25700 :    logic i0_valid_no_ebreak_ecall_r;
-     413        25700 :    logic minstret_enable_f;
-     414           64 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
-     415        25728 :    logic pc0_valid_r;
+     412          996 :    logic i0_valid_no_ebreak_ecall_r;
+     413          996 :    logic minstret_enable_f;
+     414            4 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
+     415          996 :    logic pc0_valid_r;
      416            4 :    logic [15:0] mfdc_int, mfdc_ns;
-     417           12 :    logic [31:0] mrac_in;
+     417            4 :    logic [31:0] mrac_in;
      418            4 :    logic [31:27] csr_sat;
      419            0 :    logic [8:6] dcsr_cause;
      420            0 :    logic enter_debug_halt_req_le, dcsr_cause_upgradeable;
@@ -535,23 +535,23 @@
      431            0 :    logic            mhpmc5h_wr_en0, mhpmc5h_wr_en;
      432            0 :    logic            mhpmc6h_wr_en0, mhpmc6h_wr_en;
      433            0 :    logic [63:0]     mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;
-     434           44 :    logic perfcnt_halted_d1, zero_event_r;
+     434            8 :    logic perfcnt_halted_d1, zero_event_r;
      435            0 :    logic [3:0] perfcnt_during_sleep;
      436            0 :    logic [9:0] event_r;
      437              : 
-     438         7240 :    el2_inst_pkt_t pmu_i0_itype_qual;
+     438          296 :    el2_inst_pkt_t pmu_i0_itype_qual;
      439              : 
-     440           48 :    logic dec_csr_wen_r_mod;
+     440           12 :    logic dec_csr_wen_r_mod;
      441              : 
      442            4 :    logic flush_clkvalid;
      443            0 :    logic sel_fir_addr;
      444            0 :    logic wr_mie_r;
-     445            8 :    logic mtval_capture_pc_r;
-     446            0 :    logic mtval_capture_pc_plus2_r;
-     447           12 :    logic mtval_capture_inst_r;
-     448            0 :    logic mtval_capture_lsu_r;
-     449            8 :    logic mtval_clear_r;
-     450            0 :    logic wr_mcgc_r;
+     445            0 :    logic mtval_capture_pc_r;
+     446            0 :    logic mtval_capture_pc_plus2_r;
+     447            0 :    logic mtval_capture_inst_r;
+     448            0 :    logic mtval_capture_lsu_r;
+     449            0 :    logic mtval_clear_r;
+     450            0 :    logic wr_mcgc_r;
      451            0 :    logic wr_mfdc_r;
      452            0 :    logic wr_mdeau_r;
      453            0 :    logic trigger_hit_for_dscr_cause_r_d1;
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483            0 :    logic  csr_acc_r;    // CSR access error
-     484           50 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         6314 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483              :    logic  csr_acc_r;    // CSR access error
+     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994            0 :    logic csr_wr_acc_r;
-     995            0 :    logic csr_rd_acc_r;
+     994              :    logic csr_wr_acc_r;
+     995              :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568            0 :    logic  pmp_any_region_locked;
+    1568              :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
@@ -2828,12 +2828,12 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727       404408 :    input logic clk,
-    2728       404408 :    input logic free_l2clk,
-    2729       404408 :    input logic csr_wr_clk,
+    2727        15288 :    input logic clk,
+    2728        15288 :    input logic free_l2clk,
+    2729        15288 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
-    2731           48 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
-    2732            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+    2731           12 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
+    2732            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
     2733            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
     2734              : 
     2735            0 :    input logic csr_mitctl0,
@@ -2859,12 +2859,12 @@
     2755              :    localparam MITCTL_ENABLE_HALTED      = 1;
     2756              :    localparam MITCTL_ENABLE_PAUSED      = 2;
     2757              : 
-    2758          186 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
+    2758            6 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
     2759            0 :    logic [2:0] mitctl0_ns, mitctl0;
     2760            0 :    logic [3:0] mitctl1_ns, mitctl1;
     2761            0 :    logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
     2762            2 :    logic mitcnt0_inc_ok, mitcnt1_inc_ok;
-    2763          748 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
+    2763           28 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
     2764            0 :  logic mit0_match_ns;
     2765            0 :  logic mit1_match_ns;
     2766            0 :  logic mitctl0_0_b_ns;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_trigger.sv.html
index 362f61498c7..b666512cf26 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dma_ctrl.sv.html
index 0b3dc1d2990..e4eb976d5f8 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29       404408 :    input logic         clk,
-      30       404408 :    input logic         free_clk,
+      29        15288 :    input logic         clk,
+      30        15288 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -173,8 +173,8 @@
       69            0 :    output logic        dma_active,         // DMA is busy
       70            0 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
       71            0 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
-      72         7858 :    input logic         dccm_ready, // dccm ready to accept DMA request
-      73         1238 :    input logic         iccm_ready, // iccm ready to accept DMA request
+      72          542 :    input logic         dccm_ready, // dccm ready to accept DMA request
+      73          108 :    input logic         iccm_ready, // iccm ready to accept DMA request
       74            2 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
       75              : 
       76              :    // PMU signals
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185       404408 :    logic                    dma_buffer_c1_clk;
-     186       404408 :    logic                    dma_free_clk;
+     185        15288 :    logic                    dma_buffer_c1_clk;
+     186        15288 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu.sv.html
index ddf5584d0e1..f41d7c4c972 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        78.0%
+    
+        69.0%
     
     
-        78
+        69
     
     
         100
@@ -124,86 +124,86 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       404408 :    input logic          clk,                                           // Top level clock
+      23        15288 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
-      27        25728 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
-      28        25696 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
+      27          996 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
+      28          992 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
       29            0 :    input logic  [31:0]  dbg_cmd_wrdata,                                // Debug data   to primary I0 RS1
       30            0 :    input el2_alu_pkt_t i0_ap,                                         // DEC alu {valid,predecodes}
       31              : 
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
-      34          424 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35         8682 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
-      36          544 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
+      34           20 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
+      35           30 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      36           20 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
       39            0 :    input logic  [31:0]  lsu_result_m,                                  // Load result M-stage
-      40           16 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
-      41        21740 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
-      42        11480 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
-      43           12 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
+      40            0 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
+      41          680 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
+      42          280 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
+      43            8 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
       44            4 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45         1380 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      45           20 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
       46           12 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
-      47          920 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
-      48        18816 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49         8364 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
-      50          760 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
+      47            8 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
+      48          474 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
+      49          534 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      50           28 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51           10 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
-      52          648 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      52          244 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      54          148 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55            4 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      54            4 :    input logic          dec_csr_ren_d,                                 // CSR read select
+      55            0 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57        18878 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57          712 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
       59            0 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
       61              : 
-      62          506 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
+      62           24 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
       63              : 
-      64           64 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
-      65           12 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
+      64            4 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
+      65            0 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
       66              : 
       67              : 
-      68            0 :    input logic         dec_extint_stall,                               // External stall mux select
+      68            0 :    input logic         dec_extint_stall,                               // External stall mux select
       69            0 :    input logic [31:2]  dec_tlu_meihap,                                 // External stall mux data
       70              : 
       71              : 
-      72          124 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
-      73            8 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
+      72            0 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
+      73            0 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
       74              : 
-      75         1240 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
-      76          220 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
+      75          110 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
+      76           16 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
       77              : 
-      78          688 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
+      78           16 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
       79            2 :    output logic [31:1]  exu_i0_pc_x,                                   // Primary PC  result to DEC
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            2 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83         3756 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83          184 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
-      86          116 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87         5692 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
-      88         1032 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
-      89         7436 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90         1838 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
-      91         2712 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
+      86            4 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
+      87          252 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      88          104 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
+      89          312 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
+      90            6 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      91           12 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
-      93          128 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
-      94          692 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95         1838 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      96          204 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      93            0 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
+      94           64 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
+      95            6 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      96            8 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
-     100         1032 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101         4000 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102         5370 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     100          104 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
+     101          276 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102          298 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105            0 :    output logic [31:0]  exu_div_result,                                // Divide result
@@ -213,50 +213,50 @@
      109              : 
      110              : 
      111              : 
-     112           68 :    logic [31:0]                i0_rs1_bypass_data_d;
-     113            0 :    logic [31:0]                i0_rs2_bypass_data_d;
-     114         2416 :    logic                       i0_rs1_bypass_en_d;
-     115          112 :    logic                       i0_rs2_bypass_en_d;
-     116           12 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
-     117           12 :    logic [31:0]                muldiv_rs1_d;
-     118          506 :    logic [31:1]                pred_correct_npc_r;
-     119         5568 :    logic                       i0_pred_correct_upper_r;
+     112            0 :    logic [31:0]                i0_rs1_bypass_data_d;
+     113            0 :    logic [31:0]                i0_rs2_bypass_data_d;
+     114          488 :    logic                       i0_rs1_bypass_en_d;
+     115            0 :    logic                       i0_rs2_bypass_en_d;
+     116            8 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
+     117            8 :    logic [31:0]                muldiv_rs1_d;
+     118           24 :    logic [31:1]                pred_correct_npc_r;
+     119          192 :    logic                       i0_pred_correct_upper_r;
      120            2 :    logic [31:1]                i0_flush_path_upper_r;
-     121          148 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
-     122        25696 :    logic                       x_ctl_en,  r_ctl_en;
+     121            4 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
+     122          992 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124         1838 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125         1838 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126         4032 :    logic                       i0_taken_d;
-     127         4032 :    logic                       i0_taken_x;
-     128         5692 :    logic                       i0_valid_d;
-     129         5692 :    logic                       i0_valid_x;
-     130         1838 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124            6 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125            6 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126          278 :    logic                       i0_taken_d;
+     127          276 :    logic                       i0_taken_x;
+     128          252 :    logic                       i0_valid_d;
+     129          252 :    logic                       i0_valid_x;
+     130            6 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
-     132            8 :    el2_predict_pkt_t          final_predict_mp;
-     133          424 :    el2_predict_pkt_t          i0_predict_newp_d;
+     132            0 :    el2_predict_pkt_t          final_predict_mp;
+     133           20 :    el2_predict_pkt_t          i0_predict_newp_d;
      134              : 
      135            0 :    logic                       flush_in_d;
-     136          688 :    logic [31:0]                alu_result_x;
+     136           16 :    logic [31:0]                alu_result_x;
      137              : 
      138            0 :    logic                       mul_valid_x;
      139            0 :    logic [31:0]                mul_result_x;
      140              : 
-     141          212 :    el2_predict_pkt_t          i0_pp_r;
+     141           12 :    el2_predict_pkt_t          i0_pp_r;
      142              : 
-     143         1176 :    logic                       i0_flush_upper_d;
+     143          106 :    logic                       i0_flush_upper_d;
      144           10 :    logic [31:1]                i0_flush_path_d;
-     145          424 :    el2_predict_pkt_t          i0_predict_p_d;
-     146         5568 :    logic                       i0_pred_correct_upper_d;
+     145           20 :    el2_predict_pkt_t          i0_predict_p_d;
+     146          192 :    logic                       i0_pred_correct_upper_d;
      147              : 
-     148         1176 :    logic                       i0_flush_upper_x;
+     148          104 :    logic                       i0_flush_upper_x;
      149            2 :    logic [31:1]                i0_flush_path_x;
-     150          212 :    el2_predict_pkt_t          i0_predict_p_x;
-     151         5568 :    logic                       i0_pred_correct_upper_x;
-     152         8364 :    logic                       i0_branch_x;
+     150           12 :    el2_predict_pkt_t          i0_predict_p_x;
+     151          192 :    logic                       i0_pred_correct_upper_x;
+     152          532 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
-     155          440 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
+     155            8 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
      156              : 
      157              : 
      158              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_alu_ctl.sv.html
index ea6d9c16841..4d712dd39a3 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_alu_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        53.4%
+    
+        48.9%
     
     
-        47
+        43
     
     
         88
@@ -124,52 +124,52 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       404408 :    input  logic                  clk,                // Top level clock
+      23        15288 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
-      27         1176 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
-      28           64 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
-      29        25728 :    input  logic                  enable,             // Clock enable
-      30        18816 :    input  logic                  valid_in,           // Valid
+      27          104 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
+      28            4 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
+      29          998 :    input  logic                  enable,             // Clock enable
+      30          474 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
-      32          148 :    input  logic                  csr_ren_in,         // CSR select
-      33            4 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34           12 :    input  logic signed [31:0]    a_in,               // A operand
-      35         1452 :    input  logic        [31:0]    b_in,               // B operand
+      32            4 :    input  logic                  csr_ren_in,         // CSR select
+      33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34            8 :    input  logic signed [31:0]    a_in,               // A operand
+      35           24 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
-      37          424 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
-      38          920 :    input  logic        [12:1]    brimm_in,           // Branch offset
+      37           20 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
+      38            8 :    input  logic        [12:1]    brimm_in,           // Branch offset
       39              : 
       40              : 
-      41          688 :    output logic        [31:0]    result_ff,          // final result
-      42         1176 :    output logic                  flush_upper_out,    // Branch flush
-      43         1240 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
+      41           16 :    output logic        [31:0]    result_ff,          // final result
+      42          106 :    output logic                  flush_upper_out,    // Branch flush
+      43          110 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
       44           10 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            2 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46         5568 :    output logic                  pred_correct_out,   // NPC control
-      47          424 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
+      46          192 :    output logic                  pred_correct_out,   // NPC control
+      47           20 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
       50              : 
-      51           12 :    logic               [31:0]    zba_a_in;
-      52          708 :    logic               [31:0]    aout;
-      53          220 :    logic                         cout,ov,neg;
-      54            4 :    logic               [31:0]    lout;
-      55           12 :    logic               [31:0]    sout;
-      56          832 :    logic                         sel_shift;
-      57        16656 :    logic                         sel_adder;
-      58            4 :    logic                         slt_one;
-      59         4124 :    logic                         actual_taken;
+      51            8 :    logic               [31:0]    zba_a_in;
+      52           20 :    logic               [31:0]    aout;
+      53            4 :    logic                         cout,ov,neg;
+      54            0 :    logic               [31:0]    lout;
+      55            8 :    logic               [31:0]    sout;
+      56            0 :    logic                         sel_shift;
+      57          414 :    logic                         sel_adder;
+      58            0 :    logic                         slt_one;
+      59          286 :    logic                         actual_taken;
       60           10 :    logic               [31:1]    pcout;
-      61         1548 :    logic                         cond_mispredict;
-      62           88 :    logic                         target_mispredict;
-      63        15396 :    logic                         eq, ne, lt, ge;
-      64          788 :    logic                         any_jal;
-      65         6310 :    logic               [1:0]     newhist;
-      66          788 :    logic                         sel_pc;
-      67           12 :    logic               [31:0]    csr_write_data;
-      68          700 :    logic               [31:0]    result;
+      61          286 :    logic                         cond_mispredict;
+      62           12 :    logic                         target_mispredict;
+      63          888 :    logic                         eq, ne, lt, ge;
+      64           28 :    logic                         any_jal;
+      65          450 :    logic               [1:0]     newhist;
+      66           28 :    logic                         sel_pc;
+      67            8 :    logic               [31:0]    csr_write_data;
+      68           20 :    logic               [31:0]    result;
       69              : 
       70              : 
       71              : 
@@ -348,7 +348,7 @@
      244              :                                 ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |
      245              :                                 ( {32{~ap_zba   }} &  a_in[31:0]       );
      246              : 
-     247         7684 :    logic        [31:0]    bm;
+     247          294 :    logic        [31:0]    bm;
      248              : 
      249              :    assign bm[31:0]            = ( ap.sub )  ?  ~b_in[31:0]  :  b_in[31:0];
      250              : 
@@ -383,8 +383,8 @@
      279              : 
      280            0 :    logic        [5:0]     shift_amount;
      281            2 :    logic        [31:0]    shift_mask;
-     282          448 :    logic        [62:0]    shift_extend;
-     283          420 :    logic        [62:0]    shift_long;
+     282           28 :    logic        [62:0]    shift_extend;
+     283           28 :    logic        [62:0]    shift_long;
      284              : 
      285              : 
      286              :    assign shift_amount[5:0]            = ( { 6{ap.sll}}   & (6'd32 - {1'b0,b_in[4:0]}) ) |   // [5] unused
@@ -416,7 +416,7 @@
      312              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CLZ,CTZ      * * * * * * * * * * * * * * * * * *
      313              : 
      314            0 :    logic                  bitmanip_clz_ctz_sel;
-     315           12 :    logic        [31:0]    bitmanip_a_reverse_ff;
+     315            8 :    logic        [31:0]    bitmanip_a_reverse_ff;
      316            0 :    logic        [31:0]    bitmanip_lzd_in;
      317            2 :    logic        [5:0]     bitmanip_dw_lzd_enc;
      318            0 :    logic        [5:0]     bitmanip_clz_ctz_result;
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342      3865536 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343      3865536 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342      2017728 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343      2017728 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
@@ -460,7 +460,7 @@
      356              : 
      357              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CPOP         * * * * * * * * * * * * * * * * * *
      358              : 
-     359            4 :    logic        [5:0]     bitmanip_cpop;
+     359            8 :    logic        [5:0]     bitmanip_cpop;
      360            0 :    logic        [5:0]     bitmanip_cpop_result;
      361              : 
      362              : 
@@ -499,7 +499,7 @@
      395              : 
      396              :    assign bitmanip_minmax_sel          =  ap_min | ap_max;
      397              : 
-     398        15398 :    logic                  bitmanip_minmax_sel_a;
+     398          890 :    logic                  bitmanip_minmax_sel_a;
      399              : 
      400              :    assign bitmanip_minmax_sel_a        =  ge  ^ ap_min;
      401              : 
@@ -557,7 +557,7 @@
      453              : 
      454              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  ZBSET, ZBCLR, ZBINV  * * * * * * * * * * * * * *
      455              : 
-     456           48 :    logic        [31:0]    bitmanip_sb_1hot;
+     456            4 :    logic        [31:0]    bitmanip_sb_1hot;
      457            0 :    logic        [31:0]    bitmanip_sb_data;
      458              : 
      459              :    assign bitmanip_sb_1hot[31:0]       = ( 32'h00000001 << b_in[4:0] );
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_div_ctl.sv.html
index d1c6a23d384..423b7879033 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,13 +124,13 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       404408 :    input logic           clk,                       // Top level clock
+      23        15288 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
       27            0 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
-      28           12 :    input logic  [31:0]   dividend,                  // Numerator
-      29         1452 :    input logic  [31:0]   divisor,                   // Denominator
+      28            8 :    input logic  [31:0]   dividend,                  // Numerator
+      29           24 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
@@ -1414,16 +1414,16 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313       404408 :    input  logic            clk,                       // Top level clock
+    1313        15288 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
     1317            0 :    input  logic            cancel,                    // Flush pipeline
     1318            0 :    input  logic            valid_in,
-    1319         3502 :    input  logic            signed_in,
+    1319          262 :    input  logic            signed_in,
     1320            0 :    input  logic            rem_in,
-    1321           12 :    input  logic [31:0]     dividend_in,
-    1322         1452 :    input  logic [31:0]     divisor_in,
+    1321            8 :    input  logic [31:0]     dividend_in,
+    1322           24 :    input  logic [31:0]     divisor_in,
     1323              : 
     1324            0 :    output logic            valid_out,
     1325            0 :    output logic [31:0]     data_out
@@ -1446,7 +1446,7 @@
     1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
     1344            0 :    logic                   b_enable, b_twos_comp;
-    1345         1452 :    logic        [32:0]     b_in;
+    1345           24 :    logic        [32:0]     b_in;
     1346            0 :    logic        [37:0]     b_ff;
     1347              : 
     1348            0 :    logic        [31:0]     q_in, q_ff;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_mul_ctl.sv.html
index ced98e0132d..fd7d02a2192 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23       404408 :    input logic          clk,              // Top level clock
+      23        15288 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209      3865536 :              if (bcompress_test_bit_d)
+     209      2017728 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236      3865536 :              if (bdecompress_test_bit_d)
+     236      2017728 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu.sv.html
index 6822a08eb97..fc645ee5c59 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        44.2%
+    
+        41.9%
     
     
-        76
+        72
     
     
         172
@@ -129,18 +129,18 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28       404408 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29       404408 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30       404408 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28        15288 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        15288 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        15288 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
-      33        25728 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
+      33          998 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
       34              : 
-      35         1240 :    input logic exu_flush_final, // flush, includes upper and lower
-      36        25728 :    input logic dec_tlu_i0_commit_cmt , // committed i0
+      35          110 :    input logic exu_flush_final, // flush, includes upper and lower
+      36          996 :    input logic dec_tlu_i0_commit_cmt , // committed i0
       37            0 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
       38            0 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
-      39          220 :    input logic [31:1] exu_flush_path_final, // flush fetch address
+      39           16 :    input logic [31:1] exu_flush_path_final, // flush fetch address
       40              : 
       41            0 :    input logic [31:0]  dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
       42            0 :    input logic         dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
@@ -172,10 +172,10 @@
       68            0 :    output logic                            ifu_axi_bready,
       69              : 
       70              :    // AXI Read Channels
-      71        26024 :    output logic                            ifu_axi_arvalid,
-      72        26026 :    input  logic                            ifu_axi_arready,
-      73        17884 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      74         3188 :    output logic [31:0]                     ifu_axi_araddr,
+      71          996 :    output logic                            ifu_axi_arvalid,
+      72          996 :    input  logic                            ifu_axi_arready,
+      73           88 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      74           56 :    output logic [31:0]                     ifu_axi_araddr,
       75            2 :    output logic [3:0]                      ifu_axi_arregion,
       76            0 :    output logic [7:0]                      ifu_axi_arlen,
       77            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -185,10 +185,10 @@
       81            2 :    output logic [2:0]                      ifu_axi_arprot,
       82            0 :    output logic [3:0]                      ifu_axi_arqos,
       83              : 
-      84        52048 :    input  logic                            ifu_axi_rvalid,
+      84         1990 :    input  logic                            ifu_axi_rvalid,
       85            2 :    output logic                            ifu_axi_rready,
-      86         5542 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-      87         2300 :    input  logic [63:0]                     ifu_axi_rdata,
+      86           48 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+      87           24 :    input  logic [63:0]                     ifu_axi_rdata,
       88            0 :    input  logic [1:0]                      ifu_axi_rresp,
       89              : 
       90            2 :    input  logic                      ifu_bus_clk_en,
@@ -206,10 +206,10 @@
      102            0 :    output logic                      iccm_dma_rvalid,
      103            0 :    output logic [63:0]               iccm_dma_rdata,
      104            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     105         1238 :    output logic                      iccm_ready,
+     105          108 :    output logic                      iccm_ready,
      106              : 
-     107        25728 :    output logic       ifu_pmu_instr_aligned,
-     108          950 :    output logic       ifu_pmu_fetch_stall,
+     107          998 :    output logic       ifu_pmu_instr_aligned,
+     108           42 :    output logic       ifu_pmu_fetch_stall,
      109            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
      110              : 
      111              : //   I$ & ITAG Ports
@@ -217,8 +217,8 @@
      113            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      114            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      115              : 
-     116         1164 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     117         5364 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     116            6 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     117           62 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      118            0 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      119            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
      120            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
@@ -227,8 +227,8 @@
      123              : 
      124            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
      125            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     126         5364 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     127        20614 :    output logic                      ic_sel_premux_data, // Select the premux data.
+     126           62 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     127          734 :    output logic                      ic_sel_premux_data, // Select the premux data.
      128              : 
      129            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      130            0 :    output logic                      ic_debug_rd_en,     // Icache debug rd
@@ -244,7 +244,7 @@
      140              : 
      141              : 
      142              :    // ICCM ports
-     143          152 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
+     143            8 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
      144            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
      145            0 :    output logic                      iccm_rden,          // ICCM read enable.
      146            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
@@ -259,46 +259,46 @@
      155            0 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
      156              : 
      157              : // Perf counter sigs
-     158        26024 :    output logic       ifu_pmu_ic_miss, // ic miss
+     158          996 :    output logic       ifu_pmu_ic_miss, // ic miss
      159            0 :    output logic       ifu_pmu_ic_hit, // ic hit
      160            0 :    output logic       ifu_pmu_bus_error, // iside bus error
      161            0 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
-     162        26024 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
+     162          996 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
      163              : 
      164              : 
      165            0 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
      166            0 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
      167              : 
-     168        25052 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
+     168          754 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
      169            0 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
      170            0 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
-     172          540 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
+     172           16 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173           10 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174        13532 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174          350 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
-     176        26024 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
+     176          996 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
-     178          124 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
-     179          544 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180         8682 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     178           20 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
+     179           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
+     180           30 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
-     184          128 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
-     185          692 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186         1838 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-     187          204 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+     184            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+     185           64 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
+     186            6 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     187            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
-     190         2712 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191         1838 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-     192          116 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+     190           12 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
+     191            6 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     192            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
-     195           64 :    input dec_tlu_flush_lower_wb,
+     195            4 :    input dec_tlu_flush_lower_wb,
      196              : 
-     197         3180 :    output logic [15:0] ifu_i0_cinst,
+     197          206 :    output logic [15:0] ifu_i0_cinst,
      198              : 
      199            2 :     output logic [31:1] ifu_pmp_addr,
      200            0 :     input  logic        ifu_pmp_error,
@@ -315,12 +315,12 @@
      211              :    localparam TAGWIDTH = 2 ;
      212              :    localparam IDWIDTH  = 2 ;
      213              : 
-     214         1564 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
-     215            2 :    logic [31:1]            ifc_fetch_addr_f;
+     214            0 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
+     215            2 :    logic [31:1]            ifc_fetch_addr_f;
      216            2 :    logic [31:1]            ifc_fetch_addr_bf;
      217              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
      218              : 
-     219        23690 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
+     219          932 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
      220            2 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
      221              : 
      222            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
@@ -329,33 +329,33 @@
      225              :    assign ifu_ic_error_start = ic_error_start;
      226              : 
      227              : 
-     228        10056 :    logic        ic_write_stall;
+     228          392 :    logic        ic_write_stall;
      229            0 :    logic        ic_dma_active;
-     230         1242 :    logic        ifc_dma_access_ok;
+     230          112 :    logic        ifc_dma_access_ok;
      231            0 :    logic [1:0]  ic_access_fault_f;
      232            0 :    logic [1:0]  ic_access_fault_type_f;
-     233        26036 :    logic        ifu_ic_mb_empty;
+     233          996 :    logic        ifu_ic_mb_empty;
      234              : 
-     235        25918 :    logic ic_hit_f;
+     235          936 :    logic ic_hit_f;
      236              : 
-     237         2300 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238         4160 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
-     239          212 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240         1982 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
-     241         3952 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
-     242         4140 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243         2320 :    logic [11:0] ifu_bp_poffset_f; // predicted target
-     244           48 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
-     245         1656 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
-     246         3172 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247         1838 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     237            8 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
+     238          184 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     239          184 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
+     240            6 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     241            4 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
+     242            8 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
+     243          244 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     244            0 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
+     245            0 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
+     246           12 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
+     247            6 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
-     251        23690 :    logic [1:0]   ic_fetch_val_f;
-     252         5364 :    logic [31:0] ic_data_f;
-     253         5364 :    logic [31:0] ifu_fetch_data_f;
-     254        12646 :    logic ifc_fetch_req_f;
+     251          932 :    logic [1:0]   ic_fetch_val_f;
+     252           62 :    logic [31:0] ic_data_f;
+     253           62 :    logic [31:0] ifu_fetch_data_f;
+     254          394 :    logic ifc_fetch_req_f;
      255            0 :    logic ifc_fetch_req_f_raw;
      256            0 :    logic iccm_dma_rd_ecc_double_err;
      257            0 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
@@ -369,7 +369,7 @@
      265              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
      266              : 
      267            2 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
-     268        12646 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
+     268          394 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
      269            2 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
      270            0 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
      271            0 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_aln_ctl.sv.html
index 0602e2bba32..696d8967439 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_aln_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        76.0%
+    
+        64.0%
     
     
-        95
+        80
     
     
         125
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30       404408 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31       404408 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        15288 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        15288 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -141,118 +141,118 @@
       37            0 :    input logic [1:0]                              ic_access_fault_f,        // Instruction access fault for the current fetch.
       38            0 :    input logic [1:0]                              ic_access_fault_type_f,   // Instruction access fault types
       39              : 
-      40         1240 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
+      40          110 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
       41              : 
-      42        25728 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
+      42          998 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
       43              : 
-      44         5364 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
+      44           62 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
       45              : 
-      46        23690 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
+      46          932 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
       47            2 :    input logic [31:1]                             ifu_fetch_pc,             // starting pc of fetch
       48              : 
       49              : 
       50              : 
-      51        25052 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
+      51          754 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
       52            0 :    output logic                                   ifu_i0_icaf,              // Instruction 0 has access fault
       53            0 :    output logic [1:0]                             ifu_i0_icaf_type,         // Instruction 0 access fault type
       54            0 :    output logic                                   ifu_i0_icaf_second,       // Instruction 0 has access fault on second 2B of 4B inst
       55              : 
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
-      57          540 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
+      57           16 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58           10 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59        13532 :    output logic                                   ifu_i0_pc4,
+      59          350 :    output logic                                   ifu_i0_pc4,
       60              : 
-      61        19748 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62         1564 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      61          800 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
+      62            0 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65         1838 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
-      66          212 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67         2320 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      65            6 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      66          184 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
+      67          244 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
-      70         4140 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
-      71         3952 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
-      72         1656 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
-      73         2300 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
-      74         3172 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
-      75           48 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
+      70            8 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
+      71            4 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
+      72            0 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
+      73            8 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
+      74           12 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
+      75            0 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
       76              : 
       77              : 
-      78          124 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
-      79          544 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80         8682 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      78           20 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
+      79           20 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
+      80           30 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
       84              : 
-      85        25728 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
+      85          998 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
       86              : 
-      87         3180 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
+      87          206 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
       88              :    );
       89              : 
       90              : 
       91              : 
-      92        25918 :    logic                                          ifvalid;
+      92          936 :    logic                                          ifvalid;
       93            0 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
       94            0 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
       95              : 
       96            0 :    logic [1:0]                                    f2val_in, f2val;
-      97         7356 :    logic [1:0]                                    f1val_in, f1val;
-      98        16800 :    logic [1:0]                                    f0val_in, f0val;
-      99          116 :    logic [1:0]                                    sf1val, sf0val;
+      97          706 :    logic [1:0]                                    f1val_in, f1val;
+      98          226 :    logic [1:0]                                    f0val_in, f0val;
+      99            0 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
-     101         3180 :    logic [31:0]                                   aligndata;
-     102        13532 :    logic                                          first4B, first2B;
+     101          200 :    logic [31:0]                                   aligndata;
+     102          350 :    logic                                          first4B, first2B;
      103              : 
-     104          536 :    logic [31:0]                                   uncompress0;
-     105        25728 :    logic                                          i0_shift;
-     106         9248 :    logic                                          shift_2B, shift_4B;
-     107         8504 :    logic                                          f1_shift_2B;
-     108         7360 :    logic                                          f2_valid, sf1_valid, sf0_valid;
+     104            4 :    logic [31:0]                                   uncompress0;
+     105          998 :    logic                                          i0_shift;
+     106          412 :    logic                                          shift_2B, shift_4B;
+     107          526 :    logic                                          f1_shift_2B;
+     108          706 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
-     110         3180 :    logic [31:0]                                   ifirst;
-     111        16892 :    logic [1:0]                                    alignval;
-     112         1636 :    logic [31:1]                                   firstpc, secondpc;
+     110          200 :    logic [31:0]                                   ifirst;
+     111          226 :    logic [1:0]                                    alignval;
+     112           42 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114         2260 :    logic [11:0]                                   f1poffset;
-     115         1934 :    logic [11:0]                                   f0poffset;
-     116         2910 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117         6670 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
-     118         3262 :    logic [1:0]                                    f1hist1;
-     119         2966 :    logic [1:0]                                    f0hist1;
-     120         3054 :    logic [1:0]                                    f1hist0;
-     121         4152 :    logic [1:0]                                    f0hist0;
+     114          252 :    logic [11:0]                                   f1poffset;
+     115          252 :    logic [11:0]                                   f0poffset;
+     116           18 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117            6 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     118          364 :    logic [1:0]                                    f1hist1;
+     119           12 :    logic [1:0]                                    f0hist1;
+     120          176 :    logic [1:0]                                    f1hist0;
+     121            0 :    logic [1:0]                                    f0hist0;
      122              : 
-     123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
+     123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
      124              : 
      125            0 :    logic [1:0]                                    f1ictype;
      126            0 :    logic [1:0]                                    f0ictype;
      127              : 
-     128         1548 :    logic [1:0]                                    f1pc4;
-     129         3026 :    logic [1:0]                                    f0pc4;
+     128            0 :    logic [1:0]                                    f1pc4;
+     129            0 :    logic [1:0]                                    f0pc4;
      130              : 
-     131            0 :    logic [1:0]                                    f1ret;
-     132           24 :    logic [1:0]                                    f0ret;
-     133         1496 :    logic [1:0]                                    f1way;
-     134          692 :    logic [1:0]                                    f0way;
+     131            0 :    logic [1:0]                                    f1ret;
+     132            0 :    logic [1:0]                                    f0ret;
+     133            4 :    logic [1:0]                                    f1way;
+     134            4 :    logic [1:0]                                    f0way;
      135              : 
-     136         2404 :    logic [1:0]                                    f1brend;
-     137         1892 :    logic [1:0]                                    f0brend;
+     136          244 :    logic [1:0]                                    f1brend;
+     137            0 :    logic [1:0]                                    f0brend;
      138              : 
-     139         1716 :    logic [1:0]                                    alignbrend;
-     140         3976 :    logic [1:0]                                    alignpc4;
+     139          244 :    logic [1:0]                                    alignbrend;
+     140            0 :    logic [1:0]                                    alignpc4;
      141              : 
-     142           48 :    logic [1:0]                                    alignret;
-     143         2996 :    logic [1:0]                                    alignway;
-     144         5000 :    logic [1:0]                                    alignhist1;
-     145         3576 :    logic [1:0]                                    alignhist0;
-     146         7616 :    logic [1:1]                                    alignfromf1;
-     147         4068 :    logic                                          i0_ends_f1;
+     142            0 :    logic [1:0]                                    alignret;
+     143           16 :    logic [1:0]                                    alignway;
+     144          208 :    logic [1:0]                                    alignhist1;
+     145          180 :    logic [1:0]                                    alignhist0;
+     146          298 :    logic [1:1]                                    alignfromf1;
+     147          270 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
-     150          416 :    logic [31:1]                                   f1prett;
-     151          220 :    logic [31:1]                                   f0prett;
+     150          196 :    logic [31:1]                                   f1prett;
+     151          188 :    logic [31:1]                                   f0prett;
      152            0 :    logic [1:0]                                    f1dbecc;
      153            0 :    logic [1:0]                                    f0dbecc;
      154            0 :    logic [1:0]                                    f1icaf;
@@ -260,47 +260,47 @@
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159         3976 :    logic                                          i0_brp_pc4;
+     159            0 :    logic                                          i0_brp_pc4;
      160              : 
-     161          520 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
+     161           12 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165         8652 :    logic [1:0]                                    wrptr, wrptr_in;
-     166         7760 :    logic [1:0]                                    rdptr, rdptr_in;
-     167         8288 :    logic [2:0]                                    qwen;
-     168          818 :    logic [31:0]                                   q2,q1,q0;
-     169         5432 :    logic                                          q2off_in, q2off;
-     170         5252 :    logic                                          q1off_in, q1off;
-     171         5720 :    logic                                          q0off_in, q0off;
-     172        16264 :    logic                                          f0_shift_2B;
+     165          308 :    logic [1:0]                                    wrptr, wrptr_in;
+     166          302 :    logic [1:0]                                    rdptr, rdptr_in;
+     167          304 :    logic [2:0]                                    qwen;
+     168            2 :    logic [31:0]                                   q2,q1,q0;
+     169          294 :    logic                                          q2off_in, q2off;
+     170          274 :    logic                                          q1off_in, q1off;
+     171          276 :    logic                                          q0off_in, q0off;
+     172          918 :    logic                                          f0_shift_2B;
      173              : 
-     174         3848 :    logic [31:0]                                   q0eff;
-     175         2886 :    logic [31:0]                                   q0final;
-     176        12784 :    logic                                          q0ptr;
-     177        12784 :    logic [1:0]                                    q0sel;
+     174           44 :    logic [31:0]                                   q0eff;
+     175           28 :    logic [31:0]                                   q0final;
+     176          346 :    logic                                          q0ptr;
+     177          346 :    logic [1:0]                                    q0sel;
      178              : 
-     179         3612 :    logic [31:0]                                   q1eff;
-     180         4832 :    logic [15:0]                                   q1final;
-     181         8464 :    logic                                          q1ptr;
-     182         8464 :    logic [1:0]                                    q1sel;
+     179           20 :    logic [31:0]                                   q1eff;
+     180           36 :    logic [15:0]                                   q1final;
+     181          716 :    logic                                          q1ptr;
+     182          716 :    logic [1:0]                                    q1sel;
      183              : 
-     184         7760 :    logic [2:0]                                    qren;
+     184          302 :    logic [2:0]                                    qren;
      185              : 
-     186         1664 :    logic                                          consume_fb1, consume_fb0;
+     186          878 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
      190              :    localparam                                     BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
-     191          662 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
-     192           48 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
-     193           24 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
+     191            0 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
+     192          252 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
+     193            0 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
      194              : 
      195              :    localparam                                     MHI   = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
-     198          700 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199         4272 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     198            0 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
+     199            6 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201            0 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_bp_ctl.sv.html
index abedf979dce..ded39f44f17 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_bp_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        82.7%
+    
+        65.5%
     
     
-        91
+        72
     
     
         110
@@ -135,47 +135,47 @@
       31              :  )
       32              :   (
       33              : 
-      34       404408 :    input logic clk,
+      34        15288 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
-      37        25918 :    input logic ic_hit_f,      // Icache hit, enables F address capture
+      37          936 :    input logic ic_hit_f,      // Icache hit, enables F address capture
       38              : 
       39            2 :    input logic [31:1] ifc_fetch_addr_f, // look up btb address
-      40        12646 :    input logic ifc_fetch_req_f,  // F1 valid
+      40          394 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
-      42         2712 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43         1838 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-      44          116 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+      42           12 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
+      43            6 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      44            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
       47              : 
-      48           64 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
+      48            4 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
       49            0 :    input logic dec_tlu_flush_leak_one_wb, // don't hit for leak one fetches
       50              : 
       51            0 :    input logic dec_tlu_bpred_disable, // disable all branch prediction
       52              : 
-      53          128 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+      53            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
-      55          692 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56         1838 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      57          204 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      55           64 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
+      56            6 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      57            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
-      60         1240 :    input logic exu_flush_final, // all flushes
+      60          110 :    input logic exu_flush_final, // all flushes
       61              : 
-      62         4160 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
-      63          212 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64         1982 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      62          184 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      63          184 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      64            6 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66         1838 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66            6 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
-      68         2300 :    output logic [1:0] ifu_bp_way_f, // way
-      69           48 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
-      70         3952 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
-      71         4140 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
-      72         1656 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
-      73         3172 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74         2320 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      68            8 :    output logic [1:0] ifu_bp_way_f, // way
+      69            0 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
+      70            4 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
+      71            8 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
+      72            0 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
+      73           12 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
+      74          244 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -205,95 +205,95 @@
      101              :    localparam BHT_NO_ADDR_MATCH  = ( pt.BHT_ARRAY_DEPTH <= 16 );
      102              : 
      103              : 
-     104          224 :    logic exu_mp_valid_write;
-     105          912 :    logic exu_mp_ataken;
-     106         1064 :    logic exu_mp_valid; // conditional branch mispredict
-     107          680 :    logic exu_mp_boffset; // branch offsett
-     108          500 :    logic exu_mp_pc4; // branch is a 4B inst
-     109           92 :    logic exu_mp_call; // branch is a call inst
-     110           88 :    logic exu_mp_ret; // branch is a ret inst
-     111           52 :    logic exu_mp_ja; // branch is a jump always
-     112          108 :    logic [1:0] exu_mp_hist; // new history
-     113          472 :    logic [11:0] exu_mp_tgt; // target offset
-     114          204 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115         5116 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116         3756 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
-     117          116 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
+     104           32 :    logic exu_mp_valid_write;
+     105          100 :    logic exu_mp_ataken;
+     106          104 :    logic exu_mp_valid; // conditional branch mispredict
+     107           20 :    logic exu_mp_boffset; // branch offsett
+     108            4 :    logic exu_mp_pc4; // branch is a 4B inst
+     109           12 :    logic exu_mp_call; // branch is a call inst
+     110           12 :    logic exu_mp_ret; // branch is a ret inst
+     111            4 :    logic exu_mp_ja; // branch is a jump always
+     112            4 :    logic [1:0] exu_mp_hist; // new history
+     113            8 :    logic [11:0] exu_mp_tgt; // target offset
+     114            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
+     115          184 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116          184 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     117            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120         1838 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120            6 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122            0 :    logic use_mp_way, use_mp_way_p1;
-     123           24 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
-     124          100 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
+     123            0 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
+     124            0 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127         2320 :    logic [11:0]       btb_rd_tgt_f;
-     128          580 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
-     129         2352 :    logic [1:1]        bp_total_branch_offset_f;
+     127          244 :    logic [11:0]       btb_rd_tgt_f;
+     128            4 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
+     129           10 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
      131            2 :    logic [31:1]       bp_btb_target_adder_f;
      132            2 :    logic [31:1]       bp_rs_call_target_f;
-     133          100 :    logic              rs_push, rs_pop, rs_hold;
-     134          152 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
+     133            4 :    logic              rs_push, rs_pop, rs_hold;
+     134            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
      135            0 :    logic [pt.BTB_BTAG_SIZE-1:0] btb_wr_tag, fetch_rd_tag_f, fetch_rd_tag_p1_f;
-     136          144 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
-     137           16 :    logic               btb_wr_en_way0, btb_wr_en_way1;
+     136            4 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
+     137            0 :    logic               btb_wr_en_way0, btb_wr_en_way1;
      138              : 
      139              : 
-     140         1064 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
-     141          116 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
+     140          104 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
+     141            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
      142            0 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144            0 :    logic  branch_error_bank_conflict_f;
-     145         1838 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145            6 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146            0 :    logic [1:0] num_valids;
      147            0 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
      148            0 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
      149            0 :                         mp_wrindex_dec, mp_wrlru_b0;
-     150         3908 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
-     151         1284 :    logic  tag_match_way0_f, tag_match_way1_f;
-     152         1980 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
-     153          100 :    logic [1:0] bht_valid_f, bht_force_taken_f;
+     150           80 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
+     151            0 :    logic  tag_match_way0_f, tag_match_way1_f;
+     152            4 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
+     153            0 :    logic [1:0] bht_valid_f, bht_force_taken_f;
      154              : 
-     155            0 :    logic leak_one_f, leak_one_f_d1;
+     155            0 :    logic leak_one_f, leak_one_f_d1;
      156              : 
      157              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way0_out ;
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161         1952 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
-     162          228 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
+     161           76 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     162            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
-     164         1916 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
-     165          204 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
+     164          248 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
+     165            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
      166              : 
-     167          580 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
+     167          244 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169         4160 :    logic                                         final_h;
-     170          556 :    logic                                         btb_fg_crossing_f;
-     171          492 :    logic                                         middle_of_bank;
+     169          184 :    logic                                         final_h;
+     170            0 :    logic                                         btb_fg_crossing_f;
+     171           24 :    logic                                         middle_of_bank;
      172              : 
      173              : 
-     174         3912 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
+     174          180 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
      175            0 :    logic                                         branch_error_bank_conflict_p1_f;
-     176         1284 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
+     176            0 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
      177              : 
-     178           24 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
-     179            2 :    logic [31:2] fetch_addr_p1_f;
+     178            0 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
+     179            2 :    logic [31:2] fetch_addr_p1_f;
      180              : 
      181              : 
-     182          128 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
-     183            4 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
+     182           12 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
+     183          248 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185          580 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
-     187         1284 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
+     187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
-     190         3108 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191         3292 :     logic [1:0]                                  bht_bank1_rd_data_f;
-     192         3504 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
+     190           20 :     logic [1:0]                                  bht_bank0_rd_data_f;
+     191            0 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     192          184 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
      195              :    assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict
@@ -348,7 +348,7 @@
      244              :    // set on leak one, hold until next flush without leak one
      245              :    assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
      246              : 
-     247         1240 : logic exu_flush_final_d1;
+     247          108 : logic exu_flush_final_d1;
      248              : 
      249              :  if(!pt.BTB_FULLYA) begin : genblock1
      250              :    assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
@@ -461,8 +461,8 @@
      357              : 
      358              :  end // if (!pt.BTB_FULLYA)
      359              :    // Detect end of cache line and mask as needed
-     360         1336 :    logic eoc_near;
-     361          402 :    logic eoc_mask;
+     360           16 :    logic eoc_near;
+     361            6 :    logic eoc_mask;
      362              :    assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];
      363              :    assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));
      364              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372          580 :    logic [16:1] btb_sel_data_f;
+     372          244 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -484,7 +484,7 @@
      380              :                                     ({16{btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]) );
      381              : 
      382              : 
-     383           48 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
+     383            0 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
      384              : 
      385              :    // a valid taken target needs to kill the next fetch as we compute the target address
      386              :    assign ifu_bp_hit_taken_f = |(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f & ~leak_one_f_d1 & ~dec_tlu_bpred_disable;
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460         1838 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460            6 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500         2374 : logic [1:0] bloc_f;
-     501         3406 : logic use_fa_plus;
+     500            8 : logic [1:0] bloc_f;
+     501            8 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -719,8 +719,8 @@
      615              :                                                 exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
-     618          108 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619          320 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     618            4 :    logic [1:0] bht_wr_data0, bht_wr_data2;
+     619            0 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -732,9 +732,9 @@
      628              : 
      629              : 
      630              : 
-     631          488 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
+     631           10 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
      632              : 
-     633          488 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
+     633           10 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
      634              :    el2_btb_ghr_hash #(.pt(pt)) mpghrhs  (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      635              :    el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      636              :    el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676        96198 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676        49950 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678        96198 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679        96198 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678        49950 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679        49950 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684        96198 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684        49950 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686        96198 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687        96198 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686        49950 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687        49950 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -933,8 +933,8 @@
      829              : 
      830              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0]      bht_bank_wr_data ;
      831              :    logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0]                bht_bank_rd_data_out ;
-     832           24 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
-     833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
+     832            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
+     833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
      834              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0]           bht_bank_sel   ;
      835              : 
      836              :    for ( i=0; i<2; i++) begin : BANKS
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877        96198 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878        96198 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879        96198 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877        49950 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878        49950 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879        49950 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881        96198 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882        96198 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881        49950 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882        49950 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_compress_ctl.sv.html
index 1a48ff8f6da..4914db0e092 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_compress_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        97.4%
+    
+        81.6%
     
     
-        37
+        31
     
     
         38
@@ -127,14 +127,14 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26         1864 :    input  logic [15:0] din,        // 16-bit   compressed instruction
-      27          536 :    output logic [31:0] dout        // 32-bit uncompressed instruction
+      26           32 :    input  logic [15:0] din,        // 16-bit   compressed instruction
+      27            4 :    output logic [31:0] dout        // 32-bit uncompressed instruction
       28              :    );
       29              : 
       30              : 
-      31         9244 :    logic               legal;
+      31          412 :    logic               legal;
       32              : 
-      33         1864 :    logic [15:0]  i;
+      33           32 :    logic [15:0]  i;
       34              : 
       35            2 :    logic [31:0]  o,l1,l2,l3;
       36              : 
@@ -144,27 +144,27 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43         7032 :    logic rdrd;
-      44         4320 :    logic rdrs1;
-      45         4768 :    logic rs2rs2;
-      46          500 :    logic rdprd;
-      47         1880 :    logic rdprs1;
-      48           64 :    logic rs2prs2;
-      49         9210 :    logic rs2prd;
-      50         9246 :    logic uimm9_2;
-      51          380 :    logic ulwimm6_2;
-      52          400 :    logic ulwspimm7_2;
-      53          112 :    logic rdeq2;
-      54          140 :    logic rdeq1;
-      55         8354 :    logic rs1eq2;
-      56         1404 :    logic sbroffset8_1;
-      57          112 :    logic simm9_4;
-      58         3528 :    logic simm5_0;
-      59          536 :    logic sjaloffset11_1;
-      60            8 :    logic sluimm17_12;
-      61          720 :    logic uimm5_0;
-      62           56 :    logic uswimm6_2;
-      63          576 :    logic uswspimm7_2;
+      43          296 :    logic rdrd;
+      44          272 :    logic rdrs1;
+      45           12 :    logic rs2rs2;
+      46            4 :    logic rdprd;
+      47          268 :    logic rdprs1;
+      48            4 :    logic rs2prs2;
+      49          414 :    logic rs2prd;
+      50          414 :    logic uimm9_2;
+      51            0 :    logic ulwimm6_2;
+      52            8 :    logic ulwspimm7_2;
+      53            0 :    logic rdeq2;
+      54           12 :    logic rdeq1;
+      55          402 :    logic rs1eq2;
+      56          264 :    logic sbroffset8_1;
+      57            0 :    logic simm9_4;
+      58          288 :    logic simm5_0;
+      59           16 :    logic sjaloffset11_1;
+      60            0 :    logic sluimm17_12;
+      61            0 :    logic uimm5_0;
+      62            0 :    logic uswimm6_2;
+      63            8 :    logic uswspimm7_2;
       64              : 
       65              : 
       66              : 
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115         2968 :    logic [5:0] simm5d;
-     116         2968 :    logic [9:2] uimm9d;
+     115          260 :    logic [5:0] simm5d;
+     116          260 :    logic [9:2] uimm9d;
      117              : 
-     118         2968 :    logic [9:4] simm9d;
-     119         2968 :    logic [6:2] ulwimm6d;
-     120         2968 :    logic [7:2] ulwspimm7d;
-     121         2968 :    logic [5:0] uimm5d;
-     122         2968 :    logic [20:1] sjald;
+     118          260 :    logic [9:4] simm9d;
+     119          260 :    logic [6:2] ulwimm6d;
+     120          260 :    logic [7:2] ulwspimm7d;
+     121          260 :    logic [5:0] uimm5d;
+     122          260 :    logic [20:1] sjald;
      123              : 
-     124         2968 :    logic [31:12] sluimmd;
+     124          260 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,9 +272,9 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171         2968 :    logic [8:1]   sbr8d;
-     172         2968 :    logic [6:2]   uswimm6d;
-     173         3600 :    logic [7:2]   uswspimm7d;
+     171          260 :    logic [8:1]   sbr8d;
+     172          260 :    logic [6:2]   uswimm6d;
+     173          260 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
      176              :    assign sbr8d[8:1] =   { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ic_mem.sv.html
index 2f097926b02..72ffae7d137 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26       404408 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27       404408 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26        15288 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27        15288 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -141,11 +141,11 @@
       37            0 :       input logic                                   ic_debug_wr_en,     // Icache debug wr
       38            0 :       input logic                                   ic_debug_tag_array, // Debug tag array
       39            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_debug_way,       // Debug way. Rd or Wr.
-      40         5364 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-      41        20614 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
+      40           62 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+      41          734 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
       42              : 
-      43         1164 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
-      44         5364 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      43            6 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
+      44           62 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       45            0 :       output logic [70:0]                           ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       46            0 :       output logic [25:0]                           ictag_debug_rd_data,// Debug icache tag.
       47            0 :       input logic  [70:0]                           ic_debug_wr_data,   // Debug wr cache.
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91       404408 :       input logic clk,
-      92       404408 :       input logic active_clk,
+      91        15288 :       input logic clk,
+      92        15288 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -201,8 +201,8 @@
       97            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en,
       98            0 :       input logic                          ic_rd_en,           // Read enable
       99              : 
-     100         1164 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
-     101         5364 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     100            6 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
+     101           62 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      102            0 :       input  logic [70:0]                             ic_debug_wr_data,   // Debug wr cache.
      103            0 :       output logic [70:0]                             ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      104            0 :       output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
@@ -212,8 +212,8 @@
      108            0 :       input logic                            ic_debug_wr_en,      // Icache debug wr
      109            0 :       input logic                            ic_debug_tag_array,  // Debug tag array
      110            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way,        // Debug way. Rd or Wr.
-     111         5364 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-     112        20614 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
+     111           62 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+     112          734 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
      113              : 
      114            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
      115            0 :       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
@@ -221,7 +221,7 @@
      117              : 
      118              :       ) ;
      119              : 
-     120          722 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
+     120            8 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
      121            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_wren;    //bank x ways
      122            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_rden;    //bank x ways
      123              : 
@@ -231,9 +231,9 @@
      127            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                ic_debug_sel_sb;
      128              : 
      129              :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0]                  wb_dout ;       //  ways x bank
-     130         1164 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
+     130            6 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
      131              :    logic [pt.ICACHE_NUM_WAYS-1:0] [141:0]                                         wb_dout_way_pre;
-     132         5364 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
+     132           62 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
      133            0 :    logic [141:0]                                                                  wb_dout_ecc;
      134              : 
      135            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                bank_check_en;
@@ -245,11 +245,11 @@
      141            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en;    // debug wr_way
      142            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en_ff; // debug wr_way
      143            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_wr_way_en;    // debug wr_way
-     144          152 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
+     144            8 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
      145              : 
-     146          152 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
+     146            8 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
      147              : 
-     148          160 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
+     148           12 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
      149            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_rd_hit_q;
      150              : 
      151              : 
@@ -278,7 +278,7 @@
      174              : 
      175              : 
      176            2 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr;
-     177          152 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
+     177            8 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
      178              : 
      179            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_up;
      180            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only_up;
@@ -296,7 +296,7 @@
      192              :    assign  ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      193              :    assign  ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      194              : 
-     195         2802 :    logic end_of_cache_line;
+     195           16 :    logic end_of_cache_line;
      196              :    assign end_of_cache_line = (pt.ICACHE_LN_SZ==7'h40) ? (&ic_rw_addr_q[5:4]) : ic_rw_addr_q[4];
      197            2 :    always_comb begin : clkens
      198            2 :       ic_bank_way_clken  = '0;
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803       404408 :       input logic                                                   clk,
-     804       404408 :       input logic                                                   active_clk,
+     803        15288 :       input logic                                                   clk,
+     804        15288 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
@@ -945,7 +945,7 @@
      841            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en ;
      842            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en_ff ;
      843              : 
-     844          152 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
+     844            8 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
      845            2 :    logic [31:pt.ICACHE_TAG_LO]                                     ic_rw_addr_ff;
      846            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_rden_q;          // way
      847            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_wren;          // way
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_iccm_mem.sv.html
index c4d3a2ed317..e2e65df8317 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,14 +129,14 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28       404408 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29       404408 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28        15288 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29        15288 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
       33            0 :    input logic                                        iccm_wren,                           // ICCM write enable
       34            0 :    input logic                                        iccm_rden,                           // ICCM read enable
-      35          152 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
+      35            8 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
       36            0 :    input logic                                        iccm_buf_correct_ecc,                // ICCM is doing a single bit error correct cycle
       37            0 :    input logic                                        iccm_correction_state,               // ICCM under a correction - This is needed to guard replacements when hit
       38            0 :    input logic [2:0]                                  iccm_wr_size,                        // ICCM write size
@@ -154,13 +154,13 @@
       50            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                wren_bank;
       51            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
       52            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
-      53          152 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
+      53            8 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
       54              : 
       55            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
-      57          152 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58         7010 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
-      59          722 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
+      57           12 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
+      58          300 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      59            8 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
       60            0 :    logic             [63:0]              iccm_rd_data_pre;
       61            0 :    logic             [63:0]              iccm_data;
       62            0 :    logic [1:0]                           addr_incr;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ifc_ctl.sv.html
index be805b29c8f..722fe191686 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_ifc_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        78.6%
+    
+        71.4%
     
     
-        33
+        30
     
     
         42
@@ -130,27 +130,27 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29       404408 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30       404408 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        15288 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        15288 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
       34              : 
-      35        25918 :    input logic ic_hit_f,      // Icache hit
-      36        26036 :    input logic ifu_ic_mb_empty, // Miss buffer empty
+      35          936 :    input logic ic_hit_f,      // Icache hit
+      36          996 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
-      38        19748 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39         1564 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      38          800 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
+      39            0 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
-      41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
-      42         1240 :    input logic exu_flush_final, // FLush
-      43          220 :    input logic [31:1] exu_flush_path_final, // Flush path
+      41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
+      42          110 :    input logic exu_flush_final, // FLush
+      43           16 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45         4160 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
-      46          212 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      45          184 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      46          184 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
       48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
-      49        10056 :    input logic ic_write_stall, // IC is writing, stop fetching
+      49          392 :    input logic ic_write_stall, // IC is writing, stop fetching
       50            0 :    input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
       51              : 
       52            0 :    input logic [31:0]  dec_tlu_mrac_ff ,   // side_effect and cacheable for each region
@@ -158,34 +158,34 @@
       54            2 :    output logic [31:1] ifc_fetch_addr_f, // fetch addr F
       55            2 :    output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
       56              : 
-      57        12646 :    output logic  ifc_fetch_req_f,  // fetch request valid F
+      57          394 :    output logic  ifc_fetch_req_f,  // fetch request valid F
       58              : 
-      59          950 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
+      59           42 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
       60              : 
       61            2 :    output logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. BF stage
-      62        12646 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
+      62          394 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
       63            2 :    output logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. BF stage
       64            0 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       65            0 :    output logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       66              : 
-      67         1242 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
+      67          112 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
       68              : 
       69              : 
       70              :    );
       71              : 
       72            2 :    logic [31:1]  fetch_addr_bf;
       73            2 :    logic [31:1]  fetch_addr_next;
-      74         2588 :    logic [3:0]   fb_write_f, fb_write_ns;
+      74            0 :    logic [3:0]   fb_write_f, fb_write_ns;
       75              : 
-      76         2588 :    logic     fb_full_f_ns, fb_full_f;
-      77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
-      78        22458 :    logic     sel_last_addr_bf, sel_next_addr_bf;
-      79        36250 :    logic     miss_f, miss_a;
+      76            0 :    logic     fb_full_f_ns, fb_full_f;
+      77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
+      78          752 :    logic     sel_last_addr_bf, sel_next_addr_bf;
+      79         1392 :    logic     miss_f, miss_a;
       80            0 :    logic     flush_fb, dma_iccm_stall_any_f;
       81            4 :    logic     mb_empty_mod, goto_idle, leave_idle;
-      82        12570 :    logic     fetch_bf_en;
-      83          960 :    logic         line_wrap;
-      84          650 :    logic         fetch_addr_next_1;
+      82          398 :    logic     fetch_bf_en;
+      83           16 :    logic         line_wrap;
+      84            8 :    logic         fetch_addr_next_1;
       85              : 
       86              :    // FSM assignment
       87              :     typedef enum logic [1:0] { IDLE  = 2'b00 ,
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_mem_ctl.sv.html
index 13507125394..14302fb52ec 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_ifu_mem_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        45.0%
+    
+        44.7%
     
     
-        158
+        157
     
     
         351
@@ -131,40 +131,40 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30       404408 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31       404408 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32       404408 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30        15288 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        15288 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32        15288 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
-      35         1240 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
-      36           64 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
+      35          110 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
+      36            4 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
       37            0 :    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
-      38        25728 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
+      38          996 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
       39            0 :    input logic                       dec_tlu_force_halt,            // force halt.
       40              : 
       41            2 :    input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
       42            2 :    input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
-      43        12646 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
+      43          394 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
       44            2 :    input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
       45            0 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
-      47         1242 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
+      47          112 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49         4160 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49          184 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51         1982 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51            6 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
-      53        26024 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
-      54        26036 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
+      53          996 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
+      54          996 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
       55            0 :    output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
-      56        10056 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
+      56          392 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
       57              : 
       58              : /// PMU signals
-      59        26024 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
+      59          996 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
       60            0 :    output logic                      ifu_pmu_ic_hit,                // IC hit event
       61            0 :    output logic                      ifu_pmu_bus_error,             // Bus error event
       62            0 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
-      63        26024 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
+      63          996 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
       64              : 
       65              :   //-------------------------- IFU AXI signals--------------------------
       66              :    // AXI Write Channels
@@ -188,10 +188,10 @@
       84            0 :    output logic                            ifu_axi_bready,
       85              : 
       86              :    // AXI Read Channels
-      87        26024 :    output logic                            ifu_axi_arvalid,
-      88        26026 :    input  logic                            ifu_axi_arready,
-      89        17884 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      90         3188 :    output logic [31:0]                     ifu_axi_araddr,
+      87          996 :    output logic                            ifu_axi_arvalid,
+      88          996 :    input  logic                            ifu_axi_arready,
+      89           88 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      90           56 :    output logic [31:0]                     ifu_axi_araddr,
       91            2 :    output logic [3:0]                      ifu_axi_arregion,
       92            0 :    output logic [7:0]                      ifu_axi_arlen,
       93            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -201,10 +201,10 @@
       97            2 :    output logic [2:0]                      ifu_axi_arprot,
       98            0 :    output logic [3:0]                      ifu_axi_arqos,
       99              : 
-     100        52048 :    input  logic                            ifu_axi_rvalid,
+     100         1990 :    input  logic                            ifu_axi_rvalid,
      101            2 :    output logic                            ifu_axi_rready,
-     102         5542 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     103         2300 :    input  logic [63:0]                     ifu_axi_rdata,
+     102           48 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     103           24 :    input  logic [63:0]                     ifu_axi_rdata,
      104            0 :    input  logic [1:0]                      ifu_axi_rresp,
      105              : 
      106            2 :     input  logic                     ifu_bus_clk_en,
@@ -221,7 +221,7 @@
      117            0 :    output logic                      iccm_dma_rvalid,   //   Data read from iccm is valid
      118            0 :    output logic [63:0]               iccm_dma_rdata,    //   dma data read from iccm
      119            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     120         1238 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
+     120          108 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
      121              : 
      122              : 
      123              : //   I$ & ITAG Ports
@@ -229,8 +229,8 @@
      125            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      126            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      127              : 
-     128         1164 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
-     129         5364 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     128            6 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
+     129           62 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      130            0 :    input  logic [70:0]               ic_debug_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      131            0 :    input  logic [25:0]               ictag_debug_rd_data,  // Debug icache tag.
      132            0 :    output logic [70:0]               ic_debug_wr_data,     // Debug wr cache.
@@ -253,7 +253,7 @@
      149            0 :    input  logic                      ic_tag_perr,        // Icache Tag parity error
      150              : 
      151              :    // ICCM ports
-     152          152 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
+     152            8 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
      153            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
      154            0 :    output logic                      iccm_rden,          // ICCM read enable.
      155            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
@@ -261,9 +261,9 @@
      157              : 
      158            0 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
      159            0 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
-     160        23690 :    input  logic [1:0]                ifu_fetch_val,
+     160          932 :    input  logic [1:0]                ifu_fetch_val,
      161              :    // IFU control signals
-     162        25918 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
+     162          936 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
      163            0 :    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
      164            0 :    output logic [1:0]                ic_access_fault_type_f, // Access fault types
      165            0 :    output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
@@ -274,10 +274,10 @@
      170              : 
      171            0 :    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
      172            0 :    output logic                      iccm_dma_sb_error,      // Single Bit ECC error from a DMA access
-     173        23690 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
-     174         5364 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
-     175         5364 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
-     176        20614 :    output logic                      ic_sel_premux_data,     // Select premux data.
+     173          932 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
+     174           62 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
+     175           62 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
+     176          734 :    output logic                      ic_sel_premux_data,     // Select premux data.
      177              : 
      178              : /////  Debug
      179            0 :    input  el2_cache_debug_pkt_t     dec_tlu_ic_diag_pkt ,       // Icache/tag debug read/write packet
@@ -304,8 +304,8 @@
      200              : 
      201              : 
      202              : 
-     203        52048 :    logic           bus_ifu_wr_en     ;
-     204        52046 :    logic           bus_ifu_wr_en_ff  ;
+     203         1990 :    logic           bus_ifu_wr_en     ;
+     204         1988 :    logic           bus_ifu_wr_en_ff  ;
      205            0 :    logic           bus_ifu_wr_en_ff_q  ;
      206            0 :    logic           bus_ifu_wr_en_ff_wo_err  ;
      207            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     bus_ic_wr_en ;
@@ -333,36 +333,36 @@
      229            0 :    logic           scnd_miss_index_match ;
      230              : 
      231              : 
-     232         1238 :    logic           ifc_dma_access_q_ok;
+     232          108 :    logic           ifc_dma_access_q_ok;
      233            0 :    logic           ifc_iccm_access_f ;
      234            0 :    logic           ifc_region_acc_fault_f;
      235            0 :    logic           ifc_region_acc_fault_final_f;
      236            0 :    logic  [1:0]    ifc_bus_acc_fault_f;
-     237        26024 :    logic           ic_act_miss_f;
+     237          996 :    logic           ic_act_miss_f;
      238            0 :    logic           ic_miss_under_miss_f;
-     239          808 :    logic           ic_ignore_2nd_miss_f;
+     239           84 :    logic           ic_ignore_2nd_miss_f;
      240            0 :    logic           ic_act_hit_f;
-     241        26022 :    logic           miss_pending;
+     241          994 :    logic           miss_pending;
      242            2 :    logic [31:1]    imb_in , imb_ff  ;
      243            2 :    logic [31:pt.ICACHE_BEAT_ADDR_HI+1]    miss_addr_in , miss_addr  ;
-     244         1676 :    logic           miss_wrap_f ;
-     245         1240 :    logic           flush_final_f;
-     246        13654 :    logic           ifc_fetch_req_f;
-     247        12646 :    logic           ifc_fetch_req_f_raw;
-     248        25918 :    logic           fetch_req_f_qual   ;
-     249        12646 :    logic           ifc_fetch_req_qual_bf ;
+     244           22 :    logic           miss_wrap_f ;
+     245          108 :    logic           flush_final_f;
+     246          496 :    logic           ifc_fetch_req_f;
+     247          394 :    logic           ifc_fetch_req_f_raw;
+     248          936 :    logic           fetch_req_f_qual   ;
+     249          394 :    logic           ifc_fetch_req_qual_bf ;
      250            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     replace_way_mb_any;
-     251        26022 :    logic           last_beat;
-     252        36222 :    logic           reset_beat_cnt  ;
-     253         9572 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
-     254        25262 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
+     251          992 :    logic           last_beat;
+     252         1400 :    logic           reset_beat_cnt  ;
+     253          416 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
+     254          120 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
      255            2 :    logic [31:1]    ifu_fetch_addr_int_f ;
      256            2 :    logic [31:1]    ifu_ic_rw_int_addr ;
-     257        26022 :    logic           crit_wd_byp_ok_ff ;
-     258        25922 :    logic           ic_crit_wd_rdy_new_ff;
-     259         2786 :    logic   [79:0]  ic_byp_data_only_pre_new;
-     260         2516 :    logic   [79:0]  ic_byp_data_only_new;
-     261        25918 :    logic           ic_byp_hit_f ;
+     257          996 :    logic           crit_wd_byp_ok_ff ;
+     258          934 :    logic           ic_crit_wd_rdy_new_ff;
+     259           24 :    logic   [79:0]  ic_byp_data_only_pre_new;
+     260           28 :    logic   [79:0]  ic_byp_data_only_new;
+     261          936 :    logic           ic_byp_hit_f ;
      262            2 :    logic           ic_valid ;
      263            2 :    logic           ic_valid_ff;
      264            0 :    logic           reset_all_tags;
@@ -380,94 +380,94 @@
      276              : 
      277            0 :    logic           reset_ic_in ;
      278            0 :    logic           reset_ic_ff ;
-     279          722 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
+     279            8 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
      280            2 :    logic [31:1]    ifu_status_wr_addr;
      281            0 :    logic           sel_mb_addr ;
      282            0 :    logic           sel_mb_addr_ff ;
      283            0 :    logic           sel_mb_status_addr ;
-     284         5364 :    logic [63:0]    ic_final_data;
+     284           62 :    logic [63:0]    ic_final_data;
      285              : 
      286            0 :    logic [pt.ICACHE_STATUS_BITS-1:0]                              way_status_new_ff ;
      287            0 :    logic                                    way_status_wr_en_ff ;
      288            0 :    logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0]        way_status_out ;
      289            0 :    logic [1:0]                              ic_debug_way_enc;
      290              : 
-     291         5542 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
+     291           46 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
      292              : 
-     293        13654 :    logic         fetch_req_icache_f;
+     293          496 :    logic         fetch_req_icache_f;
      294            0 :    logic         fetch_req_iccm_f;
      295            0 :    logic         ic_iccm_hit_f;
      296            2 :    logic         fetch_uncacheable_ff;
      297            0 :    logic         way_status_wr_en;
-     298        20614 :    logic         sel_byp_data;
-     299        20616 :    logic         sel_ic_data;
+     298          734 :    logic         sel_byp_data;
+     299          736 :    logic         sel_ic_data;
      300            0 :    logic         sel_iccm_data;
      301            0 :    logic         ic_rd_parity_final_err;
-     302        26024 :    logic         ic_act_miss_f_delayed;
+     302          996 :    logic         ic_act_miss_f_delayed;
      303            0 :    logic         bus_ifu_wr_data_error;
      304            0 :    logic         bus_ifu_wr_data_error_ff;
      305            0 :    logic         way_status_wr_en_w_debug;
      306            0 :    logic         ic_debug_tag_val_rd_out;
-     307        26024 :    logic         ifu_pmu_ic_miss_in;
+     307          996 :    logic         ifu_pmu_ic_miss_in;
      308            0 :    logic         ifu_pmu_ic_hit_in;
      309            0 :    logic         ifu_pmu_bus_error_in;
-     310        26024 :    logic         ifu_pmu_bus_trxn_in;
+     310          996 :    logic         ifu_pmu_bus_trxn_in;
      311            0 :    logic         ifu_pmu_bus_busy_in;
      312            0 :    logic         ic_debug_ict_array_sel_in;
      313            0 :    logic         ic_debug_ict_array_sel_ff;
      314            0 :    logic         debug_data_clken;
-     315        26022 :    logic         last_data_recieved_in ;
-     316        26020 :    logic         last_data_recieved_ff ;
+     315          992 :    logic         last_data_recieved_in ;
+     316          992 :    logic         last_data_recieved_ff ;
      317              : 
-     318        52048 :    logic                          ifu_bus_rvalid           ;
-     319        52046 :    logic                          ifu_bus_rvalid_ff        ;
-     320        52046 :    logic                          ifu_bus_rvalid_unq_ff    ;
-     321        26026 :    logic                          ifu_bus_arready_unq       ;
-     322        26024 :    logic                          ifu_bus_arready_unq_ff    ;
-     323        26024 :    logic                          ifu_bus_arvalid           ;
-     324        26024 :    logic                          ifu_bus_arvalid_ff        ;
-     325        26026 :    logic                          ifu_bus_arready           ;
-     326        26024 :    logic                          ifu_bus_arready_ff        ;
-     327         2300 :    logic [63:0]                   ifu_bus_rdata_ff        ;
+     318         1990 :    logic                          ifu_bus_rvalid           ;
+     319         1988 :    logic                          ifu_bus_rvalid_ff        ;
+     320         1988 :    logic                          ifu_bus_rvalid_unq_ff    ;
+     321          996 :    logic                          ifu_bus_arready_unq       ;
+     322          996 :    logic                          ifu_bus_arready_unq_ff    ;
+     323          996 :    logic                          ifu_bus_arvalid           ;
+     324          996 :    logic                          ifu_bus_arvalid_ff        ;
+     325          996 :    logic                          ifu_bus_arready           ;
+     326          996 :    logic                          ifu_bus_arready_ff        ;
+     327           24 :    logic [63:0]                   ifu_bus_rdata_ff        ;
      328            0 :    logic [1:0]                    ifu_bus_rresp_ff          ;
-     329        52048 :    logic                          ifu_bus_rsp_valid ;
+     329         1990 :    logic                          ifu_bus_rsp_valid ;
      330            2 :    logic                          ifu_bus_rsp_ready ;
-     331         5542 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
-     332         2300 :    logic [63:0]                   ifu_bus_rsp_rdata;
+     331           48 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
+     332           24 :    logic [63:0]                   ifu_bus_rsp_rdata;
      333            0 :    logic [1:0]                    ifu_bus_rsp_opc;
      334              : 
-     335         3860 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
+     335           16 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
      336            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    wr_data_c1_clk;
-     337         3860 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
-     338         3860 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
+     337           16 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
+     338           16 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
      339            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error_in;
      340            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error;
-     341          722 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
-     342         2678 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
+     341            8 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
+     342           24 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
      343            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_1;
-     344         1494 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
-     345         1494 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
+     344           28 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
+     345           28 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
      346            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_1;
-     347        36858 :    logic          miss_buff_hit_unq_f ;
+     347         1324 :    logic          miss_buff_hit_unq_f ;
      348            0 :    logic          stream_hit_f ;
      349            0 :    logic          stream_miss_f ;
      350            0 :    logic          stream_eol_f ;
-     351        25922 :    logic          crit_byp_hit_f ;
-     352         5542 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
+     351          936 :    logic          crit_byp_hit_f ;
+     352           46 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
      353              :    logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;
-     354         2404 :    logic [63:0] ic_miss_buff_half;
+     354           16 :    logic [63:0] ic_miss_buff_half;
      355            0 :    logic        scnd_miss_req, scnd_miss_req_q;
      356            0 :    logic        scnd_miss_req_in;
      357              : 
      358              : 
      359            0 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_ff;
-     360          156 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
+     360           12 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
      361            0 :    logic [38:0]                         iccm_ecc_corr_data_ff;
      362            0 :    logic                                iccm_ecc_write_status     ;
      363            0 :    logic                                iccm_rd_ecc_single_err_ff   ;
      364            0 :    logic                                iccm_error_start;     // start the error fsm
      365            0 :    logic                                perr_state_en;
-     366        55934 :    logic                                miss_state_en;
+     366         2038 :    logic                                miss_state_en;
      367              : 
      368            0 :    logic        busclk;
      369            0 :    logic        busclk_force;
@@ -475,46 +475,46 @@
      371            2 :    logic        bus_ifu_bus_clk_en_ff;
      372            2 :    logic        bus_ifu_bus_clk_en ;
      373              : 
-     374        26024 :    logic        ifc_bus_ic_req_ff_in;
-     375        26024 :    logic        ifu_bus_cmd_valid ;
-     376        26026 :    logic        ifu_bus_cmd_ready ;
+     374          996 :    logic        ifc_bus_ic_req_ff_in;
+     375          996 :    logic        ifu_bus_cmd_valid ;
+     376          996 :    logic        ifu_bus_cmd_ready ;
      377              : 
-     378        26024 :    logic        bus_inc_data_beat_cnt     ;
-     379        36222 :    logic        bus_reset_data_beat_cnt   ;
-     380        62248 :    logic        bus_hold_data_beat_cnt    ;
+     378          996 :    logic        bus_inc_data_beat_cnt     ;
+     379         1400 :    logic        bus_reset_data_beat_cnt   ;
+     380         2398 :    logic        bus_hold_data_beat_cnt    ;
      381              : 
-     382        26024 :    logic        bus_inc_cmd_beat_cnt     ;
+     382          996 :    logic        bus_inc_cmd_beat_cnt     ;
      383            0 :    logic        bus_reset_cmd_beat_cnt_0   ;
-     384        26024 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
-     385        26026 :    logic        bus_hold_cmd_beat_cnt    ;
+     384          996 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
+     385          998 :    logic        bus_hold_cmd_beat_cnt    ;
      386              : 
      387            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_data_beat_count  ;
      388            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_data_beat_count      ;
      389              : 
-     390        26024 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
-     391        26024 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
+     390          996 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
+     391          996 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
      392              : 
      393              : 
-     394         9572 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
-     395         9572 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
+     394          416 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
+     395          416 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
      396              : 
      397              : 
-     398        26024 :    logic        bus_cmd_sent           ;
-     399        26022 :    logic        bus_last_data_beat     ;
+     398          996 :    logic        bus_cmd_sent           ;
+     399          994 :    logic        bus_last_data_beat     ;
      400              : 
      401              : 
      402            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren            ;
      403              : 
      404            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren_last       ;
      405            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       wren_reset_miss      ;
-     406         1242 :    logic        ifc_dma_access_ok_d;
-     407         1242 :    logic        ifc_dma_access_ok_prev;
+     406          112 :    logic        ifc_dma_access_ok_d;
+     407          110 :    logic        ifc_dma_access_ok_prev;
      408              : 
-     409        26024 :    logic   bus_cmd_req_in ;
-     410        26024 :    logic   bus_cmd_req_hold ;
+     409          996 :    logic   bus_cmd_req_in ;
+     410          996 :    logic   bus_cmd_req_hold ;
      411              : 
-     412        11830 :    logic   second_half_available ;
-     413        11830 :    logic   write_ic_16_bytes ;
+     412          408 :    logic   second_half_available ;
+     413          408 :    logic   write_ic_16_bytes ;
      414              : 
      415            0 :    logic   ifc_region_acc_fault_final_bf;
      416            0 :    logic   ifc_region_acc_fault_memory_bf;
@@ -523,21 +523,21 @@
      419              : 
      420            0 :    logic   iccm_correct_ecc;
      421            0 :    logic   dma_sb_err_state, dma_sb_err_state_ff;
-     422        14788 :    logic   two_byte_instr;
+     422          624 :    logic   two_byte_instr;
      423              : 
      424              :    typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;
-     425           12 :    miss_state_t miss_state, miss_nxtstate;
+     425            0 :    miss_state_t miss_state, miss_nxtstate;
      426              : 
      427              :    typedef enum logic [1:0] {ERR_STOP_IDLE=2'b00, ERR_FETCH1=2'b01 , ERR_FETCH2=2'b10 , ERR_STOP_FETCH=2'b11} err_stop_state_t;
-     428            0 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
+     428            0 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
      429            0 :    logic   err_stop_state_en ;
      430            0 :    logic   err_stop_fetch ;
      431              : 
-     432        25922 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
+     432          934 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434         3460 :    logic   ifu_bp_hit_taken_q_f;
-     435        52048 :    logic   ifu_bus_rvalid_unq;
-     436        26024 :    logic   bus_cmd_beat_en;
+     434          184 :    logic   ifu_bp_hit_taken_q_f;
+     435         1990 :    logic   ifu_bus_rvalid_unq;
+     436          996 :    logic   bus_cmd_beat_en;
      437              : 
      438              : 
      439              : // ---- Clock gating section -----
@@ -587,21 +587,21 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486        18126 :          IDLE: begin : idle
-     487        18126 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488        18126 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486         9421 :          IDLE: begin : idle
+     487         9421 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488         9421 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490        57592 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491        57592 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492        57592 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493        57592 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494        57592 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495        57592 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496        57592 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497        57592 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498        57592 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499        57592 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500        57592 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490        29943 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491        29943 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492        29943 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493        29943 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494        29943 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495        29943 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496        29943 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497        29943 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498        29943 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499        29943 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500        29943 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,24 +611,24 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510        20060 :          MISS_WAIT: begin : miss_wait
-     511        20060 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512        20060 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510        10355 :          MISS_WAIT: begin : miss_wait
+     511        10355 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512        10355 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514          404 :          HIT_U_MISS: begin : hit_u_miss
-     515          404 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516          404 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517          404 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514          223 :          HIT_U_MISS: begin : hit_u_miss
+     515          223 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516          223 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517          223 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
      521            0 :                                     exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;
      522            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      523              :          end
-     524           16 :          STALL_SCND_MISS: begin : stall_scnd_miss
-     525           16 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
-     526           16 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
-     527           16 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
+     524            8 :          STALL_SCND_MISS: begin : stall_scnd_miss
+     525            8 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
+     526            8 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
+     527            8 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      528              :          end
      529            0 :          default: begin : def_case
      530            0 :                   miss_nxtstate   = IDLE;
@@ -638,7 +638,7 @@
      534              :    end
      535              :    rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en),   .*);
      536              : 
-     537        26024 :   logic    sel_hold_imb     ;
+     537          994 :   logic    sel_hold_imb     ;
      538              : 
      539              :    assign miss_pending       =  (miss_state != IDLE) ;
      540              :    assign crit_wd_byp_ok_ff  =  (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
@@ -902,7 +902,7 @@
      798              : /////////////////////////////////////////////////////////////////////////////////////
      799              : //  Create full buffer...                                                          //
      800              : /////////////////////////////////////////////////////////////////////////////////////
-     801         2300 :      logic [63:0]       ic_miss_buff_data_in;
+     801           24 :      logic [63:0]       ic_miss_buff_data_in;
      802              :      assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
      803              : 
      804              :      for (genvar i=0; i<pt.ICACHE_NUM_BEATS; i++) begin :  wr_flop
@@ -939,10 +939,10 @@
      835              : /////////////////////////////////////////////////////////////////////////////////////
      836              : // New bypass ready                                                                //
      837              : /////////////////////////////////////////////////////////////////////////////////////
-     838          710 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
-     839         1350 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
-     840        26022 :    logic   bypass_data_ready_in;
-     841        25922 :    logic   ic_crit_wd_rdy_new_in;
+     838            8 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
+     839           20 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
+     840          994 :    logic   bypass_data_ready_in;
+     841          936 :    logic   ic_crit_wd_rdy_new_in;
      842              : 
      843              :    assign bypass_index[pt.ICACHE_BEAT_ADDR_HI:1] = imb_ff[pt.ICACHE_BEAT_ADDR_HI:1] ;
      844              :    assign bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3] = bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] + 1 ;
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945        96198 :       ERR_IDLE: begin : err_idle
-     946        96198 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947        96198 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948        96198 :         perr_sb_write_status = perr_state_en;
+     945        49950 :       ERR_IDLE: begin : err_idle
+     946        49950 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947        49950 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948        49950 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990        96198 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991        96198 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992        96198 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990        49950 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991        49950 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992        49950 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1469,7 +1469,7 @@
     1365              :                               ((miss_state == CRIT_BYP_OK) &  miss_state_en &  (miss_nxtstate == MISS_WAIT))  ))  |
     1366              :                              ( ifc_fetch_req_bf & exu_flush_final  & ~ifc_fetch_uncacheable_bf & ~ifc_iccm_access_bf )     ;
     1367              : 
-    1368        26566 : logic   ic_real_rd_wp_unused;
+    1368         1074 : logic   ic_real_rd_wp_unused;
     1369              : assign  ic_real_rd_wp_unused  =  (ifc_fetch_req_bf &  ~ifc_iccm_access_bf  &  ~ifc_region_acc_fault_final_bf & ~dec_tlu_fence_i_wb & ~stream_miss_f & ~ic_act_miss_f &
     1370              :                             ~(((miss_state == STREAM) & ~miss_state_en) |
     1371              :                               ((miss_state == CRIT_BYP_OK) & ~miss_state_en & ~(miss_nxtstate == MISS_WAIT)) |
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446        96198 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447        96198 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446        49950 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447        49950 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509        96198 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510        96198 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511       192396 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509        49950 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510        49950 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511        99900 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lib.sv.html
index dc066af0891..f14f4327447 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35         2464 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
-      36         2464 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
+      35          132 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
+      36          132 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
       37              :                         );
       38              : 
       39              : 
@@ -158,9 +158,9 @@
       54              : #(
       55              : `include "el2_param.vh"
       56              :  )(
-      57          784 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58         6206 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59         6502 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      57           60 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
+      58           82 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59           78 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu.sv.html
index 697c052113f..c05de98a9f0 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        42.4%
+    
+        26.8%
     
     
-        84
+        53
     
     
         198
@@ -137,7 +137,7 @@
       33              : (
       34              : 
       35            0 :    input logic                             clk_override,             // Override non-functional clock gating
-      36           64 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
+      36            4 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
       37            0 :    input logic                             dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
       38            0 :    input logic                             dec_tlu_force_halt,       // This will be high till TLU goes to debug halt
       39              : 
@@ -147,21 +147,21 @@
       43            0 :    input logic                             dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
       44            0 :    input logic                             dec_tlu_core_ecc_disable,          // disable the generation of the ecc
       45              : 
-      46          124 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
-      47            8 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
-      48          484 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
+      46            0 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
+      47            0 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
+      48            0 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
       49              : 
-      50         1432 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
-      51         7856 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
+      50           16 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
+      51          540 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
       52            0 :    input logic [31:0]                      dec_tlu_mrac_ff,       // CSR for memory region control
       53              : 
       54            0 :    output logic [31:0]                     lsu_result_m,          // lsu load data
       55            0 :    output logic [31:0]                     lsu_result_corr_r,     // This is the ECC corrected data going to RF
-      56            8 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
-      57            8 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
-      58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
-      59         6290 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
-      60         6288 :    output logic                            lsu_active,            // Used to turn off top level clk
+      56            0 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
+      57            0 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
+      58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
+      59          280 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
+      60          278 :    output logic                            lsu_active,            // Used to turn off top level clk
       61              : 
       62            0 :    output logic [31:1]                     lsu_fir_addr,        // fast interrupt address
       63            0 :    output logic [1:0]                      lsu_fir_error,       // Error during fast interrupt lookup
@@ -170,28 +170,28 @@
       66            0 :    output el2_lsu_error_pkt_t             lsu_error_pkt_r,               // lsu exception packet
       67            0 :    output logic                            lsu_imprecise_error_load_any,  // bus load imprecise error
       68            0 :    output logic                            lsu_imprecise_error_store_any, // bus store imprecise error
-      69            2 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
+      69            0 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
       70              : 
       71              :    // Non-blocking loads
-      72         3944 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
-      73         1424 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
+      72          268 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
+      73          252 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
       74            0 :    output logic                               lsu_nonblock_load_inv_r,        // invalidate signal for the cam entry for non block loads
-      75         1424 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
-      76         4032 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
+      75          252 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
+      76          268 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
       77            0 :    output logic                               lsu_nonblock_load_data_error,   // non block load has an error
-      78           36 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
-      79           16 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
+      78            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
+      79            0 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
       80              : 
-      81         3944 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
-      82         3968 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
-      83           12 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
-      84         8288 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
-      85           12 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
-      86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
-      87           32 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
+      81          268 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
+      82          272 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
+      83            0 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
+      84          544 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
+      85            0 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
+      86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
+      87            0 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
       88              : 
       89              :    // Trigger signals
-      90            0 :    input                                   el2_trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode
+      90            0 :    input                                   el2_trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode
       91            0 :    output logic [3:0]                      lsu_trigger_match_m,                      // lsu trigger hit (one bit per trigger)
       92              : 
       93              :    // DCCM ports
@@ -199,9 +199,9 @@
       95            0 :    output logic                            dccm_rden,       // DCCM read enable
       96            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo, // DCCM write address low bank
       97            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi, // DCCM write address hi bank
-      98          128 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
-      99          128 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
-     100            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo, // DCCM write data for lo bank
+      98            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
+      99            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
+     100            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo, // DCCM write data for lo bank
      101            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi, // DCCM write data for hi bank
      102              : 
      103            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_rd_data_lo, // DCCM read data low bank
@@ -211,17 +211,17 @@
      107            0 :    output logic                            picm_wren,    // PIC memory write enable
      108            0 :    output logic                            picm_rden,    // PIC memory read enable
      109            0 :    output logic                            picm_mken,    // Need to read the mask for stores to determine which bits to write/forward
-     110            2 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
-     111            2 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
-     112           28 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
-     113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
+     110            0 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
+     111            0 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
+     112            0 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
+     113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
      114              : 
      115              :    // AXI Write Channels
-     116         4340 :    output logic                            lsu_axi_awvalid,
-     117         8290 :    input  logic                            lsu_axi_awready,
+     116          276 :    output logic                            lsu_axi_awvalid,
+     117          544 :    input  logic                            lsu_axi_awready,
      118            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     119            2 :    output logic [31:0]                     lsu_axi_awaddr,
-     120            2 :    output logic [3:0]                      lsu_axi_awregion,
+     119            0 :    output logic [31:0]                     lsu_axi_awaddr,
+     120            2 :    output logic [3:0]                      lsu_axi_awregion,
      121            0 :    output logic [7:0]                      lsu_axi_awlen,
      122            0 :    output logic [2:0]                      lsu_axi_awsize,
      123            0 :    output logic [1:0]                      lsu_axi_awburst,
@@ -230,23 +230,23 @@
      126            0 :    output logic [2:0]                      lsu_axi_awprot,
      127            0 :    output logic [3:0]                      lsu_axi_awqos,
      128              : 
-     129         4340 :    output logic                            lsu_axi_wvalid,
-     130         8290 :    input  logic                            lsu_axi_wready,
-     131           48 :    output logic [63:0]                     lsu_axi_wdata,
-     132          512 :    output logic [7:0]                      lsu_axi_wstrb,
+     129          276 :    output logic                            lsu_axi_wvalid,
+     130          544 :    input  logic                            lsu_axi_wready,
+     131            0 :    output logic [63:0]                     lsu_axi_wdata,
+     132            4 :    output logic [7:0]                      lsu_axi_wstrb,
      133            2 :    output logic                            lsu_axi_wlast,
      134              : 
-     135         4340 :    input  logic                            lsu_axi_bvalid,
+     135          272 :    input  logic                            lsu_axi_bvalid,
      136            2 :    output logic                            lsu_axi_bready,
      137            0 :    input  logic [1:0]                      lsu_axi_bresp,
      138            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      139              : 
      140              :    // AXI Read Channels
-     141         3944 :    output logic                            lsu_axi_arvalid,
-     142         8290 :    input  logic                            lsu_axi_arready,
+     141          268 :    output logic                            lsu_axi_arvalid,
+     142          544 :    input  logic                            lsu_axi_arready,
      143            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     144            2 :    output logic [31:0]                     lsu_axi_araddr,
-     145            2 :    output logic [3:0]                      lsu_axi_arregion,
+     144            0 :    output logic [31:0]                     lsu_axi_araddr,
+     145            2 :    output logic [3:0]                      lsu_axi_arregion,
      146            0 :    output logic [7:0]                      lsu_axi_arlen,
      147            0 :    output logic [2:0]                      lsu_axi_arsize,
      148            0 :    output logic [1:0]                      lsu_axi_arburst,
@@ -255,10 +255,10 @@
      151            0 :    output logic [2:0]                      lsu_axi_arprot,
      152            0 :    output logic [3:0]                      lsu_axi_arqos,
      153              : 
-     154         4036 :    input  logic                            lsu_axi_rvalid,
+     154          268 :    input  logic                            lsu_axi_rvalid,
      155            2 :    output logic                            lsu_axi_rready,
      156            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     157            4 :    input  logic [63:0]                     lsu_axi_rdata,
+     157            8 :    input  logic [63:0]                     lsu_axi_rdata,
      158            0 :    input  logic [1:0]                      lsu_axi_rresp,
      159            2 :    input  logic                            lsu_axi_rlast,
      160              : 
@@ -276,33 +276,33 @@
      172            0 :    output logic                            dccm_dma_ecc_error,  // DMA load had ecc error
      173            0 :    output logic [2:0]                      dccm_dma_rtag,       // DMA request tag
      174            0 :    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
-     175         7858 :    output logic                            dccm_ready,          // lsu ready for DMA access
+     175          542 :    output logic                            dccm_ready,          // lsu ready for DMA access
      176              : 
      177              :    // DCCM ECC status
      178            0 :    output logic                            lsu_dccm_rd_ecc_single_err,
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182       404408 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183       404408 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182        15288 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183        15288 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
-     186          128 :     output logic [31:0] lsu_pmp_addr_start,
-     187          128 :     output logic [31:0] lsu_pmp_addr_end,
-     188         1238 :     input  logic        lsu_pmp_error_start,
-     189         1238 :     input  logic        lsu_pmp_error_end,
-     190         3968 :     output logic        lsu_pmp_we,
-     191         3944 :     output logic        lsu_pmp_re
+     186            0 :     output logic [31:0] lsu_pmp_addr_start,
+     187            0 :     output logic [31:0] lsu_pmp_addr_end,
+     188            0 :     input  logic        lsu_pmp_error_start,
+     189            0 :     input  logic        lsu_pmp_error_end,
+     190          272 :     output logic        lsu_pmp_we,
+     191          268 :     output logic        lsu_pmp_re
      192              : 
      193              :    );
      194              : 
      195            0 :    logic        lsu_dccm_rden_m;
      196            0 :    logic        lsu_dccm_rden_r;
-     197            8 :    logic [31:0] store_data_m;
-     198            8 :    logic [31:0] store_data_r;
-     199           28 :    logic [31:0] store_data_hi_r, store_data_lo_r;
-     200           28 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
-     201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
+     197            0 :    logic [31:0] store_data_m;
+     198            0 :    logic [31:0] store_data_r;
+     199            0 :    logic [31:0] store_data_hi_r, store_data_lo_r;
+     200            0 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
+     201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
      202            0 :    logic [31:0] sec_data_lo_r, sec_data_hi_r;
      203              : 
      204            0 :    logic [31:0] lsu_ld_data_m;
@@ -324,12 +324,12 @@
      220              : 
      221            0 :    logic [31:0] picm_mask_data_m;
      222              : 
-     223          128 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
-     224          128 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
+     223            0 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
+     224            0 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
      225              :   assign lsu_pmp_addr_start = lsu_addr_d;
      226              :   assign lsu_pmp_addr_end   = end_addr_d;
      227              : 
-     228         1432 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
+     228           16 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
      229            0 :    logic        lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
      230              :   assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
      231              :   assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
@@ -338,13 +338,13 @@
      234            0 :    logic        store_stbuf_reqvld_r;
      235            0 :    logic        ldst_stbuf_reqvld_r;
      236              : 
-     237         7856 :    logic        lsu_commit_r;
+     237          540 :    logic        lsu_commit_r;
      238            0 :    logic        lsu_exc_m;
      239              : 
      240            0 :    logic        addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
      241            0 :    logic        addr_in_pic_d, addr_in_pic_m, addr_in_pic_r;
-     242           12 :    logic        ldst_dual_d, ldst_dual_m, ldst_dual_r;
-     243            2 :    logic        addr_external_m;
+     242            0 :    logic        ldst_dual_d, ldst_dual_m, ldst_dual_r;
+     243            2 :    logic        addr_external_m;
      244              : 
      245            0 :    logic                          stbuf_reqvld_any;
      246            0 :    logic                          stbuf_reqvld_flushed_any;
@@ -365,11 +365,11 @@
      261            0 :    logic        lsu_stbuf_full_any;
      262              : 
      263              :     // Bus signals
-     264         7856 :    logic        lsu_busreq_r;
-     265         4168 :    logic        lsu_bus_buffer_pend_any;
-     266         6802 :    logic        lsu_bus_buffer_empty_any;
-     267            8 :    logic        lsu_bus_buffer_full_any;
-     268         7856 :    logic        lsu_busreq_m;
+     264          540 :    logic        lsu_busreq_r;
+     265          272 :    logic        lsu_bus_buffer_pend_any;
+     266          292 :    logic        lsu_bus_buffer_empty_any;
+     267            0 :    logic        lsu_bus_buffer_full_any;
+     268          540 :    logic        lsu_busreq_m;
      269            0 :    logic [31:0] bus_read_data_m;
      270              : 
      271            0 :    logic        flush_m_up, flush_r;
@@ -381,16 +381,16 @@
      277            0 :    logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
      278              : 
      279              :    // Clocks
-     280         6444 :    logic        lsu_busm_clken;
-     281        11768 :    logic        lsu_bus_obuf_c1_clken;
-     282       404408 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283       404408 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284       404408 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     280          278 :    logic        lsu_busm_clken;
+     281          812 :    logic        lsu_bus_obuf_c1_clken;
+     282        15288 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283        15288 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284        15288 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286       404408 :    logic        lsu_stbuf_c1_clk;
-     287       404408 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286        15288 :    logic        lsu_stbuf_c1_clk;
+     287        15288 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289       404408 :    logic        lsu_free_c2_clk;
+     289        15288 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_addrcheck.sv.html
index 0471eee4ca2..511232a48e0 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_addrcheck.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        24.0%
+    
+        14.0%
     
     
-        12
+        7
     
     
         50
@@ -131,18 +131,18 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30       404408 :    input logic          lsu_c2_m_clk,              // clock
+      30        15288 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
-      33          128 :    input logic [31:0]   start_addr_d,              // start address for lsu
-      34          128 :    input logic [31:0]   end_addr_d,                // end address for lsu
-      35         1432 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
+      33            0 :    input logic [31:0]   start_addr_d,              // start address for lsu
+      34            0 :    input logic [31:0]   end_addr_d,                // end address for lsu
+      35           16 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
       36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
-      37         2780 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
+      37          264 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
       38              : 
-      39          124 :    input logic [31:0]   rs1_d,                     // address rs operand
+      39            0 :    input logic [31:0]   rs1_d,                     // address rs operand
       40              : 
-      41            0 :    output logic         is_sideeffects_m,          // is sideffects space
+      41            0 :    output logic         is_sideeffects_m,          // is sideffects space
       42            0 :    output logic         addr_in_dccm_d,            // address in dccm
       43            0 :    output logic         addr_in_pic_d,             // address in pic
       44            2 :    output logic         addr_external_d,           // address in external
@@ -154,20 +154,20 @@
       50            0 :    output logic         fir_dccm_access_error_d,   // Fast interrupt dccm access error
       51            0 :    output logic         fir_nondccm_access_error_d,// Fast interrupt dccm access error
       52              : 
-      53         1238 :     input logic lsu_pmp_error_start,
-      54         1238 :     input logic lsu_pmp_error_end,
+      53            0 :     input logic lsu_pmp_error_start,
+      54            0 :     input logic lsu_pmp_error_end,
       55              : 
-      56            0 :    input  logic         scan_mode                  // Scan mode
+      56            0 :    input  logic         scan_mode                  // Scan mode
       57              : );
       58              : 
       59              : 
       60            0 :    logic        non_dccm_access_ok;
-      61           14 :    logic        is_sideeffects_d, is_aligned_d;
+      61            2 :    logic        is_sideeffects_d, is_aligned_d;
       62            0 :    logic        start_addr_in_dccm_d, end_addr_in_dccm_d;
       63            0 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
       64            0 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
       65            0 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
-      66         2780 :    logic [4:0]  csr_idx;
+      66          264 :    logic [4:0]  csr_idx;
       67            0 :    logic        addr_in_iccm;
       68            0 :    logic        start_addr_dccm_or_pic;
       69            0 :    logic        base_reg_dccm_or_pic;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_buffer.sv.html
index 7ee62d9e14a..963e6bc53c7 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_buffer.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        64.5%
+    
+        44.5%
     
     
-        165
+        114
     
     
         256
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31       404408 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        15288 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -142,74 +142,74 @@
       38            0 :    input logic                          dec_tlu_force_halt,
       39              : 
       40              :    // various clocks needed for the bus reads and writes
-      41        11768 :    input logic                          lsu_bus_obuf_c1_clken,
-      42         6444 :    input logic                          lsu_busm_clken,
-      43       404408 :    input logic                          lsu_c2_r_clk,
-      44       404408 :    input logic                          lsu_bus_ibuf_c1_clk,
+      41          812 :    input logic                          lsu_bus_obuf_c1_clken,
+      42          278 :    input logic                          lsu_busm_clken,
+      43        15288 :    input logic                          lsu_c2_r_clk,
+      44        15288 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46       404408 :    input logic                          lsu_bus_buf_c1_clk,
-      47       404408 :    input logic                          lsu_free_c2_clk,
+      46        15288 :    input logic                          lsu_bus_buf_c1_clk,
+      47        15288 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
-      51         7856 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
-      52         1432 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
-      53         1432 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
+      51          540 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
+      52           16 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
+      53           16 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
       54              : 
-      55          128 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
-      56          128 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
-      57          128 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
-      58          128 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
-      59            8 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
+      55            0 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
+      56            0 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
+      57            0 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
+      58            0 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
+      59            0 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
       60              : 
-      61          728 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
-      62          476 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
-      63         7856 :    input logic                          lsu_busreq_m,                   // bus request is in m
-      64         7856 :    output logic                         lsu_busreq_r,                   // bus request is in r
+      61            8 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
+      62            8 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
+      63          540 :    input logic                          lsu_busreq_m,                   // bus request is in m
+      64          540 :    output logic                         lsu_busreq_r,                   // bus request is in r
       65            0 :    input logic                          ld_full_hit_m,                  // load can get all its byte from a write buffer entry
-      66           64 :    input logic                          flush_m_up,                     // flush
+      66            4 :    input logic                          flush_m_up,                     // flush
       67            0 :    input logic                          flush_r,                        // flush
-      68         7856 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
+      68          540 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
       69            0 :    input logic                          is_sideeffects_r,               // lsu attribute is side_effects
-      70           12 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
-      71           12 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
-      72           12 :    input logic                          ldst_dual_r,                    // load/store is unaligned at 32 bit boundary
+      70            0 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
+      71            0 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
+      72            0 :    input logic                          ldst_dual_r,                    // load/store is unaligned at 32 bit boundary
       73              : 
-      74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
+      74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
       75              : 
-      76         4168 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
-      77            8 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
-      78         6802 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
+      76          272 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
+      77            0 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
+      78          292 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
       79              : 
       80            0 :    output logic [3:0]                   ld_byte_hit_buf_lo, ld_byte_hit_buf_hi,    // Byte enables for forwarding data
       81            0 :    output logic [31:0]                  ld_fwddata_buf_lo, ld_fwddata_buf_hi,      // load forwarding data
       82              : 
       83            0 :    output logic                         lsu_imprecise_error_load_any,     // imprecise load bus error
       84            0 :    output logic                         lsu_imprecise_error_store_any,    // imprecise store bus error
-      85            2 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
+      85            0 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
       86              : 
       87              :    // Non-blocking loads
-      88         3944 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
-      89         1424 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
+      88          268 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
+      89          252 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
       90            0 :    output logic                               lsu_nonblock_load_inv_r,       // invalidate signal for the cam entry for non block loads
-      91         1424 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
-      92         4032 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
+      91          252 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
+      92          268 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
       93            0 :    output logic                               lsu_nonblock_load_data_error,  // non block load has an error
-      94           36 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
-      95           16 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
+      94            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
+      95            0 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
       96              : 
       97              :    // PMU events
-      98         8288 :    output logic                         lsu_pmu_bus_trxn,
-      99           12 :    output logic                         lsu_pmu_bus_misaligned,
-     100            0 :    output logic                         lsu_pmu_bus_error,
-     101           32 :    output logic                         lsu_pmu_bus_busy,
+      98          544 :    output logic                         lsu_pmu_bus_trxn,
+      99            0 :    output logic                         lsu_pmu_bus_misaligned,
+     100            0 :    output logic                         lsu_pmu_bus_error,
+     101            0 :    output logic                         lsu_pmu_bus_busy,
      102              : 
      103              :    // AXI Write Channels
-     104         4340 :    output logic                            lsu_axi_awvalid,
-     105         8290 :    input  logic                            lsu_axi_awready,
+     104          276 :    output logic                            lsu_axi_awvalid,
+     105          544 :    input  logic                            lsu_axi_awready,
      106            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     107            2 :    output logic [31:0]                     lsu_axi_awaddr,
-     108            2 :    output logic [3:0]                      lsu_axi_awregion,
+     107            0 :    output logic [31:0]                     lsu_axi_awaddr,
+     108            2 :    output logic [3:0]                      lsu_axi_awregion,
      109            0 :    output logic [7:0]                      lsu_axi_awlen,
      110            0 :    output logic [2:0]                      lsu_axi_awsize,
      111            0 :    output logic [1:0]                      lsu_axi_awburst,
@@ -218,23 +218,23 @@
      114            0 :    output logic [2:0]                      lsu_axi_awprot,
      115            0 :    output logic [3:0]                      lsu_axi_awqos,
      116              : 
-     117         4340 :    output logic                            lsu_axi_wvalid,
-     118         8290 :    input  logic                            lsu_axi_wready,
-     119           48 :    output logic [63:0]                     lsu_axi_wdata,
-     120          512 :    output logic [7:0]                      lsu_axi_wstrb,
+     117          276 :    output logic                            lsu_axi_wvalid,
+     118          544 :    input  logic                            lsu_axi_wready,
+     119            0 :    output logic [63:0]                     lsu_axi_wdata,
+     120            4 :    output logic [7:0]                      lsu_axi_wstrb,
      121            2 :    output logic                            lsu_axi_wlast,
      122              : 
-     123         4340 :    input  logic                            lsu_axi_bvalid,
+     123          272 :    input  logic                            lsu_axi_bvalid,
      124            2 :    output logic                            lsu_axi_bready,
      125            0 :    input  logic [1:0]                      lsu_axi_bresp,
      126            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      127              : 
      128              :    // AXI Read Channels
-     129         3944 :    output logic                            lsu_axi_arvalid,
-     130         8290 :    input  logic                            lsu_axi_arready,
+     129          268 :    output logic                            lsu_axi_arvalid,
+     130          544 :    input  logic                            lsu_axi_arready,
      131            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     132            2 :    output logic [31:0]                     lsu_axi_araddr,
-     133            2 :    output logic [3:0]                      lsu_axi_arregion,
+     132            0 :    output logic [31:0]                     lsu_axi_araddr,
+     133            2 :    output logic [3:0]                      lsu_axi_arregion,
      134            0 :    output logic [7:0]                      lsu_axi_arlen,
      135            0 :    output logic [2:0]                      lsu_axi_arsize,
      136            0 :    output logic [1:0]                      lsu_axi_arburst,
@@ -243,10 +243,10 @@
      139            0 :    output logic [2:0]                      lsu_axi_arprot,
      140            0 :    output logic [3:0]                      lsu_axi_arqos,
      141              : 
-     142         4036 :    input  logic                            lsu_axi_rvalid,
+     142          268 :    input  logic                            lsu_axi_rvalid,
      143            2 :    output logic                            lsu_axi_rready,
      144            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     145            4 :    input  logic [63:0]                     lsu_axi_rdata,
+     145            8 :    input  logic [63:0]                     lsu_axi_rdata,
      146            0 :    input  logic [1:0]                      lsu_axi_rresp,
      147              : 
      148            2 :    input logic                             lsu_bus_clk_en,
@@ -264,7 +264,7 @@
      160              :    localparam TIMER_MAX = TIMER - 1;  // Maximum value of timer
      161              :    localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);
      162              : 
-     163         2280 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
+     163           76 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
      164            0 :    logic [DEPTH-1:0]                    ld_addr_hitvec_lo, ld_addr_hitvec_hi;
      165            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvec_lo, ld_byte_hitvec_hi;
      166            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;
@@ -273,187 +273,187 @@
      169            0 :    logic [3:0]                          ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;
      170              : 
      171            2 :    logic [3:0]                          ldst_byteen_r;
-     172         2280 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
-     173           28 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
-     174           14 :    logic                                is_aligned_r;                   // Aligned load/store
-     175            6 :    logic                                ldst_samedw_r;
+     172           76 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
+     173            0 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
+     174            2 :    logic                                is_aligned_r;                   // Aligned load/store
+     175            2 :    logic                                ldst_samedw_r;
      176              : 
-     177         3944 :    logic                                lsu_nonblock_load_valid_r;
-     178           68 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
-     179         1376 :    logic [1:0]                          lsu_nonblock_addr_offset;
-     180          216 :    logic [1:0]                          lsu_nonblock_sz;
-     181         2712 :    logic                                lsu_nonblock_unsign;
-     182         4032 :    logic                                lsu_nonblock_load_data_ready;
+     177          268 :    logic                                lsu_nonblock_load_valid_r;
+     178           76 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
+     179          124 :    logic [1:0]                          lsu_nonblock_addr_offset;
+     180            8 :    logic [1:0]                          lsu_nonblock_sz;
+     181          260 :    logic                                lsu_nonblock_unsign;
+     182          268 :    logic                                lsu_nonblock_load_data_ready;
      183              : 
      184            0 :    logic [DEPTH-1:0]                    CmdPtr0Dec, CmdPtr1Dec;
-     185            8 :    logic [DEPTH-1:0]                    RspPtrDec;
-     186            0 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
-     187           36 :    logic [DEPTH_LOG2-1:0]               RspPtr;
-     188         1424 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
-     189         1424 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
+     185            0 :    logic [DEPTH-1:0]                    RspPtrDec;
+     186            0 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
+     187            0 :    logic [DEPTH_LOG2-1:0]               RspPtr;
+     188          252 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
+     189          260 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
      190            0 :    logic                                found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;
      191            0 :    logic [3:0]                          buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;
-     192          212 :    logic                                any_done_wait_state;
+     192            4 :    logic                                any_done_wait_state;
      193            0 :    logic                                bus_sideeffect_pend;
      194            2 :    logic                                bus_coalescing_disable;
      195              : 
-     196          492 :    logic                                bus_addr_match_pending;
-     197         8288 :    logic                                bus_cmd_sent, bus_cmd_ready;
-     198         4340 :    logic                                bus_wcmd_sent, bus_wdata_sent;
-     199         4036 :    logic                                bus_rsp_read, bus_rsp_write;
+     196            4 :    logic                                bus_addr_match_pending;
+     197          544 :    logic                                bus_cmd_sent, bus_cmd_ready;
+     198          276 :    logic                                bus_wcmd_sent, bus_wdata_sent;
+     199          268 :    logic                                bus_rsp_read, bus_rsp_write;
      200            0 :    logic [pt.LSU_BUS_TAG-1:0]           bus_rsp_read_tag, bus_rsp_write_tag;
      201            0 :    logic                                bus_rsp_read_error, bus_rsp_write_error;
-     202            4 :    logic [63:0]                         bus_rsp_rdata;
+     202            8 :    logic [63:0]                         bus_rsp_rdata;
      203              : 
      204              :    // Bus buffer signals
-     205            8 :    state_t [DEPTH-1:0]                  buf_state;
-     206            2 :    logic   [DEPTH-1:0][1:0]             buf_sz;
-     207            0 :    logic   [DEPTH-1:0][31:0]            buf_addr;
-     208            2 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
-     209            0 :    logic   [DEPTH-1:0]                  buf_sideeffect;
+     205            0 :    state_t [DEPTH-1:0]                  buf_state;
+     206            0 :    logic   [DEPTH-1:0][1:0]             buf_sz;
+     207            0 :    logic   [DEPTH-1:0][31:0]            buf_addr;
+     208            0 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
+     209            0 :    logic   [DEPTH-1:0]                  buf_sideeffect;
      210            0 :    logic   [DEPTH-1:0]                  buf_write;
      211            0 :    logic   [DEPTH-1:0]                  buf_unsign;
      212            0 :    logic   [DEPTH-1:0]                  buf_dual;
-     213            2 :    logic   [DEPTH-1:0]                  buf_samedw;
-     214            0 :    logic   [DEPTH-1:0]                  buf_nomerge;
+     213            0 :    logic   [DEPTH-1:0]                  buf_samedw;
+     214            0 :    logic   [DEPTH-1:0]                  buf_nomerge;
      215            0 :    logic   [DEPTH-1:0]                  buf_dualhi;
-     216            2 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
-     217            8 :    logic   [DEPTH-1:0]                  buf_ldfwd;
-     218            8 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
-     219            0 :    logic   [DEPTH-1:0]                  buf_error;
+     216            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
+     217            0 :    logic   [DEPTH-1:0]                  buf_ldfwd;
+     218            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
+     219            0 :    logic   [DEPTH-1:0]                  buf_error;
      220            0 :    logic   [DEPTH-1:0][31:0]            buf_data;
      221            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age, buf_age_younger;
      222            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage, buf_rsp_pickage;
      223              : 
-     224            8 :    state_t [DEPTH-1:0]                  buf_nxtstate;
-     225            8 :    logic   [DEPTH-1:0]                  buf_rst;
-     226           16 :    logic   [DEPTH-1:0]                  buf_state_en;
-     227            8 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
-     228            8 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
-     229           16 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
-     230           12 :    logic   [DEPTH-1:0]                  buf_dual_in;
-     231            6 :    logic   [DEPTH-1:0]                  buf_samedw_in;
-     232          476 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
+     224            0 :    state_t [DEPTH-1:0]                  buf_nxtstate;
+     225            0 :    logic   [DEPTH-1:0]                  buf_rst;
+     226            0 :    logic   [DEPTH-1:0]                  buf_state_en;
+     227            0 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
+     228            0 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
+     229            0 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
+     230            0 :    logic   [DEPTH-1:0]                  buf_dual_in;
+     231            2 :    logic   [DEPTH-1:0]                  buf_samedw_in;
+     232            8 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
      233            0 :    logic   [DEPTH-1:0]                  buf_sideeffect_in;
-     234         3160 :    logic   [DEPTH-1:0]                  buf_unsign_in;
-     235         1432 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
-     236         3968 :    logic   [DEPTH-1:0]                  buf_write_in;
-     237            8 :    logic   [DEPTH-1:0]                  buf_wr_en;
-     238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
-     239         1424 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
-     240           16 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
-     241            8 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
-     242            8 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
-     243         2280 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
-     244          128 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
-     245           28 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
-     246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
-     247           16 :    logic   [DEPTH-1:0]                  buf_data_en;
-     248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
+     234          260 :    logic   [DEPTH-1:0]                  buf_unsign_in;
+     235           16 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
+     236          272 :    logic   [DEPTH-1:0]                  buf_write_in;
+     237            0 :    logic   [DEPTH-1:0]                  buf_wr_en;
+     238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
+     239          260 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
+     240            0 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
+     241            0 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
+     242            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
+     243           76 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
+     244            0 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
+     245            0 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
+     246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
+     247            0 :    logic   [DEPTH-1:0]                  buf_data_en;
+     248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
      249            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_ageQ;
      250            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage_set;
      251            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage_in;
      252            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspageQ;
      253              : 
      254              :    // Input buffer signals
-     255         3912 :    logic                               ibuf_valid;
+     255          272 :    logic                               ibuf_valid;
      256            0 :    logic                               ibuf_dual;
      257            2 :    logic                               ibuf_samedw;
      258            0 :    logic                               ibuf_nomerge;
-     259          152 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
-     260          152 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
+     259            4 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
+     260            4 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
      261            0 :    logic                               ibuf_sideeffect;
      262            0 :    logic                               ibuf_unsign;
      263            2 :    logic                               ibuf_write;
-     264           44 :    logic [1:0]                         ibuf_sz;
-     265          126 :    logic [3:0]                         ibuf_byteen;
+     264            4 :    logic [1:0]                         ibuf_sz;
+     265            2 :    logic [3:0]                         ibuf_byteen;
      266            0 :    logic [31:0]                        ibuf_addr;
-     267           76 :    logic [31:0]                        ibuf_data;
-     268         3914 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
+     267            0 :    logic [31:0]                        ibuf_data;
+     268          274 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
      269              : 
-     270         4316 :    logic                               ibuf_byp;
-     271         3912 :    logic                               ibuf_wr_en;
-     272         3912 :    logic                               ibuf_rst;
+     270          272 :    logic                               ibuf_byp;
+     271          272 :    logic                               ibuf_wr_en;
+     272          272 :    logic                               ibuf_rst;
      273            0 :    logic                               ibuf_force_drain;
-     274         3912 :    logic                               ibuf_drain_vld;
+     274          272 :    logic                               ibuf_drain_vld;
      275            0 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
-     276         1424 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
-     277         1424 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
-     278         1432 :    logic [1:0]                         ibuf_sz_in;
-     279          128 :    logic [31:0]                        ibuf_addr_in;
-     280         2280 :    logic [3:0]                         ibuf_byteen_in;
-     281           28 :    logic [31:0]                        ibuf_data_in;
-     282         3914 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
-     283          126 :    logic [3:0]                         ibuf_byteen_out;
-     284           76 :    logic [31:0]                        ibuf_data_out;
-     285           14 :    logic                               ibuf_merge_en, ibuf_merge_in;
+     276          252 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
+     277          252 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
+     278           16 :    logic [1:0]                         ibuf_sz_in;
+     279            0 :    logic [31:0]                        ibuf_addr_in;
+     280           76 :    logic [3:0]                         ibuf_byteen_in;
+     281            0 :    logic [31:0]                        ibuf_data_in;
+     282          274 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
+     283            2 :    logic [3:0]                         ibuf_byteen_out;
+     284            0 :    logic [31:0]                        ibuf_data_out;
+     285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
      286              : 
      287              :    // Output buffer signals
-     288         8228 :    logic                               obuf_valid;
-     289         2774 :    logic                               obuf_write;
-     290          212 :    logic                               obuf_nosend;
-     291         3944 :    logic                               obuf_rdrsp_pend;
+     288          544 :    logic                               obuf_valid;
+     289          266 :    logic                               obuf_write;
+     290            4 :    logic                               obuf_nosend;
+     291          268 :    logic                               obuf_rdrsp_pend;
      292            0 :    logic                               obuf_sideeffect;
-     293            2 :    logic [31:0]                        obuf_addr;
-     294           48 :    logic [63:0]                        obuf_data;
-     295          216 :    logic [1:0]                         obuf_sz;
-     296         1276 :    logic [7:0]                         obuf_byteen;
-     297            8 :    logic                               obuf_merge;
-     298            0 :    logic                               obuf_cmd_done, obuf_data_done;
+     293            0 :    logic [31:0]                        obuf_addr;
+     294            0 :    logic [63:0]                        obuf_data;
+     295            8 :    logic [1:0]                         obuf_sz;
+     296           40 :    logic [7:0]                         obuf_byteen;
+     297            0 :    logic                               obuf_merge;
+     298            0 :    logic                               obuf_cmd_done, obuf_data_done;
      299            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0;
      300            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1;
      301            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag;
      302              : 
-     303         4064 :    logic                               ibuf_buf_byp;
+     303          272 :    logic                               ibuf_buf_byp;
      304            0 :    logic                               obuf_force_wr_en;
      305            0 :    logic                               obuf_wr_wait;
-     306         8232 :    logic                               obuf_wr_en, obuf_wr_enQ;
-     307         8228 :    logic                               obuf_rst;
-     308         2802 :    logic                               obuf_write_in;
-     309         3080 :    logic                               obuf_nosend_in;
+     306          544 :    logic                               obuf_wr_en, obuf_wr_enQ;
+     307          544 :    logic                               obuf_rst;
+     308          266 :    logic                               obuf_write_in;
+     309           16 :    logic                               obuf_nosend_in;
      310            2 :    logic                               obuf_rdrsp_pend_en;
-     311         3944 :    logic                               obuf_rdrsp_pend_in;
+     311          268 :    logic                               obuf_rdrsp_pend_in;
      312            0 :    logic                               obuf_sideeffect_in;
-     313           14 :    logic                               obuf_aligned_in;
-     314            2 :    logic [31:0]                        obuf_addr_in;
-     315          132 :    logic [63:0]                        obuf_data_in;
-     316          216 :    logic [1:0]                         obuf_sz_in;
-     317         1324 :    logic [7:0]                         obuf_byteen_in;
-     318           12 :    logic                               obuf_merge_in;
-     319            0 :    logic                               obuf_cmd_done_in, obuf_data_done_in;
+     313            2 :    logic                               obuf_aligned_in;
+     314            0 :    logic [31:0]                        obuf_addr_in;
+     315            4 :    logic [63:0]                        obuf_data_in;
+     316            8 :    logic [1:0]                         obuf_sz_in;
+     317           40 :    logic [7:0]                         obuf_byteen_in;
+     318            0 :    logic                               obuf_merge_in;
+     319            0 :    logic                               obuf_cmd_done_in, obuf_data_done_in;
      320            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0_in;
      321            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1_in;
      322            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag_in;
      323              : 
-     324           12 :    logic                               obuf_merge_en;
-     325            0 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
-     326          812 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
-     327          130 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
+     324            0 :    logic                               obuf_merge_en;
+     325            0 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
+     326           16 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
+     327            4 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
      328              : 
-     329         4340 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
-     330         4340 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
-     331         3944 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
+     329          276 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
+     330          276 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
+     331          268 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
      332            2 :    logic                               lsu_axi_bvalid_q, lsu_axi_bready_q;
      333            2 :    logic                               lsu_axi_rvalid_q, lsu_axi_rready_q;
      334            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_axi_bid_q, lsu_axi_rid_q;
      335            0 :    logic [1:0]                         lsu_axi_bresp_q, lsu_axi_rresp_q;
      336            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_imprecise_error_store_tag;
-     337            4 :    logic [63:0]                        lsu_axi_rdata_q;
+     337            8 :    logic [63:0]                        lsu_axi_rdata_q;
      338              : 
      339              :    //------------------------------------------------------------------------------
      340              :    // Load forwarding logic start
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344       322154 :    function automatic logic [2:0] f_Enc8to3;
+     344       167714 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348       322154 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349       322154 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350       322154 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348       167714 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349       167714 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350       167714 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352       322154 :       return Enc_value[2:0];
+     352       167714 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -672,11 +672,11 @@
      568              : 
      569              :       // Find second write pointer
      570            2 :       for (int i=0; i<DEPTH; i++) begin
-     571           14 :          if (~found_wrptr1) begin
-     572           14 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     573           14 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     574           14 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
-     575           14 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     571            8 :          if (~found_wrptr1) begin
+     572            8 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     573            8 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     574            8 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
+     575            8 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      576              :          end
      577              :       end
      578              :    end
@@ -758,71 +758,71 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657       362756 :             IDLE: begin
-     658       362756 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659       362756 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660       362756 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661       362756 :                      buf_wr_en[i]    = buf_state_en[i];
-     662       362756 :                      buf_data_en[i]  = buf_state_en[i];
-     663       362756 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664       362756 :                      buf_cmd_state_bus_en[i]  = '0;
+     657       188038 :             IDLE: begin
+     658       188038 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659       188038 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660       188038 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661       188038 :                      buf_wr_en[i]    = buf_state_en[i];
+     662       188038 :                      buf_data_en[i]  = buf_state_en[i];
+     663       188038 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664       188038 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         6386 :             CMD: begin
-     672         6386 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         6386 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         6386 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         6386 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         6386 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         6386 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         6386 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         6386 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         6386 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         6386 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671         3398 :             CMD: begin
+     672         3398 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673         3398 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674         3398 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675         3398 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676         3398 :                      buf_ldfwd_in[i]          = 1'b1;
+     677         3398 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678         3398 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679         3398 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680         3398 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681         3398 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683        13412 :             RESP: begin
-     684        13412 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685        13412 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686        13412 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687        13412 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688        13412 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689        13412 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690        13412 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691        13412 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692        13412 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693        13412 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694        13412 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695        13412 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683         7176 :             RESP: begin
+     684         7176 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685         7176 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686         7176 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687         7176 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688         7176 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689         7176 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690         7176 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691         7176 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692         7176 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693         7176 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694         7176 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695         7176 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697        13412 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698        13412 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699        13412 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700        13412 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701        13412 :                      buf_cmd_state_bus_en[i]  = '0;
+     697         7176 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698         7176 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699         7176 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700         7176 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701         7176 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
-     703            4 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
-     704            4 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
-     705            4 :                      buf_state_bus_en[i]       = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
-     706            4 :                                                                  (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
-     707            4 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     708            4 :                      buf_cmd_state_bus_en[i]  = '0;
+     703            2 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
+     704            2 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
+     705            2 :                      buf_state_bus_en[i]       = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
+     706            2 :                                                                  (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
+     707            2 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     708            2 :                      buf_cmd_state_bus_en[i]  = '0;
      709              :             end
-     710          106 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
-     711          106 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
-     712          106 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
-     713          106 :                       buf_cmd_state_bus_en[i]  = '0;
+     710           54 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
+     711           54 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
+     712           54 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
+     713           54 :                       buf_cmd_state_bus_en[i]  = '0;
      714              :             end
-     715         2128 :             DONE: begin
-     716         2128 :                      buf_nxtstate[i]           = IDLE;
-     717         2128 :                      buf_rst[i]                = 1'b1;
-     718         2128 :                      buf_state_en[i]           = 1'b1;
-     719         2128 :                      buf_ldfwd_in[i]           = 1'b0;
-     720         2128 :                      buf_ldfwd_en[i]           = buf_state_en[i];
-     721         2128 :                      buf_cmd_state_bus_en[i]  = '0;
+     715         1132 :             DONE: begin
+     716         1132 :                      buf_nxtstate[i]           = IDLE;
+     717         1132 :                      buf_rst[i]                = 1'b1;
+     718         1132 :                      buf_state_en[i]           = 1'b1;
+     719         1132 :                      buf_ldfwd_in[i]           = 1'b0;
+     720         1132 :                      buf_ldfwd_en[i]           = buf_state_en[i];
+     721         1132 :                      buf_cmd_state_bus_en[i]  = '0;
      722              :             end
      723            0 :             default : begin
      724            0 :                      buf_nxtstate[i]          = IDLE;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_intf.sv.html
index 183f1cb781d..e0bc8a780a2 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_bus_intf.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        57.4%
+    
+        42.6%
     
     
-        66
+        49
     
     
         115
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30       404408 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        15288 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -140,72 +140,72 @@
       36            0 :    input logic                          dec_tlu_sideeffect_posted_disable,  // disable the posted sideeffect load store to the bus
       37              : 
       38              :    // various clocks needed for the bus reads and writes
-      39        11768 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
-      40         6444 :    input logic                          lsu_busm_clken,                     // bus clock enable
+      39          812 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
+      40          278 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42       404408 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43       404408 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44       404408 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42        15288 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43        15288 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44        15288 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46       404408 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47       404408 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48       404408 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46        15288 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47        15288 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48        15288 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
-      51         7856 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
-      52         7856 :    input logic                          lsu_busreq_m,                      // bus request is in m
+      51          540 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
+      52          540 :    input logic                          lsu_busreq_m,                      // bus request is in m
       53              : 
-      54         1432 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
-      55         1432 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
+      54           16 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
+      55           16 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
       56              : 
-      57          128 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
-      58          128 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
+      57            0 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
+      58            0 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
       59              : 
-      60          128 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
-      61          128 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
+      60            0 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
+      61            0 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
       62              : 
-      63            8 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
-      64            0 :    input logic                          dec_tlu_force_halt,
+      63            0 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
+      64            0 :    input logic                          dec_tlu_force_halt,
       65              : 
-      66         7856 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
+      66          540 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
       67            0 :    input logic                          is_sideeffects_m,                  // lsu attribute is side_effects
-      68           64 :    input logic                          flush_m_up,                        // flush
+      68            4 :    input logic                          flush_m_up,                        // flush
       69            0 :    input logic                          flush_r,                           // flush
-      70           12 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
+      70            0 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71              : 
-      72         7856 :    output logic                         lsu_busreq_r,                      // bus request is in r
-      73         4168 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      74            8 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
-      75         6802 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
+      72          540 :    output logic                         lsu_busreq_r,                      // bus request is in r
+      73          272 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      74            0 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
+      75          292 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
       76            0 :    output logic [31:0]                  bus_read_data_m,                   // the bus return data
       77              : 
       78              : 
       79            0 :    output logic                         lsu_imprecise_error_load_any,      // imprecise load bus error
       80            0 :    output logic                         lsu_imprecise_error_store_any,     // imprecise store bus error
-      81            2 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
+      81            0 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
       82              : 
       83              :    // Non-blocking loads
-      84         3944 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
-      85         1424 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
+      84          268 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
+      85          252 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
       86            0 :    output logic                               lsu_nonblock_load_inv_r,     // invalidate signal for the cam entry for non block loads
-      87         1424 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
-      88         4032 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
+      87          252 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
+      88          268 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
       89            0 :    output logic                               lsu_nonblock_load_data_error,// non block load has an error
-      90           36 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
-      91           16 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
+      90            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
+      91            0 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
       92              : 
       93              :    // PMU events
-      94         8288 :    output logic                         lsu_pmu_bus_trxn,
-      95           12 :    output logic                         lsu_pmu_bus_misaligned,
-      96            0 :    output logic                         lsu_pmu_bus_error,
-      97           32 :    output logic                         lsu_pmu_bus_busy,
+      94          544 :    output logic                         lsu_pmu_bus_trxn,
+      95            0 :    output logic                         lsu_pmu_bus_misaligned,
+      96            0 :    output logic                         lsu_pmu_bus_error,
+      97            0 :    output logic                         lsu_pmu_bus_busy,
       98              : 
       99              :    // AXI Write Channels
-     100         4340 :    output logic                        lsu_axi_awvalid,
-     101         8290 :    input  logic                        lsu_axi_awready,
+     100          276 :    output logic                        lsu_axi_awvalid,
+     101          544 :    input  logic                        lsu_axi_awready,
      102            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_awid,
-     103            2 :    output logic [31:0]                 lsu_axi_awaddr,
-     104            2 :    output logic [3:0]                  lsu_axi_awregion,
+     103            0 :    output logic [31:0]                 lsu_axi_awaddr,
+     104            2 :    output logic [3:0]                  lsu_axi_awregion,
      105            0 :    output logic [7:0]                  lsu_axi_awlen,
      106            0 :    output logic [2:0]                  lsu_axi_awsize,
      107            0 :    output logic [1:0]                  lsu_axi_awburst,
@@ -214,23 +214,23 @@
      110            0 :    output logic [2:0]                  lsu_axi_awprot,
      111            0 :    output logic [3:0]                  lsu_axi_awqos,
      112              : 
-     113         4340 :    output logic                        lsu_axi_wvalid,
-     114         8290 :    input  logic                        lsu_axi_wready,
-     115           48 :    output logic [63:0]                 lsu_axi_wdata,
-     116          512 :    output logic [7:0]                  lsu_axi_wstrb,
+     113          276 :    output logic                        lsu_axi_wvalid,
+     114          544 :    input  logic                        lsu_axi_wready,
+     115            0 :    output logic [63:0]                 lsu_axi_wdata,
+     116            4 :    output logic [7:0]                  lsu_axi_wstrb,
      117            2 :    output logic                        lsu_axi_wlast,
      118              : 
-     119         4340 :    input  logic                        lsu_axi_bvalid,
+     119          272 :    input  logic                        lsu_axi_bvalid,
      120            2 :    output logic                        lsu_axi_bready,
      121            0 :    input  logic [1:0]                  lsu_axi_bresp,
      122            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_bid,
      123              : 
      124              :    // AXI Read Channels
-     125         3944 :    output logic                        lsu_axi_arvalid,
-     126         8290 :    input  logic                        lsu_axi_arready,
+     125          268 :    output logic                        lsu_axi_arvalid,
+     126          544 :    input  logic                        lsu_axi_arready,
      127            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_arid,
-     128            2 :    output logic [31:0]                 lsu_axi_araddr,
-     129            2 :    output logic [3:0]                  lsu_axi_arregion,
+     128            0 :    output logic [31:0]                 lsu_axi_araddr,
+     129            2 :    output logic [3:0]                  lsu_axi_arregion,
      130            0 :    output logic [7:0]                  lsu_axi_arlen,
      131            0 :    output logic [2:0]                  lsu_axi_arsize,
      132            0 :    output logic [1:0]                  lsu_axi_arburst,
@@ -239,10 +239,10 @@
      135            0 :    output logic [2:0]                  lsu_axi_arprot,
      136            0 :    output logic [3:0]                  lsu_axi_arqos,
      137              : 
-     138         4036 :    input  logic                        lsu_axi_rvalid,
+     138          268 :    input  logic                        lsu_axi_rvalid,
      139            2 :    output logic                        lsu_axi_rready,
      140            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_rid,
-     141            4 :    input  logic [63:0]                 lsu_axi_rdata,
+     141            8 :    input  logic [63:0]                 lsu_axi_rdata,
      142            0 :    input  logic [1:0]                  lsu_axi_rresp,
      143              : 
      144            2 :    input logic                         lsu_bus_clk_en
@@ -256,16 +256,16 @@
      152            2 :    logic [3:0]        ldst_byteen_m, ldst_byteen_r;
      153            0 :    logic [7:0]        ldst_byteen_ext_m, ldst_byteen_ext_r;
      154            0 :    logic [3:0]        ldst_byteen_hi_m, ldst_byteen_hi_r;
-     155         2280 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
+     155           76 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
      156            0 :    logic              is_sideeffects_r;
      157              : 
-     158           76 :    logic [63:0]       store_data_ext_r;
-     159            0 :    logic [31:0]       store_data_hi_r;
-     160           28 :    logic [31:0]       store_data_lo_r;
+     158            0 :    logic [63:0]       store_data_ext_r;
+     159            0 :    logic [31:0]       store_data_hi_r;
+     160            0 :    logic [31:0]       store_data_lo_r;
      161              : 
-     162         8350 :    logic              addr_match_dw_lo_r_m;
-     163         7858 :    logic              addr_match_word_lo_r_m;
-     164          476 :    logic              no_word_merge_r, no_dword_merge_r;
+     162          546 :    logic              addr_match_dw_lo_r_m;
+     163          542 :    logic              addr_match_word_lo_r_m;
+     164            8 :    logic              no_word_merge_r, no_dword_merge_r;
      165              : 
      166            0 :    logic              ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
      167            0 :    logic [3:0]        ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
@@ -282,7 +282,7 @@
      178            0 :    logic [63:0]       ld_fwddata_lo, ld_fwddata_hi;
      179            0 :    logic [63:0]       ld_fwddata_m;
      180              : 
-     181            4 :    logic              ld_full_hit_hi_m, ld_full_hit_lo_m;
+     181            2 :    logic              ld_full_hit_hi_m, ld_full_hit_lo_m;
      182            0 :    logic              ld_full_hit_m;
      183              : 
      184              :    assign ldst_byteen_m[3:0] = ({4{lsu_pkt_m.by}}   & 4'b0001) |
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_clkdomain.sv.html
index b097fbb4de5..e844b037ee0 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31       404408 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32       404408 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31        15288 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32        15288 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -144,52 +144,52 @@
       40              : 
       41            0 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
       42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
-      43         7856 :    input logic      lsu_busreq_r,                      // busreq in r
-      44         4168 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      45         6802 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
+      43          540 :    input logic      lsu_busreq_r,                      // busreq in r
+      44          272 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      45          292 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
       46            2 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
       47              : 
       48            2 :    input logic      lsu_bus_clk_en,                    // bus clock enable
       49              : 
-      50         1432 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
-      51         1432 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
-      52         1432 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
-      53         1432 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
+      50           16 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
+      51           16 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
+      52           16 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
+      53           16 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
       54              : 
       55              :    // Outputs
-      56        11768 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
-      57         6444 :    output logic     lsu_busm_clken,                    // bus clock enable
+      56          812 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
+      57          278 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59       404408 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60       404408 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59        15288 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60        15288 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62       404408 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63       404408 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62        15288 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63        15288 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65       404408 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66       404408 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65        15288 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66        15288 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68       404408 :    output logic     lsu_stbuf_c1_clk,
+      68        15288 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70       404408 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71       404408 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70        15288 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71        15288 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74       404408 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74        15288 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
       78              : 
-      79         7856 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
-      80         7856 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
-      81         7856 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
-      82         3968 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
+      79          540 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
+      80          540 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
+      81          540 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
+      82          272 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
       83              : 
       84              : 
       85            0 :    logic lsu_stbuf_c1_clken;
-      86         6444 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
+      86          278 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
       87              : 
-      88         6272 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
+      88          278 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
       89              : 
       90              :    //-------------------------------------------------------------------------------------------
       91              :    // Clock Enable logic
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_ctl.sv.html
index 28f7da69f5b..59a0e2a3366 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        25.0%
+    
+        10.7%
     
     
-        28
+        12
     
     
         112
@@ -136,40 +136,40 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35       404408 :    input logic                             lsu_c2_m_clk,            // clocks
-      36       404408 :    input logic                             lsu_c2_r_clk,            // clocks
-      37       404408 :    input logic                             lsu_c1_r_clk,            // clocks
-      38       404408 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39       404408 :    input logic                             lsu_free_c2_clk,         // clocks
+      35        15288 :    input logic                             lsu_c2_m_clk,            // clocks
+      36        15288 :    input logic                             lsu_c2_r_clk,            // clocks
+      37        15288 :    input logic                             lsu_c1_r_clk,            // clocks
+      38        15288 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39        15288 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41       404408 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41        15288 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
-      45         1432 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
-      46         1432 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
-      47         1432 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
+      45           16 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
+      46           16 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
+      47           16 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
       48            0 :    input logic                             addr_in_dccm_d,          // address maps to dccm
       49            0 :    input logic                             addr_in_pic_d,           // address maps to pic
       50            0 :    input logic                             addr_in_pic_m,           // address maps to pic
       51            0 :    input logic                             addr_in_dccm_m, addr_in_dccm_r,   // address in dccm per pipe stage
       52            0 :    input logic                             addr_in_pic_r,                    // address in pic  per pipe stage
       53            0 :    input logic                             lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
-      54         7856 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
-      55           12 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
+      54          540 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
+      55            0 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
       56              : 
       57              :    // lsu address down the pipe
-      58          128 :    input logic [31:0]                      lsu_addr_d,
-      59          128 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
-      60          128 :    input logic [31:0]                      lsu_addr_r,
+      58            0 :    input logic [31:0]                      lsu_addr_d,
+      59            0 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
+      60            0 :    input logic [31:0]                      lsu_addr_r,
       61              : 
       62              :    // lsu address down the pipe - needed to check unaligned
-      63          128 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
-      64          128 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
-      65          128 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
+      63            0 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
+      64            0 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
+      65            0 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
       66              : 
       67              : 
-      68            0 :    input logic                             stbuf_reqvld_any,        // write enable
+      68            0 :    input logic                             stbuf_reqvld_any,        // write enable
       69            0 :    input logic [pt.LSU_SB_BITS-1:0]        stbuf_addr_any,          // stbuf address (aligned)
       70              : 
       71            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    stbuf_data_any,          // the read out from stbuf
@@ -206,8 +206,8 @@
      102            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_hi_m,           // corrected dccm data
      103            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_lo_m,           // corrected dccm data
      104              : 
-     105            8 :    input logic [31:0]                      store_data_m,            // Store data M-stage
-     106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
+     105            0 :    input logic [31:0]                      store_data_m,            // Store data M-stage
+     106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
      107            0 :    input logic                             dma_pic_wen,             // Perform PIC writes
      108            0 :    input logic [2:0]                       dma_mem_tag_m,           // DMA Buffer entry number M-stage
      109            0 :    input logic [31:0]                      dma_mem_addr,            // DMA request address
@@ -218,11 +218,11 @@
      114            0 :    input logic [pt.DCCM_ECC_WIDTH-1:0]     dma_dccm_wdata_ecc_lo,   // ECC bits for the DMA wdata
      115              : 
      116            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_hi_r,
-     117           28 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
-     118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
-     119           28 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
-     120            8 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
-     121            0 :    output logic                            ld_single_ecc_error_r,
+     117            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
+     118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
+     119            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
+     120            0 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
+     121            0 :    output logic                            ld_single_ecc_error_r,
      122            0 :    output logic                            ld_single_ecc_error_r_ff,
      123              : 
      124            0 :    output logic [31:0]                     picm_mask_data_m,        // pic data to stbuf
@@ -240,9 +240,9 @@
      136            0 :    output logic                            dccm_rden,               // dccm interface -- write
      137            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo,         // dccm interface -- wr addr for lo bank
      138            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi,         // dccm interface -- wr addr for hi bank
-     139          128 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
-     140          128 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
-     141            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,         // dccm write data for lo bank
+     139            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
+     140            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
+     141            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,         // dccm write data for lo bank
      142            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,         // dccm write data for hi bank
      143              : 
      144            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_rd_data_lo,         // dccm read data back from the dccm
@@ -252,10 +252,10 @@
      148            0 :    output logic                            picm_wren,               // write to pic
      149            0 :    output logic                            picm_rden,               // read to pick
      150            0 :    output logic                            picm_mken,               // write to pic need a mask
-     151            2 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
-     152            2 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
-     153           28 :    output logic [31:0]                     picm_wr_data,            // write data
-     154            0 :    input logic [31:0]                      picm_rd_data,            // read data
+     151            0 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
+     152            0 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
+     153            0 :    output logic [31:0]                     picm_wr_data,            // write data
+     154            0 :    input logic [31:0]                      picm_rd_data,            // read data
      155              : 
      156            0 :    input logic                             scan_mode                // scan mode
      157              : );
@@ -277,7 +277,7 @@
      173            0 :    logic                           kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
      174              : 
      175              :     // byte_en flowing down
-     176          704 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
+     176            8 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
      177            0 :    logic [7:0]                     store_byteen_ext_m, store_byteen_ext_r;
      178              : 
      179              :    if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_mem.sv.html
index 2d057707c49..02971644bb1 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_dccm_mem.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        30.8%
+    
+        19.2%
     
     
-        8
+        5
     
     
         26
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35       404408 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36       404408 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35        15288 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        15288 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
@@ -145,9 +145,9 @@
       41            0 :    input logic         dccm_rden,                                       // read enable
       42            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,                     // write address
       43            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,                     // write address
-      44          128 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
-      45          128 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
-      46            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,              // write data
+      44            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
+      45            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
+      46            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,              // write data
       47            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,              // write data
       48              :    el2_mem_if.veer_dccm                   dccm_mem_export,              // RAM repositioned in testbench and connected by this interface
       49              : 
@@ -164,16 +164,16 @@
       60              : 
       61            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        wren_bank;
       62            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        rden_bank;
-      63          128 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
-      64            0 :    logic [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+DCCM_WIDTH_BITS)]           rd_addr_even, rd_addr_odd;
+      63            0 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
+      64            0 :    logic [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+DCCM_WIDTH_BITS)]           rd_addr_even, rd_addr_odd;
       65            0 :    logic                                                                rd_unaligned, wr_unaligned;
       66            0 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0]              dccm_bank_dout;
       67            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]                                      wrdata;
       68              : 
       69            0 :    logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0]               wr_data_bank;
       70              : 
-      71         2712 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
-      72         2716 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
+      71          148 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
+      72          148 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
       73              : 
       74            0 :    logic [pt.DCCM_NUM_BANKS-1:0]            dccm_clken;
       75              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_ecc.sv.html
index dcce367bb77..2c6ebe99436 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_ecc.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        15.3%
+    
+        8.5%
     
     
-        9
+        5
     
     
         59
@@ -135,23 +135,23 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34       404408 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35       404408 :    input logic                           lsu_c2_r_clk,       // clock
+      34        15288 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        15288 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
       39              : 
-      40         1432 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
-      41         1432 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
+      40           16 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
+      41           16 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
       42            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  stbuf_data_any,
       43              : 
       44            0 :    input logic                           dec_tlu_core_ecc_disable,  // disables the ecc computation and error flagging
       45              : 
       46            0 :    input logic                           lsu_dccm_rden_r,          // dccm rden
       47            0 :    input logic                           addr_in_dccm_r,           // address in dccm
-      48          128 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
-      49          128 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
-      50            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r,          // data from the dccm
+      48            0 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
+      49            0 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
+      50            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r,          // data from the dccm
       51            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r,          // data from the dccm
       52            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_r,       // data from the dccm + ecc
       53            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_lo_r,       // data from the dccm + ecc
@@ -164,9 +164,9 @@
       60            0 :    input logic                           ld_single_ecc_error_r_ff,  // ld has a single ecc error
       61            0 :    input logic                           lsu_dccm_rden_m,           // dccm rden
       62            0 :    input logic                           addr_in_dccm_m,            // address in dccm
-      63          128 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
-      64          128 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
-      65            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m,           // raw data from mem
+      63            0 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
+      64            0 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
+      65            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m,           // raw data from mem
       66            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m,           // raw data from mem
       67            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_m,        // ecc read out from mem
       68            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_lo_m,        // ecc read out from mem
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_lsc_ctl.sv.html
index cc601fd342d..e61fd0aa1fe 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_lsc_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.6%
+    
+        21.2%
     
     
-        43
+        18
     
     
         85
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35       404408 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        15288 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38       404408 :    input logic                lsu_c1_m_clk,
-      39       404408 :    input logic                lsu_c1_r_clk,
-      40       404408 :    input logic                lsu_c2_m_clk,
-      41       404408 :    input logic                lsu_c2_r_clk,
-      42       404408 :    input logic                lsu_store_c1_m_clk,
+      38        15288 :    input logic                lsu_c1_m_clk,
+      39        15288 :    input logic                lsu_c1_r_clk,
+      40        15288 :    input logic                lsu_c2_m_clk,
+      41        15288 :    input logic                lsu_c2_r_clk,
+      42        15288 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
@@ -154,38 +154,38 @@
       50            0 :    input logic                lsu_single_ecc_error_m,    // ECC single bit error M-stage
       51            0 :    input logic                lsu_double_ecc_error_m,    // ECC double bit error M-stage
       52              : 
-      53           64 :    input logic                flush_m_up,                // Flush M and D stage
+      53            4 :    input logic                flush_m_up,                // Flush M and D stage
       54            0 :    input logic                flush_r,                   // Flush R-stage
-      55           12 :    input logic                ldst_dual_d,               // load/store is unaligned at 32 bit boundary D-stage
-      56           12 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
-      57           12 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
+      55            0 :    input logic                ldst_dual_d,               // load/store is unaligned at 32 bit boundary D-stage
+      56            0 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
+      57            0 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
       58              : 
-      59          124 :    input logic [31:0]         exu_lsu_rs1_d,             // address
-      60            8 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
+      59            0 :    input logic [31:0]         exu_lsu_rs1_d,             // address
+      60            0 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
       61              : 
-      62         1432 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
-      63         7856 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
-      64          484 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
+      62           16 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
+      63          540 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
+      64            0 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
       65              : 
-      66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
+      66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
       67            0 :    input  logic [31:0]        bus_read_data_m,           // the bus return data
       68            0 :    output logic [31:0]        lsu_result_m,              // lsu load data
       69            0 :    output logic [31:0]        lsu_result_corr_r,         // This is the ECC corrected data going to RF
       70              :    // lsu address down the pipe
-      71          128 :    output logic [31:0]        lsu_addr_d,
-      72          128 :    output logic [31:0]        lsu_addr_m,
-      73          128 :    output logic [31:0]        lsu_addr_r,
+      71            0 :    output logic [31:0]        lsu_addr_d,
+      72            0 :    output logic [31:0]        lsu_addr_m,
+      73            0 :    output logic [31:0]        lsu_addr_r,
       74              :    // lsu address down the pipe - needed to check unaligned
-      75          128 :    output logic [31:0]        end_addr_d,
-      76          128 :    output logic [31:0]        end_addr_m,
-      77          128 :    output logic [31:0]        end_addr_r,
+      75            0 :    output logic [31:0]        end_addr_d,
+      76            0 :    output logic [31:0]        end_addr_m,
+      77            0 :    output logic [31:0]        end_addr_r,
       78              :    // store data down the pipe
-      79            8 :    output logic [31:0]        store_data_m,
+      79            0 :    output logic [31:0]        store_data_m,
       80              : 
-      81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
+      81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
       82            0 :    output logic                lsu_exc_m,                // Access or misaligned fault
       83            0 :    output logic                is_sideeffects_m,         // is sideffects space
-      84         7856 :    output logic                lsu_commit_r,             // lsu instruction in r commits
+      84          540 :    output logic                lsu_commit_r,             // lsu instruction in r commits
       85            0 :    output logic                lsu_single_ecc_error_incr,// LSU inc SB error counter
       86            0 :    output el2_lsu_error_pkt_t lsu_error_pkt_r,          // lsu exception packet
       87              : 
@@ -211,26 +211,26 @@
      107            0 :    input logic [63:0]         dma_mem_wdata,
      108              : 
      109              :    // Store buffer related signals
-     110         1432 :    output el2_lsu_pkt_t      lsu_pkt_d,
-     111         1432 :    output el2_lsu_pkt_t      lsu_pkt_m,
-     112         1432 :    output el2_lsu_pkt_t      lsu_pkt_r,
+     110           16 :    output el2_lsu_pkt_t      lsu_pkt_d,
+     111           16 :    output el2_lsu_pkt_t      lsu_pkt_m,
+     112           16 :    output el2_lsu_pkt_t      lsu_pkt_r,
      113              : 
-     114         1238 :     input logic lsu_pmp_error_start,
-     115         1238 :     input logic lsu_pmp_error_end,
+     114            0 :     input logic lsu_pmp_error_start,
+     115            0 :     input logic lsu_pmp_error_end,
      116              : 
-     117            0 :    input  logic               scan_mode                  // Scan mode
+     117            0 :    input  logic               scan_mode                  // Scan mode
      118              : 
      119              :    );
      120              : 
-     121            2 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
-     122          128 :    logic [31:0]        full_addr_d;
-     123          128 :    logic [31:0]        full_end_addr_d;
-     124          124 :    logic [31:0]        lsu_rs1_d;
-     125          484 :    logic [11:0]        lsu_offset_d;
-     126          124 :    logic [31:0]        rs1_d;
-     127          484 :    logic [11:0]        offset_d;
-     128          484 :    logic [12:0]        end_addr_offset_d;
-     129            0 :    logic [2:0]         addr_offset_d;
+     121            0 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
+     122            0 :    logic [31:0]        full_addr_d;
+     123            0 :    logic [31:0]        full_end_addr_d;
+     124            0 :    logic [31:0]        lsu_rs1_d;
+     125            0 :    logic [11:0]        lsu_offset_d;
+     126            0 :    logic [31:0]        rs1_d;
+     127            0 :    logic [11:0]        offset_d;
+     128            0 :    logic [12:0]        end_addr_offset_d;
+     129            0 :    logic [2:0]         addr_offset_d;
      130              : 
      131            0 :    logic [63:0]        dma_mem_wdata_shifted;
      132            2 :    logic               addr_external_d;
@@ -242,12 +242,12 @@
      138            0 :    logic               fir_dccm_access_error_m, fir_nondccm_access_error_m;
      139              : 
      140            0 :    logic [3:0]         exc_mscause_d, exc_mscause_m;
-     141          124 :    logic [31:0]        rs1_d_raw;
-     142            8 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
-     143            0 :    logic [31:0]        bus_read_data_r;
+     141            0 :    logic [31:0]        rs1_d_raw;
+     142            0 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
+     143            0 :    logic [31:0]        bus_read_data_r;
      144              : 
      145            0 :    el2_lsu_pkt_t           dma_pkt_d;
-     146         1432 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
+     146           16 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
      147            0 :    el2_lsu_error_pkt_t     lsu_error_pkt_m;
      148              : 
      149              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_stbuf.sv.html
index beb48f5e58d..b87700deb52 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_stbuf.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.9%
+    
+        14.5%
     
     
-        22
+        11
     
     
         76
@@ -137,23 +137,23 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36       404408 :    input logic                           clk,                         // core clock
+      36        15288 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39       404408 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40       404408 :    input logic                           lsu_free_c2_clk,             // free clk
+      39        15288 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40        15288 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
-      44         7856 :    input logic                           lsu_commit_r,                // lsu commits
-      45         7856 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
+      44          540 :    input logic                           lsu_commit_r,                // lsu commits
+      45          540 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
       46            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_hi_r,             // merged data from the dccm for stores. This is used for fwding
-      47           28 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
-      48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
-      49           28 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
+      47            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
+      48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
+      49            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
       50              : 
       51              :    // Store Buffer output
-      52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
+      52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
       53            0 :    output logic                          stbuf_reqvld_flushed_any,    // Top entry is flushed
       54            0 :    output logic [pt.LSU_SB_BITS-1:0]     stbuf_addr_any,              // address
       55            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any,              // stbuf data
@@ -163,22 +163,22 @@
       59            2 :    output logic                          lsu_stbuf_empty_any,         // stbuf is empty
       60            0 :    output logic                          ldst_stbuf_reqvld_r,         // needed for clocking
       61              : 
-      62          128 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
-      63          128 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
-      64          128 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
+      62            0 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
+      63            0 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
+      64            0 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
       65              : 
-      66          128 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
-      67          128 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
-      68          128 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
+      66            0 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
+      67            0 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
+      68            0 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
       69              : 
-      70           12 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
-      71            0 :    input logic                           addr_in_dccm_m,              // address is in dccm
+      70            0 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
+      71            0 :    input logic                           addr_in_dccm_m,              // address is in dccm
       72            0 :    input logic                           addr_in_dccm_r,              // address is in dccm
       73              : 
       74              :    // Forwarding signals
       75            0 :    input logic                           lsu_cmpen_m,                 // needed for forwarding stbuf - load
-      76         1432 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
-      77         1432 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
+      76           16 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
+      77           16 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
       78              : 
       79            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m,          // stbuf data
       80            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m,          // stbuf data
@@ -206,13 +206,13 @@
      102            0 :    logic [DEPTH-1:0]                     stbuf_wr_en;
      103            0 :    logic [DEPTH-1:0]                     stbuf_dma_kill_en;
      104            0 :    logic [DEPTH-1:0]                     stbuf_reset;
-     105          128 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
-     106            0 :    logic [DEPTH-1:0][DATA_WIDTH-1:0]     stbuf_datain;
+     105            0 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
+     106            0 :    logic [DEPTH-1:0][DATA_WIDTH-1:0]     stbuf_datain;
      107            0 :    logic [DEPTH-1:0][BYTE_WIDTH-1:0]     stbuf_byteenin;
      108              : 
      109            0 :    logic [7:0]             store_byteen_ext_r;
      110            0 :    logic [BYTE_WIDTH-1:0]  store_byteen_hi_r;
-     111          804 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
+     111            8 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
      112              : 
      113            0 :    logic                   WrPtrEn, RdPtrEn;
      114            0 :    logic [DEPTH_LOG2-1:0]  WrPtr, RdPtr;
@@ -225,10 +225,10 @@
      121            0 :    logic [3:0]             stbuf_numvld_any, stbuf_specvld_any;
      122            0 :    logic [1:0]             stbuf_specvld_m, stbuf_specvld_r;
      123              : 
-     124          128 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
+     124            0 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
      125              : 
      126              :    // variables to detect matching from the store queue
-     127            0 :    logic [DEPTH-1:0]                 stbuf_match_hi, stbuf_match_lo;
+     127            0 :    logic [DEPTH-1:0]                 stbuf_match_hi, stbuf_match_lo;
      128            0 :    logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_fwdbyteenvec_hi, stbuf_fwdbyteenvec_lo;
      129            0 :    logic [DATA_WIDTH-1:0]            stbuf_fwddata_hi_pre_m, stbuf_fwddata_lo_pre_m;
      130            0 :    logic [BYTE_WIDTH-1:0]            stbuf_fwdbyteen_hi_pre_m, stbuf_fwdbyteen_lo_pre_m;
@@ -241,7 +241,7 @@
      137            0 :    logic [BYTE_WIDTH-1:0]  ld_byte_hit_hi, ld_byte_rhit_hi;
      138              : 
      139            0 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_hi_r;
-     140         2280 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
+     140           76 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
      141              :    // byte_en flowing down
      142            0 :    logic [7:0]             ldst_byteen_r;
      143            0 :    logic [7:0]             ldst_byteen_ext_r;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_trigger.sv.html
index 0d19c7edf62..220d0f9cdbc 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_lsu_trigger.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        40.0%
+    
+        20.0%
     
     
-        4
+        2
     
     
         10
@@ -132,11 +132,11 @@
       28              : `include "el2_param.vh"
       29              :  )(
       30            0 :    input el2_trigger_pkt_t [3:0] trigger_pkt_any,            // trigger packet from dec
-      31         1432 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
-      32          128 :    input logic [31:0]             lsu_addr_m,                 // address
-      33            8 :    input logic [31:0]             store_data_m,               // store data
+      31           16 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
+      32            0 :    input logic [31:0]             lsu_addr_m,                 // address
+      33            0 :    input logic [31:0]             store_data_m,               // store data
       34              : 
-      35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
+      35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
       36              : );
       37              : 
       38            0 :    logic               trigger_enable;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem.sv.html
index 0dc3504669b..0b417b5d692 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        22.9%
+    
+        18.8%
     
     
-        11
+        9
     
     
         48
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25       404408 :    input logic         clk,
+      25        15288 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -137,9 +137,9 @@
       33            0 :    input logic         dccm_rden,
       34            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,
       35            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,
-      36          128 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
-      37          128 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
-      38            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
+      36            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
+      37            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
+      38            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
       39            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
       40              : 
       41              : 
@@ -147,7 +147,7 @@
       43            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
       44              : 
       45              :    //ICCM ports
-      46          152 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
+      46            8 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
       47            0 :    input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
       48            0 :    input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
       49            0 :    input logic         iccm_wren,
@@ -164,12 +164,12 @@
       60            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
       61            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
       62            0 :    input  logic         ic_rd_en,
-      63         5364 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-      64        20614 :    input  logic         ic_sel_premux_data, // Premux data sel
+      63           62 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+      64          734 :    input  logic         ic_sel_premux_data, // Premux data sel
       65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
       66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
       67              : 
-      68         1164 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+      68            6 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
       69            0 :    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
       70            0 :    output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       71            0 :    input  logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -178,7 +178,7 @@
       74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
       75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
       76              : 
-      77         5364 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      77           62 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
       79              : 
       80              : 
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92       404408 :    logic active_clk;
+      92        15288 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem_if.sv.html
index 0df734e06ee..040002e4636 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_mem_if.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        20.0%
+    
+        13.3%
     
     
-        3
+        2
     
     
         15
@@ -130,14 +130,14 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29       577188 :   logic                                                               clk;
+      29        22212 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
       33              :   // ICCM
       34            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
       35            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_wren_bank;
-      36          456 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
+      36           24 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
       37              : 
       38            0 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_wr_data;
       39            0 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
@@ -149,8 +149,8 @@
       45              :   // DCCM
       46            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_clken;
       47            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
-      48          384 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
-      49            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
+      48            0 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
+      49            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
       50            0 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
       51            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
       52            0 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_pic_ctrl.sv.html
index d6d0c2ccfdc..6facb727293 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_pic_ctrl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        24.1%
+    
+        17.6%
     
     
-        26
+        19
     
     
         108
@@ -131,16 +131,16 @@
       27              :  )
       28              :                   (
       29              : 
-      30       404408 :                      input  logic                   clk,                  // Core clock
-      31       404408 :                      input  logic                   free_clk,             // free clock
+      30        15288 :                      input  logic                   clk,                  // Core clock
+      31        15288 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
       35            0 :                      input  logic [pt.PIC_TOTAL_INT_PLUS1-1:0]   extintsrc_req,  // Interrupt requests
-      36            2 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
-      37            2 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
-      38           28 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
-      39            0 :                      input  logic                   picm_wren,            // Write enable to the register
+      36            0 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
+      37            0 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
+      38            0 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
+      39            0 :                      input  logic                   picm_wren,            // Write enable to the register
       40            0 :                      input  logic                   picm_rden,            // Read enable for the register
       41            0 :                      input  logic                   picm_mken,            // Read the Mask for the register
       42            0 :                      input  logic [3:0]             meicurpl,             // Current Priority Level
@@ -185,11 +185,11 @@
       81              : 
       82            0 : logic  raddr_config_pic_match ;
       83            0 : logic  raddr_intenable_base_match;
-      84         5078 : logic  raddr_intpriority_base_match;
+      84          278 : logic  raddr_intpriority_base_match;
       85            0 : logic  raddr_config_gw_base_match ;
       86              : 
       87            0 : logic  waddr_config_pic_match ;
-      88         5078 : logic  waddr_intpriority_base_match;
+      88          278 : logic  waddr_intpriority_base_match;
       89            0 : logic  waddr_intenable_base_match;
       90            0 : logic  waddr_config_gw_base_match ;
       91            0 : logic  addr_clear_gw_base_match ;
@@ -228,16 +228,16 @@
      124            0 : logic                                        intpriord;
      125            0 : logic                                        config_reg_we ;
      126            0 : logic                                        config_reg_re ;
-     127         1560 : logic                                        config_reg_in ;
+     127          116 : logic                                        config_reg_in ;
      128            0 : logic                                        prithresh_reg_write , prithresh_reg_read;
      129            0 : logic                                        intpriority_reg_read ;
      130            0 : logic                                        intenable_reg_read   ;
      131            0 : logic                                        gw_config_reg_read   ;
      132            0 : logic                                        picm_wren_ff , picm_rden_ff ;
-     133            2 : logic [31:0]                                 picm_raddr_ff;
-     134            2 : logic [31:0]                                 picm_waddr_ff;
-     135           28 : logic [31:0]                                 picm_wr_data_ff;
-     136            0 : logic [3:0]                                  mask;
+     133            0 : logic [31:0]                                 picm_raddr_ff;
+     134            0 : logic [31:0]                                 picm_waddr_ff;
+     135            0 : logic [31:0]                                 picm_wr_data_ff;
+     136            0 : logic [3:0]                                  mask;
      137            0 : logic                                        picm_mken_ff;
      138            0 : logic [ID_BITS-1:0]                          claimid_in ;
      139            0 : logic [INTPRIORITY_BITS-1:0]                 pl_in ;
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155       404408 :    logic                                     pic_raddr_c1_clk;
-     156       404408 :    logic                                     pic_data_c1_clk;
-     157       404408 :    logic                                     pic_pri_c1_clk;
-     158       404408 :    logic                                     pic_int_c1_clk;
-     159       404408 :    logic                                     gw_config_c1_clk;
+     155        15288 :    logic                                     pic_raddr_c1_clk;
+     156        15288 :    logic                                     pic_data_c1_clk;
+     157        15288 :    logic                                     pic_pri_c1_clk;
+     158        15288 :    logic                                     pic_int_c1_clk;
+     159        15288 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500      3078336 :               if (intenable_reg_re[i]) begin
+     500      1598400 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503      3078336 :               if (intpriority_reg_re[i]) begin
+     503      1598400 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506      3078336 :               if (gw_config_reg_re[i]) begin
+     506      1598400 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -627,7 +627,7 @@
      523              : 
      524              : assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0] ;
      525              : 
-     526          128 : logic [14:0] address;
+     526            0 : logic [14:0] address;
      527              : 
      528              : assign address[14:0] = picm_raddr_ff[14:0];
      529              : 
@@ -639,7 +639,7 @@
      535              : module el2_cmp_and_mux #(parameter ID_BITS=8,
      536              :                                INTPRIORITY_BITS = 4)
      537              :                     (
-     538           10 :                         input  logic [ID_BITS-1:0]       a_id,
+     538           10 :                         input  logic [ID_BITS-1:0]       a_id,
      539            0 :                         input  logic [INTPRIORITY_BITS-1:0] a_priority,
      540              : 
      541            2 :                         input  logic [ID_BITS-1:0]       b_id,
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562      5964276 :                              input logic rawclk,
+     562       229524 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_pmp.sv.html
index b57e30406a7..1d0ca4064e2 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        60.0%
+    
+        35.7%
     
     
-        12
+        5
     
     
-        20
+        14
     
 
             
@@ -127,33 +127,33 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26       404408 :     input logic clk,       // Top level clock
+      26        15288 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35           18 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36           18 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36              :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
-      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
+      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
       40              :     input logic             [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],
       41              : 
-      42          128 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
-      43            0 :     input  el2_pmp_type_pkt_t        pmp_chan_type[PMP_CHANNELS],
-      44         1238 :     output logic                     pmp_chan_err [PMP_CHANNELS]
+      42            0 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
+      43            0 :     input  el2_pmp_type_pkt_t        pmp_chan_type[PMP_CHANNELS],
+      44            0 :     output logic                     pmp_chan_err [PMP_CHANNELS]
       45              : );
       46              : 
       47              :   logic [                33:0]                     csr_pmp_addr_i          [pt.PMP_ENTRIES];
-      48          128 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
+      48            0 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
       49              : 
       50              :   logic [                33:0]                     region_start_addr       [pt.PMP_ENTRIES];
       51              :   logic [33:PMP_GRANULARITY+2]                     region_addr_mask        [pt.PMP_ENTRIES];
-      52            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;
+      52            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;
       53            0 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;
       54            4 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;
       55            0 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60            2 :   logic any_region_enabled;
+      60              :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133      5798880 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133      3026880 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139      5798880 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139      3026880 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            3 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       367458 :       if (!matched && match_all[r]) begin
-     170       367458 :         access_fail = ~final_perm_check[r];
-     171       367458 :         matched = 1'b1;
+     169       191502 :       if (!matched && match_all[r]) begin
+     170       191502 :         access_fail = ~final_perm_check[r];
+     171       191502 :         matched = 1'b1;
      172              :       end
      173              :     end
      174            6 :     return access_fail;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223           18 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -348,12 +348,12 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247      4329366 :           OFF:     region_match_all[c][r] = 1'b0;
+     247      2248206 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250       288138 :           TOR: begin
-     251       288138 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252       288138 :                                      region_match_lt[c][r];
+     250       149394 :           TOR: begin
+     251       149394 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252       149394 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer.sv.html
index 889172d0db6..e7983aaa15b 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        35.3%
+    
+        30.1%
     
     
-        223
+        189
     
     
-        631
+        627
     
 
             
@@ -130,7 +130,7 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29       404408 :    input logic                  clk,
+      29        15288 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
@@ -138,19 +138,19 @@
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37       404408 :    output logic                 active_l2clk,
-      38       404408 :    output logic                 free_l2clk,
+      37        15288 :    output logic                 active_l2clk,
+      38        15288 :    output logic                 free_l2clk,
       39              : 
-      40         2908 :    output logic [31:0] trace_rv_i_insn_ip,
+      40           12 :    output logic [31:0] trace_rv_i_insn_ip,
       41            2 :    output logic [31:0] trace_rv_i_address_ip,
-      42        25728 :    output logic   trace_rv_i_valid_ip,
-      43           28 :    output logic   trace_rv_i_exception_ip,
-      44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
+      42          996 :    output logic   trace_rv_i_valid_ip,
+      43            0 :    output logic   trace_rv_i_exception_ip,
+      44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
       45            0 :    output logic   trace_rv_i_interrupt_ip,
-      46            4 :    output logic [31:0] trace_rv_i_tval_ip,
+      46            0 :    output logic [31:0] trace_rv_i_tval_ip,
       47              : 
       48              : 
-      49            0 :    output logic                 dccm_clk_override,
+      49            0 :    output logic                 dccm_clk_override,
       50            0 :    output logic                 icm_clk_override,
       51            0 :    output logic                 dec_tlu_core_ecc_disable,
       52              : 
@@ -182,16 +182,16 @@
       78            0 :    output logic                          dccm_rden,
       79            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_lo,
       80            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_hi,
-      81          128 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
-      82          128 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
-      83            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
+      81            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
+      82            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
+      83            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
       84            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_hi,
       85              : 
       86            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_lo,
       87            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_hi,
       88              : 
       89              :    // ICCM ports
-      90          152 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
+      90            8 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
       91            0 :    output logic                  iccm_wren,
       92            0 :    output logic                  iccm_rden,
       93            0 :    output logic [2:0]            iccm_wr_size,
@@ -208,16 +208,16 @@
      104            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_wr_en,
      105            0 :    output logic                  ic_rd_en,
      106              : 
-     107         1164 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     108         5364 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     107            6 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     108           62 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      109            0 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      112              : 
      113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
      114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     115         5364 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     116        20614 :    output logic                      ic_sel_premux_data, // Select premux data
+     115           62 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     116          734 :    output logic                      ic_sel_premux_data, // Select premux data
      117              : 
      118              : 
      119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -233,11 +233,11 @@
      129              : 
      130              :    //-------------------------- LSU AXI signals--------------------------
      131              :    // AXI Write Channels
-     132         4340 :    output logic                            lsu_axi_awvalid,
+     132          276 :    output logic                            lsu_axi_awvalid,
      133            0 :    input  logic                            lsu_axi_awready,
      134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
-     135            2 :    output logic [31:0]                     lsu_axi_awaddr,
-     136            2 :    output logic [3:0]                      lsu_axi_awregion,
+     135            0 :    output logic [31:0]                     lsu_axi_awaddr,
+     136            2 :    output logic [3:0]                      lsu_axi_awregion,
      137            0 :    output logic [7:0]                      lsu_axi_awlen,
      138            0 :    output logic [2:0]                      lsu_axi_awsize,
      139            0 :    output logic [1:0]                      lsu_axi_awburst,
@@ -246,10 +246,10 @@
      142            0 :    output logic [2:0]                      lsu_axi_awprot,
      143            0 :    output logic [3:0]                      lsu_axi_awqos,
      144              : 
-     145         4340 :    output logic                            lsu_axi_wvalid,
+     145          276 :    output logic                            lsu_axi_wvalid,
      146            0 :    input  logic                            lsu_axi_wready,
-     147           48 :    output logic [63:0]                     lsu_axi_wdata,
-     148          512 :    output logic [7:0]                      lsu_axi_wstrb,
+     147            0 :    output logic [63:0]                     lsu_axi_wdata,
+     148            4 :    output logic [7:0]                      lsu_axi_wstrb,
      149            2 :    output logic                            lsu_axi_wlast,
      150              : 
      151            0 :    input  logic                            lsu_axi_bvalid,
@@ -258,11 +258,11 @@
      154            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      155              : 
      156              :    // AXI Read Channels
-     157         3944 :    output logic                            lsu_axi_arvalid,
+     157          268 :    output logic                            lsu_axi_arvalid,
      158            0 :    input  logic                            lsu_axi_arready,
      159            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
-     160            2 :    output logic [31:0]                     lsu_axi_araddr,
-     161            2 :    output logic [3:0]                      lsu_axi_arregion,
+     160            0 :    output logic [31:0]                     lsu_axi_araddr,
+     161            2 :    output logic [3:0]                      lsu_axi_arregion,
      162            0 :    output logic [7:0]                      lsu_axi_arlen,
      163            0 :    output logic [2:0]                      lsu_axi_arsize,
      164            0 :    output logic [1:0]                      lsu_axi_arburst,
@@ -305,10 +305,10 @@
      201            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      202              : 
      203              :    // AXI Read Channels
-     204        26024 :    output logic                            ifu_axi_arvalid,
+     204          996 :    output logic                            ifu_axi_arvalid,
      205            0 :    input  logic                            ifu_axi_arready,
-     206        17884 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-     207         3188 :    output logic [31:0]                     ifu_axi_araddr,
+     206           88 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     207           56 :    output logic [31:0]                     ifu_axi_araddr,
      208            2 :    output logic [3:0]                      ifu_axi_arregion,
      209            0 :    output logic [7:0]                      ifu_axi_arlen,
      210            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -419,24 +419,24 @@
      315            0 :    output logic                  hmastlock,
      316            0 :    output logic [3:0]            hprot,
      317            0 :    output logic [2:0]            hsize,
-     318        26024 :    output logic [1:0]            htrans,
+     318          996 :    output logic [1:0]            htrans,
      319            0 :    output logic                  hwrite,
      320              : 
-     321         2300 :    input  logic [63:0]           hrdata,
+     321           24 :    input  logic [63:0]           hrdata,
      322            2 :    input  logic                  hready,
      323            0 :    input  logic                  hresp,
      324              : 
      325              :    // LSU AHB Master
-     326            2 :    output logic [31:0]          lsu_haddr,
-     327            0 :    output logic [2:0]           lsu_hburst,
+     326            0 :    output logic [31:0]          lsu_haddr,
+     327            0 :    output logic [2:0]           lsu_hburst,
      328            0 :    output logic                 lsu_hmastlock,
      329            0 :    output logic [3:0]           lsu_hprot,
      330            0 :    output logic [2:0]           lsu_hsize,
-     331         8284 :    output logic [1:0]           lsu_htrans,
-     332         2774 :    output logic                 lsu_hwrite,
-     333            4 :    output logic [63:0]          lsu_hwdata,
+     331          544 :    output logic [1:0]           lsu_htrans,
+     332          266 :    output logic                 lsu_hwrite,
+     333           48 :    output logic [63:0]          lsu_hwdata,
      334              : 
-     335            4 :    input  logic [63:0]          lsu_hrdata,
+     335            8 :    input  logic [63:0]          lsu_hrdata,
      336            2 :    input  logic                 lsu_hready,
      337            0 :    input  logic                 lsu_hresp,
      338              : 
@@ -496,12 +496,12 @@
      392              : 
      393              : 
      394              : 
-     395         2176 :    logic [63:0]                  hwdata_nc;
+     395           16 :    logic [63:0]                  hwdata_nc;
      396              :    //----------------------------------------------------------------------
      397              :    //
      398              :    //----------------------------------------------------------------------
      399              : 
-     400        25728 :    logic                         ifu_pmu_instr_aligned;
+     400          998 :    logic                         ifu_pmu_instr_aligned;
      401            0 :    logic                         ifu_ic_error_start;
      402            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
      403            0 :    logic                         ifu_iccm_rd_ecc_single_err;
@@ -509,55 +509,55 @@
      405            0 :    logic                         lsu_dccm_rd_ecc_single_err;
      406            0 :    logic                         lsu_dccm_rd_ecc_double_err;
      407              : 
-     408         8290 :    logic                         lsu_axi_awready_ahb;
-     409         8290 :    logic                         lsu_axi_wready_ahb;
-     410         4340 :    logic                         lsu_axi_bvalid_ahb;
+     408          544 :    logic                         lsu_axi_awready_ahb;
+     409          544 :    logic                         lsu_axi_wready_ahb;
+     410          272 :    logic                         lsu_axi_bvalid_ahb;
      411            0 :    logic                         lsu_axi_bready_ahb;
      412            0 :    logic [1:0]                   lsu_axi_bresp_ahb;
      413            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
-     414         8290 :    logic                         lsu_axi_arready_ahb;
-     415         4036 :    logic                         lsu_axi_rvalid_ahb;
+     414          544 :    logic                         lsu_axi_arready_ahb;
+     415          268 :    logic                         lsu_axi_rvalid_ahb;
      416            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
-     417            4 :    logic [63:0]                  lsu_axi_rdata_ahb;
+     417            8 :    logic [63:0]                  lsu_axi_rdata_ahb;
      418            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
      419            2 :    logic                         lsu_axi_rlast_ahb;
      420              : 
-     421         8290 :    logic                         lsu_axi_awready_int;
-     422         8290 :    logic                         lsu_axi_wready_int;
-     423         4340 :    logic                         lsu_axi_bvalid_int;
+     421          544 :    logic                         lsu_axi_awready_int;
+     422          544 :    logic                         lsu_axi_wready_int;
+     423          272 :    logic                         lsu_axi_bvalid_int;
      424            0 :    logic                         lsu_axi_bready_int;
      425            0 :    logic [1:0]                   lsu_axi_bresp_int;
      426            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
-     427         8290 :    logic                         lsu_axi_arready_int;
-     428         4036 :    logic                         lsu_axi_rvalid_int;
+     427          544 :    logic                         lsu_axi_arready_int;
+     428          268 :    logic                         lsu_axi_rvalid_int;
      429            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
-     430            4 :    logic [63:0]                  lsu_axi_rdata_int;
+     430            8 :    logic [63:0]                  lsu_axi_rdata_int;
      431            0 :    logic [1:0]                   lsu_axi_rresp_int;
      432            2 :    logic                         lsu_axi_rlast_int;
      433              : 
-     434        26026 :    logic                         ifu_axi_awready_ahb;
-     435        26026 :    logic                         ifu_axi_wready_ahb;
+     434          996 :    logic                         ifu_axi_awready_ahb;
+     435          996 :    logic                         ifu_axi_wready_ahb;
      436            0 :    logic                         ifu_axi_bvalid_ahb;
      437            0 :    logic                         ifu_axi_bready_ahb;
      438            0 :    logic [1:0]                   ifu_axi_bresp_ahb;
-     439         5542 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
-     440        26026 :    logic                         ifu_axi_arready_ahb;
-     441        52048 :    logic                         ifu_axi_rvalid_ahb;
-     442         5542 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
-     443         2300 :    logic [63:0]                  ifu_axi_rdata_ahb;
+     439           48 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
+     440          996 :    logic                         ifu_axi_arready_ahb;
+     441         1990 :    logic                         ifu_axi_rvalid_ahb;
+     442           48 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
+     443           24 :    logic [63:0]                  ifu_axi_rdata_ahb;
      444            0 :    logic [1:0]                   ifu_axi_rresp_ahb;
      445            2 :    logic                         ifu_axi_rlast_ahb;
      446              : 
-     447        26026 :    logic                         ifu_axi_awready_int;
-     448        26026 :    logic                         ifu_axi_wready_int;
+     447          996 :    logic                         ifu_axi_awready_int;
+     448          996 :    logic                         ifu_axi_wready_int;
      449            0 :    logic                         ifu_axi_bvalid_int;
      450            0 :    logic                         ifu_axi_bready_int;
      451            0 :    logic [1:0]                   ifu_axi_bresp_int;
-     452         5542 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
-     453        26026 :    logic                         ifu_axi_arready_int;
-     454        52048 :    logic                         ifu_axi_rvalid_int;
-     455         5542 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
-     456         2300 :    logic [63:0]                  ifu_axi_rdata_int;
+     452           48 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
+     453          996 :    logic                         ifu_axi_arready_int;
+     454         1990 :    logic                         ifu_axi_rvalid_int;
+     455           48 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
+     456           24 :    logic [63:0]                  ifu_axi_rdata_int;
      457            0 :    logic [1:0]                   ifu_axi_rresp_int;
      458            2 :    logic                         ifu_axi_rlast_int;
      459              : 
@@ -636,13 +636,13 @@
      532            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
      533              : 
      534              : 
-     535        21740 :    logic         dec_i0_rs1_en_d;
-     536        11480 :    logic         dec_i0_rs2_en_d;
-     537           12 :    logic  [31:0] gpr_i0_rs1_d;
+     535          680 :    logic         dec_i0_rs1_en_d;
+     536          280 :    logic         dec_i0_rs2_en_d;
+     537            8 :    logic  [31:0] gpr_i0_rs1_d;
      538            4 :    logic  [31:0] gpr_i0_rs2_d;
      539              : 
      540           12 :    logic [31:0] dec_i0_result_r;
-     541          688 :    logic [31:0] exu_i0_result_x;
+     541           16 :    logic [31:0] exu_i0_result_x;
      542            2 :    logic [31:1] exu_i0_pc_x;
      543            2 :    logic [31:1] exu_npc_r;
      544              : 
@@ -653,79 +653,79 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552         1380 :    logic [31:0] dec_i0_immed_d;
-     553          920 :    logic [12:1] dec_i0_br_immed_d;
-     554          760 :    logic         dec_i0_select_pc_d;
+     552           20 :    logic [31:0] dec_i0_immed_d;
+     553            8 :    logic [12:1] dec_i0_br_immed_d;
+     554           28 :    logic         dec_i0_select_pc_d;
      555              : 
      556           10 :    logic [31:1] dec_i0_pc_d;
-     557          648 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
+     557          244 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
      558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
-     560        18816 :    logic         dec_i0_alu_decode_d;
-     561         8364 :    logic         dec_i0_branch_d;
+     560          474 :    logic         dec_i0_alu_decode_d;
+     561          534 :    logic         dec_i0_branch_d;
      562              : 
-     563        26024 :    logic         ifu_miss_state_idle;
+     563          996 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
      565            0 :    logic         dec_tlu_flush_leak_one_r;
      566            0 :    logic         dec_tlu_flush_err_r;
-     567        25052 :    logic         ifu_i0_valid;
-     568          540 :    logic [31:0]  ifu_i0_instr;
+     567          754 :    logic         ifu_i0_valid;
+     568           16 :    logic [31:0]  ifu_i0_instr;
      569           10 :    logic [31:1]  ifu_i0_pc;
      570              : 
-     571         1240 :    logic        exu_flush_final;
+     571          110 :    logic        exu_flush_final;
      572              : 
-     573          220 :    logic [31:1] exu_flush_path_final;
+     573           16 :    logic [31:1] exu_flush_path_final;
      574              : 
-     575          124 :    logic [31:0] exu_lsu_rs1_d;
-     576            8 :    logic [31:0] exu_lsu_rs2_d;
+     575            0 :    logic [31:0] exu_lsu_rs1_d;
+     576            0 :    logic [31:0] exu_lsu_rs2_d;
      577              : 
      578              : 
-     579         1432 :    el2_lsu_pkt_t    lsu_p;
-     580        18878 :    logic             dec_qual_lsu_d;
+     579           16 :    el2_lsu_pkt_t    lsu_p;
+     580          712 :    logic             dec_qual_lsu_d;
      581              : 
-     582         7856 :    logic        dec_lsu_valid_raw_d;
-     583          484 :    logic [11:0] dec_lsu_offset_d;
+     582          540 :    logic        dec_lsu_valid_raw_d;
+     583            0 :    logic [11:0] dec_lsu_offset_d;
      584              : 
-     585            0 :    logic [31:0]  lsu_result_m;
+     585            0 :    logic [31:0]  lsu_result_m;
      586            0 :    logic [31:0]  lsu_result_corr_r;     // This is the ECC corrected data going to RF
      587            0 :    logic         lsu_single_ecc_error_incr;     // Increment the ecc counter
      588            0 :    el2_lsu_error_pkt_t lsu_error_pkt_r;
      589            0 :    logic         lsu_imprecise_error_load_any;
      590            0 :    logic         lsu_imprecise_error_store_any;
-     591            2 :    logic [31:0]  lsu_imprecise_error_addr_any;
-     592            8 :    logic         lsu_load_stall_any;       // This is for blocking loads
-     593            8 :    logic         lsu_store_stall_any;      // This is for blocking stores
-     594         6290 :    logic         lsu_idle_any;             // doesn't include DMA
-     595         6288 :    logic         lsu_active;               // lsu is active. used for clock
+     591            0 :    logic [31:0]  lsu_imprecise_error_addr_any;
+     592            0 :    logic         lsu_load_stall_any;       // This is for blocking loads
+     593            0 :    logic         lsu_store_stall_any;      // This is for blocking stores
+     594          280 :    logic         lsu_idle_any;             // doesn't include DMA
+     595          278 :    logic         lsu_active;               // lsu is active. used for clock
      596              : 
      597              : 
      598            0 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
      599            0 :    logic [1:0]   lsu_fir_error;       // Error during fast interrupt lookup
      600              : 
      601              :    // Non-blocking loads
-     602         3944 :    logic                                 lsu_nonblock_load_valid_m;
-     603         1424 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
+     602          268 :    logic                                 lsu_nonblock_load_valid_m;
+     603          252 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
      604            0 :    logic                                 lsu_nonblock_load_inv_r;
-     605         1424 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
-     606         4032 :    logic                                 lsu_nonblock_load_data_valid;
-     607           36 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
-     608           16 :    logic [31:0]                          lsu_nonblock_load_data;
+     605          252 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
+     606          268 :    logic                                 lsu_nonblock_load_data_valid;
+     607            0 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
+     608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
-     610          148 :    logic        dec_csr_ren_d;
-     611            4 :    logic [31:0] dec_csr_rddata_d;
+     610            4 :    logic        dec_csr_ren_d;
+     611            0 :    logic [31:0] dec_csr_rddata_d;
      612              : 
-     613            0 :    logic [31:0] exu_csr_rs1_x;
+     613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
-     615        25728 :    logic        dec_tlu_i0_commit_cmt;
-     616           64 :    logic        dec_tlu_flush_lower_r;
-     617           64 :    logic        dec_tlu_flush_lower_wb;
+     615          996 :    logic        dec_tlu_i0_commit_cmt;
+     616            4 :    logic        dec_tlu_flush_lower_r;
+     617            4 :    logic        dec_tlu_flush_lower_wb;
      618            0 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
      619            0 :    logic        dec_tlu_fence_i_r;            // flush is a fence_i rfnpc, flush icache
      620              : 
-     621           12 :    logic [31:1] dec_tlu_flush_path_r;
-     622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
+     621            0 :    logic [31:1] dec_tlu_flush_path_r;
+     622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624        13532 :    logic        ifu_i0_pc4;
+     624          350 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
@@ -735,30 +735,30 @@
      631            0 :    logic [31:0] exu_div_result;
      632            0 :    logic exu_div_wren;
      633              : 
-     634        25728 :    logic dec_i0_decode_d;
+     634          998 :    logic dec_i0_decode_d;
      635              : 
      636              : 
-     637          506 :    logic [31:1] pred_correct_npc_x;
+     637           24 :    logic [31:1] pred_correct_npc_x;
      638              : 
-     639         2712 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
+     639           12 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
      640              : 
-     641          128 :    el2_predict_pkt_t  exu_mp_pkt;
-     642          692 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643         1838 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
-     644          204 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
+     641            0 :    el2_predict_pkt_t  exu_mp_pkt;
+     642           64 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
+     643            6 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     644            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647         1838 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648         3756 :    logic [1:0]  exu_i0_br_hist_r;
+     647            6 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648          184 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651         5692 :    logic        exu_i0_br_valid_r;
-     652         1032 :    logic        exu_i0_br_mp_r;
-     653         7436 :    logic        exu_i0_br_middle_r;
+     651          252 :    logic        exu_i0_br_valid_r;
+     652          104 :    logic        exu_i0_br_mp_r;
+     653          312 :    logic        exu_i0_br_middle_r;
      654              : 
-     655         2712 :    logic        exu_i0_br_way_r;
+     655           12 :    logic        exu_i0_br_way_r;
      656              : 
-     657          116 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
+     657            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
      658              : 
      659            0 :    logic        dma_dccm_req;
      660            0 :    logic        dma_iccm_req;
@@ -779,8 +779,8 @@
      675              : 
      676            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
      677            0 :    logic        dma_iccm_stall_any;       // Stall the fetch
-     678         7858 :    logic        dccm_ready;
-     679         1238 :    logic        iccm_ready;
+     678          542 :    logic        dccm_ready;
+     679          108 :    logic        iccm_ready;
      680              : 
      681            0 :    logic        dma_pmu_dccm_read;
      682            0 :    logic        dma_pmu_dccm_write;
@@ -795,29 +795,29 @@
      691            0 :    logic        ifu_i0_dbecc;
      692            0 :    logic        iccm_dma_sb_error;
      693              : 
-     694          124 :    el2_br_pkt_t i0_brp;
-     695          544 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696         8682 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     694           20 :    el2_br_pkt_t i0_brp;
+     695           20 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
+     696           30 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697            0 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
      700            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
      701              : 
      702              : 
-     703          424 :    el2_predict_pkt_t dec_i0_predict_p_d;
+     703           20 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705         8682 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
-     706          544 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
+     705           30 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     706           20 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707            0 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
      709              :    // PIC ports
      710            0 :    logic                  picm_wren;
      711            0 :    logic                  picm_rden;
      712            0 :    logic                  picm_mken;
-     713            2 :    logic [31:0]           picm_rdaddr;
-     714            2 :    logic [31:0]           picm_wraddr;
-     715           28 :    logic [31:0]           picm_wr_data;
-     716            0 :    logic [31:0]           picm_rd_data;
+     713            0 :    logic [31:0]           picm_rdaddr;
+     714            0 :    logic [31:0]           picm_wraddr;
+     715            0 :    logic [31:0]           picm_wr_data;
+     716            0 :    logic [31:0]           picm_rd_data;
      717              : 
      718              :    // feature disable from mfdc
      719            0 :    logic  dec_tlu_external_ldfwd_disable; // disable external load forwarding
@@ -843,18 +843,18 @@
      739              :   // PMP Signals
      740            0 :   el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
      741              :   logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
-     742          128 :   logic [31:0]            pmp_chan_addr [3];
-     743            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
-     744         1238 :   logic                   pmp_chan_err  [3];
+     742            0 :   logic [31:0]            pmp_chan_addr [3];
+     743            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
+     744            0 :   logic                   pmp_chan_err  [3];
      745              : 
-     746            2 :   logic [31:1] ifu_pmp_addr;
+     746            2 :   logic [31:1] ifu_pmp_addr;
      747            0 :   logic        ifu_pmp_error;
-     748          128 :   logic [31:0] lsu_pmp_addr_start;
-     749         1238 :   logic        lsu_pmp_error_start;
-     750          128 :   logic [31:0] lsu_pmp_addr_end;
-     751         1238 :   logic        lsu_pmp_error_end;
-     752         3968 :   logic        lsu_pmp_we;
-     753         3944 :   logic        lsu_pmp_re;
+     748            0 :   logic [31:0] lsu_pmp_addr_start;
+     749            0 :   logic        lsu_pmp_error_start;
+     750            0 :   logic [31:0] lsu_pmp_addr_end;
+     751            0 :   logic        lsu_pmp_error_end;
+     752          272 :   logic        lsu_pmp_we;
+     753          268 :   logic        lsu_pmp_re;
      754              : 
      755              :    // -----------------------DEBUG  START -------------------------------
      756              : 
@@ -889,43 +889,43 @@
      785            0 :    logic                   dec_debug_wdata_rs1_d;
      786            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
      787              : 
-     788        25728 :    logic [1:0]             dec_data_en;
-     789        25696 :    logic [1:0]             dec_ctl_en;
+     788          996 :    logic [1:0]             dec_data_en;
+     789          992 :    logic [1:0]             dec_ctl_en;
      790              : 
      791              :    // PMU Signals
-     792         1032 :    logic                   exu_pmu_i0_br_misp;
-     793         4000 :    logic                   exu_pmu_i0_br_ataken;
-     794         5370 :    logic                   exu_pmu_i0_pc4;
+     792          104 :    logic                   exu_pmu_i0_br_misp;
+     793          276 :    logic                   exu_pmu_i0_br_ataken;
+     794          298 :    logic                   exu_pmu_i0_pc4;
      795              : 
-     796         3944 :    logic                   lsu_pmu_load_external_m;
-     797         3968 :    logic                   lsu_pmu_store_external_m;
-     798           12 :    logic                   lsu_pmu_misaligned_m;
-     799         8288 :    logic                   lsu_pmu_bus_trxn;
-     800           12 :    logic                   lsu_pmu_bus_misaligned;
-     801            0 :    logic                   lsu_pmu_bus_error;
-     802           32 :    logic                   lsu_pmu_bus_busy;
+     796          268 :    logic                   lsu_pmu_load_external_m;
+     797          272 :    logic                   lsu_pmu_store_external_m;
+     798            0 :    logic                   lsu_pmu_misaligned_m;
+     799          544 :    logic                   lsu_pmu_bus_trxn;
+     800            0 :    logic                   lsu_pmu_bus_misaligned;
+     801            0 :    logic                   lsu_pmu_bus_error;
+     802            0 :    logic                   lsu_pmu_bus_busy;
      803              : 
-     804          950 :    logic                   ifu_pmu_fetch_stall;
-     805        26024 :    logic                   ifu_pmu_ic_miss;
+     804           42 :    logic                   ifu_pmu_fetch_stall;
+     805          996 :    logic                   ifu_pmu_ic_miss;
      806            0 :    logic                   ifu_pmu_ic_hit;
      807            0 :    logic                   ifu_pmu_bus_error;
      808            0 :    logic                   ifu_pmu_bus_busy;
-     809        26024 :    logic                   ifu_pmu_bus_trxn;
+     809          996 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812       404408 :    logic                   free_clk;
-     813       404408 :    logic                   active_clk;
+     812        15288 :    logic                   free_clk;
+     813        15288 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
      817              : 
-     818         3180 :    logic [15:0]            ifu_i0_cinst;
+     818          206 :    logic [15:0]            ifu_i0_cinst;
      819              : 
      820              : // fast interrupt
      821            0 :    logic [31:2]            dec_tlu_meihap;
      822            0 :    logic                   dec_extint_stall;
      823              : 
-     824            4 :    el2_trace_pkt_t  trace_rv_trace_pkt;
+     824          996 :    el2_trace_pkt_t  trace_rv_trace_pkt;
      825              : 
      826              : 
      827            0 :    logic                   lsu_fastint_stall_any;
@@ -941,7 +941,7 @@
      837            0 :    logic        pause_state;
      838            0 :    logic        halt_state;
      839              : 
-     840         7392 :    logic        dec_tlu_core_empty;
+     840          144 :    logic        dec_tlu_core_empty;
      841              : 
      842              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
      843              : 
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890           18 :    logic priv_mode;
+     890              :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892           18 :    logic priv_mode_eff;
+     892              :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894           18 :    logic priv_mode_ns;
+     894              :    logic priv_mode_ns;
      895              : 
-     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer_wrapper.sv.html
index 630255f1434..a549560e13e 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_el2_veer_wrapper.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        22.9%
+    
+        20.3%
     
     
-        70
+        62
     
     
         306
@@ -131,7 +131,7 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30       404408 :    input logic                             clk,
+      30        15288 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
@@ -140,13 +140,13 @@
       36            0 :    input logic [31:1]                      jtag_id,
       37              : 
       38              : 
-      39         2908 :    output logic [31:0]                     trace_rv_i_insn_ip,
+      39           12 :    output logic [31:0]                     trace_rv_i_insn_ip,
       40            2 :    output logic [31:0]                     trace_rv_i_address_ip,
-      41        25728 :    output logic                            trace_rv_i_valid_ip,
-      42           28 :    output logic                            trace_rv_i_exception_ip,
-      43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
+      41          996 :    output logic                            trace_rv_i_valid_ip,
+      42            0 :    output logic                            trace_rv_i_exception_ip,
+      43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
       44            0 :    output logic                            trace_rv_i_interrupt_ip,
-      45            4 :    output logic [31:0]                     trace_rv_i_tval_ip,
+      45            0 :    output logic [31:0]                     trace_rv_i_tval_ip,
       46              : 
       47              :    // Bus signals
       48              : `ifdef RV_BUILD_AXI4
@@ -334,29 +334,29 @@
      230              : 
      231              : `ifdef RV_BUILD_AHB_LITE
      232              :  //// AHB LITE BUS
-     233            2 :    output logic [31:0]                     haddr,
+     233            2 :    output logic [31:0]                     haddr,
      234            0 :    output logic [2:0]                      hburst,
      235            0 :    output logic                            hmastlock,
      236            0 :    output logic [3:0]                      hprot,
      237            0 :    output logic [2:0]                      hsize,
-     238        26024 :    output logic [1:0]                      htrans,
+     238          996 :    output logic [1:0]                      htrans,
      239            0 :    output logic                            hwrite,
      240              : 
-     241         2300 :    input logic [63:0]                      hrdata,
+     241           24 :    input logic [63:0]                      hrdata,
      242            2 :    input logic                             hready,
      243            0 :    input logic                             hresp,
      244              : 
      245              :    // LSU AHB Master
-     246            2 :    output logic [31:0]                     lsu_haddr,
-     247            0 :    output logic [2:0]                      lsu_hburst,
+     246            0 :    output logic [31:0]                     lsu_haddr,
+     247            0 :    output logic [2:0]                      lsu_hburst,
      248            0 :    output logic                            lsu_hmastlock,
      249            0 :    output logic [3:0]                      lsu_hprot,
      250            0 :    output logic [2:0]                      lsu_hsize,
-     251         8284 :    output logic [1:0]                      lsu_htrans,
-     252         2774 :    output logic                            lsu_hwrite,
-     253            4 :    output logic [63:0]                     lsu_hwdata,
+     251          544 :    output logic [1:0]                      lsu_htrans,
+     252          266 :    output logic                            lsu_hwrite,
+     253           48 :    output logic [63:0]                     lsu_hwdata,
      254              : 
-     255            4 :    input logic [63:0]                      lsu_hrdata,
+     255            8 :    input logic [63:0]                      lsu_hrdata,
      256            2 :    input logic                             lsu_hready,
      257            0 :    input logic                             lsu_hresp,
      258              :    // Debug Syster Bus AHB
@@ -454,17 +454,17 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353       404408 :    logic                             active_l2clk;
-     354       404408 :    logic                             free_l2clk;
+     353        15288 :    logic                             active_l2clk;
+     354        15288 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
      358            0 :    logic         dccm_rden;
      359            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo;
      360            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi;
-     361          128 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
-     362          128 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
-     363            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
+     361            0 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
+     362            0 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
+     363            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
      364            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi;
      365              : 
      366            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_lo;
@@ -490,19 +490,19 @@
      386            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way;   // Debug way. Rd or Wr.
      387              : 
      388            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
-     389         1164 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
-     390         5364 :    logic [63:0]  ic_rd_data;
+     389            6 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
+     390           62 :    logic [63:0]  ic_rd_data;
      391            0 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      392            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
      393              : 
      394            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
      395            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
      396              : 
-     397         5364 :    logic [63:0]  ic_premux_data;
-     398        20614 :    logic         ic_sel_premux_data;
+     397           62 :    logic [63:0]  ic_premux_data;
+     398          734 :    logic         ic_sel_premux_data;
      399              : 
      400              :    // ICCM ports
-     401          152 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
+     401            8 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
      402            0 :    logic           iccm_wren;
      403            0 :    logic           iccm_rden;
      404            0 :    logic [2:0]     iccm_wr_size;
@@ -610,11 +610,11 @@
      506              : 
      507              : 
      508              : `ifdef RV_BUILD_AHB_LITE
-     509         4340 :    wire                            lsu_axi_awvalid;
+     509          276 :    wire                            lsu_axi_awvalid;
      510            0 :    wire                            lsu_axi_awready;
      511            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid;
-     512            2 :    wire [31:0]                     lsu_axi_awaddr;
-     513            2 :    wire [3:0]                      lsu_axi_awregion;
+     512            0 :    wire [31:0]                     lsu_axi_awaddr;
+     513            2 :    wire [3:0]                      lsu_axi_awregion;
      514            0 :    wire [7:0]                      lsu_axi_awlen;
      515            0 :    wire [2:0]                      lsu_axi_awsize;
      516            0 :    wire [1:0]                      lsu_axi_awburst;
@@ -624,10 +624,10 @@
      520            0 :    wire [3:0]                      lsu_axi_awqos;
      521              : 
      522              : 
-     523         4340 :    wire                            lsu_axi_wvalid;
+     523          276 :    wire                            lsu_axi_wvalid;
      524            0 :    wire                            lsu_axi_wready;
-     525           48 :    wire [63:0]                     lsu_axi_wdata;
-     526          512 :    wire [7:0]                      lsu_axi_wstrb;
+     525            0 :    wire [63:0]                     lsu_axi_wdata;
+     526            4 :    wire [7:0]                      lsu_axi_wstrb;
      527            2 :    wire                            lsu_axi_wlast;
      528              : 
      529            0 :    wire                            lsu_axi_bvalid;
@@ -636,11 +636,11 @@
      532            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid;
      533              : 
      534              :    // AXI Read Channels
-     535         3944 :    wire                            lsu_axi_arvalid;
+     535          268 :    wire                            lsu_axi_arvalid;
      536            0 :    wire                            lsu_axi_arready;
      537            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid;
-     538            2 :    wire [31:0]                     lsu_axi_araddr;
-     539            2 :    wire [3:0]                      lsu_axi_arregion;
+     538            0 :    wire [31:0]                     lsu_axi_araddr;
+     539            2 :    wire [3:0]                      lsu_axi_arregion;
      540            0 :    wire [7:0]                      lsu_axi_arlen;
      541            0 :    wire [2:0]                      lsu_axi_arsize;
      542            0 :    wire [1:0]                      lsu_axi_arburst;
@@ -694,10 +694,10 @@
      590            0 :    wire [pt.IFU_BUS_TAG-1:0]      ifu_axi_bid;
      591              : 
      592              :    // AXI Read Channels
-     593        26024 :    wire                            ifu_axi_arvalid;
+     593          996 :    wire                            ifu_axi_arvalid;
      594            0 :    wire                            ifu_axi_arready;
-     595        17884 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
-     596         3188 :    wire [31:0]                     ifu_axi_araddr;
+     595           88 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
+     596           56 :    wire [31:0]                     ifu_axi_araddr;
      597            2 :    wire [3:0]                      ifu_axi_arregion;
      598            0 :    wire [7:0]                      ifu_axi_arlen;
      599            0 :    wire [2:0]                      ifu_axi_arsize;
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_insns/index_mem_lib.sv.html
index 7abadb42e6e..294561bac5b 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111      1539136 : `EL2_RAM(4096, 39)
+     111       799168 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175       384784 : `EL2_RAM_BE(512, 142)
+     175       199792 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208       192392 : `EL2_RAM_BE(128, 52)
+     208        99896 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_ahb_insns/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_insns/index_rvjtag_tap.v.html
index f62510fad51..ca1687ceff0 100644
--- a/html/main/coverage_dashboard/all_ahb_insns/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_insns/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index.html b/html/main/coverage_dashboard/all_ahb_irq/index.html
index b25dd884fc9..bef778416cb 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -59,13 +59,13 @@
         Toggle
     
     
-        41.1%
+        41.0%
     
     
-        2207
+        2179
     
     
-        5364
+        5317
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    29.4%
+                    28.7%
                 
             
 
             
-                375
+                363
                 /
-                1275
+                1265
             
         
             
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    46.8%
+                    46.6%
                 
             
 
             
-                471
+                460
                 /
-                1007
+                987
             
         
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    55.1%
+                    54.5%
                 
             
 
             
-                190
+                188
                 /
                 345
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    54.4%
+                    54.8%
                 
             
 
             
-                552
+                556
                 /
                 1014
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    10.9%
+                    11.9%
                 
             
 
             
-                11
+                10
                 /
-                101
+                84
             
         
             
@@ -683,19 +683,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    44.4%
+                    43.8%
                 
             
 
             
-                456
+                450
                 /
                 1027
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design.html
index bfd3b4265c9..3e347b1badd 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        29.4%
+    
+        28.7%
     
     
-        375
+        363
     
     
-        1275
+        1265
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    60.0%
+                    50.0%
                 
             
 
             
-                12
+                7
                 /
-                20
+                14
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    36.3%
+                    35.4%
                 
             
 
             
-                229
+                222
                 /
-                631
+                627
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dbg.html
index c1a979585cd..65c9647d060 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dec.html
index 3b2893f0de9..f47aedd0ede 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        46.8%
+    
+        46.6%
     
     
-        471
+        460
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    47.9%
+                    47.0%
                 
             
 
             
-                123
+                119
                 /
-                257
+                253
             
         
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    68.4%
+                    68.0%
                 
             
 
             
-                188
+                187
                 /
                 275
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    42.4%
+                    43.8%
                 
             
 
             
                 14
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    30.4%
+                    30.0%
                 
             
 
             
-                114
+                108
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dmi.html
index 2defef30d79..ada702876f3 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_exu.html
index e1471fc2873..66a85e61f0c 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_exu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        55.1%
+    
+        54.5%
     
     
-        190
+        188
     
     
         345
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    81.0%
+                    80.0%
                 
             
 
             
-                81
+                80
                 /
                 100
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.3%
+                    51.1%
                 
             
 
             
-                46
+                45
                 /
                 88
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_ifu.html
index 840a0a4c512..9b7858ac901 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        54.4%
+    
+        54.8%
     
     
-        552
+        556
     
     
         1014
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    80.9%
+                    84.5%
                 
             
 
             
-                89
+                93
                 /
                 110
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_include.html
index 9d8d3b9106f..4698f92ec2e 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        10.9%
+    
+        11.9%
     
     
-        11
+        10
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    10.9%
+                    11.9%
                 
             
 
             
-                11
+                10
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lib.html
index 1a25b158a05..5be051e1b10 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lsu.html
index dd9adf89d72..d0866c8ad07 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        44.4%
+    
+        43.8%
     
     
-        456
+        450
     
     
         1027
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.9%
+                    39.9%
                 
             
 
             
-                81
+                79
                 /
                 198
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    24.0%
+                    20.0%
                 
             
 
             
-                12
+                10
                 /
                 50
             
@@ -683,19 +683,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.9%
+                    43.5%
                 
             
 
             
-                39
+                37
                 /
                 85
             
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_ahb_to_axi4.sv.html
index 3b15c561166..993b1f6d5e1 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : )
       29              : //   ,TAG  = 1)
       30              : (
-      31       584906 :    input                   clk,
+      31       359918 :    input                   clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -242,9 +242,9 @@
      138            2 :       buf_read_error_in = 1'b0;              // signal indicating that an error came back with the read from the core
      139            2 :       cmdbuf_wr_en      = 1'b0;              // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
      140            2 :       case (buf_state)
-     141       108831 :          IDLE: begin  // No commands recieved
-     142       108831 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
-     143       108831 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
+     141        82994 :          IDLE: begin  // No commands recieved
+     142        82994 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
+     143        82994 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
      144              :           end
      145            0 :          WR: begin // Write command recieved last cycle
      146            0 :                   buf_nxtstate      = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite  ? WR : RD;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_axi4_to_ahb.sv.html
index 19febbd3acf..e970b0586b2 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : `include "el2_param.vh"
       28              : ,parameter TAG  = 1) (
       29              : 
-      30       538672 :    input                   clk,
-      31       538672 :    input                   free_clk,
+      30       331976 :    input                   clk,
+      31       331976 :    input                   free_clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -389,18 +389,18 @@
      285            2 :       rd_bypass_idle   = 1'b0;
      286              : 
      287            2 :       case (buf_state)
-     288       108831 :          IDLE: begin
-     289       108831 :                   master_ready   = 1'b1;
-     290       108831 :                   buf_write_in = (master_opc[2:1] == 2'b01);
-     291       108831 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
-     292       108831 :                   buf_state_en = master_valid & master_ready;
-     293       108831 :                   buf_wr_en    = buf_state_en;
-     294       108831 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
-     295       108831 :                   buf_cmd_byte_ptr_en   = buf_state_en;
-     296       108831 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
-     297       108831 :                   bypass_en       = buf_state_en;
-     298       108831 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
-     299       108831 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
+     288        82994 :          IDLE: begin
+     289        82994 :                   master_ready   = 1'b1;
+     290        82994 :                   buf_write_in = (master_opc[2:1] == 2'b01);
+     291        82994 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
+     292        82994 :                   buf_state_en = master_valid & master_ready;
+     293        82994 :                   buf_wr_en    = buf_state_en;
+     294        82994 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
+     295        82994 :                   buf_cmd_byte_ptr_en   = buf_state_en;
+     296        82994 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
+     297        82994 :                   bypass_en       = buf_state_en;
+     298        82994 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
+     299        82994 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
      300              :           end
      301            0 :          CMD_RD: begin
      302            0 :                   buf_nxtstate    = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_beh_lib.sv.html
index d220c8c1698..ddaf4140a11 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22       538672 :      input logic           clk,
+      22       331976 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38       108829 :    always_ff @(posedge clk or negedge rst_l) begin
+      38        82992 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42       108819 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42        82982 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52            0 :      input logic             en,
-      53       538672 :      input logic           clk,
+      53       331976 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -171,10 +171,10 @@
       67              : // rvdff with en and clear
       68              : module rvdffsc #( parameter WIDTH=1, SHORT=0 )
       69              :    (
-      70         1304 :      input logic [WIDTH-1:0] din,
+      70          780 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73      2339624 :      input logic           clk,
+      73      1439672 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -192,13 +192,13 @@
       88              : // _fpga versions
       89              : module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
       90              :    (
-      91        30536 :      input logic [WIDTH-1:0] din,
+      91        19068 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94       584906 :      input logic           rawclk,
+      94       359918 :      input logic           rawclk,
       95            2 :      input logic           rst_l,
       96              : 
-      97        30536 :      output logic [WIDTH-1:0] dout
+      97        19068 :      output logic [WIDTH-1:0] dout
       98              :      );
       99              : 
      100              : if (SHORT == 1) begin : genblock
@@ -220,7 +220,7 @@
      116            0 :      input logic             en,
      117            0 :      input logic           clk,
      118            6 :      input logic           clken,
-     119      1123578 :      input logic           rawclk,
+     119       691894 :      input logic           rawclk,
      120            6 :      input logic           rst_l,
      121              : 
      122            0 :      output logic [WIDTH-1:0] dout
@@ -243,14 +243,14 @@
      139              : module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
      140              :    (
      141           26 :      input logic [WIDTH-1:0] din,
-     142        90038 :      input logic             en,
+     142        55342 :      input logic             en,
      143            0 :      input logic             clear,
-     144        92734 :      input logic             clk,
+     144        58158 :      input logic             clk,
      145            6 :      input logic             clken,
-     146      1123578 :      input logic             rawclk,
+     146       691894 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
-     149         6008 :      output logic [WIDTH-1:0] dout
+     149         3812 :      output logic [WIDTH-1:0] dout
      150              :      );
      151              : 
      152            0 :    logic [WIDTH-1:0]          din_new;
@@ -269,9 +269,9 @@
      165              : 
      166              : module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
      167              :    (
-     168         8424 :      input  logic [WIDTH-1:0] din,
+     168         2592 :      input  logic [WIDTH-1:0] din,
      169            0 :      input  logic           en,
-     170       538672 :      input  logic           clk,
+     170       331976 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -309,12 +309,12 @@
      205              : 
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
-     208         1046 :      input  logic [WIDTH-1:0] din,
-     209      3232032 :      input  logic             clk,
+     208          678 :      input  logic [WIDTH-1:0] din,
+     209      1991856 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
-     211       271252 :      input  logic             en,
+     211       166472 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
-     213         1046 :      output logic [WIDTH-1:0] dout
+     213          678 :      output logic [WIDTH-1:0] dout
      214              :      );
      215              : 
      216              : 
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            2 :      input  logic [WIDTH-1:0] din,
-     242       538672 :      input  logic             clk,
+     242       331976 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -397,12 +397,12 @@
      293              : // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
-     296         1280 :      input  logic [WIDTH-1:0] din,
-     297       584906 :      input  logic             clk,
+     296          772 :      input  logic [WIDTH-1:0] din,
+     297       359918 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
-     299        36284 :      input  logic             en,
+     299        22292 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
-     301         1280 :      output logic [WIDTH-1:0] dout
+     301          772 :      output logic [WIDTH-1:0] dout
      302              :      );
      303              : 
      304              :    localparam integer RIGHT = 31;
@@ -440,16 +440,16 @@
      336              : 
      337              : module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
      338              :    (
-     339          164 :      input  logic [WIDTH-1:0] din,
+     339          136 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341       584906 :      input  logic           clk,
+     341       359918 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
-     344          164 :      output logic [WIDTH-1:0] dout
+     344          136 :      output logic [WIDTH-1:0] dout
      345              :      );
      346              : 
      347            0 :    logic                      l1clk;
-     348           28 :    logic                      en;
+     348           16 :    logic                      en;
      349              : 
      350              : 
      351              : 
@@ -519,13 +519,13 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418       584906 :      input  logic                 clk,
+     418       359918 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
-     420           12 :      input  logic [WIDTH-1:0]     din,
-     421           12 :      output logic [WIDTH-1:0]     dout
+     420            8 :      input  logic [WIDTH-1:0]     din,
+     421            8 :      output logic [WIDTH-1:0]     dout
      422              :      );
      423              : 
-     424           12 :    logic [WIDTH-1:0]              din_ff1;
+     424            8 :    logic [WIDTH-1:0]              din_ff1;
      425              : 
      426              :    rvdff #(WIDTH) sync_ff1  (.*, .din (din[WIDTH-1:0]),     .dout(din_ff1[WIDTH-1:0]));
      427              :    rvdff #(WIDTH) sync_ff2  (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434      8349416 :      input  logic                 rawclk,
+     434      5145628 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -551,17 +551,17 @@
      447              : 
      448              : module rvlsadder
      449              :   (
-     450         1284 :     input logic [31:0] rs1,
-     451          684 :     input logic [11:0] offset,
+     450          300 :     input logic [31:0] rs1,
+     451          420 :     input logic [11:0] offset,
      452              : 
-     453         1404 :     output logic [31:0] dout
+     453          432 :     output logic [31:0] dout
      454              :     );
      455              : 
-     456          684 :    logic                cout;
-     457          892 :    logic                sign;
+     456          420 :    logic                cout;
+     457          548 :    logic                sign;
      458              : 
-     459         3764 :    logic [31:12]        rs1_inc;
-     460         3338 :    logic [31:12]        rs1_dec;
+     459         2448 :    logic [31:12]        rs1_inc;
+     460         2014 :    logic [31:12]        rs1_dec;
      461              : 
      462              :    assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
      463              : 
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480           16 :     input [31:1] pc,
-     481        12436 :     input [12:1] offset,
+     481         7768 :     input [12:1] offset,
      482              : 
-     483         1046 :     output [31:1] dout
+     483          678 :     output [31:1] dout
      484              :     );
      485              : 
-     486        12420 :    logic          cout;
-     487        13318 :    logic          sign;
+     486         7816 :    logic          cout;
+     487         8406 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -615,10 +615,10 @@
      511              :    (
      512            0 :      input logic [WIDTH-1:0] din,
      513              : 
-     514           56 :      output logic [WIDTH-1:0] dout
+     514           40 :      output logic [WIDTH-1:0] dout
      515              :      );
      516              : 
-     517           56 :    logic [WIDTH-1:1]          dout_temp;   // holding for all other bits except for the lsb. LSB is always din
+     517           40 :    logic [WIDTH-1:1]          dout_temp;   // holding for all other bits except for the lsb. LSB is always din
      518              : 
      519              :    genvar                     i;
      520              : 
@@ -700,7 +700,7 @@
      596              : // Check if the S_ADDR <= addr < E_ADDR
      597              : module rvrangecheck  #(CCM_SADR = 32'h0,
      598              :                        CCM_SIZE  = 128) (
-     599         2808 :    input  logic [31:0]   addr,                             // Address to be checked for range
+     599          864 :    input  logic [31:0]   addr,                             // Address to be checked for range
      600            0 :    output logic          in_range,                            // S_ADDR <= start_addr < E_ADDR
      601            0 :    output logic          in_region
      602              : );
@@ -744,7 +744,7 @@
      640              : 
      641              : module rvecc_encode  (
      642            0 :                       input [31:0] din,
-     643           26 :                       output [6:0] ecc_out
+     643           18 :                       output [6:0] ecc_out
      644              :                       );
      645            0 : logic [5:0] ecc_out_temp;
      646              : 
@@ -760,12 +760,12 @@
      656              : endmodule // rvecc_encode
      657              : 
      658              : module rvecc_decode  (
-     659          256 :                       input         en,
-     660          336 :                       input [31:0]  din,
-     661           48 :                       input [6:0]   ecc_in,
+     659          172 :                       input         en,
+     660          224 :                       input [31:0]  din,
+     661           32 :                       input [6:0]   ecc_in,
      662            4 :                       input         sed_ded,    // only do detection and no correction. Used for the I$
-     663          336 :                       output [31:0] dout,
-     664           48 :                       output [6:0]  ecc_out,
+     663          224 :                       output [31:0] dout,
+     664           32 :                       output [6:0]  ecc_out,
      665            0 :                       output        single_ecc_error,
      666            0 :                       output        double_ecc_error
      667              : 
@@ -773,7 +773,7 @@
      669              : 
      670            0 :    logic [6:0]                      ecc_check;
      671            0 :    logic [38:0]                     error_mask;
-     672          480 :    logic [38:0]                     din_plus_parity, dout_plus_parity;
+     672          320 :    logic [38:0]                     din_plus_parity, dout_plus_parity;
      673              : 
      674              :    // Generate the ecc bits
      675              :    assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
@@ -804,8 +804,8 @@
      700              : endmodule // rvecc_decode
      701              : 
      702              : module rvecc_encode_64  (
-     703         7666 :                       input [63:0] din,
-     704        23032 :                       output [6:0] ecc_out
+     703         4754 :                       input [63:0] din,
+     704        14140 :                       output [6:0] ecc_out
      705              :                       );
      706              :   assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
      707              : 
@@ -896,10 +896,10 @@
      792              : 
      793              : module rvoclkhdr
      794              :   (
-     795       159414 :    input  logic en,
-     796     15792462 :    input  logic clk,
+     795        98130 :    input  logic en,
+     796      9717786 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798     15792462 :    output logic l1clk
+     798      9717786 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_irq/index_dmi_jtag_to_core_sync.v.html
index e38f87cc2db..2052ce1777a 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32       584906 : input       clk,        // Core clock
+      32       359918 : input       clk,        // Core clock
       33              : 
       34            0 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35            0 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49       108829 : always @ ( posedge clk or negedge rst_n) begin
+      49        82992 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54       108825 :     else begin
-      55       108825 :         rden <= {rden[1:0], rd_en};
-      56       108825 :         wren <= {wren[1:0], wr_en};
+      54        82988 :     else begin
+      55        82988 :         rden <= {rden[1:0], rd_en};
+      56        82988 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_irq/index_dmi_mux.v.html
index 89bebe054f6..dd867ef0403 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_irq/index_dmi_wrapper.v.html
index dbd64cf3fd8..ac97d0408a4 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36       584906 :   input              core_clk,            // Core clock                  
+      36       359918 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38            0 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39            0 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dbg.sv.html
index 52bb8dd1ca6..bdb09c1bc90 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110       584906 :    input logic                         clk,
-     111       584906 :    input logic                         free_clk,
+     110       359918 :    input logic                         clk,
+     111       359918 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254            0 :    logic              dbg_free_clken;
-     255       584906 :    logic              dbg_free_clk;
+     255       359918 :    logic              dbg_free_clk;
      256              : 
      257            0 :    logic              sb_free_clken;
-     258       584906 :    logic              sb_free_clk;
+     258       359918 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474       108831 :             IDLE: begin
-     475       108831 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476       108831 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477       108831 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474        82994 :             IDLE: begin
+     475        82994 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476        82994 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477        82994 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604       108831 :             SBIDLE: begin
-     605       108831 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606       108831 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607       108831 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608       108831 :                      sbcs_sbbusy_din        = 1'b1;
-     609       108831 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610       108831 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604        82994 :             SBIDLE: begin
+     605        82994 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606        82994 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607        82994 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608        82994 :                      sbcs_sbbusy_din        = 1'b1;
+     609        82994 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610        82994 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec.sv.html
index b4f02b26606..ad518598465 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        47.9%
+    
+        47.0%
     
     
-        123
+        119
     
     
-        257
+        253
     
 
             
@@ -136,24 +136,24 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35       584906 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36       584906 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37       584906 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38       584906 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35       359918 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36       359918 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37       359918 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38       359918 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
       42            0 :     output logic dec_extint_stall,  // Stall on external interrupt
       43              : 
-      44        36372 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
+      44        22352 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
       45            0 :     output logic dec_pause_state_cg, // to top for active state clock gating
       46              : 
-      47         9752 :     output logic dec_tlu_core_empty,
+      47         5948 :     output logic dec_tlu_core_empty,
       48              : 
       49            2 :     input logic        rst_l,   // reset, active low
       50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
       51              : 
-      52           12 :     input logic        nmi_int,  // NMI pin
+      52            8 :     input logic        nmi_int,  // NMI pin
       53            0 :     input logic [31:1] nmi_vec,  // NMI vector, from pins
       54              : 
       55            0 :     input logic i_cpu_halt_req,  // Asynchronous Halt request to CPU
@@ -174,27 +174,27 @@
       70            2 :     output logic mpc_debug_run_ack,   // Run ack
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
-      73         1280 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74         5720 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
-      75         7718 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
+      73          940 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
+      74         3488 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      75         4698 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
-      78         5868 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
-      79         1920 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
+      78         3496 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
+      79         1280 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
       80            0 :     input logic lsu_nonblock_load_inv_r,  // invalidate request for nonblock load r
-      81         1920 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
-      82         6000 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
+      81         1280 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
+      82         3576 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
       83            0 :     input logic lsu_nonblock_load_data_error,  // nonblock load bus error
-      84          120 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
-      85           12 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
+      84           76 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
+      85            8 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
       86              : 
-      87        11876 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
+      87         7308 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
       88            0 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
       89            0 :     input logic lsu_pmu_bus_error,         // D side bus error
-      90           56 :     input logic lsu_pmu_bus_busy,          // D side bus busy
+      90           32 :     input logic lsu_pmu_bus_busy,          // D side bus busy
       91            0 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
-      92         5868 :     input logic lsu_pmu_load_external_m,   // D side bus load
-      93         5664 :     input logic lsu_pmu_store_external_m,  // D side bus store
+      92         3496 :     input logic lsu_pmu_load_external_m,   // D side bus load
+      93         3596 :     input logic lsu_pmu_store_external_m,  // D side bus store
       94            0 :     input logic dma_pmu_dccm_read,         // DMA DCCM read
       95            0 :     input logic dma_pmu_dccm_write,        // DMA DCCM write
       96            0 :     input logic dma_pmu_any_read,          // DMA read
@@ -203,13 +203,13 @@
       99            0 :     input logic [31:1] lsu_fir_addr,  // Fast int address
      100            0 :     input logic [ 1:0] lsu_fir_error, // Fast int lookup error
      101              : 
-     102        36372 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
-     103         1382 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
-     104        36324 :     input logic ifu_pmu_ic_miss,        // icache miss
+     102        22352 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
+     103          942 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
+     104        22384 :     input logic ifu_pmu_ic_miss,        // icache miss
      105            0 :     input logic ifu_pmu_ic_hit,         // icache hit
      106            0 :     input logic ifu_pmu_bus_error,      // Instruction side bus error
      107            0 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
-     108        36322 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
+     108        22382 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
      109              : 
      110            0 :     input logic ifu_ic_error_start,         // IC single bit error
      111            0 :     input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
@@ -228,11 +228,11 @@
      124            0 :     input logic ifu_i0_icaf_second,  // i0 has access fault on second 2B of 4B inst
      125            0 :     input logic ifu_i0_dbecc,        // icache/iccm double-bit error
      126              : 
-     127         8954 :     input logic lsu_idle_any,  // lsu idle for halting
+     127         5458 :     input logic lsu_idle_any,  // lsu idle for halting
      128              : 
-     129          188 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
-     130          792 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
-     131        12010 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
+     129          116 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
+     130          500 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
+     131         7134 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
      132            0 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
      133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
      134              : 
@@ -244,36 +244,36 @@
      140            2 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
      141              : 
      142            0 :     input logic [31:0] exu_div_result,  // final div result
-     143           56 :     input logic        exu_div_wren,    // Divide write enable to GPR
+     143           40 :     input logic        exu_div_wren,    // Divide write enable to GPR
      144              : 
      145            0 :     input logic [31:0] exu_csr_rs1_x,  // rs1 for csr instruction
      146              : 
      147            0 :     input logic [31:0] lsu_result_m,      // load result
      148            0 :     input logic [31:0] lsu_result_corr_r, // load result - corrected load data
      149              : 
-     150          248 :     input logic lsu_load_stall_any,   // This is for blocking loads
-     151          248 :     input logic lsu_store_stall_any,  // This is for blocking stores
+     150          160 :     input logic lsu_load_stall_any,   // This is for blocking loads
+     151          160 :     input logic lsu_store_stall_any,  // This is for blocking stores
      152            0 :     input logic dma_dccm_stall_any,   // stall any load/store at decode, pmu event
      153            0 :     input logic dma_iccm_stall_any,   // iccm stalled, pmu event
      154              : 
      155            0 :     input logic iccm_dma_sb_error,  // ICCM DMA single bit error
      156              : 
-     157         1524 :     input logic exu_flush_final,  // slot0 flush
+     157         1084 :     input logic exu_flush_final,  // slot0 flush
      158              : 
      159            2 :     input logic [31:1] exu_npc_r,  // next PC
      160              : 
-     161         1012 :     input logic [31:0] exu_i0_result_x,  // alu result x
+     161          616 :     input logic [31:0] exu_i0_result_x,  // alu result x
      162              : 
      163              : 
-     164        34772 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
-     165          656 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
+     164        21400 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
+     165          392 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166           10 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167        19040 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167        11620 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            2 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
-     171           12 :     input logic timer_int,   // Timer interrupt pending (from pin)
-     172           12 :     input logic soft_int,    // Software interrupt pending (from pin)
+     171            8 :     input logic timer_int,   // Timer interrupt pending (from pin)
+     172            8 :     input logic soft_int,    // Software interrupt pending (from pin)
      173              : 
      174            0 :     input logic [7:0] pic_claimid,  // PIC claimid
      175            0 :     input logic [3:0] pic_pl,       // PIC priv level
@@ -290,7 +290,7 @@
      186              :     // Debug start
      187            0 :     input logic dbg_halt_req,        // DM requests a halt
      188            0 :     input logic dbg_resume_req,      // DM requests a resume
-     189        36324 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
+     189        22384 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
      190              : 
      191            0 :     output logic        dec_tlu_dbg_halted,        // Core is halted and ready for debug command
      192            0 :     output logic        dec_tlu_debug_mode,        // Core is in debug mode
@@ -313,81 +313,81 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212         5260 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212         3160 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215         7996 :     input  logic       exu_i0_br_valid_r,        // valid
-     216         1280 :     input  logic       exu_i0_br_mp_r,           // mispredict
-     217        10172 :     input  logic       exu_i0_br_middle_r,       // middle of bank
+     215         4780 :     input  logic       exu_i0_br_valid_r,        // valid
+     216          940 :     input  logic       exu_i0_br_mp_r,           // mispredict
+     217         6176 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
      219              :     // branch info from pipe1 for errors or counter updates
      220              : 
-     221         2256 :     input logic exu_i0_br_way_r,  // way hit or repl
+     221         1384 :     input logic exu_i0_br_way_r,  // way hit or repl
      222              : 
-     223        30300 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
-     224        16396 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
+     223        18512 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
+     224         9920 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
      225            4 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
-     226            4 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
+     226           16 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228         1876 :     output logic [31:0] dec_i0_immed_d,    // immediate data
-     229         1192 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
+     228         1192 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     229          840 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
-     233        26004 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234        11376 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     233        15936 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
+     234         7028 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
-     236          844 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
+     236          576 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
      238           10 :     output logic [31:1] dec_i0_pc_d,             // pc's at decode
-     239         1380 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
-     240           28 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
+     239          808 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
+     240            4 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
      241              : 
      242            4 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
      243              : 
-     244         2568 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
-     245        26638 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
+     244         1396 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
+     245        16414 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
      246            0 :     output el2_mul_pkt_t mul_p,           // mul packet
-     247           28 :     output el2_div_pkt_t div_p,           // div packet
+     247           20 :     output el2_div_pkt_t div_p,           // div packet
      248            0 :     output logic         dec_div_cancel,  // cancel divide operation
      249              : 
-     250          684 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
+     250          420 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
-     252          124 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253            4 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     252           72 :     output logic        dec_csr_ren_d,    // CSR read enable
+     253            0 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
-     255           64 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
-     256           64 :     output logic dec_tlu_flush_lower_wb,
+     255           36 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+     256           36 :     output logic dec_tlu_flush_lower_wb,
      257            0 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
      258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      259            0 :     output logic dec_tlu_fence_i_r,  // flush is a fence_i rfnpc, flush icache
      260              : 
-     261          650 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
+     261          470 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
      262              : 
-     263         2256 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
+     263         1384 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
      264              : 
      265            0 :     output logic dec_tlu_perfcnt0,  // toggles when slot0 perf counter 0 has an event inc
      266            0 :     output logic dec_tlu_perfcnt1,  // toggles when slot0 perf counter 1 has an event inc
      267            0 :     output logic dec_tlu_perfcnt2,  // toggles when slot0 perf counter 2 has an event inc
      268            0 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
      269              : 
-     270         1864 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
-     271        12010 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
-     272          792 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
+     270         1120 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
+     271         7134 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
+     272          500 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
      273            0 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
      274              : 
      275            0 :     output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index,  // Fully associt btb error index
      276              : 
-     277        11276 :     output logic dec_lsu_valid_raw_d,
+     277         6928 :     output logic dec_lsu_valid_raw_d,
      278              : 
      279            0 :     output logic [31:0] dec_tlu_mrac_ff,  // CSR for memory region control
      280              : 
-     281        36372 :     output logic [1:0] dec_data_en,  // clock-gate control logic
-     282        36284 :     output logic [1:0] dec_ctl_en,
+     281        22352 :     output logic [1:0] dec_data_en,  // clock-gate control logic
+     282        22292 :     output logic [1:0] dec_ctl_en,
      283              : 
-     284         5236 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
+     284         3260 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
      285              : 
-     286        36388 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
+     286        22364 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
      287              : 
      288              :     // PMP signals
      289            0 :     output el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295           14 :     output logic priv_mode,
-     296           14 :     output logic priv_mode_eff,
-     297           14 :     output logic priv_mode_ns,
+     295              :     output logic priv_mode,
+     296              :     output logic priv_mode_eff,
+     297              :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300            0 :     output el2_mseccfg_pkt_t mseccfg,
+     300              :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
@@ -423,7 +423,7 @@
      319            0 :     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
      320            0 :     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
      321              : 
-     322        36368 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+     322        22348 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
      323            0 :     input  logic scan_mode               // Flop scan mode control
      324              : 
      325              : );
@@ -432,44 +432,44 @@
      328            0 :   logic dec_tlu_dec_clk_override;  // to and from dec blocks
      329            0 :   logic clk_override;
      330              : 
-     331        34772 :   logic dec_ib0_valid_d;
+     331        21400 :   logic dec_ib0_valid_d;
      332              : 
-     333        36372 :   logic dec_pmu_instr_decoded;
-     334         1676 :   logic dec_pmu_decode_stall;
+     333        22352 :   logic dec_pmu_instr_decoded;
+     334         1000 :   logic dec_pmu_decode_stall;
      335            0 :   logic dec_pmu_presync_stall;
-     336           32 :   logic dec_pmu_postsync_stall;
+     336           16 :   logic dec_pmu_postsync_stall;
      337              : 
      338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
-     340        10480 :   logic [4:0] dec_i0_rs1_d;
-     341        10496 :   logic [4:0] dec_i0_rs2_d;
+     340         6404 :   logic [4:0] dec_i0_rs1_d;
+     341         6336 :   logic [4:0] dec_i0_rs2_d;
      342              : 
-     343          656 :   logic [31:0] dec_i0_instr_d;
+     343          392 :   logic [31:0] dec_i0_instr_d;
      344              : 
      345            0 :   logic dec_tlu_trace_disable;
      346            0 :   logic dec_tlu_pipelining_disable;
      347              : 
      348              : 
-     349        11748 :   logic [4:0] dec_i0_waddr_r;
-     350        18372 :   logic dec_i0_wen_r;
+     349         7300 :   logic [4:0] dec_i0_waddr_r;
+     350        11212 :   logic dec_i0_wen_r;
      351            4 :   logic [31:0] dec_i0_wdata_r;
-     352           36 :   logic dec_csr_wen_r;  // csr write enable at wb
-     353         8028 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
-     354            4 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
+     352           24 :   logic dec_csr_wen_r;  // csr write enable at wb
+     353         5092 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
+     354            8 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
      355            4 :   logic [31:0] dec_csr_wrdata_r;  // csr write data at wb
      356              : 
      357            4 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
-     358          160 :   logic dec_csr_legal_d;  // csr indicates legal operation
+     358           96 :   logic dec_csr_legal_d;  // csr indicates legal operation
      359              : 
-     360           36 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
-     361          160 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
-     362           20 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
+     360           24 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
+     361           96 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
+     362           12 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
      363              : 
      364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366        19040 :   logic dec_i0_pc4_d;
+     366        11620 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
-     368           96 :   logic dec_tlu_postsync_d;
+     368           52 :   logic dec_tlu_postsync_d;
      369            0 :   logic dec_tlu_debug_stall;
      370              : 
      371            0 :   logic [31:0] dec_illegal_inst;
@@ -480,18 +480,18 @@
      376            0 :   logic dec_i0_icaf_second_d;
      377            0 :   logic [3:0] dec_i0_trigger_match_d;
      378            0 :   logic dec_debug_fence_d;
-     379         6000 :   logic dec_nonblock_load_wen;
-     380          824 :   logic [4:0] dec_nonblock_load_waddr;
+     379         3576 :   logic dec_nonblock_load_wen;
+     380          496 :   logic [4:0] dec_nonblock_load_waddr;
      381            0 :   logic dec_tlu_flush_pause_r;
-     382          188 :   el2_br_pkt_t dec_i0_brp;
-     383          792 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
-     384        12010 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
+     382          116 :   el2_br_pkt_t dec_i0_brp;
+     383          500 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
+     384         7134 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
      385            0 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
      386            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
      387              : 
      388            2 :   logic [31:1] dec_tlu_i0_pc_r;
      389            0 :   logic dec_tlu_i0_kill_writeb_wb;
-     390        36368 :   logic dec_tlu_i0_valid_r;
+     390        22348 :   logic dec_tlu_i0_valid_r;
      391              : 
      392            0 :   logic dec_pause_state;
      393              : 
@@ -499,15 +499,15 @@
      395              : 
      396            0 :   logic dec_tlu_flush_extint;  // Fast ext int started
      397              : 
-     398         4348 :   logic [31:0] dec_i0_inst_wb;
+     398         2724 :   logic [31:0] dec_i0_inst_wb;
      399            2 :   logic [31:1] dec_i0_pc_wb;
-     400           28 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
+     400           16 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
      401            0 :   logic [ 4:0] dec_tlu_exc_cause_wb1;
      402            0 :   logic [31:0] dec_tlu_mtval_wb1;
      403            0 :   logic        dec_tlu_i0_exc_valid_wb1;
      404              : 
      405            2 :   logic [ 4:0] div_waddr_wb;
-     406           56 :   logic        dec_div_active;
+     406           40 :   logic        dec_div_active;
      407              : 
      408            0 :   logic        dec_debug_valid_d;
      409              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_csr_equ_m.svh.html
new file mode 100644
index 00000000000..e89d072b5f2
--- /dev/null
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_csr_equ_m.svh.html
@@ -0,0 +1,573 @@
+
+
+
+
+    
+    
+        Full
+        coverage report
+    
+    
+    
+
+
+
+    
+        
+    

+            
+                
+                
+            

+                    Project
+                    Full
+                    coverage report
+                

+        

+    

+        
+            
+                
+                
+                
+                
+                
+                
+                
+            
+            
+                
+                
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+    
+
+            
+            
+                
+                
+                
+                
+    
+    
+    
+    
+
+            
+            
+        
Current view:
+                    Cores-VeeR-EL2—Cores-VeeR-EL2—design—include—el2_dec_csr_equ_m.svh
+                CoverageHitTotal
Test Date:
+                    25-09-2024
+                
+        Toggle
+    
+        11.9%
+    
+        10
+    
+        84
+    
Test:
+                    ahb_irq
+                
+        Branch
+    
+        0.0%
+    
+        0
+    
+        0
+    

+    

+
+    
+
+
+
+
+
+
+


+
            Line data    Source code

+
+       1            4 : logic csr_misa;
+       2            0 : logic csr_mvendorid;
+       3            0 : logic csr_marchid;
+       4            0 : logic csr_mimpid;
+       5            0 : logic csr_mhartid;
+       6           66 : logic csr_mstatus;
+       7            4 : logic csr_mtvec;
+       8            0 : logic csr_mip;
+       9            8 : logic csr_mie;
+      10            0 : logic csr_mcyclel;
+      11            0 : logic csr_mcycleh;
+      12            0 : logic csr_minstretl;
+      13            0 : logic csr_minstreth;
+      14            0 : logic csr_mscratch;
+      15           16 : logic csr_mepc;
+      16           24 : logic csr_mcause;
+      17            0 : logic csr_mscause;
+      18            0 : logic csr_mtval;
+      19            0 : logic csr_mrac;
+      20            0 : logic csr_dmst;
+      21            0 : logic csr_mdseac;
+      22            0 : logic csr_meihap;
+      23            0 : logic csr_meivt;
+      24            0 : logic csr_meipt;
+      25            0 : logic csr_meicurpl;
+      26            0 : logic csr_meicidpl;
+      27            0 : logic csr_dcsr;
+      28            0 : logic csr_mcgc;
+      29            0 : logic csr_mfdc;
+      30            0 : logic csr_dpc;
+      31            0 : logic csr_mtsel;
+      32            0 : logic csr_mtdata1;
+      33            0 : logic csr_mtdata2;
+      34            0 : logic csr_mhpmc3;
+      35            0 : logic csr_mhpmc4;
+      36            0 : logic csr_mhpmc5;
+      37            0 : logic csr_mhpmc6;
+      38            0 : logic csr_mhpmc3h;
+      39            0 : logic csr_mhpmc4h;
+      40            0 : logic csr_mhpmc5h;
+      41            0 : logic csr_mhpmc6h;
+      42            0 : logic csr_mhpme3;
+      43            0 : logic csr_mhpme4;
+      44            0 : logic csr_mhpme5;
+      45            0 : logic csr_mhpme6;
+      46            0 : logic csr_mcountinhibit;
+      47            0 : logic csr_mitctl0;
+      48            0 : logic csr_mitctl1;
+      49            0 : logic csr_mitb0;
+      50            0 : logic csr_mitb1;
+      51            0 : logic csr_mitcnt0;
+      52            0 : logic csr_mitcnt1;
+      53            0 : logic csr_perfva;
+      54            0 : logic csr_perfvb;
+      55            0 : logic csr_perfvc;
+      56            0 : logic csr_perfvd;
+      57            0 : logic csr_perfve;
+      58            0 : logic csr_perfvf;
+      59            0 : logic csr_perfvg;
+      60            0 : logic csr_perfvh;
+      61            0 : logic csr_perfvi;
+      62            0 : logic csr_mpmc;
+      63            0 : logic csr_mcpc;
+      64            0 : logic csr_meicpct;
+      65            0 : logic csr_mdeau;
+      66            0 : logic csr_micect;
+      67            0 : logic csr_miccmect;
+      68            0 : logic csr_mdccmect;
+      69            0 : logic csr_mfdht;
+      70            0 : logic csr_mfdhs;
+      71            0 : logic csr_dicawics;
+      72            0 : logic csr_dicad0h;
+      73            0 : logic csr_dicad0;
+      74            0 : logic csr_dicad1;
+      75            0 : logic csr_dicago;
+      76            4 : logic csr_pmpcfg;
+      77            4 : logic csr_pmpaddr0;
+      78            0 : logic csr_pmpaddr16;
+      79            0 : logic csr_pmpaddr32;
+      80            0 : logic csr_pmpaddr48;
+      81            0 : logic valid_only;
+      82            0 : logic presync;
+      83           46 : logic postsync;
+      84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+      85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+      86              : 
+      87              : assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+      88              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+      89              : 
+      90              : assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+      91              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+      92              : 
+      93              : assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]
+      94              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+      95              : 
+      96              : assign csr_mhartid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+      97              :     &dec_csr_rdaddr_d[2]);
+      98              : 
+      99              : assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     100              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);
+     101              : 
+     102              : assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     103              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     104              : 
+     105              : assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]);
+     106              : 
+     107              : assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     108              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);
+     109              : 
+     110              : assign csr_mcyclel = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     111              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     112              :     &!dec_csr_rdaddr_d[1]);
+     113              : 
+     114              : assign csr_mcycleh = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     115              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     116              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     117              : 
+     118              : assign csr_minstretl = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     119              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     120              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     121              : 
+     122              : assign csr_minstreth = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     123              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     124              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     125              : 
+     126              : assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     127              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     128              : 
+     129              : assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     130              :     &dec_csr_rdaddr_d[0]);
+     131              : 
+     132              : assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     133              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     134              : 
+     135              : assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     136              :     &dec_csr_rdaddr_d[2]);
+     137              : 
+     138              : assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[1]
+     139              :     &dec_csr_rdaddr_d[0]);
+     140              : 
+     141              : assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     142              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     143              :     &!dec_csr_rdaddr_d[1]);
+     144              : 
+     145              : assign csr_dmst = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     146              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     147              : 
+     148              : assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     149              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]);
+     150              : 
+     151              : assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     152              :     &dec_csr_rdaddr_d[3]);
+     153              : 
+     154              : assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     155              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     156              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     157              : 
+     158              : assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     159              :     &dec_csr_rdaddr_d[0]);
+     160              : 
+     161              : assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     162              :     &dec_csr_rdaddr_d[2]);
+     163              : 
+     164              : assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     165              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     166              : 
+     167              : assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     168              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);
+     169              : 
+     170              : assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     171              :     &!dec_csr_rdaddr_d[0]);
+     172              : 
+     173              : assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     174              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     175              : 
+     176              : assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     177              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
+     178              : 
+     179              : assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     180              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     181              : 
+     182              : assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     183              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
+     184              : 
+     185              : assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     186              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);
+     187              : 
+     188              : assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     189              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     190              :     &dec_csr_rdaddr_d[0]);
+     191              : 
+     192              : assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     193              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     194              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     195              : 
+     196              : assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     197              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     198              :     &dec_csr_rdaddr_d[0]);
+     199              : 
+     200              : assign csr_mhpmc6 = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]
+     201              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     202              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     203              : 
+     204              : assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     205              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     206              :     &dec_csr_rdaddr_d[0]);
+     207              : 
+     208              : assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     209              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     210              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     211              : 
+     212              : assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     213              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     214              :     &dec_csr_rdaddr_d[0]);
+     215              : 
+     216              : assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     217              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     218              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     219              : 
+     220              : assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     221              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     222              :     &dec_csr_rdaddr_d[0]);
+     223              : 
+     224              : assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     225              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     226              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     227              : 
+     228              : assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     229              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     230              :     &dec_csr_rdaddr_d[0]);
+     231              : 
+     232              : assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     233              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
+     234              :     &!dec_csr_rdaddr_d[0]);
+     235              : 
+     236              : assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     237              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     238              :     &!dec_csr_rdaddr_d[0]);
+     239              : 
+     240              : assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     241              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
+     242              :     &!dec_csr_rdaddr_d[0]);
+     243              : 
+     244              : assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]
+     245              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     246              : 
+     247              : assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
+     248              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     249              : 
+     250              : assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
+     251              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     252              : 
+     253              : assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     254              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
+     255              :     &!dec_csr_rdaddr_d[0]);
+     256              : 
+     257              : assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[2]
+     258              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     259              : 
+     260              : assign csr_perfva  = 1'b0;
+     261              : 
+     262              : assign csr_perfvb  = 1'b0;
+     263              : 
+     264              : assign csr_perfvc  = 1'b0;
+     265              : 
+     266              : assign csr_perfvd  = 1'b0;
+     267              : 
+     268              : assign csr_perfve  = 1'b0;
+     269              : 
+     270              : assign csr_perfvf  = 1'b0;
+     271              : 
+     272              : assign csr_perfvg  = 1'b0;
+     273              : 
+     274              : assign csr_perfvh  = 1'b0;
+     275              : 
+     276              : assign csr_perfvi  = 1'b0;
+     277              : 
+     278              : assign csr_mpmc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     279              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     280              : 
+     281              : assign csr_mcpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     282              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     283              : 
+     284              : assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     285              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     286              : 
+     287              : assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     288              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
+     289              : 
+     290              : assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     291              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     292              : 
+     293              : assign csr_miccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     294              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
+     295              : 
+     296              : assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     297              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     298              : 
+     299              : assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     300              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     301              : 
+     302              : assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     303              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     304              : 
+     305              : assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     306              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     307              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     308              : 
+     309              : assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     310              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     311              : 
+     312              : assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     313              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     314              : 
+     315              : assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     316              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     317              : 
+     318              : assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     319              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     320              : 
+     321              : assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     322              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
+     323              : 
+     324              : assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     325              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
+     326              : 
+     327              : assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     328              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
+     329              : 
+     330              : assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     331              :     &dec_csr_rdaddr_d[4]);
+     332              : 
+     333              : assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     334              :     &!dec_csr_rdaddr_d[4]);
+     335              : 
+     336              : assign valid_only = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[2]
+     337              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[7]
+     338              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
+     339              :     !dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[4]) | (
+     340              :     !dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (
+     341              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+     342              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[3]);
+     343              : 
+     344              : assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     345              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     346              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     347              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
+     348              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     349              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     350              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | (
+     351              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     352              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]
+     353              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     354              :     &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
+     355              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     356              : 
+     357              : assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     358              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     359              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]
+     360              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     361              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     362              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     363              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | (
+     364              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]
+     365              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
+     366              :     dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
+     368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     369              : 
+     370           96 : logic legal;
+     371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     374              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
+     375              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     376              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     377              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     378              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     379              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     380              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     381              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     382              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     383              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     384              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
+     385              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     386              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (
+     387              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     388              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     389              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
+     390              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     391              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     392              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     393              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     394              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     395              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]
+     396              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     397              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     398              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     399              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     400              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     401              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     402              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
+     403              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     404              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     405              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     406              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
+     407              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     408              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     409              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     410              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     411              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     412              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     413              :     &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
+     414              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     415              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     416              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     417              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     418              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     419              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     420              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     421              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     422              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     423              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     424              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
+     425              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     426              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]
+     427              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     428              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     429              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     430              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     431              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     432              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[9]
+     433              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     434              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
+     435              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     436              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     437              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     438              :     &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     439              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     440              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
+     441              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     442              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     443              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     444              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     445              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     446              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
+     447              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     448              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     449              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
+     450              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     451              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     452              :     &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     453              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     454              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]
+     455              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     456              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
+     457              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     458              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     459              :     &dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     460              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     461              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);
+     462              : 
+        

+

+
+
+
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_csr_equ_mu.svh.html
deleted file mode 100644
index 611a5230854..00000000000
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_csr_equ_mu.svh.html
+++ /dev/null
@@ -1,666 +0,0 @@
-
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-    
-    
-        Full
-        coverage report
-    
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-        
-    

-            
-                
-                
-            

-                    Project
-                    Full
-                    coverage report
-                

-        

-    

-        
-            
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-        
Current view:
-                    Cores-VeeR-EL2—Cores-VeeR-EL2—design—include—el2_dec_csr_equ_mu.svh
-                CoverageHitTotal
Test Date:
-                    19-09-2024
-                
-        Toggle
-    
-        10.9%
-    
-        11
-    
-        101
-    
Test:
-                    ahb_irq
-                
-        Branch
-    
-        0.0%
-    
-        0
-    
-        0
-    

-    

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-    
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-


-
            Line data    Source code

-
-       1            4 : logic csr_misa;
-       2            0 : logic csr_mvendorid;
-       3            0 : logic csr_marchid;
-       4            0 : logic csr_mimpid;
-       5            0 : logic csr_mhartid;
-       6          102 : logic csr_mstatus;
-       7            4 : logic csr_mtvec;
-       8            0 : logic csr_mip;
-       9            8 : logic csr_mie;
-      10            0 : logic csr_mcyclel;
-      11            0 : logic csr_mcycleh;
-      12            0 : logic csr_minstretl;
-      13            0 : logic csr_minstreth;
-      14            0 : logic csr_mscratch;
-      15           32 : logic csr_mepc;
-      16           44 : logic csr_mcause;
-      17            0 : logic csr_mscause;
-      18            0 : logic csr_mtval;
-      19            0 : logic csr_mrac;
-      20            0 : logic csr_dmst;
-      21            0 : logic csr_mdseac;
-      22            0 : logic csr_meihap;
-      23            0 : logic csr_meivt;
-      24            0 : logic csr_meipt;
-      25            0 : logic csr_meicurpl;
-      26            0 : logic csr_meicidpl;
-      27            0 : logic csr_dcsr;
-      28            0 : logic csr_mcgc;
-      29            0 : logic csr_mfdc;
-      30            0 : logic csr_dpc;
-      31            0 : logic csr_mtsel;
-      32            0 : logic csr_mtdata1;
-      33            0 : logic csr_mtdata2;
-      34            0 : logic csr_mhpmc3;
-      35            0 : logic csr_mhpmc4;
-      36            0 : logic csr_mhpmc5;
-      37            0 : logic csr_mhpmc6;
-      38            0 : logic csr_mhpmc3h;
-      39            0 : logic csr_mhpmc4h;
-      40            0 : logic csr_mhpmc5h;
-      41            0 : logic csr_mhpmc6h;
-      42            0 : logic csr_mhpme3;
-      43            0 : logic csr_mhpme4;
-      44            0 : logic csr_mhpme5;
-      45            0 : logic csr_mhpme6;
-      46            0 : logic csr_mcounteren;
-      47            0 : logic csr_mcountinhibit;
-      48            0 : logic csr_mitctl0;
-      49            0 : logic csr_mitctl1;
-      50            0 : logic csr_mitb0;
-      51            0 : logic csr_mitb1;
-      52            0 : logic csr_mitcnt0;
-      53            0 : logic csr_mitcnt1;
-      54            0 : logic csr_perfva;
-      55            0 : logic csr_perfvb;
-      56            0 : logic csr_perfvc;
-      57            0 : logic csr_perfvd;
-      58            0 : logic csr_perfve;
-      59            0 : logic csr_perfvf;
-      60            0 : logic csr_perfvg;
-      61            0 : logic csr_perfvh;
-      62            0 : logic csr_perfvi;
-      63            0 : logic csr_mpmc;
-      64            0 : logic csr_mcpc;
-      65            0 : logic csr_meicpct;
-      66            0 : logic csr_mdeau;
-      67            0 : logic csr_micect;
-      68            0 : logic csr_miccmect;
-      69            0 : logic csr_mdccmect;
-      70            0 : logic csr_mfdht;
-      71            0 : logic csr_mfdhs;
-      72            0 : logic csr_dicawics;
-      73            0 : logic csr_dicad0h;
-      74            0 : logic csr_dicad0;
-      75            0 : logic csr_dicad1;
-      76            0 : logic csr_dicago;
-      77            0 : logic csr_menvcfg;
-      78            0 : logic csr_menvcfgh;
-      79            4 : logic csr_pmpcfg;
-      80            4 : logic csr_pmpaddr0;
-      81            0 : logic csr_pmpaddr16;
-      82            0 : logic csr_pmpaddr32;
-      83            0 : logic csr_pmpaddr48;
-      84          162 : logic csr_cyclel;
-      85            0 : logic csr_cycleh;
-      86            0 : logic csr_instretl;
-      87            0 : logic csr_instreth;
-      88            0 : logic csr_hpmc3;
-      89            0 : logic csr_hpmc4;
-      90            0 : logic csr_hpmc5;
-      91            0 : logic csr_hpmc6;
-      92            0 : logic csr_hpmc3h;
-      93            0 : logic csr_hpmc4h;
-      94            0 : logic csr_hpmc5h;
-      95            0 : logic csr_hpmc6h;
-      96            0 : logic csr_mseccfgl;
-      97            0 : logic csr_mseccfgh;
-      98            0 : logic valid_only;
-      99            0 : logic presync;
-     100           66 : logic postsync;
-     101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     103              : 
-     104              : assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     105              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     106              : 
-     107              : assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     108              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     109              : 
-     110              : assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]
-     111              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     112              : 
-     113              : assign csr_mhartid = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     114              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]);
-     115              : 
-     116              : assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     117              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
-     118              :     &!dec_csr_rdaddr_d[0]);
-     119              : 
-     120              : assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     121              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     122              : 
-     123              : assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
-     124              :     &!dec_csr_rdaddr_d[0]);
-     125              : 
-     126              : assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     127              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     128              : 
-     129              : assign csr_mcyclel = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     130              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     131              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     132              : 
-     133              : assign csr_mcycleh = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     134              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     135              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     136              : 
-     137              : assign csr_minstretl = (dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     138              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     139              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     140              : 
-     141              : assign csr_minstreth = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     142              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     143              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     144              : 
-     145              : assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     146              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     147              : 
-     148              : assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     149              :     &dec_csr_rdaddr_d[0]);
-     150              : 
-     151              : assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     152              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     153              : 
-     154              : assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     155              :     &dec_csr_rdaddr_d[2]);
-     156              : 
-     157              : assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[2]
-     158              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     159              : 
-     160              : assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     161              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     162              :     &!dec_csr_rdaddr_d[1]);
-     163              : 
-     164              : assign csr_dmst = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
-     165              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     166              : 
-     167              : assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     168              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
-     169              : 
-     170              : assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     171              :     &dec_csr_rdaddr_d[3]);
-     172              : 
-     173              : assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     174              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     175              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     176              : 
-     177              : assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     178              :     &dec_csr_rdaddr_d[0]);
-     179              : 
-     180              : assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     181              :     &dec_csr_rdaddr_d[2]);
-     182              : 
-     183              : assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     184              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     185              : 
-     186              : assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     187              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);
-     188              : 
-     189              : assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     190              :     &!dec_csr_rdaddr_d[0]);
-     191              : 
-     192              : assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     193              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     194              : 
-     195              : assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     196              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
-     197              : 
-     198              : assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     199              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     200              : 
-     201              : assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     202              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
-     203              : 
-     204              : assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     205              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);
-     206              : 
-     207              : assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     208              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     209              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     210              : 
-     211              : assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     212              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     213              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     214              : 
-     215              : assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     216              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     217              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     218              : 
-     219              : assign csr_mhpmc6 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     220              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     221              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     222              : 
-     223              : assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     224              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     225              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     226              : 
-     227              : assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     228              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     229              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     230              : 
-     231              : assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     232              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     233              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     234              : 
-     235              : assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     236              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     237              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     238              : 
-     239              : assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     240              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     241              :     &dec_csr_rdaddr_d[0]);
-     242              : 
-     243              : assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     244              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     245              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     246              : 
-     247              : assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     248              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
-     249              :     &dec_csr_rdaddr_d[0]);
-     250              : 
-     251              : assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     252              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
-     253              :     &!dec_csr_rdaddr_d[0]);
-     254              : 
-     255              : assign csr_mcounteren = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     256              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     257              : 
-     258              : assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     259              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     260              :     &!dec_csr_rdaddr_d[0]);
-     261              : 
-     262              : assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     263              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
-     264              :     &!dec_csr_rdaddr_d[0]);
-     265              : 
-     266              : assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     267              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     268              :     &dec_csr_rdaddr_d[0]);
-     269              : 
-     270              : assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
-     271              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     272              : 
-     273              : assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
-     274              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     275              : 
-     276              : assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     277              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
-     278              :     &!dec_csr_rdaddr_d[0]);
-     279              : 
-     280              : assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]
-     281              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     282              : 
-     283              : assign csr_perfva  = 1'b0;
-     284              : 
-     285              : assign csr_perfvb  = 1'b0;
-     286              : 
-     287              : assign csr_perfvc  = 1'b0;
-     288              : 
-     289              : assign csr_perfvd  = 1'b0;
-     290              : 
-     291              : assign csr_perfve  = 1'b0;
-     292              : 
-     293              : assign csr_perfvf  = 1'b0;
-     294              : 
-     295              : assign csr_perfvg  = 1'b0;
-     296              : 
-     297              : assign csr_perfvh  = 1'b0;
-     298              : 
-     299              : assign csr_perfvi  = 1'b0;
-     300              : 
-     301              : assign csr_mpmc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     302              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     303              :     &dec_csr_rdaddr_d[1]);
-     304              : 
-     305              : assign csr_mcpc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
-     306              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     307              : 
-     308              : assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     309              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     310              : 
-     311              : assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     312              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
-     313              : 
-     314              : assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     315              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     316              : 
-     317              : assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     318              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
-     319              : 
-     320              : assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     321              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     322              : 
-     323              : assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     324              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     325              : 
-     326              : assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
-     327              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     328              : 
-     329              : assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     330              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     331              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     332              : 
-     333              : assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     334              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     335              : 
-     336              : assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
-     337              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     338              : 
-     339              : assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     340              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     341              : 
-     342              : assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     343              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     344              : 
-     345              : assign csr_menvcfg = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     346              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]);
-     347              : 
-     348              : assign csr_menvcfgh = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     349              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
-     350              : 
-     351              : assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     352              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
-     353              : 
-     354              : assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     355              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
-     356              : 
-     357              : assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     358              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
-     359              : 
-     360              : assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     361              :     &dec_csr_rdaddr_d[4]);
-     362              : 
-     363              : assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     364              :     &!dec_csr_rdaddr_d[4]);
-     365              : 
-     366              : assign csr_cyclel = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     367              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     368              : 
-     369              : assign csr_cycleh = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     370              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     371              : 
-     372              : assign csr_instretl = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     373              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     374              : 
-     375              : assign csr_instreth = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     376              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     377              : 
-     378              : assign csr_hpmc3 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     379              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     380              : 
-     381              : assign csr_hpmc4 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     382              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     383              : 
-     384              : assign csr_hpmc5 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     385              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     386              : 
-     387              : assign csr_hpmc6 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     388              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     389              : 
-     390              : assign csr_hpmc3h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     391              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     392              : 
-     393              : assign csr_hpmc4h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     394              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     395              : 
-     396              : assign csr_hpmc5h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     397              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     398              : 
-     399              : assign csr_hpmc6h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     400              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     401              : 
-     402              : assign csr_mseccfgl = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     403              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]);
-     404              : 
-     405              : assign csr_mseccfgh = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     406              :     &dec_csr_rdaddr_d[4]);
-     407              : 
-     408              : assign valid_only = (!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     409              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (
-     410              :     !dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
-     411              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
-     412              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[7]
-     413              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
-     414              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
-     415              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]);
-     416              : 
-     417              : assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     418              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
-     419              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     420              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
-     421              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
-     422              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     423              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
-     424              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
-     425              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
-     426              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
-     427              :     dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     428              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     429              : 
-     430              : assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     431              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     432              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]
-     433              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
-     434              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     435              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
-     436              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
-     437              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]
-     438              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
-     439              :     dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[4]
-     440              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
-     441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     442              :     &dec_csr_rdaddr_d[0]);
-     443              : 
-     444          160 : logic legal;
-     445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     448              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
-     449              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     450              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     451              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     452              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     453              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     454              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     455              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     456              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     457              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     458              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     459              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     460              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     461              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     462              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]
-     463              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     464              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
-     465              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     466              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     467              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
-     468              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     469              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (
-     470              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     471              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
-     472              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     473              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     474              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     475              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
-     476              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     477              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (
-     478              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]
-     479              :     &!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     480              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     481              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     482              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     483              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     484              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     485              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     486              :     &!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     487              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     488              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
-     489              :     &dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]
-     490              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     491              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     492              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     493              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     494              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
-     495              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     496              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     497              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
-     498              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     499              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     500              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (
-     501              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     502              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     503              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     504              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
-     505              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     506              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     507              :     &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
-     508              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
-     509              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     510              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     511              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     512              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     513              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     514              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     515              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     516              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
-     517              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     518              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     519              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
-     520              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     521              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     522              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
-     523              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     524              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     525              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[9]
-     526              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     527              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
-     528              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     529              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     530              :     &!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     531              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     532              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     533              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     534              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
-     535              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     536              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     537              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
-     538              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     539              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     540              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
-     541              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     542              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     543              :     &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     544              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     545              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]
-     546              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     547              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
-     548              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     549              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     550              :     &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     551              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     552              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]
-     553              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     554              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);
-     555              : 
-        

-

-
-
-
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_decode_ctl.sv.html
index d500e74fe3d..14637d7d512 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_decode_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        68.4%
+    
+        68.0%
     
     
-        188
+        187
     
     
         275
@@ -133,18 +133,18 @@
       29              : 
       30            0 :    output logic dec_extint_stall,            // Stall from external interrupt
       31              : 
-      32         5236 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
-      33         4348 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
+      32         3260 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
+      33         2724 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
       34            2 :    output logic [31:1] dec_i0_pc_wb,         // 31b pc at wb+1 for trace encoder
       35              : 
       36              : 
-      37         5868 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
-      38         1920 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
+      37         3496 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
+      38         1280 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
       39            0 :    input logic                                lsu_nonblock_load_inv_r,         // invalidate request for nonblock load r
-      40         1920 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
-      41         6000 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
+      40         1280 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
+      41         3576 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
       42            0 :    input logic                                lsu_nonblock_load_data_error,    // nonblock load bus error
-      43          120 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
+      43           76 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
       44              : 
       45              : 
       46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
@@ -168,137 +168,137 @@
       64              : 
       65            0 :    input logic dec_i0_dbecc_d,                        // icache/iccm double-bit error
       66              : 
-      67          188 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
-      68          792 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69        12010 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      67          116 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
+      68          500 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      69         7134 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
-      73         8954 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
+      73         5458 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
       74              : 
-      75          248 :    input logic lsu_load_stall_any,                    // stall any load at decode
-      76          248 :    input logic lsu_store_stall_any,                   // stall any store at decode
+      75          160 :    input logic lsu_load_stall_any,                    // stall any load at decode
+      76          160 :    input logic lsu_store_stall_any,                   // stall any store at decode
       77            0 :    input logic dma_dccm_stall_any,                    // stall any load/store at decode
       78              : 
-      79           56 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
+      79           40 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
       80              : 
       81            0 :    input logic dec_tlu_i0_kill_writeb_wb,             // I0 is flushed, don't writeback any results to arch state
-      82           64 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
+      82           36 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
       83            0 :    input logic dec_tlu_i0_kill_writeb_r,              // I0 is flushed, don't writeback any results to arch state
-      84           64 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
+      84           36 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
       85            0 :    input logic dec_tlu_flush_pause_r,                 // don't clear pause state on initial lower flush
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
-      87           96 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
+      87           52 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89        19040 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89        11620 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91            4 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92          160 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92           96 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
       96            0 :    input logic [31:0] lsu_result_m,                   // load result
       97            0 :    input logic [31:0] lsu_result_corr_r,              // load result - corrected data for writing gpr's, not for bypassing
       98              : 
-      99         1524 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
+      99         1084 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
      100              : 
      101            2 :    input logic [31:1] exu_i0_pc_x,                    // pcs at e1
      102              : 
-     103          656 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
+     103          392 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
      104              : 
-     105        34772 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
+     105        21400 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
      106              : 
-     107         1012 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
+     107          616 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109       584906 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110       584906 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111       584906 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109       359918 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110       359918 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111       359918 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
      115              : 
      116              : 
      117              : 
-     118        30300 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
-     119        16396 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
+     118        18512 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
+     119         9920 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
-     121        10480 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122        10496 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     121         6404 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
+     122         6336 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124         1876 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124         1192 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
-     127         1192 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
+     127          840 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
      128              : 
      129            0 :    output el2_alu_pkt_t i0_ap,                       // alu packets
      130              : 
-     131        36372 :    output logic        dec_i0_decode_d,               // i0 decode
+     131        22352 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
-     133        26004 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134        11376 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     133        15936 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
+     134         7028 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
-     136        11748 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137        18372 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     136         7300 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
+     137        11212 :    output logic        dec_i0_wen_r,                  // i0 write enable
      138            4 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
-     140          844 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
+     140          576 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
      141              : 
-     142         1380 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
-     143           28 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
+     142          808 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
+     143            4 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
      144            4 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
      145              : 
-     146         2568 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
-     147        26638 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
+     146         1396 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
+     147        16414 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
      148              : 
      149            0 :    output el2_mul_pkt_t    mul_p,                    // multiply packet
      150              : 
-     151           28 :    output el2_div_pkt_t    div_p,                    // divide packet
+     151           20 :    output el2_div_pkt_t    div_p,                    // divide packet
      152            2 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
      153            0 :    output logic             dec_div_cancel,           // cancel the divide operation
      154              : 
-     155        11276 :    output logic        dec_lsu_valid_raw_d,
-     156          684 :    output logic [11:0] dec_lsu_offset_d,
+     155         6928 :    output logic        dec_lsu_valid_raw_d,
+     156          420 :    output logic [11:0] dec_lsu_offset_d,
      157              : 
-     158          124 :    output logic        dec_csr_ren_d,                 // valid csr decode
-     159           36 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
-     160          160 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
+     158           72 :    output logic        dec_csr_ren_d,                 // valid csr decode
+     159           24 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
+     160           96 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
      161            4 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
-     162           36 :    output logic        dec_csr_wen_r,                 // csr write enable at r
-     163         8028 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
-     164            4 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
+     162           24 :    output logic        dec_csr_wen_r,                 // csr write enable at r
+     163         5092 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
+     164            8 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
      165            4 :    output logic [31:0] dec_csr_wrdata_r,              // csr write data at r
-     166           20 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
+     166           12 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
      167              : 
-     168        36368 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
+     168        22348 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
      169              : 
      170            0 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
      171              : 
      172            2 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
      173              : 
      174            0 :    output logic [31:0] dec_illegal_inst,              // illegal inst
-     175          650 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
+     175          470 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
-     177         1864 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178        12010 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
-     179          792 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
+     177         1120 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
+     178         7134 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     179          500 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      183              : 
-     184        36372 :    output logic [1:0] dec_data_en,                    // clock-gating logic
-     185        36284 :    output logic [1:0] dec_ctl_en,
+     184        22352 :    output logic [1:0] dec_data_en,                    // clock-gating logic
+     185        22292 :    output logic [1:0] dec_ctl_en,
      186              : 
-     187        36372 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
-     188         1676 :    output logic       dec_pmu_decode_stall,           // decode is stalled
+     187        22352 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
+     188         1000 :    output logic       dec_pmu_decode_stall,           // decode is stalled
      189            0 :    output logic       dec_pmu_presync_stall,          // decode has presync stall
-     190           32 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
+     190           16 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
      191              : 
-     192         6000 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
-     193          824 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
+     192         3576 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
+     193          496 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
      194            0 :    output logic       dec_pause_state,                // core in pause state
      195            0 :    output logic       dec_pause_state_cg,             // pause state for clock-gating
      196              : 
-     197           56 :    output logic       dec_div_active,                 // non-block divide is active
+     197           40 :    output logic       dec_div_active,                 // non-block divide is active
      198              : 
      199            0 :    input  logic       scan_mode
      200              :    );
@@ -308,27 +308,27 @@
      204              : 
      205            0 :    el2_dec_pkt_t           i0_dp_raw, i0_dp;
      206              : 
-     207          656 :    logic [31:0]        i0;
-     208        34772 :    logic               i0_valid_d;
+     207          392 :    logic [31:0]        i0;
+     208        21400 :    logic               i0_valid_d;
      209              : 
      210            4 :    logic [31:0]        i0_result_r;
      211              : 
-     212          160 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
+     212           88 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
      213              : 
-     214          656 :    logic               i0_jalimm20;
-     215          584 :    logic               i0_uiimm20;
+     214          392 :    logic               i0_jalimm20;
+     215          436 :    logic               i0_uiimm20;
      216              : 
-     217        11500 :    logic               lsu_decode_d;
-     218         1876 :    logic [31:0]        i0_immed_d;
+     217         7076 :    logic               lsu_decode_d;
+     218         1192 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
-     220         1464 :    logic               i0_postsync;
+     220          968 :    logic               i0_postsync;
      221              : 
-     222          128 :    logic               postsync_stall;
-     223          128 :    logic               ps_stall;
+     222           68 :    logic               postsync_stall;
+     223           68 :    logic               ps_stall;
      224              : 
-     225        36284 :    logic               prior_inflight, prior_inflight_wb;
+     225        22292 :    logic               prior_inflight, prior_inflight_wb;
      226              : 
-     227           36 :    logic               csr_clr_d, csr_set_d, csr_write_d;
+     227           24 :    logic               csr_clr_d, csr_set_d, csr_write_d;
      228              : 
      229            0 :    logic               csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
      230            0 :    logic [31:0]        csr_mask_x;
@@ -342,58 +342,58 @@
      238            0 :    logic [31:0]        csr_rddata_x;
      239              : 
      240            0 :    logic               mul_decode_d;
-     241           56 :    logic               div_decode_d;
-     242           56 :    logic               div_e1_to_r;
+     241           40 :    logic               div_decode_d;
+     242           40 :    logic               div_e1_to_r;
      243            0 :    logic               div_flush;
-     244           56 :    logic               div_active_in;
-     245           56 :    logic               div_active;
+     244           40 :    logic               div_active_in;
+     245           40 :    logic               div_active;
      246            0 :    logic               i0_nonblock_div_stall;
      247            0 :    logic               i0_div_prior_div_stall;
      248            0 :    logic               nonblock_div_cancel;
      249              : 
-     250        33440 :    logic               i0_legal;
+     250        20504 :    logic               i0_legal;
      251            0 :    logic               shift_illegal;
      252            0 :    logic               illegal_inst_en;
      253            0 :    logic               illegal_lockout_in, illegal_lockout;
-     254        36372 :    logic               i0_legal_decode_d;
-     255         1536 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
+     254        22352 :    logic               i0_legal_decode_d;
+     255          892 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
-     257         6624 :    logic [12:1]        last_br_immed_d;
-     258         1392 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
+     257         4100 :    logic [12:1]        last_br_immed_d;
+     258          816 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
-     261           56 :    logic               i0_div_decode_d;
+     261           40 :    logic               i0_div_decode_d;
      262            0 :    logic               i0_load_block_d;
      263            0 :    logic [1:0]         i0_rs1_depth_d, i0_rs2_depth_d;
      264              : 
-     265          108 :    logic               i0_load_stall_d;
-     266          144 :    logic               i0_store_stall_d;
+     265           68 :    logic               i0_load_stall_d;
+     266           96 :    logic               i0_store_stall_d;
      267              : 
-     268         4896 :    logic               i0_predict_nt, i0_predict_t;
+     268         2824 :    logic               i0_predict_nt, i0_predict_t;
      269              : 
-     270         1204 :    logic               i0_notbr_error, i0_br_toffset_error;
+     270          772 :    logic               i0_notbr_error, i0_br_toffset_error;
      271            8 :    logic               i0_ret_error;
-     272         1336 :    logic               i0_br_error;
-     273         1336 :    logic               i0_br_error_all;
-     274         8036 :    logic [11:0]        i0_br_offset;
+     272          900 :    logic               i0_br_error;
+     273          900 :    logic               i0_br_error_all;
+     274         5112 :    logic [11:0]        i0_br_offset;
      275              : 
-     276         4636 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
-     277        31138 :    logic               i0_pcall_12b_offset;
-     278          200 :    logic               i0_pcall_raw;
-     279          204 :    logic               i0_pcall_case;
-     280          200 :    logic               i0_pcall;
+     276         2624 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
+     277        19162 :    logic               i0_pcall_12b_offset;
+     278          132 :    logic               i0_pcall_raw;
+     279          136 :    logic               i0_pcall_case;
+     280          132 :    logic               i0_pcall;
      281              : 
-     282          456 :    logic               i0_pja_raw;
-     283          460 :    logic               i0_pja_case;
-     284          456 :    logic               i0_pja;
+     282          260 :    logic               i0_pja_raw;
+     283          264 :    logic               i0_pja_case;
+     284          260 :    logic               i0_pja;
      285              : 
-     286          200 :    logic               i0_pret_case;
-     287          200 :    logic               i0_pret_raw, i0_pret;
+     286          132 :    logic               i0_pret_case;
+     287          132 :    logic               i0_pret_raw, i0_pret;
      288              : 
-     289          180 :    logic               i0_jal;                                // jal's that are not predicted
+     289          108 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292         9864 :    logic               i0_predict_br;
+     292         6024 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301        19040 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301        11620 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303        23512 :    logic               i0_rd_en_d;
+     303        14420 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -412,43 +412,43 @@
      308            0 :    logic               leak1_i1_stall_in, leak1_i1_stall;
      309            0 :    logic               leak1_mode;
      310              : 
-     311           36 :    logic               i0_csr_write_only_d;
+     311           24 :    logic               i0_csr_write_only_d;
      312              : 
-     313        36284 :    logic               prior_inflight_x, prior_inflight_eff;
-     314          160 :    logic               any_csr_d;
+     313        22292 :    logic               prior_inflight_x, prior_inflight_eff;
+     314           96 :    logic               any_csr_d;
      315              : 
-     316           36 :    logic               prior_csr_write;
+     316           24 :    logic               prior_csr_write;
      317              : 
-     318        36372 :    logic [3:0]        i0_pipe_en;
-     319        36284 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
-     320        36372 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
+     318        22352 :    logic [3:0]        i0_pipe_en;
+     319        22292 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
+     320        22352 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
      321              : 
      322            0 :    logic              debug_fence_i;
      323            0 :    logic              debug_fence;
      324              : 
-     325           36 :    logic              i0_csr_write;
+     325           24 :    logic              i0_csr_write;
      326            0 :    logic              presync_stall;
      327              : 
      328            0 :    logic              i0_instr_error;
      329            0 :    logic              i0_icaf_d;
      330              : 
-     331           64 :    logic              clear_pause;
+     331           36 :    logic              clear_pause;
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335         9328 :    logic              i0_brp_valid;
-     336         4492 :    logic              nonblock_load_cancel;
-     337         8954 :    logic              lsu_idle;
+     335         5680 :    logic              i0_brp_valid;
+     336         2576 :    logic              nonblock_load_cancel;
+     337         5458 :    logic              lsu_idle;
      338            0 :    logic              lsu_pmu_misaligned_r;
-     339          124 :    logic              csr_ren_qual_d;
-     340          124 :    logic              csr_read_x;
-     341         1784 :    logic              i0_block_d;
-     342         1536 :    logic              i0_block_raw_d;  // This is use to create the raw valid
-     343          128 :    logic              ps_stall_in;
-     344         1528 :    logic [31:0]       i0_result_x;
+     339           72 :    logic              csr_ren_qual_d;
+     340           72 :    logic              csr_read_x;
+     341         1052 :    logic              i0_block_d;
+     342          892 :    logic              i0_block_raw_d;  // This is use to create the raw valid
+     343           68 :    logic              ps_stall_in;
+     344          948 :    logic [31:0]       i0_result_x;
      345              : 
-     346           36 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
-     347           36 :    el2_dest_pkt_t         x_d_in, r_d_in;
+     346           24 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
+     347           24 :    el2_dest_pkt_t         x_d_in, r_d_in;
      348              : 
      349            0 :    el2_trap_pkt_t         d_t, x_t, x_t_in, r_t_in, r_t;
      350              : 
@@ -456,16 +456,16 @@
      352              : 
      353            2 :    logic [31:1]       dec_i0_pc_r;
      354              : 
-     355           36 :    logic csr_read, csr_write;
-     356          180 :    logic i0_br_unpred;
+     355           24 :    logic csr_read, csr_write;
+     356          108 :    logic i0_br_unpred;
      357              : 
-     358         5868 :    logic nonblock_load_valid_m_delay;
-     359        23808 :    logic i0_wen_r;
+     358         3496 :    logic nonblock_load_valid_m_delay;
+     359        14484 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
      363              : 
-     364         1524 :    logic flush_final_r;
+     364         1084 :    logic flush_final_r;
      365              : 
      366            2 :    logic bitmanip_zbb_legal;
      367            2 :    logic bitmanip_zbs_legal;
@@ -489,52 +489,52 @@
      385              :    localparam NBLOAD_TAG_MSB  = pt.LSU_NUM_NBLOAD_WIDTH-1;
      386              : 
      387              : 
-     388         6000 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
-     389          120 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
-     390           36 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
+     388         3576 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
+     389           76 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
+     390           24 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
      391              : 
-     392          120 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
-     393           36 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
+     392           76 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
+     393           24 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
      394              : 
-     395           36 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
-     396           36 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
-     397           36 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
+     395           24 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
+     396           24 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
+     397           24 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
      398              : 
-     399          852 :    logic [4:0] nonblock_load_rd;
-     400         1408 :    logic i0_nonblock_load_stall;
-     401         1380 :    logic i0_nonblock_boundary_stall;
+     399          520 :    logic [4:0] nonblock_load_rd;
+     400          824 :    logic i0_nonblock_load_stall;
+     401          808 :    logic i0_nonblock_boundary_stall;
      402              : 
-     403           28 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
+     403            4 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
      404              : 
-     405         5868 :    logic i0_load_kill_wen_r;
+     405         3496 :    logic i0_load_kill_wen_r;
      406              : 
-     407           14 :    logic found;
+     407           10 :    logic found;
      408              : 
-     409           36 :    logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;
+     409           24 :    logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;
      410              : 
      411            0 :    logic debug_fence_raw;
      412              : 
      413            4 :    logic [31:0] i0_result_r_raw;
      414            4 :    logic [31:0] i0_result_corr_r;
      415              : 
-     416         6110 :    logic [12:1] last_br_immed_x;
+     416         3714 :    logic [12:1] last_br_immed_x;
      417              : 
-     418         5008 :    logic [31:0]        i0_inst_d;
-     419         4348 :    logic [31:0]        i0_inst_x;
-     420         4348 :    logic [31:0]        i0_inst_r;
-     421         4348 :    logic [31:0]        i0_inst_wb_in;
-     422         4348 :    logic [31:0]        i0_inst_wb;
+     418         3148 :    logic [31:0]        i0_inst_d;
+     419         2724 :    logic [31:0]        i0_inst_x;
+     420         2724 :    logic [31:0]        i0_inst_r;
+     421         2724 :    logic [31:0]        i0_inst_wb_in;
+     422         2724 :    logic [31:0]        i0_inst_wb;
      423              : 
      424            2 :    logic [31:1]        i0_pc_wb;
      425              : 
-     426        36372 :    logic               i0_wb_en;
+     426        22352 :    logic               i0_wb_en;
      427              : 
      428            2 :    logic               trace_enable;
      429              : 
      430            0 :    logic               debug_valid_x;
      431              : 
-     432        10068 :    el2_inst_pkt_t i0_itype;
-     433        10480 :    el2_reg_pkt_t i0r;
+     432         6140 :    el2_inst_pkt_t i0_itype;
+     433         6336 :    el2_reg_pkt_t i0r;
      434              : 
      435              : 
      436              :    rvdffie  #(8) misc1ff (.*,
@@ -631,14 +631,14 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530         2548 :       if (i0_br_error_all | i0_instr_error) begin
-     531         2548 :          i0_dp          =   '0;
-     532         2548 :          i0_dp.alu      = 1'b1;
-     533         2548 :          i0_dp.rs1      = 1'b1;
-     534         2548 :          i0_dp.rs2      = 1'b1;
-     535         2548 :          i0_dp.lor      = 1'b1;
-     536         2548 :          i0_dp.legal    = 1'b1;
-     537         2548 :          i0_dp.postsync = 1'b1;
+     530         2038 :       if (i0_br_error_all | i0_instr_error) begin
+     531         2038 :          i0_dp          =   '0;
+     532         2038 :          i0_dp.alu      = 1'b1;
+     533         2038 :          i0_dp.rs1      = 1'b1;
+     534         2038 :          i0_dp.rs2      = 1'b1;
+     535         2038 :          i0_dp.lor      = 1'b1;
+     536         2038 :          i0_dp.legal    = 1'b1;
+     537         2038 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -708,17 +708,17 @@
      604            2 :    always_comb begin
      605            2 :       found = 0;
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
-     607           47 :          if (~found) begin
-     608        16865 :             if (~cam[i].valid) begin
-     609       101677 :                cam_wen[i] = cam_write;
-     610       101677 :                found = 1'b1;
+     607           38 :          if (~found) begin
+     608        12652 :             if (~cam[i].valid) begin
+     609        77614 :                cam_wen[i] = cam_write;
+     610        77614 :                found = 1'b1;
      611              :             end
-     612        16865 :             else begin
-     613        16865 :                cam_wen[i] = 0;
+     612        12652 :             else begin
+     613        12652 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617       412116 :             cam_wen[i] = 0;
+     617       313842 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,28 +756,28 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655         2490 :          if (cam_data_reset_val[i])
-     656         2490 :            cam[i].valid = 1'b0;
+     655         1868 :          if (cam_data_reset_val[i])
+     656         1868 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
      659              : 
-     660         7470 :          if (cam_wen[i]) begin
-     661         7470 :             cam_in[i].valid    = 1'b1;
-     662         7470 :             cam_in[i].wb       = 1'b0;
-     663         7470 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
-     664         7470 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
+     660         5604 :          if (cam_wen[i]) begin
+     661         5604 :             cam_in[i].valid    = 1'b1;
+     662         5604 :             cam_in[i].wb       = 1'b0;
+     663         5604 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
+     664         5604 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666          254 :          else if ( (cam_inv_reset_val[i]) |
+     666          152 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
-     668          254 :            cam_in[i].valid = 1'b0;
+     668          152 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670       541824 :            cam_in[i] = cam[i];
+     670       412748 :            cam_in[i] = cam[i];
      671              : 
-     672         7470 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
-     673         7470 :            cam_in[i].wb = 1'b1;
+     672         5604 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     673         5604 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676       435324 :          if (dec_tlu_force_halt)
+     676       331976 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746        21628 :       if (i0_legal_decode_d) begin
-     747        21628 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748         2988 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749         3006 :          if (i0_dp.store)                i0_itype = STORE;
-     750         9768 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751        21628 :          if (i0_dp.zbb | i0_dp.zbs |
+     746        16420 :       if (i0_legal_decode_d) begin
+     747        16420 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748         2252 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749         2326 :          if (i0_dp.store)                i0_itype = STORE;
+     750         7304 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751        16420 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756           71 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757           15 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758        21628 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759        21628 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760        21628 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761        21628 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762        21628 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763           22 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764         5051 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765          683 :          if (i0_dp.jal)                  i0_itype = JAL;
+     756           52 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757           12 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758        16420 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759        16420 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760        16420 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761        16420 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762        16420 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763           16 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764         3922 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765          516 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862       108831 :       if (dec_extint_stall) begin
+     862        82994 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868       108831 :       else begin
-     869       108831 :          lsu_p.valid = lsu_decode_d;
+     868        82994 :       else begin
+     869        82994 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871       108831 :          lsu_p.load                         =  i0_dp.load ;
-     872       108831 :          lsu_p.store                        =  i0_dp.store;
-     873       108831 :          lsu_p.by                           =  i0_dp.by   ;
-     874       108831 :          lsu_p.half                         =  i0_dp.half ;
-     875       108831 :          lsu_p.word                         =  i0_dp.word ;
-     876       108831 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871        82994 :          lsu_p.load                         =  i0_dp.load ;
+     872        82994 :          lsu_p.store                        =  i0_dp.store;
+     873        82994 :          lsu_p.by                           =  i0_dp.by   ;
+     874        82994 :          lsu_p.half                         =  i0_dp.half ;
+     875        82994 :          lsu_p.word                         =  i0_dp.word ;
+     876        82994 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878       108831 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879       108831 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880       108831 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878        82994 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879        82994 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880        82994 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882       108831 :          lsu_p.unsign  =  i0_dp.unsign;
+     882        82994 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1380,7 +1380,7 @@
     1276            2 :       r_t_in.i0trigger[3:0]              = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
     1277            2 :       r_t_in.pmu_lsu_misaligned          = lsu_pmu_misaligned_r;   // only valid if a load/store is valid in DC3 stage
     1278              : 
-    1279           25 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
+    1279           18 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
     1280              : 
     1281              :    end
     1282              : 
@@ -1614,11 +1614,11 @@
     1510              : module el2_dec_dec_ctl
     1511              :   import el2_pkg::*;
     1512              : (
-    1513          656 :     input logic [31:0] inst,
+    1513          392 :     input logic [31:0] inst,
     1514            0 :     output el2_dec_pkt_t out
     1515              : );
     1516              : 
-    1517          656 :   logic [31:0] i;
+    1517          392 :   logic [31:0] i;
     1518              : 
     1519              :   assign i[31:0] = inst[31:0];
     1520              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_gpr_ctl.sv.html
index 43dfb424398..221eca74640 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -122,26 +122,26 @@
       18              : #(
       19              :    `include "el2_param.vh"
       20              :  )  (
-      21        10480 :     input logic [4:0]  raddr0,       // logical read addresses
-      22        10496 :     input logic [4:0]  raddr1,
+      21         6404 :     input logic [4:0]  raddr0,       // logical read addresses
+      22         6336 :     input logic [4:0]  raddr1,
       23              : 
-      24        18372 :     input logic        wen0,         // write enable
-      25        11748 :     input logic [4:0]  waddr0,       // write address
+      24        11212 :     input logic        wen0,         // write enable
+      25         7300 :     input logic [4:0]  waddr0,       // write address
       26            4 :     input logic [31:0] wd0,          // write data
       27              : 
-      28         6000 :     input logic        wen1,         // write enable
-      29          824 :     input logic [4:0]  waddr1,       // write address
-      30           12 :     input logic [31:0] wd1,          // write data
+      28         3576 :     input logic        wen1,         // write enable
+      29          496 :     input logic [4:0]  waddr1,       // write address
+      30            8 :     input logic [31:0] wd1,          // write data
       31              : 
-      32           56 :     input logic        wen2,         // write enable
+      32           40 :     input logic        wen2,         // write enable
       33            2 :     input logic [4:0]  waddr2,       // write address
       34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36       584906 :     input logic        clk,
+      36       359918 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
       39            4 :     output logic [31:0] rd0,         // read data
-      40            4 :     output logic [31:0] rd1,
+      40           16 :     output logic [31:0] rd1,
       41              : 
       42            0 :     input  logic        scan_mode
       43              : );
@@ -149,7 +149,7 @@
       45              :    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
       46              :    logic [31:1] [31:0] gpr_in;
       47            0 :    logic [31:1] w0v,w1v,w2v;
-      48           84 :    logic [31:1] gpr_wr_en;
+      48           52 :    logic [31:1] gpr_wr_en;
       49              : 
       50              :    // GPR Write Enables
       51              :    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_ib_ctl.sv.html
index 98440c49078..aff58443451 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,36 +129,36 @@
       25            0 :    input logic [1:0]           dbg_cmd_type,                       // dbg type
       26            0 :    input logic [31:0]          dbg_cmd_addr,                       // expand to 31:0
       27              : 
-      28          188 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
-      29          792 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30        12010 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      28          116 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
+      29          500 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
+      30         7134 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34        19040 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
-      35        34772 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
+      34        11620 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      35        21400 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
       38              : 
       39            0 :    input logic   ifu_i0_icaf_second,                               // i0 has access fault on second 2B of 4B inst
       40            0 :    input logic   ifu_i0_dbecc,                                     // i0 double-bit error
-      41          656 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
+      41          392 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
       42           10 :    input logic [31:1]  ifu_i0_pc,                                  // i0 pc from the aligner
       43              : 
       44              : 
-      45        34772 :    output logic dec_ib0_valid_d,                                   // ib0 valid
+      45        21400 :    output logic dec_ib0_valid_d,                                   // ib0 valid
       46            0 :    output logic dec_debug_valid_d,                                 // Debug read or write at D-stage
       47              : 
       48              : 
-      49          656 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
+      49          392 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
       50              : 
       51           10 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53        19040 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53        11620 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
-      55          188 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
-      56          792 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57        12010 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      55          116 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
+      56          500 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      57         7134 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
@@ -185,7 +185,7 @@
       81            0 :    logic         debug_read_csr;
       82            0 :    logic         debug_write_csr;
       83              : 
-      84          588 :    logic [34:0]  ifu_i0_pcdata, pc0;
+      84          376 :    logic [34:0]  ifu_i0_pcdata, pc0;
       85              : 
       86              :    assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
       87              :                                   ifu_i0_pc[31:1], ifu_i0_pc4 };
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_pmp_ctl.sv.html
index 0daeb2d1952..306b425ca6a 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        42.4%
+    
+        43.8%
     
     
         14
     
     
-        33
+        32
     
 
             
@@ -133,12 +133,12 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32       584906 :    input logic clk,
-      33       584906 :    input logic free_l2clk,
-      34       584906 :    input logic csr_wr_clk,
+      32       359918 :    input logic clk,
+      33       359918 :    input logic free_l2clk,
+      34       359918 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
-      36           36 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
-      37            4 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
+      36           24 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+      37            8 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
       38            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       39            4 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
       40              : 
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52            0 :    input el2_mseccfg_pkt_t mseccfg,
+      52              :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_tlu_ctl.sv.html
index 207a9ec6b56..002604efc02 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        30.4%
+    
+        30.0%
     
     
-        114
+        108
     
     
-        375
+        360
     
 
             
@@ -133,14 +133,14 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32       584906 :    input logic clk,
-      33       584906 :    input logic free_clk,
-      34       584906 :    input logic free_l2clk,
+      32       359918 :    input logic clk,
+      33       359918 :    input logic free_clk,
+      34       359918 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
       38            0 :    input logic [31:1] rst_vec, // reset vector, from core pins
-      39           12 :    input logic        nmi_int, // nmi pin
+      39            8 :    input logic        nmi_int, // nmi pin
       40            0 :    input logic [31:1] nmi_vec, // nmi vector
       41            0 :    input logic  i_cpu_halt_req,    // Asynchronous Halt request to CPU
       42            0 :    input logic  i_cpu_run_req,     // Asynchronous Restart request to CPU
@@ -149,29 +149,29 @@
       45              : 
       46              : 
       47              :    // perf counter inputs
-      48        36372 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
-      49         1382 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
-      50        36324 :    input logic       ifu_pmu_ic_miss, // icache miss
+      48        22352 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
+      49          942 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
+      50        22384 :    input logic       ifu_pmu_ic_miss, // icache miss
       51            0 :    input logic       ifu_pmu_ic_hit, // icache hit
       52            0 :    input logic       ifu_pmu_bus_error, // Instruction side bus error
       53            0 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
-      54        36322 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
-      55        36372 :    input logic       dec_pmu_instr_decoded, // decoded instructions
-      56         1676 :    input logic       dec_pmu_decode_stall, // decode stall
+      54        22382 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
+      55        22352 :    input logic       dec_pmu_instr_decoded, // decoded instructions
+      56         1000 :    input logic       dec_pmu_decode_stall, // decode stall
       57            0 :    input logic       dec_pmu_presync_stall, // decode stall due to presync'd inst
-      58           32 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
-      59          248 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
+      58           16 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
+      59          160 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
       60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
-      62         1280 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63         5720 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64         7718 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
-      65        11876 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
+      62          940 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
+      63         3488 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64         4698 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      65         7308 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
       66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
-      68           56 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
-      69         5868 :    input logic       lsu_pmu_load_external_m, // D side bus load
-      70         5664 :    input logic       lsu_pmu_store_external_m, // D side bus store
+      68           32 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
+      69         3496 :    input logic       lsu_pmu_load_external_m, // D side bus load
+      70         3596 :    input logic       lsu_pmu_store_external_m, // D side bus store
       71            0 :    input logic       dma_pmu_dccm_read,          // DMA DCCM read
       72            0 :    input logic       dma_pmu_dccm_write,         // DMA DCCM write
       73            0 :    input logic       dma_pmu_any_read,           // DMA read
@@ -190,18 +190,18 @@
       86            0 :    input logic         lsu_imprecise_error_load_any,      // store bus error
       87            2 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
       88              : 
-      89           36 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
-      90          160 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
+      89           24 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
+      90           96 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
       91            4 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
       92              : 
-      93           36 :    input logic        dec_csr_wen_r,      // csr write enable at wb
-      94         8028 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
-      95            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+      93           24 :    input logic        dec_csr_wen_r,      // csr write enable at wb
+      94         5092 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
+      95            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
       96            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       97              : 
-      98           20 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
+      98           12 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
       99              : 
-     100        36368 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
+     100        22348 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
      101              : 
      102            2 :    input logic [31:1] exu_npc_r, // for NPC tracking
      103              : 
@@ -210,21 +210,21 @@
      106            0 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
      107              : 
      108            0 :    input logic [31:0] dec_illegal_inst, // For mtval
-     109        36372 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
+     109        22352 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112         5260 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112         3160 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115         7996 :    input logic        exu_i0_br_valid_r, // valid
-     116         1280 :    input logic        exu_i0_br_mp_r, // mispredict
-     117        10172 :    input logic        exu_i0_br_middle_r, // middle of bank
+     115         4780 :    input logic        exu_i0_br_valid_r, // valid
+     116          940 :    input logic        exu_i0_br_mp_r, // mispredict
+     117         6176 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
      119              :    // branch info from pipe1 for errors or counter updates
      120              : 
-     121         2256 :    input logic             exu_i0_br_way_r, // way hit or repl
+     121         1384 :    input logic             exu_i0_br_way_r, // way hit or repl
      122              : 
-     123         9752 :    output logic dec_tlu_core_empty,  // core is empty
+     123         5948 :    output logic dec_tlu_core_empty,  // core is empty
      124              :    // Debug start
      125            0 :    output logic dec_dbg_cmd_done, // abstract command done
      126            0 :    output logic dec_dbg_cmd_fail, // abstract command failed
@@ -243,9 +243,9 @@
      139              : 
      140            0 :    input  logic dbg_halt_req, // DM requests a halt
      141            0 :    input  logic dbg_resume_req, // DM requests a resume
-     142        36324 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
-     143         8954 :    input  logic lsu_idle_any, // lsu is idle
-     144           56 :    input  logic dec_div_active, // oop div is active
+     142        22384 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
+     143         5458 :    input  logic lsu_idle_any, // lsu is idle
+     144           40 :    input  logic dec_div_active, // oop div is active
      145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
      146              : 
      147            0 :    input logic  ifu_ic_error_start,     // IC single bit error
@@ -262,8 +262,8 @@
      158            0 :    input logic       mhwakeup, // high priority external int, wakeup if halted
      159              : 
      160            0 :    input logic mexintpend, // external interrupt pending
-     161           12 :    input logic timer_int, // timer interrupt pending
-     162           12 :    input logic soft_int, // software interrupt pending
+     161            8 :    input logic timer_int, // timer interrupt pending
+     162            8 :    input logic soft_int, // software interrupt pending
      163              : 
      164            0 :    output logic o_cpu_halt_status, // PMU interface, halted
      165            0 :    output logic o_cpu_halt_ack, // halt req ack
@@ -284,24 +284,24 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183            4 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184          160 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183            0 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184           96 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
-     186         2256 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
+     186         1384 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
      188            0 :    output logic dec_tlu_i0_kill_writeb_wb,    // I0 is flushed, don't writeback any results to arch state
-     189           64 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
-     190        36368 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
+     189           36 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
+     190        22348 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
      191              : 
      192            0 :    output logic dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
-     193           64 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
+     193           36 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
      194            0 :    output logic [31:1] dec_tlu_flush_path_r, // flush pc
      195            0 :    output logic dec_tlu_fence_i_r,           // flush is a fence_i rfnpc, flush icache
      196            0 :    output logic dec_tlu_wr_pause_r,           // CSR write to pause reg is at R.
      197            0 :    output logic dec_tlu_flush_pause_r,        // Flush is due to pause
      198              : 
      199            0 :    output logic dec_tlu_presync_d,            // CSR read needs to be presync'd
-     200           96 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
+     200           52 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
      201              : 
      202              : 
      203            0 :    output logic [31:0] dec_tlu_mrac_ff,        // CSR for memory region control
@@ -314,8 +314,8 @@
      210            0 :    output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
      211              : 
      212            0 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
-     213        36368 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
-     214           28 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
+     213        22348 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
+     214           16 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
      215            0 :    output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
      216            0 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
      217              : 
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243           14 :    output logic  priv_mode,
-     244           14 :    output logic  priv_mode_eff,
-     245           14 :    output logic  priv_mode_ns,
+     243              :    output logic  priv_mode,
+     244              :    output logic  priv_mode_eff,
+     245              :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248            0 :    output logic [2:0] mseccfg,
+     248              :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -358,7 +358,7 @@
      254              :    output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES]
      255              :    );
      256              : 
-     257           12 :    logic         clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f,
+     257            8 :    logic         clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f,
      258            0 :                  nmi_lsu_store_type_f, allow_dbg_halt_csr_write, dbg_cmd_done_ns, i_cpu_run_req_d1_raw, debug_mode_status, lsu_single_ecc_error_r_d1,
      259            0 :                  sel_npc_r, sel_npc_resume, ce_int,
      260            0 :                  nmi_in_debug_mode, dpc_capture_npc, dpc_capture_pc, tdata_load, tdata_opcode, tdata_action, perfcnt_halted, tdata_chain,
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275            0 :    logic wr_mcounteren_r;
-     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277            0 :    logic wr_mseccfg_r;
-     278            8 :    logic [2:0] mseccfg_ns;
+     275              :    logic wr_mcounteren_r;
+     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277              :    logic wr_mseccfg_r;
+     278              :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,22 +389,22 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286            0 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            2 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
-     292            0 :    logic [1:0] mfdhs_ns, mfdhs;
+     292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
      294            0 :    logic        force_halt;
      295            0 :    logic [5:0]  mfdht, mfdht_ns;
-     296           26 :    logic mstatus_mie_ns;
+     296           14 :    logic mstatus_mie_ns;
      297            0 :    logic [30:0] mtvec_ns, mtvec;
      298            0 :    logic [15:2] dcsr_ns, dcsr;
      299            0 :    logic [5:0] mip_ns, mip;
      300            0 :    logic [5:0] mie_ns, mie;
-     301          262 :    logic [31:0] mcyclel_ns, mcyclel;
+     301          162 :    logic [31:0] mcyclel_ns, mcyclel;
      302            0 :    logic [31:0] mcycleh_ns, mcycleh;
-     303           42 :    logic [31:0] minstretl_ns, minstretl;
+     303           26 :    logic [31:0] minstretl_ns, minstretl;
      304            0 :    logic [31:0] minstreth_ns, minstreth;
      305            0 :    logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;
      306            0 :    logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;
@@ -426,10 +426,10 @@
      322            0 :    logic [3:0] mscause_ns, mscause, mscause_type;
      323            0 :    logic [31:0] mtval_ns, mtval;
      324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
-     325           64 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
+     325           36 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
      326            0 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
-     327        36368 :    logic i0_valid_wb;
-     328        36368 :    logic tlu_i0_commit_cmt;
+     327        22348 :    logic i0_valid_wb;
+     328        22348 :    logic tlu_i0_commit_cmt;
      329            0 :    logic [31:1] vectored_path, interrupt_path;
      330            0 :    logic [16:0] dicawics_ns, dicawics;
      331            0 :    logic        wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
@@ -441,25 +441,25 @@
      337            0 :                 ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r;
      338            0 :    logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready,
      339            0 :          take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible;
-     340           28 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
+     340           16 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
      341            0 :    logic synchronous_flush_r;
      342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
-     343         1052 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
-     344          262 :    logic [31:0] mcyclel_inc;
+     343          648 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
+     344          162 :    logic [31:0] mcyclel_inc;
      345            0 :    logic [31:0] mcycleh_inc;
      346              : 
-     347          168 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
+     347          104 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
      348              : 
-     349           42 :    logic [31:0] minstretl_inc, minstretl_read;
+     349           26 :    logic [31:0] minstretl_inc, minstretl_read;
      350            0 :    logic [31:0] minstreth_inc, minstreth_read;
      351            2 :    logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;
-     352          160 :    logic valid_csr;
+     352           96 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355         7208 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355         4176 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
-     357           60 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
-     358        36368 :    logic i0_trigger_eval_r;
+     357           32 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
+     358        22348 :    logic i0_trigger_eval_r;
      359              : 
      360            0 :    logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
      361            4 :    logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
@@ -481,7 +481,7 @@
      377            0 :    logic i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, pmu_fw_halt_req_ns, pmu_fw_halt_req_f, int_timer_stalled,
      378            0 :          fw_halt_req, enter_pmu_fw_halt_req, pmu_fw_tlu_halted, pmu_fw_tlu_halted_f, internal_pmu_fw_halt_mode,
      379            0 :          internal_pmu_fw_halt_mode_f, int_timer0_int_hold, int_timer1_int_hold, int_timer0_int_hold_f, int_timer1_int_hold_f;
-     380           12 :    logic nmi_int_delayed, nmi_int_detected;
+     380            8 :    logic nmi_int_delayed, nmi_int_detected;
      381            0 :    logic [3:0] trigger_execute, trigger_data, trigger_store;
      382            0 :    logic dec_tlu_pmu_fw_halted;
      383              : 
@@ -506,17 +506,17 @@
      402            8 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405       584906 :    logic csr_wr_clk;
+     405       359918 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
-     407         5664 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
+     407         3496 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
      409            0 :    logic lsu_single_ecc_error_r;
      410            0 :    logic [31:0] lsu_error_pkt_addr_r;
      411            2 :    logic mcyclel_cout_in;
-     412        36368 :    logic i0_valid_no_ebreak_ecall_r;
-     413        36368 :    logic minstret_enable_f;
-     414           64 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
-     415        36368 :    logic pc0_valid_r;
+     412        22348 :    logic i0_valid_no_ebreak_ecall_r;
+     413        22348 :    logic minstret_enable_f;
+     414           36 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
+     415        22348 :    logic pc0_valid_r;
      416            4 :    logic [15:0] mfdc_int, mfdc_ns;
      417            4 :    logic [31:0] mrac_in;
      418            4 :    logic [31:27] csr_sat;
@@ -535,22 +535,22 @@
      431            0 :    logic            mhpmc5h_wr_en0, mhpmc5h_wr_en;
      432            0 :    logic            mhpmc6h_wr_en0, mhpmc6h_wr_en;
      433            0 :    logic [63:0]     mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;
-     434           24 :    logic perfcnt_halted_d1, zero_event_r;
+     434           20 :    logic perfcnt_halted_d1, zero_event_r;
      435            0 :    logic [3:0] perfcnt_during_sleep;
      436            0 :    logic [9:0] event_r;
      437              : 
-     438        10068 :    el2_inst_pkt_t pmu_i0_itype_qual;
+     438         6140 :    el2_inst_pkt_t pmu_i0_itype_qual;
      439              : 
-     440           36 :    logic dec_csr_wen_r_mod;
+     440           24 :    logic dec_csr_wen_r_mod;
      441              : 
-     442           32 :    logic flush_clkvalid;
+     442           20 :    logic flush_clkvalid;
      443            0 :    logic sel_fir_addr;
      444            4 :    logic wr_mie_r;
      445            0 :    logic mtval_capture_pc_r;
      446            0 :    logic mtval_capture_pc_plus2_r;
      447            0 :    logic mtval_capture_inst_r;
      448            0 :    logic mtval_capture_lsu_r;
-     449           28 :    logic mtval_clear_r;
+     449           16 :    logic mtval_clear_r;
      450            0 :    logic wr_mcgc_r;
      451            0 :    logic wr_mfdc_r;
      452            0 :    logic wr_mdeau_r;
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483            0 :    logic  csr_acc_r;    // CSR access error
-     484           38 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         8782 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483              :    logic  csr_acc_r;    // CSR access error
+     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994            0 :    logic csr_wr_acc_r;
-     995            0 :    logic csr_rd_acc_r;
+     994              :    logic csr_wr_acc_r;
+     995              :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568            0 :    logic  pmp_any_region_locked;
+    1568              :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
@@ -2685,7 +2685,7 @@
     2581              :    // trace
     2582              :    //--------------------------------------------------------------------------------
     2583            0 :    logic [4:0] dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2;
-    2584           28 :    logic       dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2;
+    2584           16 :    logic       dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2;
     2585              : 
     2586              :    assign {dec_tlu_i0_valid_wb1,
     2587              :            dec_tlu_i0_exc_valid_wb1,
@@ -2828,12 +2828,12 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727       584906 :    input logic clk,
-    2728       584906 :    input logic free_l2clk,
-    2729       584906 :    input logic csr_wr_clk,
+    2727       359918 :    input logic clk,
+    2728       359918 :    input logic free_l2clk,
+    2729       359918 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
-    2731           36 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
-    2732            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+    2731           24 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
+    2732            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
     2733            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
     2734              : 
     2735            0 :    input logic csr_mitctl0,
@@ -2859,12 +2859,12 @@
     2755              :    localparam MITCTL_ENABLE_HALTED      = 1;
     2756              :    localparam MITCTL_ENABLE_PAUSED      = 2;
     2757              : 
-    2758          262 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
+    2758          162 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
     2759            0 :    logic [2:0] mitctl0_ns, mitctl0;
     2760            0 :    logic [3:0] mitctl1_ns, mitctl1;
     2761            0 :    logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
     2762            2 :    logic mitcnt0_inc_ok, mitcnt1_inc_ok;
-    2763         1052 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
+    2763          648 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
     2764            0 :  logic mit0_match_ns;
     2765            0 :  logic mit1_match_ns;
     2766            0 :  logic mitctl0_0_b_ns;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_trigger.sv.html
index b47b54f319d..1a2617b5212 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dma_ctrl.sv.html
index 141fff14c8c..495bf152a29 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29       584906 :    input logic         clk,
-      30       584906 :    input logic         free_clk,
+      29       359918 :    input logic         clk,
+      30       359918 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -173,8 +173,8 @@
       69            0 :    output logic        dma_active,         // DMA is busy
       70            0 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
       71            0 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
-      72        11278 :    input logic         dccm_ready, // dccm ready to accept DMA request
-      73         1550 :    input logic         iccm_ready, // iccm ready to accept DMA request
+      72         6930 :    input logic         dccm_ready, // dccm ready to accept DMA request
+      73         1106 :    input logic         iccm_ready, // iccm ready to accept DMA request
       74            2 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
       75              : 
       76              :    // PMU signals
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185       584906 :    logic                    dma_buffer_c1_clk;
-     186       584906 :    logic                    dma_free_clk;
+     185       359918 :    logic                    dma_buffer_c1_clk;
+     186       359918 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu.sv.html
index c36c0fb1d45..e8e298287f2 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        81.0%
+    
+        80.0%
     
     
-        81
+        80
     
     
         100
@@ -124,48 +124,48 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       584906 :    input logic          clk,                                           // Top level clock
+      23       359918 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
-      27        36372 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
-      28        36284 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
+      27        22352 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
+      28        22292 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
       29            0 :    input logic  [31:0]  dbg_cmd_wrdata,                                // Debug data   to primary I0 RS1
       30            0 :    input el2_alu_pkt_t i0_ap,                                         // DEC alu {valid,predecodes}
       31              : 
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
-      34         1864 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35        12010 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
-      36          792 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
+      34         1120 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
+      35         7134 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      36          500 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
       39            0 :    input logic  [31:0]  lsu_result_m,                                  // Load result M-stage
-      40           12 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
-      41        30300 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
-      42        16396 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
+      40            8 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
+      41        18512 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
+      42         9920 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
       43            4 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
-      44            4 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45         1876 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      44           16 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
+      45         1192 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
       46            4 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
-      47         1192 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
-      48        26004 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49        11376 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
-      50          844 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
+      47          840 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
+      48        15936 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
+      49         7028 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      50          576 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51           10 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
-      52         1380 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      53           28 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      54          124 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55            4 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      52          808 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      53            4 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      54           72 :    input logic          dec_csr_ren_d,                                 // CSR read select
+      55            0 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57        26638 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57        16414 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
-      59           28 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
+      59           20 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
       61              : 
-      62          650 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
+      62          470 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
       63              : 
-      64           64 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
+      64           36 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
       65            0 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
       66              : 
       67              : 
@@ -173,90 +173,90 @@
       69            0 :    input logic [31:2]  dec_tlu_meihap,                                 // External stall mux data
       70              : 
       71              : 
-      72         1284 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
-      73           12 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
+      72          300 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
+      73            8 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
       74              : 
-      75         1524 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
-      76           24 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
+      75         1084 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
+      76           16 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
       77              : 
-      78         1012 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
+      78          616 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
       79            2 :    output logic [31:1]  exu_i0_pc_x,                                   // Primary PC  result to DEC
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            2 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83         5260 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83         3160 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
-      86          172 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87         7996 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
-      88         1280 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
-      89        10172 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90         2454 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
-      91         2256 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
+      86          108 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
+      87         4780 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      88          940 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
+      89         6176 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
+      90         1454 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      91         1384 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
       93           12 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
-      94          932 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95         2454 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      96          472 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      94          676 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
+      95         1454 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      96          316 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
-     100         1280 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101         5720 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102         7718 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     100          940 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
+     101         3488 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102         4698 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105            0 :    output logic [31:0]  exu_div_result,                                // Divide result
-     106           56 :    output logic         exu_div_wren                                   // Divide write enable to GPR
+     106           40 :    output logic         exu_div_wren                                   // Divide write enable to GPR
      107              :   );
      108              : 
      109              : 
      110              : 
      111              : 
-     112          392 :    logic [31:0]                i0_rs1_bypass_data_d;
-     113           36 :    logic [31:0]                i0_rs2_bypass_data_d;
-     114         4228 :    logic                       i0_rs1_bypass_en_d;
-     115          188 :    logic                       i0_rs2_bypass_en_d;
+     112          176 :    logic [31:0]                i0_rs1_bypass_data_d;
+     113           68 :    logic [31:0]                i0_rs2_bypass_data_d;
+     114         2512 :    logic                       i0_rs1_bypass_en_d;
+     115           92 :    logic                       i0_rs2_bypass_en_d;
      116            4 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
      117            4 :    logic [31:0]                muldiv_rs1_d;
-     118          650 :    logic [31:1]                pred_correct_npc_r;
-     119         7964 :    logic                       i0_pred_correct_upper_r;
+     118          470 :    logic [31:1]                pred_correct_npc_r;
+     119         4724 :    logic                       i0_pred_correct_upper_r;
      120            2 :    logic [31:1]                i0_flush_path_upper_r;
-     121          124 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
-     122        36284 :    logic                       x_ctl_en,  r_ctl_en;
+     121           72 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
+     122        22292 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124         2454 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125         2454 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126         5720 :    logic                       i0_taken_d;
-     127         5720 :    logic                       i0_taken_x;
-     128         7996 :    logic                       i0_valid_d;
-     129         7996 :    logic                       i0_valid_x;
-     130         2454 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124         1454 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125         1454 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126         3488 :    logic                       i0_taken_d;
+     127         3488 :    logic                       i0_taken_x;
+     128         4780 :    logic                       i0_valid_d;
+     129         4780 :    logic                       i0_valid_x;
+     130         1454 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
      132           12 :    el2_predict_pkt_t          final_predict_mp;
-     133         1864 :    el2_predict_pkt_t          i0_predict_newp_d;
+     133         1120 :    el2_predict_pkt_t          i0_predict_newp_d;
      134              : 
      135            0 :    logic                       flush_in_d;
-     136         1012 :    logic [31:0]                alu_result_x;
+     136          616 :    logic [31:0]                alu_result_x;
      137              : 
      138            0 :    logic                       mul_valid_x;
      139            0 :    logic [31:0]                mul_result_x;
      140              : 
-     141         1392 :    el2_predict_pkt_t          i0_pp_r;
+     141          772 :    el2_predict_pkt_t          i0_pp_r;
      142              : 
-     143         1460 :    logic                       i0_flush_upper_d;
-     144           96 :    logic [31:1]                i0_flush_path_d;
-     145         1864 :    el2_predict_pkt_t          i0_predict_p_d;
-     146         7964 :    logic                       i0_pred_correct_upper_d;
+     143         1048 :    logic                       i0_flush_upper_d;
+     144           64 :    logic [31:1]                i0_flush_path_d;
+     145         1120 :    el2_predict_pkt_t          i0_predict_p_d;
+     146         4724 :    logic                       i0_pred_correct_upper_d;
      147              : 
-     148         1460 :    logic                       i0_flush_upper_x;
+     148         1048 :    logic                       i0_flush_upper_x;
      149            2 :    logic [31:1]                i0_flush_path_x;
-     150         1392 :    el2_predict_pkt_t          i0_predict_p_x;
-     151         7964 :    logic                       i0_pred_correct_upper_x;
-     152        11376 :    logic                       i0_branch_x;
+     150          772 :    el2_predict_pkt_t          i0_predict_p_x;
+     151         4724 :    logic                       i0_pred_correct_upper_x;
+     152         7028 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
-     155          484 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
+     155          316 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
      156              : 
      157              : 
      158              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_alu_ctl.sv.html
index 9edc604de0b..270ffac4367 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_alu_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        52.3%
+    
+        51.1%
     
     
-        46
+        45
     
     
         88
@@ -124,52 +124,52 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       584906 :    input  logic                  clk,                // Top level clock
+      23       359918 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
-      27         1460 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
-      28           64 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
-      29        36372 :    input  logic                  enable,             // Clock enable
-      30        26004 :    input  logic                  valid_in,           // Valid
+      27         1048 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
+      28           36 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
+      29        22352 :    input  logic                  enable,             // Clock enable
+      30        15936 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
-      32          124 :    input  logic                  csr_ren_in,         // CSR select
-      33            4 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34            4 :    input  logic signed [31:0]    a_in,               // A operand
-      35         1944 :    input  logic        [31:0]    b_in,               // B operand
+      32           72 :    input  logic                  csr_ren_in,         // CSR select
+      33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34            4 :    input  logic signed [31:0]    a_in,               // A operand
+      35         1252 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
-      37         1864 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
-      38         1192 :    input  logic        [12:1]    brimm_in,           // Branch offset
+      37         1120 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
+      38          840 :    input  logic        [12:1]    brimm_in,           // Branch offset
       39              : 
       40              : 
-      41         1012 :    output logic        [31:0]    result_ff,          // final result
-      42         1460 :    output logic                  flush_upper_out,    // Branch flush
-      43         1524 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
-      44           96 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
+      41          616 :    output logic        [31:0]    result_ff,          // final result
+      42         1048 :    output logic                  flush_upper_out,    // Branch flush
+      43         1084 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
+      44           64 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            2 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46         7964 :    output logic                  pred_correct_out,   // NPC control
-      47         1864 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
+      46         4724 :    output logic                  pred_correct_out,   // NPC control
+      47         1120 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
       50              : 
       51            4 :    logic               [31:0]    zba_a_in;
-      52         1016 :    logic               [31:0]    aout;
-      53          628 :    logic                         cout,ov,neg;
-      54            4 :    logic               [31:0]    lout;
+      52          620 :    logic               [31:0]    aout;
+      53          368 :    logic                         cout,ov,neg;
+      54           12 :    logic               [31:0]    lout;
       55            4 :    logic               [31:0]    sout;
-      56         1216 :    logic                         sel_shift;
-      57        23220 :    logic                         sel_adder;
+      56          708 :    logic                         sel_shift;
+      57        14300 :    logic                         sel_adder;
       58            0 :    logic                         slt_one;
-      59         5792 :    logic                         actual_taken;
+      59         3540 :    logic                         actual_taken;
       60           10 :    logic               [31:1]    pcout;
-      61         2116 :    logic                         cond_mispredict;
-      62          128 :    logic                         target_mispredict;
-      63        21904 :    logic                         eq, ne, lt, ge;
-      64         1036 :    logic                         any_jal;
-      65        10302 :    logic               [1:0]     newhist;
-      66         1036 :    logic                         sel_pc;
+      61         1520 :    logic                         cond_mispredict;
+      62           80 :    logic                         target_mispredict;
+      63        13560 :    logic                         eq, ne, lt, ge;
+      64          632 :    logic                         any_jal;
+      65         6016 :    logic               [1:0]     newhist;
+      66          632 :    logic                         sel_pc;
       67            4 :    logic               [31:0]    csr_write_data;
-      68         1016 :    logic               [31:0]    result;
+      68          620 :    logic               [31:0]    result;
       69              : 
       70              : 
       71              : 
@@ -348,7 +348,7 @@
      244              :                                 ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |
      245              :                                 ( {32{~ap_zba   }} &  a_in[31:0]       );
      246              : 
-     247        10952 :    logic        [31:0]    bm;
+     247         6752 :    logic        [31:0]    bm;
      248              : 
      249              :    assign bm[31:0]            = ( ap.sub )  ?  ~b_in[31:0]  :  b_in[31:0];
      250              : 
@@ -383,8 +383,8 @@
      279              : 
      280            0 :    logic        [5:0]     shift_amount;
      281            2 :    logic        [31:0]    shift_mask;
-     282         2952 :    logic        [62:0]    shift_extend;
-     283         2936 :    logic        [62:0]    shift_long;
+     282          856 :    logic        [62:0]    shift_extend;
+     283          852 :    logic        [62:0]    shift_long;
      284              : 
      285              : 
      286              :    assign shift_amount[5:0]            = ( { 6{ap.sll}}   & (6'd32 - {1'b0,b_in[4:0]}) ) |   // [5] unused
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342      4396384 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343      4396384 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342      3348032 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343      3348032 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
@@ -499,7 +499,7 @@
      395              : 
      396              :    assign bitmanip_minmax_sel          =  ap_min | ap_max;
      397              : 
-     398        21906 :    logic                  bitmanip_minmax_sel_a;
+     398        13562 :    logic                  bitmanip_minmax_sel_a;
      399              : 
      400              :    assign bitmanip_minmax_sel_a        =  ge  ^ ap_min;
      401              : 
@@ -557,7 +557,7 @@
      453              : 
      454              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  ZBSET, ZBCLR, ZBINV  * * * * * * * * * * * * * *
      455              : 
-     456           72 :    logic        [31:0]    bitmanip_sb_1hot;
+     456           44 :    logic        [31:0]    bitmanip_sb_1hot;
      457            0 :    logic        [31:0]    bitmanip_sb_data;
      458              : 
      459              :    assign bitmanip_sb_1hot[31:0]       = ( 32'h00000001 << b_in[4:0] );
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_div_ctl.sv.html
index 836689d2779..43305f809ed 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,18 +124,18 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       584906 :    input logic           clk,                       // Top level clock
+      23       359918 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
-      27           28 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
+      27           20 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
       28            4 :    input logic  [31:0]   dividend,                  // Numerator
-      29         1944 :    input logic  [31:0]   divisor,                   // Denominator
+      29         1252 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
       33              : 
-      34           56 :    output logic          finish_dly,                // Finish to match data
+      34           40 :    output logic          finish_dly,                // Finish to match data
       35            0 :    output logic [31:0]   out                        // Result
       36              :   );
       37              : 
@@ -1414,80 +1414,80 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313       584906 :    input  logic            clk,                       // Top level clock
+    1313       359918 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
     1317            0 :    input  logic            cancel,                    // Flush pipeline
-    1318           56 :    input  logic            valid_in,
-    1319         4898 :    input  logic            signed_in,
-    1320           28 :    input  logic            rem_in,
+    1318           40 :    input  logic            valid_in,
+    1319         3042 :    input  logic            signed_in,
+    1320           20 :    input  logic            rem_in,
     1321            4 :    input  logic [31:0]     dividend_in,
-    1322         1944 :    input  logic [31:0]     divisor_in,
+    1322         1252 :    input  logic [31:0]     divisor_in,
     1323              : 
-    1324           56 :    output logic            valid_out,
+    1324           40 :    output logic            valid_out,
     1325            0 :    output logic [31:0]     data_out
     1326              :   );
     1327              : 
     1328              : 
-    1329           56 :    logic                   valid_ff_in, valid_ff;
-    1330           56 :    logic                   finish_raw, finish, finish_ff;
-    1331           52 :    logic                   running_state;
-    1332           56 :    logic                   misc_enable;
+    1329           40 :    logic                   valid_ff_in, valid_ff;
+    1330           40 :    logic                   finish_raw, finish, finish_ff;
+    1331           36 :    logic                   running_state;
+    1332           40 :    logic                   misc_enable;
     1333            0 :    logic         [2:0]     control_in, control_ff;
-    1334           28 :    logic                   dividend_sign_ff, divisor_sign_ff, rem_ff;
-    1335           28 :    logic                   count_enable;
+    1334           20 :    logic                   dividend_sign_ff, divisor_sign_ff, rem_ff;
+    1335           20 :    logic                   count_enable;
     1336            0 :    logic         [6:0]     count_in, count_ff;
     1337              : 
-    1338           28 :    logic                   smallnum_case;
+    1338           20 :    logic                   smallnum_case;
     1339            0 :    logic         [3:0]     smallnum;
     1340              : 
-    1341           28 :    logic                   a_enable, a_shift;
+    1341           20 :    logic                   a_enable, a_shift;
     1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
-    1344           56 :    logic                   b_enable, b_twos_comp;
-    1345         2000 :    logic        [32:0]     b_in;
+    1344           40 :    logic                   b_enable, b_twos_comp;
+    1345         1292 :    logic        [32:0]     b_in;
     1346            2 :    logic        [37:0]     b_ff;
     1347              : 
     1348            0 :    logic        [31:0]     q_in, q_ff;
     1349              : 
-    1350           56 :    logic                   rq_enable;
+    1350           40 :    logic                   rq_enable;
     1351            0 :    logic                   r_sign_sel;
-    1352           28 :    logic                   r_restore_sel;
+    1352           20 :    logic                   r_restore_sel;
     1353            0 :    logic                   r_adder01_sel, r_adder02_sel, r_adder03_sel;
     1354            0 :    logic                   r_adder04_sel, r_adder05_sel, r_adder06_sel, r_adder07_sel;
     1355            0 :    logic                   r_adder08_sel, r_adder09_sel, r_adder10_sel, r_adder11_sel;
     1356            4 :    logic                   r_adder12_sel, r_adder13_sel, r_adder14_sel, r_adder15_sel;
     1357            0 :    logic        [32:0]     r_in, r_ff;
     1358              : 
-    1359           56 :    logic                   twos_comp_q_sel, twos_comp_b_sel;
-    1360           56 :    logic        [31:0]     twos_comp_in, twos_comp_out;
+    1359           40 :    logic                   twos_comp_q_sel, twos_comp_b_sel;
+    1360           40 :    logic        [31:0]     twos_comp_in, twos_comp_out;
     1361              : 
-    1362           56 :    logic        [15:1]     quotient_raw;
-    1363           64 :    logic         [3:0]     quotient_new;
-    1364           24 :    logic        [34:0]     adder01_out;
-    1365           22 :    logic        [35:0]     adder02_out;
-    1366           24 :    logic        [36:0]     adder03_out;
+    1362           40 :    logic        [15:1]     quotient_raw;
+    1363           40 :    logic         [3:0]     quotient_new;
+    1364           14 :    logic        [34:0]     adder01_out;
+    1365           10 :    logic        [35:0]     adder02_out;
+    1366           14 :    logic        [36:0]     adder03_out;
     1367            2 :    logic        [37:0]     adder04_out;
-    1368           24 :    logic        [37:0]     adder05_out;
-    1369           22 :    logic        [37:0]     adder06_out;
-    1370           24 :    logic        [37:0]     adder07_out;
-    1371           14 :    logic        [37:0]     adder08_out;
-    1372           24 :    logic        [37:0]     adder09_out;
-    1373           22 :    logic        [37:0]     adder10_out;
-    1374           24 :    logic        [37:0]     adder11_out;
+    1368           14 :    logic        [37:0]     adder05_out;
+    1369           10 :    logic        [37:0]     adder06_out;
+    1370           14 :    logic        [37:0]     adder07_out;
+    1371           10 :    logic        [37:0]     adder08_out;
+    1372           14 :    logic        [37:0]     adder09_out;
+    1373           10 :    logic        [37:0]     adder10_out;
+    1374           14 :    logic        [37:0]     adder11_out;
     1375            2 :    logic        [37:0]     adder12_out;
-    1376           24 :    logic        [37:0]     adder13_out;
-    1377           22 :    logic        [37:0]     adder14_out;
-    1378           24 :    logic        [37:0]     adder15_out;
+    1376           14 :    logic        [37:0]     adder13_out;
+    1377           10 :    logic        [37:0]     adder14_out;
+    1378           14 :    logic        [37:0]     adder15_out;
     1379              : 
     1380            0 :    logic        [64:0]     ar_shifted;
     1381            0 :    logic         [5:0]     shortq;
-    1382           48 :    logic         [4:0]     shortq_shift;
-    1383           30 :    logic         [4:0]     shortq_decode;
-    1384           48 :    logic         [4:0]     shortq_shift_ff;
-    1385           48 :    logic                   shortq_enable;
-    1386           48 :    logic                   shortq_enable_ff;
+    1382           32 :    logic         [4:0]     shortq_shift;
+    1383           22 :    logic         [4:0]     shortq_decode;
+    1384           32 :    logic         [4:0]     shortq_shift_ff;
+    1385           32 :    logic                   shortq_enable;
+    1386           32 :    logic                   shortq_enable_ff;
     1387            0 :    logic        [32:0]     shortq_dividend;
     1388              : 
     1389            0 :    logic                   by_zero_case;
@@ -1746,7 +1746,7 @@
     1642              : 
     1643            0 :    logic [5:0]  dw_a_enc;
     1644            0 :    logic [5:0]  dw_b_enc;
-    1645           26 :    logic [6:0]  dw_shortq_raw;
+    1645            6 :    logic [6:0]  dw_shortq_raw;
     1646              : 
     1647              : 
     1648              : 
@@ -1821,14 +1821,14 @@
     1717              : 
     1718              : module el2_exu_div_cls
     1719              :   (
-    1720           24 :    input  logic [32:0] operand,
+    1720           16 :    input  logic [32:0] operand,
     1721              : 
-    1722           50 :    output logic [4:0]  cls                  // Count leading sign bits - "n" format ignoring [32]
+    1722           34 :    output logic [4:0]  cls                  // Count leading sign bits - "n" format ignoring [32]
     1723              :    );
     1724              : 
     1725              : 
-    1726           16 :    logic [4:0]   cls_zeros;
-    1727           54 :    logic [4:0]   cls_ones;
+    1726           14 :    logic [4:0]   cls_zeros;
+    1727           38 :    logic [4:0]   cls_ones;
     1728              : 
     1729              : 
     1730              : assign cls_zeros[4:0]             = ({5{operand[31]    ==  {           1'b1} }} & 5'd00) |
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_mul_ctl.sv.html
index 104e4e28a2c..370f6ed9a50 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23       584906 :    input logic          clk,              // Top level clock
+      23       359918 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209      4396384 :              if (bcompress_test_bit_d)
+     209      3348032 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236      4396384 :              if (bdecompress_test_bit_d)
+     236      3348032 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu.sv.html
index 46c0487419c..7a9c9ede227 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,18 +129,18 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28       584906 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29       584906 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30       584906 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28       359918 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29       359918 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30       359918 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
-      33        36372 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
+      33        22352 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
       34              : 
-      35         1524 :    input logic exu_flush_final, // flush, includes upper and lower
-      36        36368 :    input logic dec_tlu_i0_commit_cmt , // committed i0
+      35         1084 :    input logic exu_flush_final, // flush, includes upper and lower
+      36        22348 :    input logic dec_tlu_i0_commit_cmt , // committed i0
       37            0 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
       38            0 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
-      39           24 :    input logic [31:1] exu_flush_path_final, // flush fetch address
+      39           16 :    input logic [31:1] exu_flush_path_final, // flush fetch address
       40              : 
       41            0 :    input logic [31:0]  dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
       42            0 :    input logic         dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
@@ -172,10 +172,10 @@
       68            0 :    output logic                            ifu_axi_bready,
       69              : 
       70              :    // AXI Read Channels
-      71        36322 :    output logic                            ifu_axi_arvalid,
-      72        36322 :    input  logic                            ifu_axi_arready,
-      73        27564 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      74         9128 :    output logic [31:0]                     ifu_axi_araddr,
+      71        22382 :    output logic                            ifu_axi_arvalid,
+      72        22382 :    input  logic                            ifu_axi_arready,
+      73        16956 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      74         5732 :    output logic [31:0]                     ifu_axi_araddr,
       75            2 :    output logic [3:0]                      ifu_axi_arregion,
       76            0 :    output logic [7:0]                      ifu_axi_arlen,
       77            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -185,10 +185,10 @@
       81            2 :    output logic [2:0]                      ifu_axi_arprot,
       82            0 :    output logic [3:0]                      ifu_axi_arqos,
       83              : 
-      84        72640 :    input  logic                            ifu_axi_rvalid,
+      84        44760 :    input  logic                            ifu_axi_rvalid,
       85            2 :    output logic                            ifu_axi_rready,
-      86        10872 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-      87         3994 :    input  logic [63:0]                     ifu_axi_rdata,
+      86         6856 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+      87         2522 :    input  logic [63:0]                     ifu_axi_rdata,
       88            0 :    input  logic [1:0]                      ifu_axi_rresp,
       89              : 
       90            2 :    input  logic                      ifu_bus_clk_en,
@@ -206,10 +206,10 @@
      102            0 :    output logic                      iccm_dma_rvalid,
      103            0 :    output logic [63:0]               iccm_dma_rdata,
      104            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     105         1550 :    output logic                      iccm_ready,
+     105         1106 :    output logic                      iccm_ready,
      106              : 
-     107        36372 :    output logic       ifu_pmu_instr_aligned,
-     108         1382 :    output logic       ifu_pmu_fetch_stall,
+     107        22352 :    output logic       ifu_pmu_instr_aligned,
+     108          942 :    output logic       ifu_pmu_fetch_stall,
      109            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
      110              : 
      111              : //   I$ & ITAG Ports
@@ -217,8 +217,8 @@
      113            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      114            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      115              : 
-     116         2012 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     117         7276 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     116         1172 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     117         4604 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      118            0 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      119            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
      120            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
@@ -227,8 +227,8 @@
      123              : 
      124            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
      125            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     126         7276 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     127        30354 :    output logic                      ic_sel_premux_data, // Select the premux data.
+     126         4604 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     127        18614 :    output logic                      ic_sel_premux_data, // Select the premux data.
      128              : 
      129            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      130            0 :    output logic                      ic_debug_rd_en,     // Icache debug rd
@@ -244,14 +244,14 @@
      140              : 
      141              : 
      142              :    // ICCM ports
-     143          212 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
+     143          136 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
      144            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
-     145          256 :    output logic                      iccm_rden,          // ICCM read enable.
+     145          172 :    output logic                      iccm_rden,          // ICCM read enable.
      146            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
      147            0 :    output logic [2:0]                iccm_wr_size,       // ICCM write location within DW.
      148              : 
-     149           12 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
-     150           12 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
+     149            8 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
+     150            8 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
      151              : 
      152              :    // ICCM ECC status
      153            0 :    output logic                      ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.
@@ -259,46 +259,46 @@
      155            0 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
      156              : 
      157              : // Perf counter sigs
-     158        36324 :    output logic       ifu_pmu_ic_miss, // ic miss
+     158        22384 :    output logic       ifu_pmu_ic_miss, // ic miss
      159            0 :    output logic       ifu_pmu_ic_hit, // ic hit
      160            0 :    output logic       ifu_pmu_bus_error, // iside bus error
      161            0 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
-     162        36322 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
+     162        22382 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
      163              : 
      164              : 
      165            0 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
      166            0 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
      167              : 
-     168        34772 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
+     168        21400 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
      169            0 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
      170            0 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
-     172          656 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
+     172          392 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173           10 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174        19040 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174        11620 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
-     176        36324 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
+     176        22384 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
-     178          188 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
-     179          792 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180        12010 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     178          116 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
+     179          500 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
+     180         7134 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
      184           12 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
-     185          932 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186         2454 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-     187          472 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+     185          676 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
+     186         1454 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     187          316 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
-     190         2256 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191         2454 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-     192          172 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+     190         1384 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
+     191         1454 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     192          108 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
-     195           64 :    input dec_tlu_flush_lower_wb,
+     195           36 :    input dec_tlu_flush_lower_wb,
      196              : 
-     197         5236 :    output logic [15:0] ifu_i0_cinst,
+     197         3260 :    output logic [15:0] ifu_i0_cinst,
      198              : 
      199            2 :     output logic [31:1] ifu_pmp_addr,
      200            0 :     input  logic        ifu_pmp_error,
@@ -315,12 +315,12 @@
      211              :    localparam TAGWIDTH = 2 ;
      212              :    localparam IDWIDTH  = 2 ;
      213              : 
-     214          812 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
+     214          472 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
      215            2 :    logic [31:1]            ifc_fetch_addr_f;
      216            2 :    logic [31:1]            ifc_fetch_addr_bf;
      217              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
      218              : 
-     219        33180 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
+     219        20432 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
      220            2 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
      221              : 
      222            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
@@ -329,33 +329,33 @@
      225              :    assign ifu_ic_error_start = ic_error_start;
      226              : 
      227              : 
-     228        13992 :    logic        ic_write_stall;
+     228         8604 :    logic        ic_write_stall;
      229            0 :    logic        ic_dma_active;
-     230         1654 :    logic        ifc_dma_access_ok;
+     230         1170 :    logic        ifc_dma_access_ok;
      231            0 :    logic [1:0]  ic_access_fault_f;
      232            0 :    logic [1:0]  ic_access_fault_type_f;
-     233        36332 :    logic        ifu_ic_mb_empty;
+     233        22392 :    logic        ifu_ic_mb_empty;
      234              : 
-     235        36488 :    logic ic_hit_f;
+     235        22464 :    logic ic_hit_f;
      236              : 
-     237         5076 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238         5956 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
-     239         1692 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240         1666 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
-     241         6592 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
-     242         5520 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243         3260 :    logic [11:0] ifu_bp_poffset_f; // predicted target
-     244          108 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
-     245         2404 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
-     246         3132 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247         2454 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     237         3188 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
+     238         3448 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     239         1004 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
+     240          962 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     241         3688 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
+     242         2956 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
+     243         1936 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     244           68 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
+     245         1524 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
+     246         1892 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
+     247         1454 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
-     251        33180 :    logic [1:0]   ic_fetch_val_f;
-     252         7276 :    logic [31:0] ic_data_f;
-     253         7276 :    logic [31:0] ifu_fetch_data_f;
-     254        16654 :    logic ifc_fetch_req_f;
+     251        20432 :    logic [1:0]   ic_fetch_val_f;
+     252         4604 :    logic [31:0] ic_data_f;
+     253         4604 :    logic [31:0] ifu_fetch_data_f;
+     254        10042 :    logic ifc_fetch_req_f;
      255            0 :    logic ifc_fetch_req_f_raw;
      256            0 :    logic iccm_dma_rd_ecc_double_err;
      257            0 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
@@ -369,9 +369,9 @@
      265              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
      266              : 
      267            2 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
-     268        16654 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
+     268        10042 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
      269            2 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
-     270           24 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
+     270           16 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
      271            0 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
      272              : 
      273              :    // fetch control
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_aln_ctl.sv.html
index 1d108171e61..d417c3a9801 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30       584906 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31       584906 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30       359918 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31       359918 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -141,118 +141,118 @@
       37            0 :    input logic [1:0]                              ic_access_fault_f,        // Instruction access fault for the current fetch.
       38            0 :    input logic [1:0]                              ic_access_fault_type_f,   // Instruction access fault types
       39              : 
-      40         1524 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
+      40         1084 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
       41              : 
-      42        36372 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
+      42        22352 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
       43              : 
-      44         7276 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
+      44         4604 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
       45              : 
-      46        33180 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
+      46        20432 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
       47            2 :    input logic [31:1]                             ifu_fetch_pc,             // starting pc of fetch
       48              : 
       49              : 
       50              : 
-      51        34772 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
+      51        21400 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
       52            0 :    output logic                                   ifu_i0_icaf,              // Instruction 0 has access fault
       53            0 :    output logic [1:0]                             ifu_i0_icaf_type,         // Instruction 0 access fault type
       54            0 :    output logic                                   ifu_i0_icaf_second,       // Instruction 0 has access fault on second 2B of 4B inst
       55              : 
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
-      57          656 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
+      57          392 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58           10 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59        19040 :    output logic                                   ifu_i0_pc4,
+      59        11620 :    output logic                                   ifu_i0_pc4,
       60              : 
-      61        31132 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62          812 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      61        19060 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
+      62          472 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65         2454 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
-      66         1692 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67         3260 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      65         1454 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      66         1004 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
+      67         1936 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
-      70         5520 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
-      71         6592 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
-      72         2404 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
-      73         5076 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
-      74         3132 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
-      75          108 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
+      70         2956 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
+      71         3688 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
+      72         1524 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
+      73         3188 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
+      74         1892 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
+      75           68 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
       76              : 
       77              : 
-      78          188 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
-      79          792 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80        12010 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      78          116 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
+      79          500 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
+      80         7134 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
       84              : 
-      85        36372 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
+      85        22352 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
       86              : 
-      87         5236 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
+      87         3260 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
       88              :    );
       89              : 
       90              : 
       91              : 
-      92        36488 :    logic                                          ifvalid;
-      93          228 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
-      94          240 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
+      92        22464 :    logic                                          ifvalid;
+      93          152 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
+      94          160 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
       95              : 
-      96          240 :    logic [1:0]                                    f2val_in, f2val;
-      97        10252 :    logic [1:0]                                    f1val_in, f1val;
-      98        23676 :    logic [1:0]                                    f0val_in, f0val;
-      99          272 :    logic [1:0]                                    sf1val, sf0val;
+      96          160 :    logic [1:0]                                    f2val_in, f2val;
+      97         6616 :    logic [1:0]                                    f1val_in, f1val;
+      98        14268 :    logic [1:0]                                    f0val_in, f0val;
+      99          180 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
-     101         5236 :    logic [31:0]                                   aligndata;
-     102        19040 :    logic                                          first4B, first2B;
+     101         3260 :    logic [31:0]                                   aligndata;
+     102        11620 :    logic                                          first4B, first2B;
      103              : 
-     104          604 :    logic [31:0]                                   uncompress0;
-     105        36372 :    logic                                          i0_shift;
-     106        12840 :    logic                                          shift_2B, shift_4B;
-     107         9944 :    logic                                          f1_shift_2B;
-     108          240 :    logic                                          f2_valid, sf1_valid, sf0_valid;
+     104          392 :    logic [31:0]                                   uncompress0;
+     105        22352 :    logic                                          i0_shift;
+     106         7716 :    logic                                          shift_2B, shift_4B;
+     107         6416 :    logic                                          f1_shift_2B;
+     108          160 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
-     110         5236 :    logic [31:0]                                   ifirst;
-     111        25048 :    logic [1:0]                                    alignval;
-     112           52 :    logic [31:1]                                   firstpc, secondpc;
+     110         3260 :    logic [31:0]                                   ifirst;
+     111        15172 :    logic [1:0]                                    alignval;
+     112           36 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114         2616 :    logic [11:0]                                   f1poffset;
-     115         2562 :    logic [11:0]                                   f0poffset;
-     116         3758 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117         9698 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
-     118         6506 :    logic [1:0]                                    f1hist1;
-     119         9376 :    logic [1:0]                                    f0hist1;
-     120         6342 :    logic [1:0]                                    f1hist0;
-     121         8108 :    logic [1:0]                                    f0hist0;
+     114         1520 :    logic [11:0]                                   f1poffset;
+     115         1626 :    logic [11:0]                                   f0poffset;
+     116         2190 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117         5790 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     118         3830 :    logic [1:0]                                    f1hist1;
+     119         5180 :    logic [1:0]                                    f0hist1;
+     120         3598 :    logic [1:0]                                    f1hist0;
+     121         4328 :    logic [1:0]                                    f0hist0;
      122              : 
      123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
      124              : 
      125            0 :    logic [1:0]                                    f1ictype;
      126            0 :    logic [1:0]                                    f0ictype;
      127              : 
-     128         1640 :    logic [1:0]                                    f1pc4;
-     129         5744 :    logic [1:0]                                    f0pc4;
+     128         1016 :    logic [1:0]                                    f1pc4;
+     129         3324 :    logic [1:0]                                    f0pc4;
      130              : 
      131            0 :    logic [1:0]                                    f1ret;
-     132           72 :    logic [1:0]                                    f0ret;
-     133         2712 :    logic [1:0]                                    f1way;
-     134         2616 :    logic [1:0]                                    f0way;
+     132           40 :    logic [1:0]                                    f0ret;
+     133         1732 :    logic [1:0]                                    f1way;
+     134         1656 :    logic [1:0]                                    f0way;
      135              : 
-     136         3548 :    logic [1:0]                                    f1brend;
-     137         2932 :    logic [1:0]                                    f0brend;
+     136         2248 :    logic [1:0]                                    f1brend;
+     137         1812 :    logic [1:0]                                    f0brend;
      138              : 
-     139         2488 :    logic [1:0]                                    alignbrend;
-     140         5508 :    logic [1:0]                                    alignpc4;
+     139         1544 :    logic [1:0]                                    alignbrend;
+     140         3236 :    logic [1:0]                                    alignpc4;
      141              : 
-     142          132 :    logic [1:0]                                    alignret;
-     143         4116 :    logic [1:0]                                    alignway;
-     144         9572 :    logic [1:0]                                    alignhist1;
-     145         6972 :    logic [1:0]                                    alignhist0;
-     146        10668 :    logic [1:1]                                    alignfromf1;
-     147         3848 :    logic                                          i0_ends_f1;
+     142           80 :    logic [1:0]                                    alignret;
+     143         2708 :    logic [1:0]                                    alignway;
+     144         5412 :    logic [1:0]                                    alignhist1;
+     145         3656 :    logic [1:0]                                    alignhist0;
+     146         6488 :    logic [1:1]                                    alignfromf1;
+     147         2492 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
-     150         1664 :    logic [31:1]                                   f1prett;
-     151         1360 :    logic [31:1]                                   f0prett;
+     150         1000 :    logic [31:1]                                   f1prett;
+     151          740 :    logic [31:1]                                   f0prett;
      152            0 :    logic [1:0]                                    f1dbecc;
      153            0 :    logic [1:0]                                    f0dbecc;
      154            0 :    logic [1:0]                                    f1icaf;
@@ -260,47 +260,47 @@
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159         5508 :    logic                                          i0_brp_pc4;
+     159         3236 :    logic                                          i0_brp_pc4;
      160              : 
-     161          588 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
+     161          376 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165        12296 :    logic [1:0]                                    wrptr, wrptr_in;
-     166        11436 :    logic [1:0]                                    rdptr, rdptr_in;
-     167        11704 :    logic [2:0]                                    qwen;
-     168          986 :    logic [31:0]                                   q2,q1,q0;
-     169         6864 :    logic                                          q2off_in, q2off;
-     170         6662 :    logic                                          q1off_in, q1off;
-     171         7340 :    logic                                          q0off_in, q0off;
-     172        21040 :    logic                                          f0_shift_2B;
+     165         7548 :    logic [1:0]                                    wrptr, wrptr_in;
+     166         7016 :    logic [1:0]                                    rdptr, rdptr_in;
+     167         7188 :    logic [2:0]                                    qwen;
+     168          600 :    logic [31:0]                                   q2,q1,q0;
+     169         4308 :    logic                                          q2off_in, q2off;
+     170         4122 :    logic                                          q1off_in, q1off;
+     171         4628 :    logic                                          q0off_in, q0off;
+     172        13080 :    logic                                          f0_shift_2B;
      173              : 
-     174         4498 :    logic [31:0]                                   q0eff;
-     175         5900 :    logic [31:0]                                   q0final;
-     176        16490 :    logic                                          q0ptr;
-     177        16490 :    logic [1:0]                                    q0sel;
+     174         2710 :    logic [31:0]                                   q0eff;
+     175         3740 :    logic [31:0]                                   q0final;
+     176        10030 :    logic                                          q0ptr;
+     177        10030 :    logic [1:0]                                    q0sel;
      178              : 
-     179         4384 :    logic [31:0]                                   q1eff;
-     180         5140 :    logic [15:0]                                   q1final;
-     181        12212 :    logic                                          q1ptr;
-     182        12212 :    logic [1:0]                                    q1sel;
+     179         2660 :    logic [31:0]                                   q1eff;
+     180         3308 :    logic [15:0]                                   q1final;
+     181         7744 :    logic                                          q1ptr;
+     182         7744 :    logic [1:0]                                    q1sel;
      183              : 
-     184        11436 :    logic [2:0]                                    qren;
+     184         7016 :    logic [2:0]                                    qren;
      185              : 
-     186          864 :    logic                                          consume_fb1, consume_fb0;
+     186          524 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
      190              :    localparam                                     BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
-     191           32 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
-     192          116 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
-     193           72 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
+     191            8 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
+     192           64 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
+     193           40 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
      194              : 
      195              :    localparam                                     MHI   = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
-     198          976 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199         6238 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     198          552 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
+     199         3674 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201            0 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_bp_ctl.sv.html
index 8f32144caec..9a67195e973 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_bp_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        80.9%
+    
+        84.5%
     
     
-        89
+        93
     
     
         110
@@ -135,47 +135,47 @@
       31              :  )
       32              :   (
       33              : 
-      34       584906 :    input logic clk,
+      34       359918 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
-      37        36488 :    input logic ic_hit_f,      // Icache hit, enables F address capture
+      37        22464 :    input logic ic_hit_f,      // Icache hit, enables F address capture
       38              : 
       39            2 :    input logic [31:1] ifc_fetch_addr_f, // look up btb address
-      40        16654 :    input logic ifc_fetch_req_f,  // F1 valid
+      40        10042 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
-      42         2256 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43         2454 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-      44          172 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+      42         1384 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
+      43         1454 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      44          108 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
       47              : 
-      48           64 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
+      48           36 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
       49            0 :    input logic dec_tlu_flush_leak_one_wb, // don't hit for leak one fetches
       50              : 
       51            0 :    input logic dec_tlu_bpred_disable, // disable all branch prediction
       52              : 
       53           12 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
-      55          932 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56         2454 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      57          472 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      55          676 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
+      56         1454 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      57          316 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
-      60         1524 :    input logic exu_flush_final, // all flushes
+      60         1084 :    input logic exu_flush_final, // all flushes
       61              : 
-      62         5956 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
-      63         1692 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64         1666 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      62         3448 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      63         1004 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      64          962 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66         2454 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66         1454 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
-      68         5076 :    output logic [1:0] ifu_bp_way_f, // way
-      69          108 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
-      70         6592 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
-      71         5520 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
-      72         2404 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
-      73         3132 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74         3260 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      68         3188 :    output logic [1:0] ifu_bp_way_f, // way
+      69           68 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
+      70         3688 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
+      71         2956 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
+      72         1524 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
+      73         1892 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
+      74         1936 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -205,56 +205,56 @@
      101              :    localparam BHT_NO_ADDR_MATCH  = ( pt.BHT_ARRAY_DEPTH <= 16 );
      102              : 
      103              : 
-     104          228 :    logic exu_mp_valid_write;
-     105         1196 :    logic exu_mp_ataken;
-     106         1280 :    logic exu_mp_valid; // conditional branch mispredict
-     107          788 :    logic exu_mp_boffset; // branch offsett
-     108          664 :    logic exu_mp_pc4; // branch is a 4B inst
-     109           84 :    logic exu_mp_call; // branch is a call inst
-     110          128 :    logic exu_mp_ret; // branch is a ret inst
-     111           24 :    logic exu_mp_ja; // branch is a jump always
-     112          124 :    logic [1:0] exu_mp_hist; // new history
-     113          536 :    logic [11:0] exu_mp_tgt; // target offset
-     114          472 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115         7208 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116         5260 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
-     117          172 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
+     104          172 :    logic exu_mp_valid_write;
+     105          884 :    logic exu_mp_ataken;
+     106          940 :    logic exu_mp_valid; // conditional branch mispredict
+     107          588 :    logic exu_mp_boffset; // branch offsett
+     108          504 :    logic exu_mp_pc4; // branch is a 4B inst
+     109           68 :    logic exu_mp_call; // branch is a call inst
+     110           80 :    logic exu_mp_ret; // branch is a ret inst
+     111           16 :    logic exu_mp_ja; // branch is a jump always
+     112           72 :    logic [1:0] exu_mp_hist; // new history
+     113          404 :    logic [11:0] exu_mp_tgt; // target offset
+     114          316 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
+     115         4176 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116         3160 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     117          108 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120         2454 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120         1454 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122            0 :    logic use_mp_way, use_mp_way_p1;
-     123           14 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
-     124          220 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
+     123            6 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
+     124          104 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127         3260 :    logic [11:0]       btb_rd_tgt_f;
-     128          812 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
-     129         3568 :    logic [1:1]        bp_total_branch_offset_f;
+     127         1936 :    logic [11:0]       btb_rd_tgt_f;
+     128          440 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
+     129         2104 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
      131            2 :    logic [31:1]       bp_btb_target_adder_f;
      132            2 :    logic [31:1]       bp_rs_call_target_f;
-     133          220 :    logic              rs_push, rs_pop, rs_hold;
-     134          212 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
+     133          104 :    logic              rs_push, rs_pop, rs_hold;
+     134          136 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
      135            0 :    logic [pt.BTB_BTAG_SIZE-1:0] btb_wr_tag, fetch_rd_tag_f, fetch_rd_tag_p1_f;
-     136          108 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
-     137            4 :    logic               btb_wr_en_way0, btb_wr_en_way1;
+     136           84 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
+     137           12 :    logic               btb_wr_en_way0, btb_wr_en_way1;
      138              : 
      139              : 
-     140         1280 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
-     141          172 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
+     140          940 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
+     141          108 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
      142            0 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144            0 :    logic  branch_error_bank_conflict_f;
-     145         2454 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145         1454 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146            0 :    logic [1:0] num_valids;
      147            2 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
      148            0 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
      149            4 :                         mp_wrindex_dec, mp_wrlru_b0;
-     150         7284 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
+     150         4504 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
      151           24 :    logic  tag_match_way0_f, tag_match_way1_f;
-     152         1664 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
-     153          336 :    logic [1:0] bht_valid_f, bht_force_taken_f;
+     152          960 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
+     153          192 :    logic [1:0] bht_valid_f, bht_force_taken_f;
      154              : 
      155            0 :    logic leak_one_f, leak_one_f_d1;
      156              : 
@@ -262,38 +262,38 @@
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161         1380 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
-     162            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
+     161          904 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     162           28 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
-     164         1232 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
-     165            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
+     164          832 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
+     165           28 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
      166              : 
-     167          584 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
+     167          316 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169         5956 :    logic                                         final_h;
-     170         1056 :    logic                                         btb_fg_crossing_f;
-     171          620 :    logic                                         middle_of_bank;
+     169         3448 :    logic                                         final_h;
+     170          664 :    logic                                         btb_fg_crossing_f;
+     171          428 :    logic                                         middle_of_bank;
      172              : 
      173              : 
-     174         5520 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
+     174         2956 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
      175            0 :    logic                                         branch_error_bank_conflict_p1_f;
-     176           24 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
+     176           12 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
      177              : 
-     178            0 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
-     179            2 :    logic [31:2] fetch_addr_p1_f;
+     178           24 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
+     179            2 :    logic [31:2] fetch_addr_p1_f;
      180              : 
      181              : 
      182           12 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
-     183           76 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
+     183           36 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185          720 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185          392 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
-     187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
+     187           24 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
-     190         5172 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191         5984 :     logic [1:0]                                  bht_bank1_rd_data_f;
-     192         6248 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
+     190         3008 :     logic [1:0]                                  bht_bank0_rd_data_f;
+     191         3104 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     192         3780 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
      195              :    assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict
@@ -348,7 +348,7 @@
      244              :    // set on leak one, hold until next flush without leak one
      245              :    assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
      246              : 
-     247         1524 : logic exu_flush_final_d1;
+     247         1084 : logic exu_flush_final_d1;
      248              : 
      249              :  if(!pt.BTB_FULLYA) begin : genblock1
      250              :    assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
@@ -461,8 +461,8 @@
      357              : 
      358              :  end // if (!pt.BTB_FULLYA)
      359              :    // Detect end of cache line and mask as needed
-     360         3294 :    logic eoc_near;
-     361         2000 :    logic eoc_mask;
+     360         2058 :    logic eoc_near;
+     361         1300 :    logic eoc_mask;
      362              :    assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];
      363              :    assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));
      364              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372          812 :    logic [16:1] btb_sel_data_f;
+     372          440 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -484,7 +484,7 @@
      380              :                                     ({16{btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]) );
      381              : 
      382              : 
-     383          108 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
+     383           68 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
      384              : 
      385              :    // a valid taken target needs to kill the next fetch as we compute the target address
      386              :    assign ifu_bp_hit_taken_f = |(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f & ~leak_one_f_d1 & ~dec_tlu_bpred_disable;
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460         2454 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460         1454 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500         3750 : logic [1:0] bloc_f;
-     501         4678 : logic use_fa_plus;
+     500         2246 : logic [1:0] bloc_f;
+     501         2814 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -719,8 +719,8 @@
      615              :                                                 exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
-     618          124 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619          444 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     618           72 :    logic [1:0] bht_wr_data0, bht_wr_data2;
+     619          316 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -732,9 +732,9 @@
      628              : 
      629              : 
      630              : 
-     631          632 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
+     631          464 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
      632              : 
-     633          632 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
+     633          464 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
      634              :    el2_btb_ghr_hash #(.pt(pt)) mpghrhs  (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      635              :    el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      636              :    el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676       108831 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676        82994 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678       108831 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679       108831 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678        82994 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679        82994 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684       108831 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684        82994 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686       108831 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687       108831 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686        82994 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687        82994 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -933,7 +933,7 @@
      829              : 
      830              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0]      bht_bank_wr_data ;
      831              :    logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0]                bht_bank_rd_data_out ;
-     832          104 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
+     832           72 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
      833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
      834              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0]           bht_bank_sel   ;
      835              : 
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877       108831 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878       108831 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879       108831 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877        82994 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878        82994 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879        82994 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881       108831 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882       108831 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881        82994 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882        82994 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_compress_ctl.sv.html
index f3e99b99304..013ced72f5d 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,14 +127,14 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26         2604 :    input  logic [15:0] din,        // 16-bit   compressed instruction
-      27          604 :    output logic [31:0] dout        // 32-bit uncompressed instruction
+      26         1724 :    input  logic [15:0] din,        // 16-bit   compressed instruction
+      27          392 :    output logic [31:0] dout        // 32-bit uncompressed instruction
       28              :    );
       29              : 
       30              : 
-      31        12516 :    logic               legal;
+      31         7640 :    logic               legal;
       32              : 
-      33         2604 :    logic [15:0]  i;
+      33         1724 :    logic [15:0]  i;
       34              : 
       35            2 :    logic [31:0]  o,l1,l2,l3;
       36              : 
@@ -144,27 +144,27 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43         9600 :    logic rdrd;
-      44         6028 :    logic rdrs1;
-      45         6628 :    logic rs2rs2;
-      46          868 :    logic rdprd;
-      47         2884 :    logic rdprs1;
-      48          264 :    logic rs2prs2;
-      49        12474 :    logic rs2prd;
-      50        12518 :    logic uimm9_2;
-      51          632 :    logic ulwimm6_2;
-      52          336 :    logic ulwspimm7_2;
-      53          232 :    logic rdeq2;
-      54          152 :    logic rdeq1;
-      55        11594 :    logic rs1eq2;
-      56         2080 :    logic sbroffset8_1;
-      57          232 :    logic simm9_4;
-      58         4892 :    logic simm5_0;
-      59          604 :    logic sjaloffset11_1;
-      60            8 :    logic sluimm17_12;
-      61         1020 :    logic uimm5_0;
-      62           56 :    logic uswimm6_2;
-      63          720 :    logic uswspimm7_2;
+      43         5900 :    logic rdrd;
+      44         3704 :    logic rdrs1;
+      45         3996 :    logic rs2rs2;
+      46          412 :    logic rdprd;
+      47         1680 :    logic rdprs1;
+      48           40 :    logic rs2prs2;
+      49         7626 :    logic rs2prd;
+      50         7642 :    logic uimm9_2;
+      51          208 :    logic ulwimm6_2;
+      52          236 :    logic ulwspimm7_2;
+      53          152 :    logic rdeq2;
+      54          132 :    logic rdeq1;
+      55         7046 :    logic rs1eq2;
+      56         1324 :    logic sbroffset8_1;
+      57          152 :    logic simm9_4;
+      58         3052 :    logic simm5_0;
+      59          392 :    logic sjaloffset11_1;
+      60            4 :    logic sluimm17_12;
+      61          612 :    logic uimm5_0;
+      62           32 :    logic uswimm6_2;
+      63          448 :    logic uswspimm7_2;
       64              : 
       65              : 
       66              : 
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115         4168 :    logic [5:0] simm5d;
-     116         4168 :    logic [9:2] uimm9d;
+     115         2564 :    logic [5:0] simm5d;
+     116         2564 :    logic [9:2] uimm9d;
      117              : 
-     118         4168 :    logic [9:4] simm9d;
-     119         4168 :    logic [6:2] ulwimm6d;
-     120         4168 :    logic [7:2] ulwspimm7d;
-     121         4168 :    logic [5:0] uimm5d;
-     122         4168 :    logic [20:1] sjald;
+     118         2564 :    logic [9:4] simm9d;
+     119         2564 :    logic [6:2] ulwimm6d;
+     120         2564 :    logic [7:2] ulwspimm7d;
+     121         2564 :    logic [5:0] uimm5d;
+     122         2564 :    logic [20:1] sjald;
      123              : 
-     124         4168 :    logic [31:12] sluimmd;
+     124         2564 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,9 +272,9 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171         4168 :    logic [8:1]   sbr8d;
-     172         4168 :    logic [6:2]   uswimm6d;
-     173         5204 :    logic [7:2]   uswspimm7d;
+     171         2564 :    logic [8:1]   sbr8d;
+     172         2564 :    logic [6:2]   uswimm6d;
+     173         3220 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
      176              :    assign sbr8d[8:1] =   { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ic_mem.sv.html
index 3f3679d248a..db135d8fd56 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26       584906 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27       584906 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26       359918 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27       359918 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -141,11 +141,11 @@
       37            0 :       input logic                                   ic_debug_wr_en,     // Icache debug wr
       38            0 :       input logic                                   ic_debug_tag_array, // Debug tag array
       39            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_debug_way,       // Debug way. Rd or Wr.
-      40         7276 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-      41        30354 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
+      40         4604 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+      41        18614 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
       42              : 
-      43         2012 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
-      44         7276 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      43         1172 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
+      44         4604 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       45            0 :       output logic [70:0]                           ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       46            0 :       output logic [25:0]                           ictag_debug_rd_data,// Debug icache tag.
       47            0 :       input logic  [70:0]                           ic_debug_wr_data,   // Debug wr cache.
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91       584906 :       input logic clk,
-      92       584906 :       input logic active_clk,
+      91       359918 :       input logic clk,
+      92       359918 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -201,8 +201,8 @@
       97            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en,
       98            0 :       input logic                          ic_rd_en,           // Read enable
       99              : 
-     100         2012 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
-     101         7276 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     100         1172 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
+     101         4604 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      102            0 :       input  logic [70:0]                             ic_debug_wr_data,   // Debug wr cache.
      103            0 :       output logic [70:0]                             ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      104            0 :       output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
@@ -212,8 +212,8 @@
      108            0 :       input logic                            ic_debug_wr_en,      // Icache debug wr
      109            0 :       input logic                            ic_debug_tag_array,  // Debug tag array
      110            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way,        // Debug way. Rd or Wr.
-     111         7276 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-     112        30354 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
+     111         4604 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+     112        18614 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
      113              : 
      114            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
      115            0 :       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
@@ -221,7 +221,7 @@
      117              : 
      118              :       ) ;
      119              : 
-     120         2742 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
+     120         1702 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
      121            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_wren;    //bank x ways
      122            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_rden;    //bank x ways
      123              : 
@@ -231,9 +231,9 @@
      127            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                ic_debug_sel_sb;
      128              : 
      129              :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0]                  wb_dout ;       //  ways x bank
-     130         2012 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
+     130         1172 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
      131              :    logic [pt.ICACHE_NUM_WAYS-1:0] [141:0]                                         wb_dout_way_pre;
-     132         7276 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
+     132         4604 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
      133            0 :    logic [141:0]                                                                  wb_dout_ecc;
      134              : 
      135            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                bank_check_en;
@@ -245,11 +245,11 @@
      141            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en;    // debug wr_way
      142            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en_ff; // debug wr_way
      143            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_wr_way_en;    // debug wr_way
-     144          212 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
+     144          136 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
      145              : 
-     146          212 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
+     146          136 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
      147              : 
-     148          212 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
+     148          136 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
      149            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_rd_hit_q;
      150              : 
      151              : 
@@ -278,7 +278,7 @@
      174              : 
      175              : 
      176            2 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr;
-     177          212 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
+     177          136 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
      178              : 
      179            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_up;
      180            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only_up;
@@ -296,7 +296,7 @@
      192              :    assign  ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      193              :    assign  ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      194              : 
-     195         3022 :    logic end_of_cache_line;
+     195         1902 :    logic end_of_cache_line;
      196              :    assign end_of_cache_line = (pt.ICACHE_LN_SZ==7'h40) ? (&ic_rw_addr_q[5:4]) : ic_rw_addr_q[4];
      197            2 :    always_comb begin : clkens
      198            2 :       ic_bank_way_clken  = '0;
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803       584906 :       input logic                                                   clk,
-     804       584906 :       input logic                                                   active_clk,
+     803       359918 :       input logic                                                   clk,
+     804       359918 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
@@ -939,13 +939,13 @@
      835            0 :    logic [pt.ICACHE_NUM_WAYS-1:0] [06:0]                           ic_tag_corrected_ecc_unc;
      836            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_single_ecc_error;
      837            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_double_ecc_error;
-     838           26 :    logic [6:0]                                                     ic_tag_ecc;
+     838           18 :    logic [6:0]                                                     ic_tag_ecc;
      839              : 
      840            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_way_perr ;
      841            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en ;
      842            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en_ff ;
      843              : 
-     844          212 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
+     844          136 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
      845            2 :    logic [31:pt.ICACHE_TAG_LO]                                     ic_rw_addr_ff;
      846            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_rden_q;          // way
      847            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_wren;          // way
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_iccm_mem.sv.html
index 9177ec68e29..4d93e1629af 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,14 +129,14 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28       584906 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29       584906 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28       359918 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29       359918 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
       33            0 :    input logic                                        iccm_wren,                           // ICCM write enable
-      34          256 :    input logic                                        iccm_rden,                           // ICCM read enable
-      35          212 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
+      34          172 :    input logic                                        iccm_rden,                           // ICCM read enable
+      35          136 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
       36            0 :    input logic                                        iccm_buf_correct_ecc,                // ICCM is doing a single bit error correct cycle
       37            0 :    input logic                                        iccm_correction_state,               // ICCM under a correction - This is needed to guard replacements when hit
       38            0 :    input logic [2:0]                                  iccm_wr_size,                        // ICCM write size
@@ -144,25 +144,25 @@
       40              : 
       41              :    el2_mem_if.veer_iccm                               iccm_mem_export,                     // RAM repositioned in testbench and connected by this interface
       42              : 
-      43           12 :    output logic [63:0]                                iccm_rd_data,                        // ICCM read data
-      44           12 :    output logic [77:0]                                iccm_rd_data_ecc,                    // ICCM read ecc
+      43            8 :    output logic [63:0]                                iccm_rd_data,                        // ICCM read data
+      44            8 :    output logic [77:0]                                iccm_rd_data_ecc,                    // ICCM read ecc
       45            0 :    input  logic                                       scan_mode                            // Scan mode control
       46              : 
       47              : );
       48              : 
       49              : 
       50            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                wren_bank;
-      51          120 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
-      52          120 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
-      53          212 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
+      51           80 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
+      52           80 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
+      53          136 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
       54              : 
-      55           12 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
+      55            8 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
-      57          216 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58        10004 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
-      59         2742 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
-      60           12 :    logic             [63:0]              iccm_rd_data_pre;
-      61           12 :    logic             [63:0]              iccm_data;
+      57          136 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
+      58         6164 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      59         1702 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
+      60            8 :    logic             [63:0]              iccm_rd_data_pre;
+      61            8 :    logic             [63:0]              iccm_data;
       62            0 :    logic [1:0]                           addr_incr;
       63            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data_vec;
       64              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ifc_ctl.sv.html
index 874809d7801..88a24b0ea0f 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,27 +130,27 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29       584906 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30       584906 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29       359918 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30       359918 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
       34              : 
-      35        36488 :    input logic ic_hit_f,      // Icache hit
-      36        36332 :    input logic ifu_ic_mb_empty, // Miss buffer empty
+      35        22464 :    input logic ic_hit_f,      // Icache hit
+      36        22392 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
-      38        31132 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39          812 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      38        19060 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
+      39          472 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
       41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
-      42         1524 :    input logic exu_flush_final, // FLush
-      43           24 :    input logic [31:1] exu_flush_path_final, // Flush path
+      42         1084 :    input logic exu_flush_final, // FLush
+      43           16 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45         5956 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
-      46         1692 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      45         3448 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      46         1004 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
       48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
-      49        13992 :    input logic ic_write_stall, // IC is writing, stop fetching
+      49         8604 :    input logic ic_write_stall, // IC is writing, stop fetching
       50            0 :    input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
       51              : 
       52            0 :    input logic [31:0]  dec_tlu_mrac_ff ,   // side_effect and cacheable for each region
@@ -158,34 +158,34 @@
       54            2 :    output logic [31:1] ifc_fetch_addr_f, // fetch addr F
       55            2 :    output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
       56              : 
-      57        16654 :    output logic  ifc_fetch_req_f,  // fetch request valid F
+      57        10042 :    output logic  ifc_fetch_req_f,  // fetch request valid F
       58              : 
-      59         1382 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
+      59          942 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
       60              : 
       61            2 :    output logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. BF stage
-      62        16654 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
+      62        10042 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
       63            2 :    output logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. BF stage
-      64           24 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
+      64           16 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       65            0 :    output logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       66              : 
-      67         1654 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
+      67         1170 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
       68              : 
       69              : 
       70              :    );
       71              : 
       72            2 :    logic [31:1]  fetch_addr_bf;
       73            2 :    logic [31:1]  fetch_addr_next;
-      74         2804 :    logic [3:0]   fb_write_f, fb_write_ns;
+      74         1504 :    logic [3:0]   fb_write_f, fb_write_ns;
       75              : 
-      76         2804 :    logic     fb_full_f_ns, fb_full_f;
+      76         1504 :    logic     fb_full_f_ns, fb_full_f;
       77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
-      78        31592 :    logic     sel_last_addr_bf, sel_next_addr_bf;
-      79        50366 :    logic     miss_f, miss_a;
+      78        19640 :    logic     sel_last_addr_bf, sel_next_addr_bf;
+      79        31050 :    logic     miss_f, miss_a;
       80            0 :    logic     flush_fb, dma_iccm_stall_any_f;
       81            4 :    logic     mb_empty_mod, goto_idle, leave_idle;
-      82        16562 :    logic     fetch_bf_en;
-      83         3282 :    logic         line_wrap;
-      84         2760 :    logic         fetch_addr_next_1;
+      82         9954 :    logic     fetch_bf_en;
+      83         2042 :    logic         line_wrap;
+      84         1712 :    logic         fetch_addr_next_1;
       85              : 
       86              :    // FSM assignment
       87              :     typedef enum logic [1:0] { IDLE  = 2'b00 ,
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_mem_ctl.sv.html
index 3e27eaf68f2..f0020669851 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,40 +131,40 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30       584906 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31       584906 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32       584906 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30       359918 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31       359918 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32       359918 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
-      35         1524 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
-      36           64 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
+      35         1084 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
+      36           36 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
       37            0 :    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
-      38        36368 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
+      38        22348 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
       39            0 :    input logic                       dec_tlu_force_halt,            // force halt.
       40              : 
       41            2 :    input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
       42            2 :    input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
-      43        16654 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
+      43        10042 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
       44            2 :    input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
-      45           24 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
+      45           16 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
-      47         1654 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
+      47         1170 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49         5956 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49         3448 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51         1666 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51          962 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
-      53        36324 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
-      54        36332 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
+      53        22384 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
+      54        22392 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
       55            0 :    output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
-      56        13992 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
+      56         8604 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
       57              : 
       58              : /// PMU signals
-      59        36324 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
+      59        22384 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
       60            0 :    output logic                      ifu_pmu_ic_hit,                // IC hit event
       61            0 :    output logic                      ifu_pmu_bus_error,             // Bus error event
       62            0 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
-      63        36322 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
+      63        22382 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
       64              : 
       65              :   //-------------------------- IFU AXI signals--------------------------
       66              :    // AXI Write Channels
@@ -188,10 +188,10 @@
       84            0 :    output logic                            ifu_axi_bready,
       85              : 
       86              :    // AXI Read Channels
-      87        36322 :    output logic                            ifu_axi_arvalid,
-      88        36322 :    input  logic                            ifu_axi_arready,
-      89        27564 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      90         9128 :    output logic [31:0]                     ifu_axi_araddr,
+      87        22382 :    output logic                            ifu_axi_arvalid,
+      88        22382 :    input  logic                            ifu_axi_arready,
+      89        16956 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      90         5732 :    output logic [31:0]                     ifu_axi_araddr,
       91            2 :    output logic [3:0]                      ifu_axi_arregion,
       92            0 :    output logic [7:0]                      ifu_axi_arlen,
       93            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -201,10 +201,10 @@
       97            2 :    output logic [2:0]                      ifu_axi_arprot,
       98            0 :    output logic [3:0]                      ifu_axi_arqos,
       99              : 
-     100        72640 :    input  logic                            ifu_axi_rvalid,
+     100        44760 :    input  logic                            ifu_axi_rvalid,
      101            2 :    output logic                            ifu_axi_rready,
-     102        10872 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     103         3994 :    input  logic [63:0]                     ifu_axi_rdata,
+     102         6856 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     103         2522 :    input  logic [63:0]                     ifu_axi_rdata,
      104            0 :    input  logic [1:0]                      ifu_axi_rresp,
      105              : 
      106            2 :     input  logic                     ifu_bus_clk_en,
@@ -221,7 +221,7 @@
      117            0 :    output logic                      iccm_dma_rvalid,   //   Data read from iccm is valid
      118            0 :    output logic [63:0]               iccm_dma_rdata,    //   dma data read from iccm
      119            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     120         1550 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
+     120         1106 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
      121              : 
      122              : 
      123              : //   I$ & ITAG Ports
@@ -229,8 +229,8 @@
      125            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      126            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      127              : 
-     128         2012 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
-     129         7276 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     128         1172 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
+     129         4604 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      130            0 :    input  logic [70:0]               ic_debug_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      131            0 :    input  logic [25:0]               ictag_debug_rd_data,  // Debug icache tag.
      132            0 :    output logic [70:0]               ic_debug_wr_data,     // Debug wr cache.
@@ -253,17 +253,17 @@
      149            0 :    input  logic                      ic_tag_perr,        // Icache Tag parity error
      150              : 
      151              :    // ICCM ports
-     152          212 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
+     152          136 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
      153            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
-     154          256 :    output logic                      iccm_rden,          // ICCM read enable.
+     154          172 :    output logic                      iccm_rden,          // ICCM read enable.
      155            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
      156            0 :    output logic [2:0]                iccm_wr_size,       // ICCM write location within DW.
      157              : 
-     158           12 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
-     159           12 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
-     160        33180 :    input  logic [1:0]                ifu_fetch_val,
+     158            8 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
+     159            8 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
+     160        20432 :    input  logic [1:0]                ifu_fetch_val,
      161              :    // IFU control signals
-     162        36488 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
+     162        22464 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
      163            0 :    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
      164            0 :    output logic [1:0]                ic_access_fault_type_f, // Access fault types
      165            0 :    output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
@@ -274,10 +274,10 @@
      170              : 
      171            0 :    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
      172            0 :    output logic                      iccm_dma_sb_error,      // Single Bit ECC error from a DMA access
-     173        33180 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
-     174         7276 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
-     175         7276 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
-     176        30354 :    output logic                      ic_sel_premux_data,     // Select premux data.
+     173        20432 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
+     174         4604 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
+     175         4604 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
+     176        18614 :    output logic                      ic_sel_premux_data,     // Select premux data.
      177              : 
      178              : /////  Debug
      179            0 :    input  el2_cache_debug_pkt_t     dec_tlu_ic_diag_pkt ,       // Icache/tag debug read/write packet
@@ -304,8 +304,8 @@
      200              : 
      201              : 
      202              : 
-     203        72640 :    logic           bus_ifu_wr_en     ;
-     204        72640 :    logic           bus_ifu_wr_en_ff  ;
+     203        44760 :    logic           bus_ifu_wr_en     ;
+     204        44760 :    logic           bus_ifu_wr_en_ff  ;
      205            0 :    logic           bus_ifu_wr_en_ff_q  ;
      206            0 :    logic           bus_ifu_wr_en_ff_wo_err  ;
      207            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     bus_ic_wr_en ;
@@ -333,36 +333,36 @@
      229            0 :    logic           scnd_miss_index_match ;
      230              : 
      231              : 
-     232         1550 :    logic           ifc_dma_access_q_ok;
-     233           24 :    logic           ifc_iccm_access_f ;
+     232         1106 :    logic           ifc_dma_access_q_ok;
+     233           16 :    logic           ifc_iccm_access_f ;
      234            0 :    logic           ifc_region_acc_fault_f;
      235            0 :    logic           ifc_region_acc_fault_final_f;
      236            0 :    logic  [1:0]    ifc_bus_acc_fault_f;
-     237        36324 :    logic           ic_act_miss_f;
+     237        22384 :    logic           ic_act_miss_f;
      238            0 :    logic           ic_miss_under_miss_f;
-     239          968 :    logic           ic_ignore_2nd_miss_f;
+     239          756 :    logic           ic_ignore_2nd_miss_f;
      240            0 :    logic           ic_act_hit_f;
-     241        36322 :    logic           miss_pending;
+     241        22382 :    logic           miss_pending;
      242            2 :    logic [31:1]    imb_in , imb_ff  ;
      243            2 :    logic [31:pt.ICACHE_BEAT_ADDR_HI+1]    miss_addr_in , miss_addr  ;
-     244         5328 :    logic           miss_wrap_f ;
-     245         1524 :    logic           flush_final_f;
-     246        17862 :    logic           ifc_fetch_req_f;
-     247        16654 :    logic           ifc_fetch_req_f_raw;
-     248        36488 :    logic           fetch_req_f_qual   ;
-     249        16654 :    logic           ifc_fetch_req_qual_bf ;
+     244         3332 :    logic           miss_wrap_f ;
+     245         1084 :    logic           flush_final_f;
+     246        10934 :    logic           ifc_fetch_req_f;
+     247        10042 :    logic           ifc_fetch_req_f_raw;
+     248        22464 :    logic           fetch_req_f_qual   ;
+     249        10042 :    logic           ifc_fetch_req_qual_bf ;
      250            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     replace_way_mb_any;
-     251        36320 :    logic           last_beat;
-     252        50440 :    logic           reset_beat_cnt  ;
-     253        19664 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
-     254        36320 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
+     251        22380 :    logic           last_beat;
+     252        31064 :    logic           reset_beat_cnt  ;
+     253        12212 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
+     254        22380 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
      255            2 :    logic [31:1]    ifu_fetch_addr_int_f ;
      256            2 :    logic [31:1]    ifu_ic_rw_int_addr ;
-     257        36322 :    logic           crit_wd_byp_ok_ff ;
-     258        36232 :    logic           ic_crit_wd_rdy_new_ff;
-     259         3850 :    logic   [79:0]  ic_byp_data_only_pre_new;
-     260         2536 :    logic   [79:0]  ic_byp_data_only_new;
-     261        36232 :    logic           ic_byp_hit_f ;
+     257        22382 :    logic           crit_wd_byp_ok_ff ;
+     258        22292 :    logic           ic_crit_wd_rdy_new_ff;
+     259         2498 :    logic   [79:0]  ic_byp_data_only_pre_new;
+     260         1460 :    logic   [79:0]  ic_byp_data_only_new;
+     261        22292 :    logic           ic_byp_hit_f ;
      262            2 :    logic           ic_valid ;
      263            2 :    logic           ic_valid_ff;
      264            0 :    logic           reset_all_tags;
@@ -380,94 +380,94 @@
      276              : 
      277            0 :    logic           reset_ic_in ;
      278            0 :    logic           reset_ic_ff ;
-     279         2742 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
+     279         1702 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
      280            2 :    logic [31:1]    ifu_status_wr_addr;
      281            0 :    logic           sel_mb_addr ;
      282            0 :    logic           sel_mb_addr_ff ;
      283            0 :    logic           sel_mb_status_addr ;
-     284         7276 :    logic [63:0]    ic_final_data;
+     284         4604 :    logic [63:0]    ic_final_data;
      285              : 
      286            0 :    logic [pt.ICACHE_STATUS_BITS-1:0]                              way_status_new_ff ;
      287            0 :    logic                                    way_status_wr_en_ff ;
      288            0 :    logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0]        way_status_out ;
      289            0 :    logic [1:0]                              ic_debug_way_enc;
      290              : 
-     291        10872 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
+     291         6856 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
      292              : 
-     293        17606 :    logic         fetch_req_icache_f;
-     294          256 :    logic         fetch_req_iccm_f;
-     295          256 :    logic         ic_iccm_hit_f;
+     293        10762 :    logic         fetch_req_icache_f;
+     294          172 :    logic         fetch_req_iccm_f;
+     295          172 :    logic         ic_iccm_hit_f;
      296            2 :    logic         fetch_uncacheable_ff;
      297            0 :    logic         way_status_wr_en;
-     298        30102 :    logic         sel_byp_data;
-     299        30340 :    logic         sel_ic_data;
-     300          256 :    logic         sel_iccm_data;
+     298        18446 :    logic         sel_byp_data;
+     299        18604 :    logic         sel_ic_data;
+     300          172 :    logic         sel_iccm_data;
      301            0 :    logic         ic_rd_parity_final_err;
-     302        36324 :    logic         ic_act_miss_f_delayed;
+     302        22384 :    logic         ic_act_miss_f_delayed;
      303            0 :    logic         bus_ifu_wr_data_error;
      304            0 :    logic         bus_ifu_wr_data_error_ff;
      305            0 :    logic         way_status_wr_en_w_debug;
      306            0 :    logic         ic_debug_tag_val_rd_out;
-     307        36324 :    logic         ifu_pmu_ic_miss_in;
+     307        22384 :    logic         ifu_pmu_ic_miss_in;
      308            0 :    logic         ifu_pmu_ic_hit_in;
      309            0 :    logic         ifu_pmu_bus_error_in;
-     310        36322 :    logic         ifu_pmu_bus_trxn_in;
+     310        22382 :    logic         ifu_pmu_bus_trxn_in;
      311            0 :    logic         ifu_pmu_bus_busy_in;
      312            0 :    logic         ic_debug_ict_array_sel_in;
      313            0 :    logic         ic_debug_ict_array_sel_ff;
      314            0 :    logic         debug_data_clken;
-     315        36320 :    logic         last_data_recieved_in ;
-     316        36320 :    logic         last_data_recieved_ff ;
+     315        22380 :    logic         last_data_recieved_in ;
+     316        22380 :    logic         last_data_recieved_ff ;
      317              : 
-     318        72640 :    logic                          ifu_bus_rvalid           ;
-     319        72640 :    logic                          ifu_bus_rvalid_ff        ;
-     320        72640 :    logic                          ifu_bus_rvalid_unq_ff    ;
-     321        36322 :    logic                          ifu_bus_arready_unq       ;
-     322        36322 :    logic                          ifu_bus_arready_unq_ff    ;
-     323        36322 :    logic                          ifu_bus_arvalid           ;
-     324        36322 :    logic                          ifu_bus_arvalid_ff        ;
-     325        36322 :    logic                          ifu_bus_arready           ;
-     326        36322 :    logic                          ifu_bus_arready_ff        ;
-     327         3994 :    logic [63:0]                   ifu_bus_rdata_ff        ;
+     318        44760 :    logic                          ifu_bus_rvalid           ;
+     319        44760 :    logic                          ifu_bus_rvalid_ff        ;
+     320        44760 :    logic                          ifu_bus_rvalid_unq_ff    ;
+     321        22382 :    logic                          ifu_bus_arready_unq       ;
+     322        22382 :    logic                          ifu_bus_arready_unq_ff    ;
+     323        22382 :    logic                          ifu_bus_arvalid           ;
+     324        22382 :    logic                          ifu_bus_arvalid_ff        ;
+     325        22382 :    logic                          ifu_bus_arready           ;
+     326        22382 :    logic                          ifu_bus_arready_ff        ;
+     327         2522 :    logic [63:0]                   ifu_bus_rdata_ff        ;
      328            0 :    logic [1:0]                    ifu_bus_rresp_ff          ;
-     329        72640 :    logic                          ifu_bus_rsp_valid ;
+     329        44760 :    logic                          ifu_bus_rsp_valid ;
      330            2 :    logic                          ifu_bus_rsp_ready ;
-     331        10872 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
-     332         3994 :    logic [63:0]                   ifu_bus_rsp_rdata;
+     331         6856 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
+     332         2522 :    logic [63:0]                   ifu_bus_rsp_rdata;
      333            0 :    logic [1:0]                    ifu_bus_rsp_opc;
      334              : 
-     335         5236 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
+     335         3184 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
      336            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    wr_data_c1_clk;
-     337         5236 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
-     338         5236 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
+     337         3184 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
+     338         3184 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
      339            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error_in;
      340            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error;
-     341         2742 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
-     342         4982 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
+     341         1702 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
+     342         3170 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
      343            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_1;
-     344         4220 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
-     345         4220 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
+     344         2600 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
+     345         2600 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
      346            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_1;
-     347        51584 :    logic          miss_buff_hit_unq_f ;
+     347        31616 :    logic          miss_buff_hit_unq_f ;
      348            0 :    logic          stream_hit_f ;
      349            0 :    logic          stream_miss_f ;
      350            0 :    logic          stream_eol_f ;
-     351        36232 :    logic          crit_byp_hit_f ;
-     352        10872 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
+     351        22292 :    logic          crit_byp_hit_f ;
+     352         6856 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
      353              :    logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;
-     354         3672 :    logic [63:0] ic_miss_buff_half;
+     354         2232 :    logic [63:0] ic_miss_buff_half;
      355            0 :    logic        scnd_miss_req, scnd_miss_req_q;
      356            0 :    logic        scnd_miss_req_in;
      357              : 
      358              : 
      359            0 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_ff;
-     360          216 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
+     360          136 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
      361            0 :    logic [38:0]                         iccm_ecc_corr_data_ff;
      362            0 :    logic                                iccm_ecc_write_status     ;
      363            0 :    logic                                iccm_rd_ecc_single_err_ff   ;
      364            0 :    logic                                iccm_error_start;     // start the error fsm
      365            0 :    logic                                perr_state_en;
-     366        79468 :    logic                                miss_state_en;
+     366        48692 :    logic                                miss_state_en;
      367              : 
      368            0 :    logic        busclk;
      369            0 :    logic        busclk_force;
@@ -475,46 +475,46 @@
      371            2 :    logic        bus_ifu_bus_clk_en_ff;
      372            2 :    logic        bus_ifu_bus_clk_en ;
      373              : 
-     374        36324 :    logic        ifc_bus_ic_req_ff_in;
-     375        36322 :    logic        ifu_bus_cmd_valid ;
-     376        36322 :    logic        ifu_bus_cmd_ready ;
+     374        22384 :    logic        ifc_bus_ic_req_ff_in;
+     375        22382 :    logic        ifu_bus_cmd_valid ;
+     376        22382 :    logic        ifu_bus_cmd_ready ;
      377              : 
-     378        36320 :    logic        bus_inc_data_beat_cnt     ;
-     379        50440 :    logic        bus_reset_data_beat_cnt   ;
-     380        86762 :    logic        bus_hold_data_beat_cnt    ;
+     378        22380 :    logic        bus_inc_data_beat_cnt     ;
+     379        31064 :    logic        bus_reset_data_beat_cnt   ;
+     380        53446 :    logic        bus_hold_data_beat_cnt    ;
      381              : 
-     382        36322 :    logic        bus_inc_cmd_beat_cnt     ;
+     382        22382 :    logic        bus_inc_cmd_beat_cnt     ;
      383            0 :    logic        bus_reset_cmd_beat_cnt_0   ;
-     384        36324 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
-     385        36324 :    logic        bus_hold_cmd_beat_cnt    ;
+     384        22384 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
+     385        22384 :    logic        bus_hold_cmd_beat_cnt    ;
      386              : 
      387            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_data_beat_count  ;
      388            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_data_beat_count      ;
      389              : 
-     390        36324 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
-     391        36322 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
+     390        22384 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
+     391        22382 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
      392              : 
      393              : 
-     394        19664 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
-     395        19664 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
+     394        12212 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
+     395        12212 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
      396              : 
      397              : 
-     398        36322 :    logic        bus_cmd_sent           ;
-     399        36320 :    logic        bus_last_data_beat     ;
+     398        22382 :    logic        bus_cmd_sent           ;
+     399        22380 :    logic        bus_last_data_beat     ;
      400              : 
      401              : 
      402            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren            ;
      403              : 
      404            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren_last       ;
      405            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       wren_reset_miss      ;
-     406         1654 :    logic        ifc_dma_access_ok_d;
-     407         1654 :    logic        ifc_dma_access_ok_prev;
+     406         1170 :    logic        ifc_dma_access_ok_d;
+     407         1170 :    logic        ifc_dma_access_ok_prev;
      408              : 
-     409        36324 :    logic   bus_cmd_req_in ;
-     410        36324 :    logic   bus_cmd_req_hold ;
+     409        22384 :    logic   bus_cmd_req_in ;
+     410        22384 :    logic   bus_cmd_req_hold ;
      411              : 
-     412        16552 :    logic   second_half_available ;
-     413        16552 :    logic   write_ic_16_bytes ;
+     412        10240 :    logic   second_half_available ;
+     413        10240 :    logic   write_ic_16_bytes ;
      414              : 
      415            0 :    logic   ifc_region_acc_fault_final_bf;
      416            0 :    logic   ifc_region_acc_fault_memory_bf;
@@ -523,7 +523,7 @@
      419              : 
      420            0 :    logic   iccm_correct_ecc;
      421            0 :    logic   dma_sb_err_state, dma_sb_err_state_ff;
-     422        21928 :    logic   two_byte_instr;
+     422        13404 :    logic   two_byte_instr;
      423              : 
      424              :    typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;
      425            4 :    miss_state_t miss_state, miss_nxtstate;
@@ -533,11 +533,11 @@
      429            0 :    logic   err_stop_state_en ;
      430            0 :    logic   err_stop_fetch ;
      431              : 
-     432        36232 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
+     432        22292 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434         4896 :    logic   ifu_bp_hit_taken_q_f;
-     435        72640 :    logic   ifu_bus_rvalid_unq;
-     436        36322 :    logic   bus_cmd_beat_en;
+     434         2824 :    logic   ifu_bp_hit_taken_q_f;
+     435        44760 :    logic   ifu_bus_rvalid_unq;
+     436        22382 :    logic   bus_cmd_beat_en;
      437              : 
      438              : 
      439              : // ---- Clock gating section -----
@@ -587,21 +587,21 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486        20777 :          IDLE: begin : idle
-     487        20777 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488        20777 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486        15850 :          IDLE: begin : idle
+     487        15850 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488        15850 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490        63888 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491        63888 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492        63888 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493        63888 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494        63888 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495        63888 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496        63888 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497        63888 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498        63888 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499        63888 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500        63888 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490        48784 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491        48784 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492        48784 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493        48784 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494        48784 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495        48784 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496        48784 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497        48784 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498        48784 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499        48784 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500        48784 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,14 +611,14 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510        23717 :          MISS_WAIT: begin : miss_wait
-     511        23717 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512        23717 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510        17964 :          MISS_WAIT: begin : miss_wait
+     511        17964 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512        17964 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514          441 :          HIT_U_MISS: begin : hit_u_miss
-     515          441 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516          441 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517          441 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514          388 :          HIT_U_MISS: begin : hit_u_miss
+     515          388 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516          388 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517          388 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
@@ -638,7 +638,7 @@
      534              :    end
      535              :    rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en),   .*);
      536              : 
-     537        36322 :   logic    sel_hold_imb     ;
+     537        22382 :   logic    sel_hold_imb     ;
      538              : 
      539              :    assign miss_pending       =  (miss_state != IDLE) ;
      540              :    assign crit_wd_byp_ok_ff  =  (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
@@ -902,7 +902,7 @@
      798              : /////////////////////////////////////////////////////////////////////////////////////
      799              : //  Create full buffer...                                                          //
      800              : /////////////////////////////////////////////////////////////////////////////////////
-     801         3994 :      logic [63:0]       ic_miss_buff_data_in;
+     801         2522 :      logic [63:0]       ic_miss_buff_data_in;
      802              :      assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
      803              : 
      804              :      for (genvar i=0; i<pt.ICACHE_NUM_BEATS; i++) begin :  wr_flop
@@ -939,10 +939,10 @@
      835              : /////////////////////////////////////////////////////////////////////////////////////
      836              : // New bypass ready                                                                //
      837              : /////////////////////////////////////////////////////////////////////////////////////
-     838         2698 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
-     839         3992 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
-     840        36348 :    logic   bypass_data_ready_in;
-     841        36232 :    logic   ic_crit_wd_rdy_new_in;
+     838         1678 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
+     839         2472 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
+     840        22396 :    logic   bypass_data_ready_in;
+     841        22292 :    logic   ic_crit_wd_rdy_new_in;
      842              : 
      843              :    assign bypass_index[pt.ICACHE_BEAT_ADDR_HI:1] = imb_ff[pt.ICACHE_BEAT_ADDR_HI:1] ;
      844              :    assign bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3] = bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] + 1 ;
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945       108831 :       ERR_IDLE: begin : err_idle
-     946       108831 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947       108831 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948       108831 :         perr_sb_write_status = perr_state_en;
+     945        82994 :       ERR_IDLE: begin : err_idle
+     946        82994 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947        82994 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948        82994 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990       108831 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991       108831 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992       108831 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990        82994 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991        82994 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992        82994 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1469,7 +1469,7 @@
     1365              :                               ((miss_state == CRIT_BYP_OK) &  miss_state_en &  (miss_nxtstate == MISS_WAIT))  ))  |
     1366              :                              ( ifc_fetch_req_bf & exu_flush_final  & ~ifc_fetch_uncacheable_bf & ~ifc_iccm_access_bf )     ;
     1367              : 
-    1368        36936 : logic   ic_real_rd_wp_unused;
+    1368        22892 : logic   ic_real_rd_wp_unused;
     1369              : assign  ic_real_rd_wp_unused  =  (ifc_fetch_req_bf &  ~ifc_iccm_access_bf  &  ~ifc_region_acc_fault_final_bf & ~dec_tlu_fence_i_wb & ~stream_miss_f & ~ic_act_miss_f &
     1370              :                             ~(((miss_state == STREAM) & ~miss_state_en) |
     1371              :                               ((miss_state == CRIT_BYP_OK) & ~miss_state_en & ~(miss_nxtstate == MISS_WAIT)) |
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446       108831 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447       108831 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446        82994 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447        82994 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509       108831 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510       108831 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511       217662 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509        82994 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510        82994 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511       165988 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lib.sv.html
index 8105b4d1395..43102a9ee16 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35          172 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
-      36         8004 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
+      35          116 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
+      36         4904 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
       37              :                         );
       38              : 
       39              : 
@@ -158,9 +158,9 @@
       54              : #(
       55              : `include "el2_param.vh"
       56              :  )(
-      57         1692 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58         8358 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59         8534 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      57         1084 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
+      58         5054 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59         5074 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu.sv.html
index 15d822a4e23..630a2b060f0 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        40.9%
+    
+        39.9%
     
     
-        81
+        79
     
     
         198
@@ -137,7 +137,7 @@
       33              : (
       34              : 
       35            0 :    input logic                             clk_override,             // Override non-functional clock gating
-      36           64 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
+      36           36 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
       37            0 :    input logic                             dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
       38            0 :    input logic                             dec_tlu_force_halt,       // This will be high till TLU goes to debug halt
       39              : 
@@ -147,21 +147,21 @@
       43            0 :    input logic                             dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
       44            0 :    input logic                             dec_tlu_core_ecc_disable,          // disable the generation of the ecc
       45              : 
-      46         1284 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
-      47           12 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
-      48          684 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
+      46          300 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
+      47            8 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
+      48          420 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
       49              : 
-      50         2568 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
-      51        11276 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
+      50         1396 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
+      51         6928 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
       52            0 :    input logic [31:0]                      dec_tlu_mrac_ff,       // CSR for memory region control
       53              : 
       54            0 :    output logic [31:0]                     lsu_result_m,          // lsu load data
       55            0 :    output logic [31:0]                     lsu_result_corr_r,     // This is the ECC corrected data going to RF
-      56          248 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
-      57          248 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
+      56          160 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
+      57          160 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
       58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
-      59         8954 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
-      60         8952 :    output logic                            lsu_active,            // Used to turn off top level clk
+      59         5458 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
+      60         5456 :    output logic                            lsu_active,            // Used to turn off top level clk
       61              : 
       62            0 :    output logic [31:1]                     lsu_fir_addr,        // fast interrupt address
       63            0 :    output logic [1:0]                      lsu_fir_error,       // Error during fast interrupt lookup
@@ -173,22 +173,22 @@
       69            2 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
       70              : 
       71              :    // Non-blocking loads
-      72         5868 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
-      73         1920 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
+      72         3496 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
+      73         1280 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
       74            0 :    output logic                               lsu_nonblock_load_inv_r,        // invalidate signal for the cam entry for non block loads
-      75         1920 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
-      76         6000 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
+      75         1280 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
+      76         3576 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
       77            0 :    output logic                               lsu_nonblock_load_data_error,   // non block load has an error
-      78          120 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
-      79           12 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
+      78           76 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
+      79            8 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
       80              : 
-      81         5868 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
-      82         5664 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
+      81         3496 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
+      82         3596 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
       83            0 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
-      84        11876 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
+      84         7308 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
       85            0 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
       86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
-      87           56 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
+      87           32 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
       88              : 
       89              :    // Trigger signals
       90            0 :    input                                   el2_trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode
@@ -199,8 +199,8 @@
       95            0 :    output logic                            dccm_rden,       // DCCM read enable
       96            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo, // DCCM write address low bank
       97            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi, // DCCM write address hi bank
-      98         1404 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
-      99         1404 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
+      98          432 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
+      99          432 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
      100            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo, // DCCM write data for lo bank
      101            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi, // DCCM write data for hi bank
      102              : 
@@ -213,12 +213,12 @@
      109            0 :    output logic                            picm_mken,    // Need to read the mask for stores to determine which bits to write/forward
      110            2 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
      111            2 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
-     112           12 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
+     112            8 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
      113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
      114              : 
      115              :    // AXI Write Channels
-     116         6008 :    output logic                            lsu_axi_awvalid,
-     117        11970 :    input  logic                            lsu_axi_awready,
+     116         3812 :    output logic                            lsu_axi_awvalid,
+     117         7366 :    input  logic                            lsu_axi_awready,
      118            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      119            2 :    output logic [31:0]                     lsu_axi_awaddr,
      120            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -230,20 +230,20 @@
      126            0 :    output logic [2:0]                      lsu_axi_awprot,
      127            0 :    output logic [3:0]                      lsu_axi_awqos,
      128              : 
-     129         6008 :    output logic                            lsu_axi_wvalid,
-     130        11970 :    input  logic                            lsu_axi_wready,
-     131           44 :    output logic [63:0]                     lsu_axi_wdata,
-     132          832 :    output logic [7:0]                      lsu_axi_wstrb,
+     129         3812 :    output logic                            lsu_axi_wvalid,
+     130         7366 :    input  logic                            lsu_axi_wready,
+     131           24 :    output logic [63:0]                     lsu_axi_wdata,
+     132          508 :    output logic [7:0]                      lsu_axi_wstrb,
      133            2 :    output logic                            lsu_axi_wlast,
      134              : 
-     135         6100 :    input  logic                            lsu_axi_bvalid,
+     135         3868 :    input  logic                            lsu_axi_bvalid,
      136            2 :    output logic                            lsu_axi_bready,
      137            0 :    input  logic [1:0]                      lsu_axi_bresp,
      138            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      139              : 
      140              :    // AXI Read Channels
-     141         5868 :    output logic                            lsu_axi_arvalid,
-     142        11878 :    input  logic                            lsu_axi_arready,
+     141         3496 :    output logic                            lsu_axi_arvalid,
+     142         7310 :    input  logic                            lsu_axi_arready,
      143            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      144            2 :    output logic [31:0]                     lsu_axi_araddr,
      145            2 :    output logic [3:0]                      lsu_axi_arregion,
@@ -255,10 +255,10 @@
      151            0 :    output logic [2:0]                      lsu_axi_arprot,
      152            0 :    output logic [3:0]                      lsu_axi_arqos,
      153              : 
-     154         6000 :    input  logic                            lsu_axi_rvalid,
+     154         3576 :    input  logic                            lsu_axi_rvalid,
      155            2 :    output logic                            lsu_axi_rready,
      156            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     157          124 :    input  logic [63:0]                     lsu_axi_rdata,
+     157           80 :    input  logic [63:0]                     lsu_axi_rdata,
      158            0 :    input  logic [1:0]                      lsu_axi_rresp,
      159            2 :    input  logic                            lsu_axi_rlast,
      160              : 
@@ -276,32 +276,32 @@
      172            0 :    output logic                            dccm_dma_ecc_error,  // DMA load had ecc error
      173            0 :    output logic [2:0]                      dccm_dma_rtag,       // DMA request tag
      174            0 :    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
-     175        11278 :    output logic                            dccm_ready,          // lsu ready for DMA access
+     175         6930 :    output logic                            dccm_ready,          // lsu ready for DMA access
      176              : 
      177              :    // DCCM ECC status
      178            0 :    output logic                            lsu_dccm_rd_ecc_single_err,
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182       584906 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183       584906 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182       359918 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183       359918 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
-     186         1404 :     output logic [31:0] lsu_pmp_addr_start,
-     187         1404 :     output logic [31:0] lsu_pmp_addr_end,
-     188         4414 :     input  logic        lsu_pmp_error_start,
-     189         4414 :     input  logic        lsu_pmp_error_end,
-     190         5664 :     output logic        lsu_pmp_we,
-     191         5868 :     output logic        lsu_pmp_re
+     186          432 :     output logic [31:0] lsu_pmp_addr_start,
+     187          432 :     output logic [31:0] lsu_pmp_addr_end,
+     188            0 :     input  logic        lsu_pmp_error_start,
+     189            0 :     input  logic        lsu_pmp_error_end,
+     190         3596 :     output logic        lsu_pmp_we,
+     191         3496 :     output logic        lsu_pmp_re
      192              : 
      193              :    );
      194              : 
      195            0 :    logic        lsu_dccm_rden_m;
      196            0 :    logic        lsu_dccm_rden_r;
-     197           12 :    logic [31:0] store_data_m;
-     198           12 :    logic [31:0] store_data_r;
-     199           12 :    logic [31:0] store_data_hi_r, store_data_lo_r;
-     200           12 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
+     197            8 :    logic [31:0] store_data_m;
+     198            8 :    logic [31:0] store_data_r;
+     199            8 :    logic [31:0] store_data_hi_r, store_data_lo_r;
+     200            8 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
      201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
      202            0 :    logic [31:0] sec_data_lo_r, sec_data_hi_r;
      203              : 
@@ -324,12 +324,12 @@
      220              : 
      221            0 :    logic [31:0] picm_mask_data_m;
      222              : 
-     223         1404 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
-     224         1404 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
+     223          432 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
+     224          432 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
      225              :   assign lsu_pmp_addr_start = lsu_addr_d;
      226              :   assign lsu_pmp_addr_end   = end_addr_d;
      227              : 
-     228         2568 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
+     228         1396 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
      229            0 :    logic        lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
      230              :   assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
      231              :   assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
@@ -338,7 +338,7 @@
      234            0 :    logic        store_stbuf_reqvld_r;
      235            0 :    logic        ldst_stbuf_reqvld_r;
      236              : 
-     237        11500 :    logic        lsu_commit_r;
+     237         7076 :    logic        lsu_commit_r;
      238            0 :    logic        lsu_exc_m;
      239              : 
      240            0 :    logic        addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
@@ -365,11 +365,11 @@
      261            0 :    logic        lsu_stbuf_full_any;
      262              : 
      263              :     // Bus signals
-     264        11500 :    logic        lsu_busreq_r;
-     265         5840 :    logic        lsu_bus_buffer_pend_any;
-     266         9830 :    logic        lsu_bus_buffer_empty_any;
-     267          248 :    logic        lsu_bus_buffer_full_any;
-     268        11500 :    logic        lsu_busreq_m;
+     264         7076 :    logic        lsu_busreq_r;
+     265         3708 :    logic        lsu_bus_buffer_pend_any;
+     266         5966 :    logic        lsu_bus_buffer_empty_any;
+     267          160 :    logic        lsu_bus_buffer_full_any;
+     268         7076 :    logic        lsu_busreq_m;
      269            0 :    logic [31:0] bus_read_data_m;
      270              : 
      271            0 :    logic        flush_m_up, flush_r;
@@ -381,16 +381,16 @@
      277            0 :    logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
      278              : 
      279              :    // Clocks
-     280         9264 :    logic        lsu_busm_clken;
-     281        16968 :    logic        lsu_bus_obuf_c1_clken;
-     282       584906 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283       584906 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284       584906 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     280         5628 :    logic        lsu_busm_clken;
+     281        10544 :    logic        lsu_bus_obuf_c1_clken;
+     282       359918 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283       359918 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284       359918 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286       584906 :    logic        lsu_stbuf_c1_clk;
-     287       584906 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286       359918 :    logic        lsu_stbuf_c1_clk;
+     287       359918 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289       584906 :    logic        lsu_free_c2_clk;
+     289       359918 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_addrcheck.sv.html
index d6c3c24e030..6092dc054d3 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_addrcheck.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        24.0%
+    
+        20.0%
     
     
-        12
+        10
     
     
         50
@@ -131,16 +131,16 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30       584906 :    input logic          lsu_c2_m_clk,              // clock
+      30       359918 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
-      33         1404 :    input logic [31:0]   start_addr_d,              // start address for lsu
-      34         1404 :    input logic [31:0]   end_addr_d,                // end address for lsu
-      35         2568 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
+      33          432 :    input logic [31:0]   start_addr_d,              // start address for lsu
+      34          432 :    input logic [31:0]   end_addr_d,                // end address for lsu
+      35         1396 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
       36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
-      37         3764 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
+      37         2448 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
       38              : 
-      39         1284 :    input logic [31:0]   rs1_d,                     // address rs operand
+      39          300 :    input logic [31:0]   rs1_d,                     // address rs operand
       40              : 
       41            0 :    output logic         is_sideeffects_m,          // is sideffects space
       42            0 :    output logic         addr_in_dccm_d,            // address in dccm
@@ -154,10 +154,10 @@
       50            0 :    output logic         fir_dccm_access_error_d,   // Fast interrupt dccm access error
       51            0 :    output logic         fir_nondccm_access_error_d,// Fast interrupt dccm access error
       52              : 
-      53         4414 :     input logic lsu_pmp_error_start,
-      54         4414 :     input logic lsu_pmp_error_end,
+      53            0 :     input logic lsu_pmp_error_start,
+      54            0 :     input logic lsu_pmp_error_end,
       55              : 
-      56            0 :    input  logic         scan_mode                  // Scan mode
+      56            0 :    input  logic         scan_mode                  // Scan mode
       57              : );
       58              : 
       59              : 
@@ -167,7 +167,7 @@
       63            0 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
       64            0 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
       65            0 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
-      66         3764 :    logic [4:0]  csr_idx;
+      66         2448 :    logic [4:0]  csr_idx;
       67            0 :    logic        addr_in_iccm;
       68            0 :    logic        start_addr_dccm_or_pic;
       69            0 :    logic        base_reg_dccm_or_pic;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_buffer.sv.html
index 9e90457a328..b6a7e5d6959 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31       584906 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31       359918 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -142,34 +142,34 @@
       38            0 :    input logic                          dec_tlu_force_halt,
       39              : 
       40              :    // various clocks needed for the bus reads and writes
-      41        16968 :    input logic                          lsu_bus_obuf_c1_clken,
-      42         9264 :    input logic                          lsu_busm_clken,
-      43       584906 :    input logic                          lsu_c2_r_clk,
-      44       584906 :    input logic                          lsu_bus_ibuf_c1_clk,
+      41        10544 :    input logic                          lsu_bus_obuf_c1_clken,
+      42         5628 :    input logic                          lsu_busm_clken,
+      43       359918 :    input logic                          lsu_c2_r_clk,
+      44       359918 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46       584906 :    input logic                          lsu_bus_buf_c1_clk,
-      47       584906 :    input logic                          lsu_free_c2_clk,
+      46       359918 :    input logic                          lsu_bus_buf_c1_clk,
+      47       359918 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
-      51        11276 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
-      52         2568 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
-      53         2568 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
+      51         6928 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
+      52         1396 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
+      53         1396 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
       54              : 
-      55         1404 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
-      56         1404 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
-      57         1404 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
-      58         1404 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
-      59           12 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
+      55          432 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
+      56          432 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
+      57          432 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
+      58          432 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
+      59            8 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
       60              : 
-      61          776 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
-      62          584 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
-      63        11500 :    input logic                          lsu_busreq_m,                   // bus request is in m
-      64        11500 :    output logic                         lsu_busreq_r,                   // bus request is in r
+      61          496 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
+      62          376 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
+      63         7076 :    input logic                          lsu_busreq_m,                   // bus request is in m
+      64         7076 :    output logic                         lsu_busreq_r,                   // bus request is in r
       65            0 :    input logic                          ld_full_hit_m,                  // load can get all its byte from a write buffer entry
-      66           64 :    input logic                          flush_m_up,                     // flush
+      66           36 :    input logic                          flush_m_up,                     // flush
       67            0 :    input logic                          flush_r,                        // flush
-      68        11500 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
+      68         7076 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
       69            0 :    input logic                          is_sideeffects_r,               // lsu attribute is side_effects
       70            0 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
       71            0 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
@@ -177,9 +177,9 @@
       73              : 
       74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
       75              : 
-      76         5840 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
-      77          248 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
-      78         9830 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
+      76         3708 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
+      77          160 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
+      78         5966 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
       79              : 
       80            0 :    output logic [3:0]                   ld_byte_hit_buf_lo, ld_byte_hit_buf_hi,    // Byte enables for forwarding data
       81            0 :    output logic [31:0]                  ld_fwddata_buf_lo, ld_fwddata_buf_hi,      // load forwarding data
@@ -189,24 +189,24 @@
       85            2 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
       86              : 
       87              :    // Non-blocking loads
-      88         5868 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
-      89         1920 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
+      88         3496 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
+      89         1280 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
       90            0 :    output logic                               lsu_nonblock_load_inv_r,       // invalidate signal for the cam entry for non block loads
-      91         1920 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
-      92         6000 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
+      91         1280 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
+      92         3576 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
       93            0 :    output logic                               lsu_nonblock_load_data_error,  // non block load has an error
-      94          120 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
-      95           12 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
+      94           76 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
+      95            8 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
       96              : 
       97              :    // PMU events
-      98        11876 :    output logic                         lsu_pmu_bus_trxn,
+      98         7308 :    output logic                         lsu_pmu_bus_trxn,
       99            0 :    output logic                         lsu_pmu_bus_misaligned,
      100            0 :    output logic                         lsu_pmu_bus_error,
-     101           56 :    output logic                         lsu_pmu_bus_busy,
+     101           32 :    output logic                         lsu_pmu_bus_busy,
      102              : 
      103              :    // AXI Write Channels
-     104         6008 :    output logic                            lsu_axi_awvalid,
-     105        11970 :    input  logic                            lsu_axi_awready,
+     104         3812 :    output logic                            lsu_axi_awvalid,
+     105         7366 :    input  logic                            lsu_axi_awready,
      106            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      107            2 :    output logic [31:0]                     lsu_axi_awaddr,
      108            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -218,20 +218,20 @@
      114            0 :    output logic [2:0]                      lsu_axi_awprot,
      115            0 :    output logic [3:0]                      lsu_axi_awqos,
      116              : 
-     117         6008 :    output logic                            lsu_axi_wvalid,
-     118        11970 :    input  logic                            lsu_axi_wready,
-     119           44 :    output logic [63:0]                     lsu_axi_wdata,
-     120          832 :    output logic [7:0]                      lsu_axi_wstrb,
+     117         3812 :    output logic                            lsu_axi_wvalid,
+     118         7366 :    input  logic                            lsu_axi_wready,
+     119           24 :    output logic [63:0]                     lsu_axi_wdata,
+     120          508 :    output logic [7:0]                      lsu_axi_wstrb,
      121            2 :    output logic                            lsu_axi_wlast,
      122              : 
-     123         6100 :    input  logic                            lsu_axi_bvalid,
+     123         3868 :    input  logic                            lsu_axi_bvalid,
      124            2 :    output logic                            lsu_axi_bready,
      125            0 :    input  logic [1:0]                      lsu_axi_bresp,
      126            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      127              : 
      128              :    // AXI Read Channels
-     129         5868 :    output logic                            lsu_axi_arvalid,
-     130        11878 :    input  logic                            lsu_axi_arready,
+     129         3496 :    output logic                            lsu_axi_arvalid,
+     130         7310 :    input  logic                            lsu_axi_arready,
      131            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      132            2 :    output logic [31:0]                     lsu_axi_araddr,
      133            2 :    output logic [3:0]                      lsu_axi_arregion,
@@ -243,10 +243,10 @@
      139            0 :    output logic [2:0]                      lsu_axi_arprot,
      140            0 :    output logic [3:0]                      lsu_axi_arqos,
      141              : 
-     142         6000 :    input  logic                            lsu_axi_rvalid,
+     142         3576 :    input  logic                            lsu_axi_rvalid,
      143            2 :    output logic                            lsu_axi_rready,
      144            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     145          124 :    input  logic [63:0]                     lsu_axi_rdata,
+     145           80 :    input  logic [63:0]                     lsu_axi_rdata,
      146            0 :    input  logic [1:0]                      lsu_axi_rresp,
      147              : 
      148            2 :    input logic                             lsu_bus_clk_en,
@@ -264,7 +264,7 @@
      160              :    localparam TIMER_MAX = TIMER - 1;  // Maximum value of timer
      161              :    localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);
      162              : 
-     163         3622 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
+     163         2140 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
      164            0 :    logic [DEPTH-1:0]                    ld_addr_hitvec_lo, ld_addr_hitvec_hi;
      165            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvec_lo, ld_byte_hitvec_hi;
      166            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;
@@ -273,82 +273,82 @@
      169            0 :    logic [3:0]                          ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;
      170              : 
      171            2 :    logic [3:0]                          ldst_byteen_r;
-     172         3622 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
-     173           12 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
+     172         2140 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
+     173            8 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
      174            2 :    logic                                is_aligned_r;                   // Aligned load/store
      175            2 :    logic                                ldst_samedw_r;
      176              : 
-     177         5868 :    logic                                lsu_nonblock_load_valid_r;
-     178          176 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
-     179         1920 :    logic [1:0]                          lsu_nonblock_addr_offset;
-     180          340 :    logic [1:0]                          lsu_nonblock_sz;
-     181         3748 :    logic                                lsu_nonblock_unsign;
-     182         6000 :    logic                                lsu_nonblock_load_data_ready;
+     177         3496 :    logic                                lsu_nonblock_load_valid_r;
+     178          128 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
+     179         1208 :    logic [1:0]                          lsu_nonblock_addr_offset;
+     180          212 :    logic [1:0]                          lsu_nonblock_sz;
+     181         2372 :    logic                                lsu_nonblock_unsign;
+     182         3576 :    logic                                lsu_nonblock_load_data_ready;
      183              : 
      184            0 :    logic [DEPTH-1:0]                    CmdPtr0Dec, CmdPtr1Dec;
-     185           12 :    logic [DEPTH-1:0]                    RspPtrDec;
+     185            8 :    logic [DEPTH-1:0]                    RspPtrDec;
      186            0 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
-     187          100 :    logic [DEPTH_LOG2-1:0]               RspPtr;
-     188         1920 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
-     189         2244 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
+     187           64 :    logic [DEPTH_LOG2-1:0]               RspPtr;
+     188         1280 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
+     189         1456 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
      190            0 :    logic                                found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;
      191            0 :    logic [3:0]                          buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;
-     192          224 :    logic                                any_done_wait_state;
+     192          160 :    logic                                any_done_wait_state;
      193            0 :    logic                                bus_sideeffect_pend;
      194            2 :    logic                                bus_coalescing_disable;
      195              : 
-     196          516 :    logic                                bus_addr_match_pending;
-     197        11876 :    logic                                bus_cmd_sent, bus_cmd_ready;
-     198         6008 :    logic                                bus_wcmd_sent, bus_wdata_sent;
-     199         6000 :    logic                                bus_rsp_read, bus_rsp_write;
+     196          344 :    logic                                bus_addr_match_pending;
+     197         7308 :    logic                                bus_cmd_sent, bus_cmd_ready;
+     198         3812 :    logic                                bus_wcmd_sent, bus_wdata_sent;
+     199         3576 :    logic                                bus_rsp_read, bus_rsp_write;
      200            0 :    logic [pt.LSU_BUS_TAG-1:0]           bus_rsp_read_tag, bus_rsp_write_tag;
      201            0 :    logic                                bus_rsp_read_error, bus_rsp_write_error;
-     202          124 :    logic [63:0]                         bus_rsp_rdata;
+     202           80 :    logic [63:0]                         bus_rsp_rdata;
      203              : 
      204              :    // Bus buffer signals
-     205           36 :    state_t [DEPTH-1:0]                  buf_state;
+     205           24 :    state_t [DEPTH-1:0]                  buf_state;
      206            2 :    logic   [DEPTH-1:0][1:0]             buf_sz;
      207            2 :    logic   [DEPTH-1:0][31:0]            buf_addr;
      208            2 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
      209            0 :    logic   [DEPTH-1:0]                  buf_sideeffect;
-     210           14 :    logic   [DEPTH-1:0]                  buf_write;
+     210            8 :    logic   [DEPTH-1:0]                  buf_write;
      211            0 :    logic   [DEPTH-1:0]                  buf_unsign;
      212            0 :    logic   [DEPTH-1:0]                  buf_dual;
      213            2 :    logic   [DEPTH-1:0]                  buf_samedw;
      214            0 :    logic   [DEPTH-1:0]                  buf_nomerge;
      215            0 :    logic   [DEPTH-1:0]                  buf_dualhi;
      216            2 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
-     217           12 :    logic   [DEPTH-1:0]                  buf_ldfwd;
+     217            8 :    logic   [DEPTH-1:0]                  buf_ldfwd;
      218            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
      219            0 :    logic   [DEPTH-1:0]                  buf_error;
      220            0 :    logic   [DEPTH-1:0][31:0]            buf_data;
      221            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age, buf_age_younger;
      222            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage, buf_rsp_pickage;
      223              : 
-     224           36 :    state_t [DEPTH-1:0]                  buf_nxtstate;
-     225           36 :    logic   [DEPTH-1:0]                  buf_rst;
-     226          252 :    logic   [DEPTH-1:0]                  buf_state_en;
-     227           92 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
-     228           92 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
-     229          184 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
+     224           24 :    state_t [DEPTH-1:0]                  buf_nxtstate;
+     225           24 :    logic   [DEPTH-1:0]                  buf_rst;
+     226          152 :    logic   [DEPTH-1:0]                  buf_state_en;
+     227           56 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
+     228           56 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
+     229          112 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
      230            0 :    logic   [DEPTH-1:0]                  buf_dual_in;
      231            2 :    logic   [DEPTH-1:0]                  buf_samedw_in;
-     232          584 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
+     232          376 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
      233            0 :    logic   [DEPTH-1:0]                  buf_sideeffect_in;
-     234         4336 :    logic   [DEPTH-1:0]                  buf_unsign_in;
-     235         2564 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
-     236         5520 :    logic   [DEPTH-1:0]                  buf_write_in;
-     237           92 :    logic   [DEPTH-1:0]                  buf_wr_en;
+     234         2712 :    logic   [DEPTH-1:0]                  buf_unsign_in;
+     235         1392 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
+     236         3500 :    logic   [DEPTH-1:0]                  buf_write_in;
+     237           56 :    logic   [DEPTH-1:0]                  buf_wr_en;
      238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
-     239         2244 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
-     240           60 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
-     241           92 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
+     239         1456 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
+     240           40 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
+     241           56 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
      242            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
-     243         3622 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
-     244         1404 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
-     245           16 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
+     243         2136 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
+     244          432 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
+     245           48 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
      246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
-     247          128 :    logic   [DEPTH-1:0]                  buf_data_en;
+     247           80 :    logic   [DEPTH-1:0]                  buf_data_en;
      248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
      249            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_ageQ;
      250            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage_set;
@@ -356,69 +356,69 @@
      252            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspageQ;
      253              : 
      254              :    // Input buffer signals
-     255         5636 :    logic                               ibuf_valid;
+     255         3580 :    logic                               ibuf_valid;
      256            0 :    logic                               ibuf_dual;
      257            2 :    logic                               ibuf_samedw;
      258            0 :    logic                               ibuf_nomerge;
-     259          232 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
-     260          232 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
+     259          144 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
+     260          144 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
      261            0 :    logic                               ibuf_sideeffect;
      262            0 :    logic                               ibuf_unsign;
      263            2 :    logic                               ibuf_write;
-     264          116 :    logic [1:0]                         ibuf_sz;
-     265          154 :    logic [3:0]                         ibuf_byteen;
+     264           72 :    logic [1:0]                         ibuf_sz;
+     265           98 :    logic [3:0]                         ibuf_byteen;
      266            2 :    logic [31:0]                        ibuf_addr;
-     267           12 :    logic [31:0]                        ibuf_data;
-     268         5494 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
+     267            8 :    logic [31:0]                        ibuf_data;
+     268         3486 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
      269              : 
-     270         6280 :    logic                               ibuf_byp;
-     271         5636 :    logic                               ibuf_wr_en;
-     272         5636 :    logic                               ibuf_rst;
-     273           60 :    logic                               ibuf_force_drain;
-     274         5636 :    logic                               ibuf_drain_vld;
-     275           56 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
-     276         1920 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
-     277         1920 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
-     278         2568 :    logic [1:0]                         ibuf_sz_in;
-     279         1404 :    logic [31:0]                        ibuf_addr_in;
-     280         3622 :    logic [3:0]                         ibuf_byteen_in;
-     281           12 :    logic [31:0]                        ibuf_data_in;
-     282         5494 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
-     283          154 :    logic [3:0]                         ibuf_byteen_out;
-     284           12 :    logic [31:0]                        ibuf_data_out;
+     270         3752 :    logic                               ibuf_byp;
+     271         3580 :    logic                               ibuf_wr_en;
+     272         3580 :    logic                               ibuf_rst;
+     273           40 :    logic                               ibuf_force_drain;
+     274         3580 :    logic                               ibuf_drain_vld;
+     275           32 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
+     276         1280 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
+     277         1280 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
+     278         1396 :    logic [1:0]                         ibuf_sz_in;
+     279          432 :    logic [31:0]                        ibuf_addr_in;
+     280         2140 :    logic [3:0]                         ibuf_byteen_in;
+     281            8 :    logic [31:0]                        ibuf_data_in;
+     282         3486 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
+     283           98 :    logic [3:0]                         ibuf_byteen_out;
+     284            8 :    logic [31:0]                        ibuf_data_out;
      285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
      286              : 
      287              :    // Output buffer signals
-     288        11832 :    logic                               obuf_valid;
-     289         3870 :    logic                               obuf_write;
-     290          224 :    logic                               obuf_nosend;
-     291         5868 :    logic                               obuf_rdrsp_pend;
+     288         7284 :    logic                               obuf_valid;
+     289         2446 :    logic                               obuf_write;
+     290          160 :    logic                               obuf_nosend;
+     291         3496 :    logic                               obuf_rdrsp_pend;
      292            0 :    logic                               obuf_sideeffect;
      293            2 :    logic [31:0]                        obuf_addr;
-     294           44 :    logic [63:0]                        obuf_data;
-     295          340 :    logic [1:0]                         obuf_sz;
-     296         1948 :    logic [7:0]                         obuf_byteen;
+     294           24 :    logic [63:0]                        obuf_data;
+     295          212 :    logic [1:0]                         obuf_sz;
+     296         1196 :    logic [7:0]                         obuf_byteen;
      297            0 :    logic                               obuf_merge;
      298            0 :    logic                               obuf_cmd_done, obuf_data_done;
      299            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0;
      300            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1;
      301            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag;
      302              : 
-     303         6076 :    logic                               ibuf_buf_byp;
-     304           84 :    logic                               obuf_force_wr_en;
+     303         3624 :    logic                               ibuf_buf_byp;
+     304           56 :    logic                               obuf_force_wr_en;
      305            0 :    logic                               obuf_wr_wait;
-     306        11940 :    logic                               obuf_wr_en, obuf_wr_enQ;
-     307        11832 :    logic                               obuf_rst;
-     308         3910 :    logic                               obuf_write_in;
-     309         4532 :    logic                               obuf_nosend_in;
+     306         7348 :    logic                               obuf_wr_en, obuf_wr_enQ;
+     307         7284 :    logic                               obuf_rst;
+     308         2462 :    logic                               obuf_write_in;
+     309         2604 :    logic                               obuf_nosend_in;
      310            2 :    logic                               obuf_rdrsp_pend_en;
-     311         5868 :    logic                               obuf_rdrsp_pend_in;
+     311         3496 :    logic                               obuf_rdrsp_pend_in;
      312            0 :    logic                               obuf_sideeffect_in;
      313            2 :    logic                               obuf_aligned_in;
      314            2 :    logic [31:0]                        obuf_addr_in;
-     315          308 :    logic [63:0]                        obuf_data_in;
-     316          340 :    logic [1:0]                         obuf_sz_in;
-     317         2080 :    logic [7:0]                         obuf_byteen_in;
+     315          192 :    logic [63:0]                        obuf_data_in;
+     316          212 :    logic [1:0]                         obuf_sz_in;
+     317         1272 :    logic [7:0]                         obuf_byteen_in;
      318            0 :    logic                               obuf_merge_in;
      319            0 :    logic                               obuf_cmd_done_in, obuf_data_done_in;
      320            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0_in;
@@ -427,33 +427,33 @@
      323              : 
      324            0 :    logic                               obuf_merge_en;
      325            0 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
-     326         1424 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
-     327          270 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
+     326          824 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
+     327          182 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
      328              : 
-     329         6008 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
-     330         6008 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
-     331         5868 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
+     329         3812 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
+     330         3812 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
+     331         3496 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
      332            2 :    logic                               lsu_axi_bvalid_q, lsu_axi_bready_q;
      333            2 :    logic                               lsu_axi_rvalid_q, lsu_axi_rready_q;
      334            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_axi_bid_q, lsu_axi_rid_q;
      335            0 :    logic [1:0]                         lsu_axi_bresp_q, lsu_axi_rresp_q;
      336            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_imprecise_error_store_tag;
-     337          124 :    logic [63:0]                        lsu_axi_rdata_q;
+     337           80 :    logic [63:0]                        lsu_axi_rdata_q;
      338              : 
      339              :    //------------------------------------------------------------------------------
      340              :    // Load forwarding logic start
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344       365589 :    function automatic logic [2:0] f_Enc8to3;
+     344       278766 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348       365589 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349       365589 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350       365589 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348       278766 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349       278766 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350       278766 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352       365589 :       return Enc_value[2:0];
+     352       278766 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -663,20 +663,20 @@
      559              : 
      560              :       // Find first write pointer
      561            2 :       for (int i=0; i<DEPTH; i++) begin
-     562          332 :          if (~found_wrptr0) begin
-     563          332 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     564          332 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     565          332 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     562          266 :          if (~found_wrptr0) begin
+     563          266 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     564          266 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     565          266 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      566              :          end
      567              :       end
      568              : 
      569              :       // Find second write pointer
      570            2 :       for (int i=0; i<DEPTH; i++) begin
-     571          638 :          if (~found_wrptr1) begin
-     572          638 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     573          638 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     574          638 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
-     575          638 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     571          506 :          if (~found_wrptr1) begin
+     572          506 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     573          506 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     574          506 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
+     575          506 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      576              :          end
      577              :       end
      578              :    end
@@ -758,51 +758,51 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657       409691 :             IDLE: begin
-     658       409691 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659       409691 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660       409691 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661       409691 :                      buf_wr_en[i]    = buf_state_en[i];
-     662       409691 :                      buf_data_en[i]  = buf_state_en[i];
-     663       409691 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664       409691 :                      buf_cmd_state_bus_en[i]  = '0;
+     657       312386 :             IDLE: begin
+     658       312386 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659       312386 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660       312386 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661       312386 :                      buf_wr_en[i]    = buf_state_en[i];
+     662       312386 :                      buf_data_en[i]  = buf_state_en[i];
+     663       312386 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664       312386 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         7465 :             CMD: begin
-     672         7465 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         7465 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         7465 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         7465 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         7465 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         7465 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         7465 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         7465 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         7465 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         7465 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671         5732 :             CMD: begin
+     672         5732 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673         5732 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674         5732 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675         5732 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676         5732 :                      buf_ldfwd_in[i]          = 1'b1;
+     677         5732 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678         5732 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679         5732 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680         5732 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681         5732 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683        15582 :             RESP: begin
-     684        15582 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685        15582 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686        15582 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687        15582 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688        15582 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689        15582 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690        15582 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691        15582 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692        15582 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693        15582 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694        15582 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695        15582 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683        11910 :             RESP: begin
+     684        11910 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685        11910 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686        11910 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687        11910 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688        11910 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689        11910 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690        11910 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691        11910 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692        11910 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693        11910 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694        11910 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695        11910 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697        15582 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698        15582 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699        15582 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700        15582 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701        15582 :                      buf_cmd_state_bus_en[i]  = '0;
+     697        11910 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698        11910 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699        11910 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700        11910 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701        11910 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
      703            0 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
      704            0 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
@@ -811,18 +811,18 @@
      707            0 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
      708            0 :                      buf_cmd_state_bus_en[i]  = '0;
      709              :             end
-     710           96 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
-     711           96 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
-     712           96 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
-     713           96 :                       buf_cmd_state_bus_en[i]  = '0;
+     710           80 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
+     711           80 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
+     712           80 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
+     713           80 :                       buf_cmd_state_bus_en[i]  = '0;
      714              :             end
-     715         2490 :             DONE: begin
-     716         2490 :                      buf_nxtstate[i]           = IDLE;
-     717         2490 :                      buf_rst[i]                = 1'b1;
-     718         2490 :                      buf_state_en[i]           = 1'b1;
-     719         2490 :                      buf_ldfwd_in[i]           = 1'b0;
-     720         2490 :                      buf_ldfwd_en[i]           = buf_state_en[i];
-     721         2490 :                      buf_cmd_state_bus_en[i]  = '0;
+     715         1868 :             DONE: begin
+     716         1868 :                      buf_nxtstate[i]           = IDLE;
+     717         1868 :                      buf_rst[i]                = 1'b1;
+     718         1868 :                      buf_state_en[i]           = 1'b1;
+     719         1868 :                      buf_ldfwd_in[i]           = 1'b0;
+     720         1868 :                      buf_ldfwd_en[i]           = buf_state_en[i];
+     721         1868 :                      buf_cmd_state_bus_en[i]  = '0;
      722              :             end
      723            0 :             default : begin
      724            0 :                      buf_nxtstate[i]          = IDLE;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_intf.sv.html
index 8e0de4be406..3f38e28b29d 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30       584906 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30       359918 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -140,43 +140,43 @@
       36            0 :    input logic                          dec_tlu_sideeffect_posted_disable,  // disable the posted sideeffect load store to the bus
       37              : 
       38              :    // various clocks needed for the bus reads and writes
-      39        16968 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
-      40         9264 :    input logic                          lsu_busm_clken,                     // bus clock enable
+      39        10544 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
+      40         5628 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42       584906 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43       584906 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44       584906 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42       359918 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43       359918 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44       359918 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46       584906 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47       584906 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48       584906 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46       359918 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47       359918 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48       359918 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
-      51        11276 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
-      52        11500 :    input logic                          lsu_busreq_m,                      // bus request is in m
+      51         6928 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
+      52         7076 :    input logic                          lsu_busreq_m,                      // bus request is in m
       53              : 
-      54         2568 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
-      55         2568 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
+      54         1396 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
+      55         1396 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
       56              : 
-      57         1404 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
-      58         1404 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
+      57          432 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
+      58          432 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
       59              : 
-      60         1404 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
-      61         1404 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
+      60          432 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
+      61          432 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
       62              : 
-      63           12 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
+      63            8 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
       64            0 :    input logic                          dec_tlu_force_halt,
       65              : 
-      66        11500 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
+      66         7076 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
       67            0 :    input logic                          is_sideeffects_m,                  // lsu attribute is side_effects
-      68           64 :    input logic                          flush_m_up,                        // flush
+      68           36 :    input logic                          flush_m_up,                        // flush
       69            0 :    input logic                          flush_r,                           // flush
       70            0 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71              : 
-      72        11500 :    output logic                         lsu_busreq_r,                      // bus request is in r
-      73         5840 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      74          248 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
-      75         9830 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
+      72         7076 :    output logic                         lsu_busreq_r,                      // bus request is in r
+      73         3708 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      74          160 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
+      75         5966 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
       76            0 :    output logic [31:0]                  bus_read_data_m,                   // the bus return data
       77              : 
       78              : 
@@ -185,24 +185,24 @@
       81            2 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
       82              : 
       83              :    // Non-blocking loads
-      84         5868 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
-      85         1920 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
+      84         3496 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
+      85         1280 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
       86            0 :    output logic                               lsu_nonblock_load_inv_r,     // invalidate signal for the cam entry for non block loads
-      87         1920 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
-      88         6000 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
+      87         1280 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
+      88         3576 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
       89            0 :    output logic                               lsu_nonblock_load_data_error,// non block load has an error
-      90          120 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
-      91           12 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
+      90           76 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
+      91            8 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
       92              : 
       93              :    // PMU events
-      94        11876 :    output logic                         lsu_pmu_bus_trxn,
+      94         7308 :    output logic                         lsu_pmu_bus_trxn,
       95            0 :    output logic                         lsu_pmu_bus_misaligned,
       96            0 :    output logic                         lsu_pmu_bus_error,
-      97           56 :    output logic                         lsu_pmu_bus_busy,
+      97           32 :    output logic                         lsu_pmu_bus_busy,
       98              : 
       99              :    // AXI Write Channels
-     100         6008 :    output logic                        lsu_axi_awvalid,
-     101        11970 :    input  logic                        lsu_axi_awready,
+     100         3812 :    output logic                        lsu_axi_awvalid,
+     101         7366 :    input  logic                        lsu_axi_awready,
      102            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_awid,
      103            2 :    output logic [31:0]                 lsu_axi_awaddr,
      104            2 :    output logic [3:0]                  lsu_axi_awregion,
@@ -214,20 +214,20 @@
      110            0 :    output logic [2:0]                  lsu_axi_awprot,
      111            0 :    output logic [3:0]                  lsu_axi_awqos,
      112              : 
-     113         6008 :    output logic                        lsu_axi_wvalid,
-     114        11970 :    input  logic                        lsu_axi_wready,
-     115           44 :    output logic [63:0]                 lsu_axi_wdata,
-     116          832 :    output logic [7:0]                  lsu_axi_wstrb,
+     113         3812 :    output logic                        lsu_axi_wvalid,
+     114         7366 :    input  logic                        lsu_axi_wready,
+     115           24 :    output logic [63:0]                 lsu_axi_wdata,
+     116          508 :    output logic [7:0]                  lsu_axi_wstrb,
      117            2 :    output logic                        lsu_axi_wlast,
      118              : 
-     119         6100 :    input  logic                        lsu_axi_bvalid,
+     119         3868 :    input  logic                        lsu_axi_bvalid,
      120            2 :    output logic                        lsu_axi_bready,
      121            0 :    input  logic [1:0]                  lsu_axi_bresp,
      122            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_bid,
      123              : 
      124              :    // AXI Read Channels
-     125         5868 :    output logic                        lsu_axi_arvalid,
-     126        11878 :    input  logic                        lsu_axi_arready,
+     125         3496 :    output logic                        lsu_axi_arvalid,
+     126         7310 :    input  logic                        lsu_axi_arready,
      127            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_arid,
      128            2 :    output logic [31:0]                 lsu_axi_araddr,
      129            2 :    output logic [3:0]                  lsu_axi_arregion,
@@ -239,10 +239,10 @@
      135            0 :    output logic [2:0]                  lsu_axi_arprot,
      136            0 :    output logic [3:0]                  lsu_axi_arqos,
      137              : 
-     138         6000 :    input  logic                        lsu_axi_rvalid,
+     138         3576 :    input  logic                        lsu_axi_rvalid,
      139            2 :    output logic                        lsu_axi_rready,
      140            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_rid,
-     141          124 :    input  logic [63:0]                 lsu_axi_rdata,
+     141           80 :    input  logic [63:0]                 lsu_axi_rdata,
      142            0 :    input  logic [1:0]                  lsu_axi_rresp,
      143              : 
      144            2 :    input logic                         lsu_bus_clk_en
@@ -256,16 +256,16 @@
      152            2 :    logic [3:0]        ldst_byteen_m, ldst_byteen_r;
      153            0 :    logic [7:0]        ldst_byteen_ext_m, ldst_byteen_ext_r;
      154            0 :    logic [3:0]        ldst_byteen_hi_m, ldst_byteen_hi_r;
-     155         3622 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
+     155         2140 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
      156            0 :    logic              is_sideeffects_r;
      157              : 
-     158          212 :    logic [63:0]       store_data_ext_r;
+     158          120 :    logic [63:0]       store_data_ext_r;
      159            0 :    logic [31:0]       store_data_hi_r;
-     160           12 :    logic [31:0]       store_data_lo_r;
+     160            8 :    logic [31:0]       store_data_lo_r;
      161              : 
-     162        11858 :    logic              addr_match_dw_lo_r_m;
-     163        11430 :    logic              addr_match_word_lo_r_m;
-     164          584 :    logic              no_word_merge_r, no_dword_merge_r;
+     162         7318 :    logic              addr_match_dw_lo_r_m;
+     163         7030 :    logic              addr_match_word_lo_r_m;
+     164          376 :    logic              no_word_merge_r, no_dword_merge_r;
      165              : 
      166            0 :    logic              ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
      167            0 :    logic [3:0]        ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_clkdomain.sv.html
index 7f75fbb734b..423ad96c8f9 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31       584906 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32       584906 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31       359918 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32       359918 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -144,52 +144,52 @@
       40              : 
       41            0 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
       42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
-      43        11500 :    input logic      lsu_busreq_r,                      // busreq in r
-      44         5840 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      45         9830 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
+      43         7076 :    input logic      lsu_busreq_r,                      // busreq in r
+      44         3708 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      45         5966 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
       46            2 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
       47              : 
       48            2 :    input logic      lsu_bus_clk_en,                    // bus clock enable
       49              : 
-      50         2568 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
-      51         2568 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
-      52         2568 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
-      53         2568 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
+      50         1396 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
+      51         1396 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
+      52         1396 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
+      53         1396 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
       54              : 
       55              :    // Outputs
-      56        16968 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
-      57         9264 :    output logic     lsu_busm_clken,                    // bus clock enable
+      56        10544 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
+      57         5628 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59       584906 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60       584906 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59       359918 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60       359918 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62       584906 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63       584906 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62       359918 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63       359918 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65       584906 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66       584906 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65       359918 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66       359918 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68       584906 :    output logic     lsu_stbuf_c1_clk,
+      68       359918 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70       584906 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71       584906 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70       359918 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71       359918 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74       584906 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74       359918 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
       78              : 
-      79        11500 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
-      80        11428 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
-      81        11500 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
-      82         5664 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
+      79         7076 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
+      80         7028 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
+      81         7076 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
+      82         3596 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
       83              : 
       84              : 
       85            0 :    logic lsu_stbuf_c1_clken;
-      86         9264 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
+      86         5628 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
       87              : 
-      88         8848 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
+      88         5404 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
       89              : 
       90              :    //-------------------------------------------------------------------------------------------
       91              :    // Clock Enable logic
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_ctl.sv.html
index eb7d1a3bd30..51a7ba9d21c 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,37 +136,37 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35       584906 :    input logic                             lsu_c2_m_clk,            // clocks
-      36       584906 :    input logic                             lsu_c2_r_clk,            // clocks
-      37       584906 :    input logic                             lsu_c1_r_clk,            // clocks
-      38       584906 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39       584906 :    input logic                             lsu_free_c2_clk,         // clocks
+      35       359918 :    input logic                             lsu_c2_m_clk,            // clocks
+      36       359918 :    input logic                             lsu_c2_r_clk,            // clocks
+      37       359918 :    input logic                             lsu_c1_r_clk,            // clocks
+      38       359918 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39       359918 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41       584906 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41       359918 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
-      45         2568 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
-      46         2568 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
-      47         2568 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
+      45         1396 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
+      46         1396 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
+      47         1396 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
       48            0 :    input logic                             addr_in_dccm_d,          // address maps to dccm
       49            0 :    input logic                             addr_in_pic_d,           // address maps to pic
       50            0 :    input logic                             addr_in_pic_m,           // address maps to pic
       51            0 :    input logic                             addr_in_dccm_m, addr_in_dccm_r,   // address in dccm per pipe stage
       52            0 :    input logic                             addr_in_pic_r,                    // address in pic  per pipe stage
       53            0 :    input logic                             lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
-      54        11500 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
+      54         7076 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
       55            0 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
       56              : 
       57              :    // lsu address down the pipe
-      58         1404 :    input logic [31:0]                      lsu_addr_d,
-      59         1404 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
-      60         1404 :    input logic [31:0]                      lsu_addr_r,
+      58          432 :    input logic [31:0]                      lsu_addr_d,
+      59          432 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
+      60          432 :    input logic [31:0]                      lsu_addr_r,
       61              : 
       62              :    // lsu address down the pipe - needed to check unaligned
-      63         1404 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
-      64         1404 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
-      65         1404 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
+      63          432 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
+      64          432 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
+      65          432 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
       66              : 
       67              : 
       68            0 :    input logic                             stbuf_reqvld_any,        // write enable
@@ -206,7 +206,7 @@
      102            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_hi_m,           // corrected dccm data
      103            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_lo_m,           // corrected dccm data
      104              : 
-     105           12 :    input logic [31:0]                      store_data_m,            // Store data M-stage
+     105            8 :    input logic [31:0]                      store_data_m,            // Store data M-stage
      106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
      107            0 :    input logic                             dma_pic_wen,             // Perform PIC writes
      108            0 :    input logic [2:0]                       dma_mem_tag_m,           // DMA Buffer entry number M-stage
@@ -218,10 +218,10 @@
      114            0 :    input logic [pt.DCCM_ECC_WIDTH-1:0]     dma_dccm_wdata_ecc_lo,   // ECC bits for the DMA wdata
      115              : 
      116            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_hi_r,
-     117           12 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
+     117            8 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
      118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
-     119           12 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
-     120           12 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
+     119            8 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
+     120            8 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
      121            0 :    output logic                            ld_single_ecc_error_r,
      122            0 :    output logic                            ld_single_ecc_error_r_ff,
      123              : 
@@ -240,8 +240,8 @@
      136            0 :    output logic                            dccm_rden,               // dccm interface -- write
      137            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo,         // dccm interface -- wr addr for lo bank
      138            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi,         // dccm interface -- wr addr for hi bank
-     139         1404 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
-     140         1404 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
+     139          432 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
+     140          432 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
      141            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,         // dccm write data for lo bank
      142            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,         // dccm write data for hi bank
      143              : 
@@ -254,7 +254,7 @@
      150            0 :    output logic                            picm_mken,               // write to pic need a mask
      151            2 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
      152            2 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
-     153           12 :    output logic [31:0]                     picm_wr_data,            // write data
+     153            8 :    output logic [31:0]                     picm_wr_data,            // write data
      154            0 :    input logic [31:0]                      picm_rd_data,            // read data
      155              : 
      156            0 :    input logic                             scan_mode                // scan mode
@@ -277,7 +277,7 @@
      173            0 :    logic                           kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
      174              : 
      175              :     // byte_en flowing down
-     176         1152 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
+     176          684 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
      177            0 :    logic [7:0]                     store_byteen_ext_m, store_byteen_ext_r;
      178              : 
      179              :    if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_mem.sv.html
index 9c2900f5287..c3c2bab4393 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35       584906 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36       584906 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35       359918 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36       359918 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
@@ -145,8 +145,8 @@
       41            0 :    input logic         dccm_rden,                                       // read enable
       42            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,                     // write address
       43            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,                     // write address
-      44         1404 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
-      45         1404 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
+      44          432 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
+      45          432 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
       46            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,              // write data
       47            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,              // write data
       48              :    el2_mem_if.veer_dccm                   dccm_mem_export,              // RAM repositioned in testbench and connected by this interface
@@ -164,7 +164,7 @@
       60              : 
       61            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        wren_bank;
       62            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        rden_bank;
-      63         1404 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
+      63          432 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
       64            0 :    logic [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+DCCM_WIDTH_BITS)]           rd_addr_even, rd_addr_odd;
       65            0 :    logic                                                                rd_unaligned, wr_unaligned;
       66            0 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0]              dccm_bank_dout;
@@ -172,8 +172,8 @@
       68              : 
       69            0 :    logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0]               wr_data_bank;
       70              : 
-      71         4540 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
-      72         4540 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
+      71         2692 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
+      72         2692 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
       73              : 
       74            0 :    logic [pt.DCCM_NUM_BANKS-1:0]            dccm_clken;
       75              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_ecc.sv.html
index c28f2be9156..bd257557c8e 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,22 +135,22 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34       584906 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35       584906 :    input logic                           lsu_c2_r_clk,       // clock
+      34       359918 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35       359918 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
       39              : 
-      40         2568 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
-      41         2568 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
+      40         1396 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
+      41         1396 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
       42            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  stbuf_data_any,
       43              : 
       44            0 :    input logic                           dec_tlu_core_ecc_disable,  // disables the ecc computation and error flagging
       45              : 
       46            0 :    input logic                           lsu_dccm_rden_r,          // dccm rden
       47            0 :    input logic                           addr_in_dccm_r,           // address in dccm
-      48         1404 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
-      49         1404 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
+      48          432 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
+      49          432 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
       50            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r,          // data from the dccm
       51            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r,          // data from the dccm
       52            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_r,       // data from the dccm + ecc
@@ -164,8 +164,8 @@
       60            0 :    input logic                           ld_single_ecc_error_r_ff,  // ld has a single ecc error
       61            0 :    input logic                           lsu_dccm_rden_m,           // dccm rden
       62            0 :    input logic                           addr_in_dccm_m,            // address in dccm
-      63         1404 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
-      64         1404 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
+      63          432 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
+      64          432 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
       65            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m,           // raw data from mem
       66            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m,           // raw data from mem
       67            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_m,        // ecc read out from mem
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_lsc_ctl.sv.html
index 17034ee7c71..71c7501209f 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_lsc_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        45.9%
+    
+        43.5%
     
     
-        39
+        37
     
     
         85
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35       584906 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35       359918 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38       584906 :    input logic                lsu_c1_m_clk,
-      39       584906 :    input logic                lsu_c1_r_clk,
-      40       584906 :    input logic                lsu_c2_m_clk,
-      41       584906 :    input logic                lsu_c2_r_clk,
-      42       584906 :    input logic                lsu_store_c1_m_clk,
+      38       359918 :    input logic                lsu_c1_m_clk,
+      39       359918 :    input logic                lsu_c1_r_clk,
+      40       359918 :    input logic                lsu_c2_m_clk,
+      41       359918 :    input logic                lsu_c2_r_clk,
+      42       359918 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
@@ -154,38 +154,38 @@
       50            0 :    input logic                lsu_single_ecc_error_m,    // ECC single bit error M-stage
       51            0 :    input logic                lsu_double_ecc_error_m,    // ECC double bit error M-stage
       52              : 
-      53           64 :    input logic                flush_m_up,                // Flush M and D stage
+      53           36 :    input logic                flush_m_up,                // Flush M and D stage
       54            0 :    input logic                flush_r,                   // Flush R-stage
       55            0 :    input logic                ldst_dual_d,               // load/store is unaligned at 32 bit boundary D-stage
       56            0 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
       57            0 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
       58              : 
-      59         1284 :    input logic [31:0]         exu_lsu_rs1_d,             // address
-      60           12 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
+      59          300 :    input logic [31:0]         exu_lsu_rs1_d,             // address
+      60            8 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
       61              : 
-      62         2568 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
-      63        11276 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
-      64          684 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
+      62         1396 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
+      63         6928 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
+      64          420 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
       65              : 
       66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
       67            0 :    input  logic [31:0]        bus_read_data_m,           // the bus return data
       68            0 :    output logic [31:0]        lsu_result_m,              // lsu load data
       69            0 :    output logic [31:0]        lsu_result_corr_r,         // This is the ECC corrected data going to RF
       70              :    // lsu address down the pipe
-      71         1404 :    output logic [31:0]        lsu_addr_d,
-      72         1404 :    output logic [31:0]        lsu_addr_m,
-      73         1404 :    output logic [31:0]        lsu_addr_r,
+      71          432 :    output logic [31:0]        lsu_addr_d,
+      72          432 :    output logic [31:0]        lsu_addr_m,
+      73          432 :    output logic [31:0]        lsu_addr_r,
       74              :    // lsu address down the pipe - needed to check unaligned
-      75         1404 :    output logic [31:0]        end_addr_d,
-      76         1404 :    output logic [31:0]        end_addr_m,
-      77         1404 :    output logic [31:0]        end_addr_r,
+      75          432 :    output logic [31:0]        end_addr_d,
+      76          432 :    output logic [31:0]        end_addr_m,
+      77          432 :    output logic [31:0]        end_addr_r,
       78              :    // store data down the pipe
-      79           12 :    output logic [31:0]        store_data_m,
+      79            8 :    output logic [31:0]        store_data_m,
       80              : 
       81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
       82            0 :    output logic                lsu_exc_m,                // Access or misaligned fault
       83            0 :    output logic                is_sideeffects_m,         // is sideffects space
-      84        11500 :    output logic                lsu_commit_r,             // lsu instruction in r commits
+      84         7076 :    output logic                lsu_commit_r,             // lsu instruction in r commits
       85            0 :    output logic                lsu_single_ecc_error_incr,// LSU inc SB error counter
       86            0 :    output el2_lsu_error_pkt_t lsu_error_pkt_r,          // lsu exception packet
       87              : 
@@ -211,25 +211,25 @@
      107            0 :    input logic [63:0]         dma_mem_wdata,
      108              : 
      109              :    // Store buffer related signals
-     110         2568 :    output el2_lsu_pkt_t      lsu_pkt_d,
-     111         2568 :    output el2_lsu_pkt_t      lsu_pkt_m,
-     112         2568 :    output el2_lsu_pkt_t      lsu_pkt_r,
+     110         1396 :    output el2_lsu_pkt_t      lsu_pkt_d,
+     111         1396 :    output el2_lsu_pkt_t      lsu_pkt_m,
+     112         1396 :    output el2_lsu_pkt_t      lsu_pkt_r,
      113              : 
-     114         4414 :     input logic lsu_pmp_error_start,
-     115         4414 :     input logic lsu_pmp_error_end,
+     114            0 :     input logic lsu_pmp_error_start,
+     115            0 :     input logic lsu_pmp_error_end,
      116              : 
-     117            0 :    input  logic               scan_mode                  // Scan mode
+     117            0 :    input  logic               scan_mode                  // Scan mode
      118              : 
      119              :    );
      120              : 
      121            0 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
-     122         1404 :    logic [31:0]        full_addr_d;
-     123         1404 :    logic [31:0]        full_end_addr_d;
-     124         1284 :    logic [31:0]        lsu_rs1_d;
-     125          684 :    logic [11:0]        lsu_offset_d;
-     126         1284 :    logic [31:0]        rs1_d;
-     127          684 :    logic [11:0]        offset_d;
-     128          684 :    logic [12:0]        end_addr_offset_d;
+     122          432 :    logic [31:0]        full_addr_d;
+     123          432 :    logic [31:0]        full_end_addr_d;
+     124          300 :    logic [31:0]        lsu_rs1_d;
+     125          420 :    logic [11:0]        lsu_offset_d;
+     126          300 :    logic [31:0]        rs1_d;
+     127          420 :    logic [11:0]        offset_d;
+     128          420 :    logic [12:0]        end_addr_offset_d;
      129            0 :    logic [2:0]         addr_offset_d;
      130              : 
      131            0 :    logic [63:0]        dma_mem_wdata_shifted;
@@ -242,12 +242,12 @@
      138            0 :    logic               fir_dccm_access_error_m, fir_nondccm_access_error_m;
      139              : 
      140            0 :    logic [3:0]         exc_mscause_d, exc_mscause_m;
-     141         1284 :    logic [31:0]        rs1_d_raw;
-     142           12 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
+     141          300 :    logic [31:0]        rs1_d_raw;
+     142            8 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
      143            0 :    logic [31:0]        bus_read_data_r;
      144              : 
      145            0 :    el2_lsu_pkt_t           dma_pkt_d;
-     146         2568 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
+     146         1396 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
      147            0 :    el2_lsu_error_pkt_t     lsu_error_pkt_m;
      148              : 
      149              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_stbuf.sv.html
index 7745f4aa04b..b11a0af54fe 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,20 +137,20 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36       584906 :    input logic                           clk,                         // core clock
+      36       359918 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39       584906 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40       584906 :    input logic                           lsu_free_c2_clk,             // free clk
+      39       359918 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40       359918 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
-      44        11500 :    input logic                           lsu_commit_r,                // lsu commits
-      45        11276 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
+      44         7076 :    input logic                           lsu_commit_r,                // lsu commits
+      45         6928 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
       46            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_hi_r,             // merged data from the dccm for stores. This is used for fwding
-      47           12 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
+      47            8 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
       48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
-      49           12 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
+      49            8 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
       50              : 
       51              :    // Store Buffer output
       52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
@@ -163,13 +163,13 @@
       59            2 :    output logic                          lsu_stbuf_empty_any,         // stbuf is empty
       60            0 :    output logic                          ldst_stbuf_reqvld_r,         // needed for clocking
       61              : 
-      62         1404 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
-      63         1404 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
-      64         1404 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
+      62          432 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
+      63          432 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
+      64          432 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
       65              : 
-      66         1404 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
-      67         1404 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
-      68         1404 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
+      66          432 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
+      67          432 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
+      68          432 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
       69              : 
       70            0 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71            0 :    input logic                           addr_in_dccm_m,              // address is in dccm
@@ -177,8 +177,8 @@
       73              : 
       74              :    // Forwarding signals
       75            0 :    input logic                           lsu_cmpen_m,                 // needed for forwarding stbuf - load
-      76         2568 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
-      77         2568 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
+      76         1396 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
+      77         1396 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
       78              : 
       79            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m,          // stbuf data
       80            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m,          // stbuf data
@@ -206,13 +206,13 @@
      102            0 :    logic [DEPTH-1:0]                     stbuf_wr_en;
      103            0 :    logic [DEPTH-1:0]                     stbuf_dma_kill_en;
      104            0 :    logic [DEPTH-1:0]                     stbuf_reset;
-     105         1404 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
+     105          432 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
      106            0 :    logic [DEPTH-1:0][DATA_WIDTH-1:0]     stbuf_datain;
      107            0 :    logic [DEPTH-1:0][BYTE_WIDTH-1:0]     stbuf_byteenin;
      108              : 
      109            0 :    logic [7:0]             store_byteen_ext_r;
      110            0 :    logic [BYTE_WIDTH-1:0]  store_byteen_hi_r;
-     111         1304 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
+     111          780 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
      112              : 
      113            0 :    logic                   WrPtrEn, RdPtrEn;
      114            0 :    logic [DEPTH_LOG2-1:0]  WrPtr, RdPtr;
@@ -225,7 +225,7 @@
      121            0 :    logic [3:0]             stbuf_numvld_any, stbuf_specvld_any;
      122            0 :    logic [1:0]             stbuf_specvld_m, stbuf_specvld_r;
      123              : 
-     124         1404 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
+     124          432 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
      125              : 
      126              :    // variables to detect matching from the store queue
      127            0 :    logic [DEPTH-1:0]                 stbuf_match_hi, stbuf_match_lo;
@@ -241,7 +241,7 @@
      137            0 :    logic [BYTE_WIDTH-1:0]  ld_byte_hit_hi, ld_byte_rhit_hi;
      138              : 
      139            0 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_hi_r;
-     140         3622 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
+     140         2140 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
      141              :    // byte_en flowing down
      142            0 :    logic [7:0]             ldst_byteen_r;
      143            0 :    logic [7:0]             ldst_byteen_ext_r;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_trigger.sv.html
index ed45a1d179b..b6a9a80643f 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,9 +132,9 @@
       28              : `include "el2_param.vh"
       29              :  )(
       30            0 :    input el2_trigger_pkt_t [3:0] trigger_pkt_any,            // trigger packet from dec
-      31         2568 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
-      32         1404 :    input logic [31:0]             lsu_addr_m,                 // address
-      33           12 :    input logic [31:0]             store_data_m,               // store data
+      31         1396 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
+      32          432 :    input logic [31:0]             lsu_addr_m,                 // address
+      33            8 :    input logic [31:0]             store_data_m,               // store data
       34              : 
       35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
       36              : );
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem.sv.html
index 7d73b936def..e5bf11c9fce 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25       584906 :    input logic         clk,
+      25       359918 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -137,8 +137,8 @@
       33            0 :    input logic         dccm_rden,
       34            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,
       35            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,
-      36         1404 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
-      37         1404 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
+      36          432 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
+      37          432 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
       38            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
       39            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
       40              : 
@@ -147,16 +147,16 @@
       43            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
       44              : 
       45              :    //ICCM ports
-      46          212 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
+      46          136 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
       47            0 :    input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
       48            0 :    input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
       49            0 :    input logic         iccm_wren,
-      50          256 :    input logic         iccm_rden,
+      50          172 :    input logic         iccm_rden,
       51            0 :    input logic [2:0]   iccm_wr_size,
       52            0 :    input logic [77:0]  iccm_wr_data,
       53              : 
-      54           12 :    output logic [63:0] iccm_rd_data,
-      55           12 :    output logic [77:0] iccm_rd_data_ecc,
+      54            8 :    output logic [63:0] iccm_rd_data,
+      55            8 :    output logic [77:0] iccm_rd_data_ecc,
       56              : 
       57              :    // Icache and Itag Ports
       58              : 
@@ -164,12 +164,12 @@
       60            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
       61            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
       62            0 :    input  logic         ic_rd_en,
-      63         7276 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-      64        30354 :    input  logic         ic_sel_premux_data, // Premux data sel
+      63         4604 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+      64        18614 :    input  logic         ic_sel_premux_data, // Premux data sel
       65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
       66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
       67              : 
-      68         2012 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+      68         1172 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
       69            0 :    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
       70            0 :    output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       71            0 :    input  logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -178,7 +178,7 @@
       74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
       75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
       76              : 
-      77         7276 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      77         4604 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
       79              : 
       80              : 
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92       584906 :    logic active_clk;
+      92       359918 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem_if.sv.html
index 3464bb29748..80089d30c8c 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,26 +130,26 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29       808008 :   logic                                                               clk;
+      29       497964 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
       33              :   // ICCM
-      34          360 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
+      34          240 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
       35            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_wren_bank;
-      36          636 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
+      36          408 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
       37              : 
       38            0 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_wr_data;
       39            0 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
-      40           36 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_dout;
-      41           36 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;
+      40           24 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_dout;
+      41           24 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;
       42              : 
       43              : 
       44              :   //////////////////////////////////////////
       45              :   // DCCM
       46            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_clken;
       47            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
-      48         4212 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
+      48         1296 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
       49            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
       50            0 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
       51            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_pic_ctrl.sv.html
index 59a78026afd..9d8fa9a8f27 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,15 +131,15 @@
       27              :  )
       28              :                   (
       29              : 
-      30       584906 :                      input  logic                   clk,                  // Core clock
-      31       584906 :                      input  logic                   free_clk,             // free clock
+      30       359918 :                      input  logic                   clk,                  // Core clock
+      31       359918 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
       35            0 :                      input  logic [pt.PIC_TOTAL_INT_PLUS1-1:0]   extintsrc_req,  // Interrupt requests
       36            2 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
       37            2 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
-      38           12 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
+      38            8 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
       39            0 :                      input  logic                   picm_wren,            // Write enable to the register
       40            0 :                      input  logic                   picm_rden,            // Read enable for the register
       41            0 :                      input  logic                   picm_mken,            // Read the Mask for the register
@@ -185,11 +185,11 @@
       81              : 
       82            0 : logic  raddr_config_pic_match ;
       83            0 : logic  raddr_intenable_base_match;
-      84         7514 : logic  raddr_intpriority_base_match;
+      84         4482 : logic  raddr_intpriority_base_match;
       85            0 : logic  raddr_config_gw_base_match ;
       86              : 
       87            0 : logic  waddr_config_pic_match ;
-      88         7514 : logic  waddr_intpriority_base_match;
+      88         4482 : logic  waddr_intpriority_base_match;
       89            0 : logic  waddr_intenable_base_match;
       90            0 : logic  waddr_config_gw_base_match ;
       91            0 : logic  addr_clear_gw_base_match ;
@@ -228,7 +228,7 @@
      124            0 : logic                                        intpriord;
      125            0 : logic                                        config_reg_we ;
      126            0 : logic                                        config_reg_re ;
-     127         2052 : logic                                        config_reg_in ;
+     127         1340 : logic                                        config_reg_in ;
      128            0 : logic                                        prithresh_reg_write , prithresh_reg_read;
      129            0 : logic                                        intpriority_reg_read ;
      130            0 : logic                                        intenable_reg_read   ;
@@ -236,7 +236,7 @@
      132            0 : logic                                        picm_wren_ff , picm_rden_ff ;
      133            2 : logic [31:0]                                 picm_raddr_ff;
      134            2 : logic [31:0]                                 picm_waddr_ff;
-     135           12 : logic [31:0]                                 picm_wr_data_ff;
+     135            8 : logic [31:0]                                 picm_wr_data_ff;
      136            0 : logic [3:0]                                  mask;
      137            0 : logic                                        picm_mken_ff;
      138            0 : logic [ID_BITS-1:0]                          claimid_in ;
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155       584906 :    logic                                     pic_raddr_c1_clk;
-     156       584906 :    logic                                     pic_data_c1_clk;
-     157       584906 :    logic                                     pic_pri_c1_clk;
-     158       584906 :    logic                                     pic_int_c1_clk;
-     159       584906 :    logic                                     gw_config_c1_clk;
+     155       359918 :    logic                                     pic_raddr_c1_clk;
+     156       359918 :    logic                                     pic_data_c1_clk;
+     157       359918 :    logic                                     pic_pri_c1_clk;
+     158       359918 :    logic                                     pic_int_c1_clk;
+     159       359918 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500      3482592 :               if (intenable_reg_re[i]) begin
+     500      2655808 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503      3482592 :               if (intpriority_reg_re[i]) begin
+     503      2655808 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506      3482592 :               if (gw_config_reg_re[i]) begin
+     506      2655808 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -627,7 +627,7 @@
      523              : 
      524              : assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0] ;
      525              : 
-     526         1404 : logic [14:0] address;
+     526          432 : logic [14:0] address;
      527              : 
      528              : assign address[14:0] = picm_raddr_ff[14:0];
      529              : 
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562      8349416 :                              input logic rawclk,
+     562      5145628 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_pmp.sv.html
index cae95aede57..bc452edd93e 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        60.0%
+    
+        50.0%
     
     
-        12
+        7
     
     
-        20
+        14
     
 
             
@@ -127,29 +127,29 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26       584906 :     input logic clk,       // Top level clock
+      26       359918 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35           14 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36           14 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36              :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
-      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
+      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
       40              :     input logic             [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],
       41              : 
-      42         1404 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
+      42          432 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
       43            0 :     input  el2_pmp_type_pkt_t        pmp_chan_type[PMP_CHANNELS],
-      44         4414 :     output logic                     pmp_chan_err [PMP_CHANNELS]
+      44            0 :     output logic                     pmp_chan_err [PMP_CHANNELS]
       45              : );
       46              : 
       47              :   logic [                33:0]                     csr_pmp_addr_i          [pt.PMP_ENTRIES];
-      48         1404 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
+      48          432 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
       49              : 
       50              :   logic [                33:0]                     region_start_addr       [pt.PMP_ENTRIES];
       51              :   logic [33:PMP_GRANULARITY+2]                     region_addr_mask        [pt.PMP_ENTRIES];
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60            2 :   logic any_region_enabled;
+      60              :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133      6594576 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133      5022048 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139      6594576 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139      5022048 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            3 :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       427197 :       if (!matched && match_all[r]) begin
-     170       427197 :         access_fail = ~final_perm_check[r];
-     171       427197 :         matched = 1'b1;
+     169       325290 :       if (!matched && match_all[r]) begin
+     170       325290 :         access_fail = ~final_perm_check[r];
+     171       325290 :         matched = 1'b1;
      172              :       end
      173              :     end
      174            6 :     return access_fail;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223           14 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -348,12 +348,12 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247      4897851 :           OFF:     region_match_all[c][r] = 1'b0;
+     247      3735186 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250       326037 :           TOR: begin
-     251       326037 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252       326037 :                                      region_match_lt[c][r];
+     250       248526 :           TOR: begin
+     251       248526 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252       248526 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer.sv.html
index 8744724fd91..c0b4fd0b35a 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        36.3%
+    
+        35.4%
     
     
-        229
+        222
     
     
-        631
+        627
     
 
             
@@ -130,23 +130,23 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29       584906 :    input logic                  clk,
+      29       359918 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
-      33           12 :    input logic                  nmi_int,
+      33            8 :    input logic                  nmi_int,
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37       584906 :    output logic                 active_l2clk,
-      38       584906 :    output logic                 free_l2clk,
+      37       359918 :    output logic                 active_l2clk,
+      38       359918 :    output logic                 free_l2clk,
       39              : 
-      40         4348 :    output logic [31:0] trace_rv_i_insn_ip,
+      40         2724 :    output logic [31:0] trace_rv_i_insn_ip,
       41            2 :    output logic [31:0] trace_rv_i_address_ip,
-      42        36388 :    output logic   trace_rv_i_valid_ip,
-      43           28 :    output logic   trace_rv_i_exception_ip,
+      42        22364 :    output logic   trace_rv_i_valid_ip,
+      43           16 :    output logic   trace_rv_i_exception_ip,
       44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
-      45           28 :    output logic   trace_rv_i_interrupt_ip,
+      45           16 :    output logic   trace_rv_i_interrupt_ip,
       46            0 :    output logic [31:0] trace_rv_i_tval_ip,
       47              : 
       48              : 
@@ -182,8 +182,8 @@
       78            0 :    output logic                          dccm_rden,
       79            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_lo,
       80            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_hi,
-      81         1404 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
-      82         1404 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
+      81          432 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
+      82          432 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
       83            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
       84            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_hi,
       85              : 
@@ -191,16 +191,16 @@
       87            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_hi,
       88              : 
       89              :    // ICCM ports
-      90          212 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
+      90          136 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
       91            0 :    output logic                  iccm_wren,
-      92          256 :    output logic                  iccm_rden,
+      92          172 :    output logic                  iccm_rden,
       93            0 :    output logic [2:0]            iccm_wr_size,
       94            0 :    output logic [77:0]           iccm_wr_data,
       95            0 :    output logic                  iccm_buf_correct_ecc,
       96            0 :    output logic                  iccm_correction_state,
       97              : 
-      98           12 :    input  logic [63:0]          iccm_rd_data,
-      99           12 :    input  logic [77:0]           iccm_rd_data_ecc,
+      98            8 :    input  logic [63:0]          iccm_rd_data,
+      99            8 :    input  logic [77:0]           iccm_rd_data_ecc,
      100              : 
      101              :    // ICache , ITAG  ports
      102            2 :    output logic [31:1]           ic_rw_addr,
@@ -208,16 +208,16 @@
      104            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_wr_en,
      105            0 :    output logic                  ic_rd_en,
      106              : 
-     107         2012 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     108         7276 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     107         1172 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     108         4604 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      109            0 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      112              : 
      113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
      114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     115         7276 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     116        30354 :    output logic                      ic_sel_premux_data, // Select premux data
+     115         4604 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     116        18614 :    output logic                      ic_sel_premux_data, // Select premux data
      117              : 
      118              : 
      119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -233,7 +233,7 @@
      129              : 
      130              :    //-------------------------- LSU AXI signals--------------------------
      131              :    // AXI Write Channels
-     132         6008 :    output logic                            lsu_axi_awvalid,
+     132         3812 :    output logic                            lsu_axi_awvalid,
      133            0 :    input  logic                            lsu_axi_awready,
      134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      135            2 :    output logic [31:0]                     lsu_axi_awaddr,
@@ -246,10 +246,10 @@
      142            0 :    output logic [2:0]                      lsu_axi_awprot,
      143            0 :    output logic [3:0]                      lsu_axi_awqos,
      144              : 
-     145         6008 :    output logic                            lsu_axi_wvalid,
+     145         3812 :    output logic                            lsu_axi_wvalid,
      146            0 :    input  logic                            lsu_axi_wready,
-     147           44 :    output logic [63:0]                     lsu_axi_wdata,
-     148          832 :    output logic [7:0]                      lsu_axi_wstrb,
+     147           24 :    output logic [63:0]                     lsu_axi_wdata,
+     148          508 :    output logic [7:0]                      lsu_axi_wstrb,
      149            2 :    output logic                            lsu_axi_wlast,
      150              : 
      151            0 :    input  logic                            lsu_axi_bvalid,
@@ -258,7 +258,7 @@
      154            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      155              : 
      156              :    // AXI Read Channels
-     157         5868 :    output logic                            lsu_axi_arvalid,
+     157         3496 :    output logic                            lsu_axi_arvalid,
      158            0 :    input  logic                            lsu_axi_arready,
      159            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      160            2 :    output logic [31:0]                     lsu_axi_araddr,
@@ -305,10 +305,10 @@
      201            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      202              : 
      203              :    // AXI Read Channels
-     204        36322 :    output logic                            ifu_axi_arvalid,
+     204        22382 :    output logic                            ifu_axi_arvalid,
      205            0 :    input  logic                            ifu_axi_arready,
-     206        27564 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-     207         9128 :    output logic [31:0]                     ifu_axi_araddr,
+     206        16956 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     207         5732 :    output logic [31:0]                     ifu_axi_araddr,
      208            2 :    output logic [3:0]                      ifu_axi_arregion,
      209            0 :    output logic [7:0]                      ifu_axi_arlen,
      210            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -419,10 +419,10 @@
      315            0 :    output logic                  hmastlock,
      316            0 :    output logic [3:0]            hprot,
      317            0 :    output logic [2:0]            hsize,
-     318        36322 :    output logic [1:0]            htrans,
+     318        22382 :    output logic [1:0]            htrans,
      319            0 :    output logic                  hwrite,
      320              : 
-     321         3996 :    input  logic [63:0]           hrdata,
+     321         2524 :    input  logic [63:0]           hrdata,
      322            2 :    input  logic                  hready,
      323            0 :    input  logic                  hresp,
      324              : 
@@ -432,11 +432,11 @@
      328            0 :    output logic                 lsu_hmastlock,
      329            0 :    output logic [3:0]           lsu_hprot,
      330            0 :    output logic [2:0]           lsu_hsize,
-     331        11968 :    output logic [1:0]           lsu_htrans,
-     332         3870 :    output logic                 lsu_hwrite,
-     333          418 :    output logic [63:0]          lsu_hwdata,
+     331         7364 :    output logic [1:0]           lsu_htrans,
+     332         2446 :    output logic                 lsu_hwrite,
+     333          258 :    output logic [63:0]          lsu_hwdata,
      334              : 
-     335          124 :    input  logic [63:0]          lsu_hrdata,
+     335           80 :    input  logic [63:0]          lsu_hrdata,
      336            2 :    input  logic                 lsu_hready,
      337            0 :    input  logic                 lsu_hresp,
      338              : 
@@ -488,20 +488,20 @@
      384            0 :    output logic                 dccm_ecc_double_error,
      385              : 
      386            0 :    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
-     387           12 :    input logic                   timer_int,
-     388           12 :    input logic                   soft_int,
+     387            8 :    input logic                   timer_int,
+     388            8 :    input logic                   soft_int,
      389            0 :    input logic                   scan_mode
      390              : );
      391              : 
      392              : 
      393              : 
      394              : 
-     395         3858 :    logic [63:0]                  hwdata_nc;
+     395         2328 :    logic [63:0]                  hwdata_nc;
      396              :    //----------------------------------------------------------------------
      397              :    //
      398              :    //----------------------------------------------------------------------
      399              : 
-     400        36372 :    logic                         ifu_pmu_instr_aligned;
+     400        22352 :    logic                         ifu_pmu_instr_aligned;
      401            0 :    logic                         ifu_ic_error_start;
      402            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
      403            0 :    logic                         ifu_iccm_rd_ecc_single_err;
@@ -509,55 +509,55 @@
      405            0 :    logic                         lsu_dccm_rd_ecc_single_err;
      406            0 :    logic                         lsu_dccm_rd_ecc_double_err;
      407              : 
-     408        11970 :    logic                         lsu_axi_awready_ahb;
-     409        11970 :    logic                         lsu_axi_wready_ahb;
-     410         6100 :    logic                         lsu_axi_bvalid_ahb;
+     408         7366 :    logic                         lsu_axi_awready_ahb;
+     409         7366 :    logic                         lsu_axi_wready_ahb;
+     410         3868 :    logic                         lsu_axi_bvalid_ahb;
      411            0 :    logic                         lsu_axi_bready_ahb;
      412            0 :    logic [1:0]                   lsu_axi_bresp_ahb;
      413            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
-     414        11878 :    logic                         lsu_axi_arready_ahb;
-     415         6000 :    logic                         lsu_axi_rvalid_ahb;
+     414         7310 :    logic                         lsu_axi_arready_ahb;
+     415         3576 :    logic                         lsu_axi_rvalid_ahb;
      416            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
-     417          124 :    logic [63:0]                  lsu_axi_rdata_ahb;
+     417           80 :    logic [63:0]                  lsu_axi_rdata_ahb;
      418            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
      419            2 :    logic                         lsu_axi_rlast_ahb;
      420              : 
-     421        11970 :    logic                         lsu_axi_awready_int;
-     422        11970 :    logic                         lsu_axi_wready_int;
-     423         6100 :    logic                         lsu_axi_bvalid_int;
+     421         7366 :    logic                         lsu_axi_awready_int;
+     422         7366 :    logic                         lsu_axi_wready_int;
+     423         3868 :    logic                         lsu_axi_bvalid_int;
      424            0 :    logic                         lsu_axi_bready_int;
      425            0 :    logic [1:0]                   lsu_axi_bresp_int;
      426            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
-     427        11878 :    logic                         lsu_axi_arready_int;
-     428         6000 :    logic                         lsu_axi_rvalid_int;
+     427         7310 :    logic                         lsu_axi_arready_int;
+     428         3576 :    logic                         lsu_axi_rvalid_int;
      429            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
-     430          124 :    logic [63:0]                  lsu_axi_rdata_int;
+     430           80 :    logic [63:0]                  lsu_axi_rdata_int;
      431            0 :    logic [1:0]                   lsu_axi_rresp_int;
      432            2 :    logic                         lsu_axi_rlast_int;
      433              : 
-     434        36322 :    logic                         ifu_axi_awready_ahb;
-     435        36322 :    logic                         ifu_axi_wready_ahb;
+     434        22382 :    logic                         ifu_axi_awready_ahb;
+     435        22382 :    logic                         ifu_axi_wready_ahb;
      436            0 :    logic                         ifu_axi_bvalid_ahb;
      437            0 :    logic                         ifu_axi_bready_ahb;
      438            0 :    logic [1:0]                   ifu_axi_bresp_ahb;
-     439        10872 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
-     440        36322 :    logic                         ifu_axi_arready_ahb;
-     441        72640 :    logic                         ifu_axi_rvalid_ahb;
-     442        10872 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
-     443         3994 :    logic [63:0]                  ifu_axi_rdata_ahb;
+     439         6856 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
+     440        22382 :    logic                         ifu_axi_arready_ahb;
+     441        44760 :    logic                         ifu_axi_rvalid_ahb;
+     442         6856 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
+     443         2522 :    logic [63:0]                  ifu_axi_rdata_ahb;
      444            0 :    logic [1:0]                   ifu_axi_rresp_ahb;
      445            2 :    logic                         ifu_axi_rlast_ahb;
      446              : 
-     447        36322 :    logic                         ifu_axi_awready_int;
-     448        36322 :    logic                         ifu_axi_wready_int;
+     447        22382 :    logic                         ifu_axi_awready_int;
+     448        22382 :    logic                         ifu_axi_wready_int;
      449            0 :    logic                         ifu_axi_bvalid_int;
      450            0 :    logic                         ifu_axi_bready_int;
      451            0 :    logic [1:0]                   ifu_axi_bresp_int;
-     452        10872 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
-     453        36322 :    logic                         ifu_axi_arready_int;
-     454        72640 :    logic                         ifu_axi_rvalid_int;
-     455        10872 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
-     456         3994 :    logic [63:0]                  ifu_axi_rdata_int;
+     452         6856 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
+     453        22382 :    logic                         ifu_axi_arready_int;
+     454        44760 :    logic                         ifu_axi_rvalid_int;
+     455         6856 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
+     456         2522 :    logic [63:0]                  ifu_axi_rdata_int;
      457            0 :    logic [1:0]                   ifu_axi_rresp_int;
      458            2 :    logic                         ifu_axi_rlast_int;
      459              : 
@@ -636,13 +636,13 @@
      532            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
      533              : 
      534              : 
-     535        30300 :    logic         dec_i0_rs1_en_d;
-     536        16396 :    logic         dec_i0_rs2_en_d;
+     535        18512 :    logic         dec_i0_rs1_en_d;
+     536         9920 :    logic         dec_i0_rs2_en_d;
      537            4 :    logic  [31:0] gpr_i0_rs1_d;
-     538            4 :    logic  [31:0] gpr_i0_rs2_d;
+     538           16 :    logic  [31:0] gpr_i0_rs2_d;
      539              : 
      540            4 :    logic [31:0] dec_i0_result_r;
-     541         1012 :    logic [31:0] exu_i0_result_x;
+     541          616 :    logic [31:0] exu_i0_result_x;
      542            2 :    logic [31:1] exu_i0_pc_x;
      543            2 :    logic [31:1] exu_npc_r;
      544              : 
@@ -653,38 +653,38 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552         1876 :    logic [31:0] dec_i0_immed_d;
-     553         1192 :    logic [12:1] dec_i0_br_immed_d;
-     554          844 :    logic         dec_i0_select_pc_d;
+     552         1192 :    logic [31:0] dec_i0_immed_d;
+     553          840 :    logic [12:1] dec_i0_br_immed_d;
+     554          576 :    logic         dec_i0_select_pc_d;
      555              : 
      556           10 :    logic [31:1] dec_i0_pc_d;
-     557         1380 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
-     558           28 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
+     557          808 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
+     558            4 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
-     560        26004 :    logic         dec_i0_alu_decode_d;
-     561        11376 :    logic         dec_i0_branch_d;
+     560        15936 :    logic         dec_i0_alu_decode_d;
+     561         7028 :    logic         dec_i0_branch_d;
      562              : 
-     563        36324 :    logic         ifu_miss_state_idle;
+     563        22384 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
      565            0 :    logic         dec_tlu_flush_leak_one_r;
      566            0 :    logic         dec_tlu_flush_err_r;
-     567        34772 :    logic         ifu_i0_valid;
-     568          656 :    logic [31:0]  ifu_i0_instr;
+     567        21400 :    logic         ifu_i0_valid;
+     568          392 :    logic [31:0]  ifu_i0_instr;
      569           10 :    logic [31:1]  ifu_i0_pc;
      570              : 
-     571         1524 :    logic        exu_flush_final;
+     571         1084 :    logic        exu_flush_final;
      572              : 
-     573           24 :    logic [31:1] exu_flush_path_final;
+     573           16 :    logic [31:1] exu_flush_path_final;
      574              : 
-     575         1284 :    logic [31:0] exu_lsu_rs1_d;
-     576           12 :    logic [31:0] exu_lsu_rs2_d;
+     575          300 :    logic [31:0] exu_lsu_rs1_d;
+     576            8 :    logic [31:0] exu_lsu_rs2_d;
      577              : 
      578              : 
-     579         2568 :    el2_lsu_pkt_t    lsu_p;
-     580        26638 :    logic             dec_qual_lsu_d;
+     579         1396 :    el2_lsu_pkt_t    lsu_p;
+     580        16414 :    logic             dec_qual_lsu_d;
      581              : 
-     582        11276 :    logic        dec_lsu_valid_raw_d;
-     583          684 :    logic [11:0] dec_lsu_offset_d;
+     582         6928 :    logic        dec_lsu_valid_raw_d;
+     583          420 :    logic [11:0] dec_lsu_offset_d;
      584              : 
      585            0 :    logic [31:0]  lsu_result_m;
      586            0 :    logic [31:0]  lsu_result_corr_r;     // This is the ECC corrected data going to RF
@@ -693,72 +693,72 @@
      589            0 :    logic         lsu_imprecise_error_load_any;
      590            0 :    logic         lsu_imprecise_error_store_any;
      591            2 :    logic [31:0]  lsu_imprecise_error_addr_any;
-     592          248 :    logic         lsu_load_stall_any;       // This is for blocking loads
-     593          248 :    logic         lsu_store_stall_any;      // This is for blocking stores
-     594         8954 :    logic         lsu_idle_any;             // doesn't include DMA
-     595         8952 :    logic         lsu_active;               // lsu is active. used for clock
+     592          160 :    logic         lsu_load_stall_any;       // This is for blocking loads
+     593          160 :    logic         lsu_store_stall_any;      // This is for blocking stores
+     594         5458 :    logic         lsu_idle_any;             // doesn't include DMA
+     595         5456 :    logic         lsu_active;               // lsu is active. used for clock
      596              : 
      597              : 
      598            0 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
      599            0 :    logic [1:0]   lsu_fir_error;       // Error during fast interrupt lookup
      600              : 
      601              :    // Non-blocking loads
-     602         5868 :    logic                                 lsu_nonblock_load_valid_m;
-     603         1920 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
+     602         3496 :    logic                                 lsu_nonblock_load_valid_m;
+     603         1280 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
      604            0 :    logic                                 lsu_nonblock_load_inv_r;
-     605         1920 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
-     606         6000 :    logic                                 lsu_nonblock_load_data_valid;
-     607          120 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
-     608           12 :    logic [31:0]                          lsu_nonblock_load_data;
+     605         1280 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
+     606         3576 :    logic                                 lsu_nonblock_load_data_valid;
+     607           76 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
+     608            8 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
-     610          124 :    logic        dec_csr_ren_d;
-     611            4 :    logic [31:0] dec_csr_rddata_d;
+     610           72 :    logic        dec_csr_ren_d;
+     611            0 :    logic [31:0] dec_csr_rddata_d;
      612              : 
-     613            0 :    logic [31:0] exu_csr_rs1_x;
+     613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
-     615        36368 :    logic        dec_tlu_i0_commit_cmt;
-     616           64 :    logic        dec_tlu_flush_lower_r;
-     617           64 :    logic        dec_tlu_flush_lower_wb;
+     615        22348 :    logic        dec_tlu_i0_commit_cmt;
+     616           36 :    logic        dec_tlu_flush_lower_r;
+     617           36 :    logic        dec_tlu_flush_lower_wb;
      618            0 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
      619            0 :    logic        dec_tlu_fence_i_r;            // flush is a fence_i rfnpc, flush icache
      620              : 
      621            0 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624        19040 :    logic        ifu_i0_pc4;
+     624        11620 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
-     628           28 :    el2_div_pkt_t  div_p;
+     628           20 :    el2_div_pkt_t  div_p;
      629            0 :    logic           dec_div_cancel;
      630              : 
      631            0 :    logic [31:0] exu_div_result;
-     632           56 :    logic exu_div_wren;
+     632           40 :    logic exu_div_wren;
      633              : 
-     634        36372 :    logic dec_i0_decode_d;
+     634        22352 :    logic dec_i0_decode_d;
      635              : 
      636              : 
-     637          650 :    logic [31:1] pred_correct_npc_x;
+     637          470 :    logic [31:1] pred_correct_npc_x;
      638              : 
-     639         2256 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
+     639         1384 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
      640              : 
      641           12 :    el2_predict_pkt_t  exu_mp_pkt;
-     642          932 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643         2454 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
-     644          472 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
+     642          676 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
+     643         1454 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     644          316 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647         2454 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648         5260 :    logic [1:0]  exu_i0_br_hist_r;
+     647         1454 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648         3160 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651         7996 :    logic        exu_i0_br_valid_r;
-     652         1280 :    logic        exu_i0_br_mp_r;
-     653        10172 :    logic        exu_i0_br_middle_r;
+     651         4780 :    logic        exu_i0_br_valid_r;
+     652          940 :    logic        exu_i0_br_mp_r;
+     653         6176 :    logic        exu_i0_br_middle_r;
      654              : 
-     655         2256 :    logic        exu_i0_br_way_r;
+     655         1384 :    logic        exu_i0_br_way_r;
      656              : 
-     657          172 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
+     657          108 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
      658              : 
      659            0 :    logic        dma_dccm_req;
      660            0 :    logic        dma_iccm_req;
@@ -779,8 +779,8 @@
      675              : 
      676            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
      677            0 :    logic        dma_iccm_stall_any;       // Stall the fetch
-     678        11278 :    logic        dccm_ready;
-     679         1550 :    logic        iccm_ready;
+     678         6930 :    logic        dccm_ready;
+     679         1106 :    logic        iccm_ready;
      680              : 
      681            0 :    logic        dma_pmu_dccm_read;
      682            0 :    logic        dma_pmu_dccm_write;
@@ -795,19 +795,19 @@
      691            0 :    logic        ifu_i0_dbecc;
      692            0 :    logic        iccm_dma_sb_error;
      693              : 
-     694          188 :    el2_br_pkt_t i0_brp;
-     695          792 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696        12010 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     694          116 :    el2_br_pkt_t i0_brp;
+     695          500 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
+     696         7134 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697            0 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
      700            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
      701              : 
      702              : 
-     703         1864 :    el2_predict_pkt_t dec_i0_predict_p_d;
+     703         1120 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705        12010 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
-     706          792 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
+     705         7134 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     706          500 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707            0 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
      709              :    // PIC ports
@@ -816,7 +816,7 @@
      712            0 :    logic                  picm_mken;
      713            2 :    logic [31:0]           picm_rdaddr;
      714            2 :    logic [31:0]           picm_wraddr;
-     715           12 :    logic [31:0]           picm_wr_data;
+     715            8 :    logic [31:0]           picm_wr_data;
      716            0 :    logic [31:0]           picm_rd_data;
      717              : 
      718              :    // feature disable from mfdc
@@ -843,18 +843,18 @@
      739              :   // PMP Signals
      740            0 :   el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
      741              :   logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
-     742         1404 :   logic [31:0]            pmp_chan_addr [3];
+     742          432 :   logic [31:0]            pmp_chan_addr [3];
      743            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
-     744         4414 :   logic                   pmp_chan_err  [3];
+     744            0 :   logic                   pmp_chan_err  [3];
      745              : 
-     746            2 :   logic [31:1] ifu_pmp_addr;
+     746            2 :   logic [31:1] ifu_pmp_addr;
      747            0 :   logic        ifu_pmp_error;
-     748         1404 :   logic [31:0] lsu_pmp_addr_start;
-     749         4414 :   logic        lsu_pmp_error_start;
-     750         1404 :   logic [31:0] lsu_pmp_addr_end;
-     751         4414 :   logic        lsu_pmp_error_end;
-     752         5664 :   logic        lsu_pmp_we;
-     753         5868 :   logic        lsu_pmp_re;
+     748          432 :   logic [31:0] lsu_pmp_addr_start;
+     749            0 :   logic        lsu_pmp_error_start;
+     750          432 :   logic [31:0] lsu_pmp_addr_end;
+     751            0 :   logic        lsu_pmp_error_end;
+     752         3596 :   logic        lsu_pmp_we;
+     753         3496 :   logic        lsu_pmp_re;
      754              : 
      755              :    // -----------------------DEBUG  START -------------------------------
      756              : 
@@ -889,43 +889,43 @@
      785            0 :    logic                   dec_debug_wdata_rs1_d;
      786            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
      787              : 
-     788        36372 :    logic [1:0]             dec_data_en;
-     789        36284 :    logic [1:0]             dec_ctl_en;
+     788        22352 :    logic [1:0]             dec_data_en;
+     789        22292 :    logic [1:0]             dec_ctl_en;
      790              : 
      791              :    // PMU Signals
-     792         1280 :    logic                   exu_pmu_i0_br_misp;
-     793         5720 :    logic                   exu_pmu_i0_br_ataken;
-     794         7718 :    logic                   exu_pmu_i0_pc4;
+     792          940 :    logic                   exu_pmu_i0_br_misp;
+     793         3488 :    logic                   exu_pmu_i0_br_ataken;
+     794         4698 :    logic                   exu_pmu_i0_pc4;
      795              : 
-     796         5868 :    logic                   lsu_pmu_load_external_m;
-     797         5664 :    logic                   lsu_pmu_store_external_m;
+     796         3496 :    logic                   lsu_pmu_load_external_m;
+     797         3596 :    logic                   lsu_pmu_store_external_m;
      798            0 :    logic                   lsu_pmu_misaligned_m;
-     799        11876 :    logic                   lsu_pmu_bus_trxn;
+     799         7308 :    logic                   lsu_pmu_bus_trxn;
      800            0 :    logic                   lsu_pmu_bus_misaligned;
      801            0 :    logic                   lsu_pmu_bus_error;
-     802           56 :    logic                   lsu_pmu_bus_busy;
+     802           32 :    logic                   lsu_pmu_bus_busy;
      803              : 
-     804         1382 :    logic                   ifu_pmu_fetch_stall;
-     805        36324 :    logic                   ifu_pmu_ic_miss;
+     804          942 :    logic                   ifu_pmu_fetch_stall;
+     805        22384 :    logic                   ifu_pmu_ic_miss;
      806            0 :    logic                   ifu_pmu_ic_hit;
      807            0 :    logic                   ifu_pmu_bus_error;
      808            0 :    logic                   ifu_pmu_bus_busy;
-     809        36322 :    logic                   ifu_pmu_bus_trxn;
+     809        22382 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812       584906 :    logic                   free_clk;
-     813       584906 :    logic                   active_clk;
+     812       359918 :    logic                   free_clk;
+     813       359918 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
      817              : 
-     818         5236 :    logic [15:0]            ifu_i0_cinst;
+     818         3260 :    logic [15:0]            ifu_i0_cinst;
      819              : 
      820              : // fast interrupt
      821            0 :    logic [31:2]            dec_tlu_meihap;
      822            0 :    logic                   dec_extint_stall;
      823              : 
-     824        36388 :    el2_trace_pkt_t  trace_rv_trace_pkt;
+     824        22364 :    el2_trace_pkt_t  trace_rv_trace_pkt;
      825              : 
      826              : 
      827            0 :    logic                   lsu_fastint_stall_any;
@@ -941,7 +941,7 @@
      837            0 :    logic        pause_state;
      838            0 :    logic        halt_state;
      839              : 
-     840         9752 :    logic        dec_tlu_core_empty;
+     840         5948 :    logic        dec_tlu_core_empty;
      841              : 
      842              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
      843              : 
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890           14 :    logic priv_mode;
+     890              :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892           14 :    logic priv_mode_eff;
+     892              :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894           14 :    logic priv_mode_ns;
+     894              :    logic priv_mode_ns;
      895              : 
-     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer_wrapper.sv.html
index 8b64f192adb..49d2bfd4861 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,21 +131,21 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30       584906 :    input logic                             clk,
+      30       359918 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
-      34           12 :    input logic                             nmi_int,
+      34            8 :    input logic                             nmi_int,
       35            0 :    input logic [31:1]                      nmi_vec,
       36            0 :    input logic [31:1]                      jtag_id,
       37              : 
       38              : 
-      39         4348 :    output logic [31:0]                     trace_rv_i_insn_ip,
+      39         2724 :    output logic [31:0]                     trace_rv_i_insn_ip,
       40            2 :    output logic [31:0]                     trace_rv_i_address_ip,
-      41        36388 :    output logic                            trace_rv_i_valid_ip,
-      42           28 :    output logic                            trace_rv_i_exception_ip,
+      41        22364 :    output logic                            trace_rv_i_valid_ip,
+      42           16 :    output logic                            trace_rv_i_exception_ip,
       43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
-      44           28 :    output logic                            trace_rv_i_interrupt_ip,
+      44           16 :    output logic                            trace_rv_i_interrupt_ip,
       45            0 :    output logic [31:0]                     trace_rv_i_tval_ip,
       46              : 
       47              :    // Bus signals
@@ -339,10 +339,10 @@
      235            0 :    output logic                            hmastlock,
      236            0 :    output logic [3:0]                      hprot,
      237            0 :    output logic [2:0]                      hsize,
-     238        36322 :    output logic [1:0]                      htrans,
+     238        22382 :    output logic [1:0]                      htrans,
      239            0 :    output logic                            hwrite,
      240              : 
-     241         3996 :    input logic [63:0]                      hrdata,
+     241         2524 :    input logic [63:0]                      hrdata,
      242            2 :    input logic                             hready,
      243            0 :    input logic                             hresp,
      244              : 
@@ -352,11 +352,11 @@
      248            0 :    output logic                            lsu_hmastlock,
      249            0 :    output logic [3:0]                      lsu_hprot,
      250            0 :    output logic [2:0]                      lsu_hsize,
-     251        11968 :    output logic [1:0]                      lsu_htrans,
-     252         3870 :    output logic                            lsu_hwrite,
-     253          418 :    output logic [63:0]                     lsu_hwdata,
+     251         7364 :    output logic [1:0]                      lsu_htrans,
+     252         2446 :    output logic                            lsu_hwrite,
+     253          258 :    output logic [63:0]                     lsu_hwdata,
      254              : 
-     255          124 :    input logic [63:0]                      lsu_hrdata,
+     255           80 :    input logic [63:0]                      lsu_hrdata,
      256            2 :    input logic                             lsu_hready,
      257            0 :    input logic                             lsu_hresp,
      258              :    // Debug Syster Bus AHB
@@ -406,8 +406,8 @@
      302            0 :    input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
      303            0 :    input                                   el2_ic_tag_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
      304              : 
-     305           12 :    input logic                             timer_int,
-     306           12 :    input logic                             soft_int,
+     305            8 :    input logic                             timer_int,
+     306            8 :    input logic                             soft_int,
      307            0 :    input logic [pt.PIC_TOTAL_INT:1]        extintsrc_req,
      308              : 
      309            0 :    output logic                            dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
@@ -454,16 +454,16 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353       584906 :    logic                             active_l2clk;
-     354       584906 :    logic                             free_l2clk;
+     353       359918 :    logic                             active_l2clk;
+     354       359918 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
      358            0 :    logic         dccm_rden;
      359            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo;
      360            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi;
-     361         1404 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
-     362         1404 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
+     361          432 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
+     362          432 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
      363            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
      364            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi;
      365              : 
@@ -490,28 +490,28 @@
      386            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way;   // Debug way. Rd or Wr.
      387              : 
      388            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
-     389         2012 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
-     390         7276 :    logic [63:0]  ic_rd_data;
+     389         1172 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
+     390         4604 :    logic [63:0]  ic_rd_data;
      391            0 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      392            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
      393              : 
      394            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
      395            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
      396              : 
-     397         7276 :    logic [63:0]  ic_premux_data;
-     398        30354 :    logic         ic_sel_premux_data;
+     397         4604 :    logic [63:0]  ic_premux_data;
+     398        18614 :    logic         ic_sel_premux_data;
      399              : 
      400              :    // ICCM ports
-     401          212 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
+     401          136 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
      402            0 :    logic           iccm_wren;
-     403          256 :    logic           iccm_rden;
+     403          172 :    logic           iccm_rden;
      404            0 :    logic [2:0]     iccm_wr_size;
      405            0 :    logic [77:0]    iccm_wr_data;
      406            0 :    logic           iccm_buf_correct_ecc;
      407            0 :    logic           iccm_correction_state;
      408              : 
-     409           12 :    logic [63:0]    iccm_rd_data;
-     410           12 :    logic [77:0]    iccm_rd_data_ecc;
+     409            8 :    logic [63:0]    iccm_rd_data;
+     410            8 :    logic [77:0]    iccm_rd_data_ecc;
      411              : 
      412            2 :    logic        core_rst_l;                         // Core reset including rst_l and dbg_rst_l
      413              : 
@@ -610,7 +610,7 @@
      506              : 
      507              : 
      508              : `ifdef RV_BUILD_AHB_LITE
-     509         6008 :    wire                            lsu_axi_awvalid;
+     509         3812 :    wire                            lsu_axi_awvalid;
      510            0 :    wire                            lsu_axi_awready;
      511            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid;
      512            2 :    wire [31:0]                     lsu_axi_awaddr;
@@ -624,10 +624,10 @@
      520            0 :    wire [3:0]                      lsu_axi_awqos;
      521              : 
      522              : 
-     523         6008 :    wire                            lsu_axi_wvalid;
+     523         3812 :    wire                            lsu_axi_wvalid;
      524            0 :    wire                            lsu_axi_wready;
-     525           44 :    wire [63:0]                     lsu_axi_wdata;
-     526          832 :    wire [7:0]                      lsu_axi_wstrb;
+     525           24 :    wire [63:0]                     lsu_axi_wdata;
+     526          508 :    wire [7:0]                      lsu_axi_wstrb;
      527            2 :    wire                            lsu_axi_wlast;
      528              : 
      529            0 :    wire                            lsu_axi_bvalid;
@@ -636,7 +636,7 @@
      532            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid;
      533              : 
      534              :    // AXI Read Channels
-     535         5868 :    wire                            lsu_axi_arvalid;
+     535         3496 :    wire                            lsu_axi_arvalid;
      536            0 :    wire                            lsu_axi_arready;
      537            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid;
      538            2 :    wire [31:0]                     lsu_axi_araddr;
@@ -694,10 +694,10 @@
      590            0 :    wire [pt.IFU_BUS_TAG-1:0]      ifu_axi_bid;
      591              : 
      592              :    // AXI Read Channels
-     593        36322 :    wire                            ifu_axi_arvalid;
+     593        22382 :    wire                            ifu_axi_arvalid;
      594            0 :    wire                            ifu_axi_arready;
-     595        27564 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
-     596         9128 :    wire [31:0]                     ifu_axi_araddr;
+     595        16956 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
+     596         5732 :    wire [31:0]                     ifu_axi_araddr;
      597            2 :    wire [3:0]                      ifu_axi_arregion;
      598            0 :    wire [7:0]                      ifu_axi_arlen;
      599            0 :    wire [2:0]                      ifu_axi_arsize;
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_irq/index_mem_lib.sv.html
index 0731798f11e..74c3dcbbb1b 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111          210 : `EL2_RAM(4096, 39)
+     111          168 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175       435316 : `EL2_RAM_BE(512, 142)
+     175       331968 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208       217658 : `EL2_RAM_BE(128, 52)
+     208       165984 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_ahb_irq/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_irq/index_rvjtag_tap.v.html
index 425ed464135..07375f3afb0 100644
--- a/html/main/coverage_dashboard/all_ahb_irq/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_irq/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index.html b/html/main/coverage_dashboard/all_ahb_modesw/index.html
index 650c94317d4..4eb3e0bfbe4 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        39.6%
+    
+        34.4%
     
     
-        2126
+        1830
     
     
-        5364
+        5317
     
 
       
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        63.0%
+    
+        62.5%
     
     
-        673
+        668
     
     
-        1069
+        1068
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    27.9%
+                    25.9%
                 
             
 
             
-                356
+                328
                 /
-                1275
+                1265
             
         
             
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    59.2%
+                    58.6%
                 
             
 
             
-                42
+                41
                 /
-                71
+                70
             
         
     
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    44.8%
+                    39.0%
                 
             
 
             
-                451
+                385
                 /
-                1007
+                987
             
         
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    54.8%
+                    38.3%
                 
             
 
             
-                189
+                132
                 /
                 345
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.3%
+                    46.4%
                 
             
 
             
-                530
+                470
                 /
                 1014
             
@@ -507,19 +507,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    74.8%
+                    72.8%
                 
             
 
             
-                154
+                150
                 /
                 206
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    9.9%
+                    8.3%
                 
             
 
             
-                10
+                7
                 /
-                101
+                84
             
         
             
@@ -615,19 +615,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    32.6%
+                    30.5%
                 
             
 
             
-                113
+                106
                 /
                 347
             
@@ -683,19 +683,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    43.8%
+                    36.5%
                 
             
 
             
-                450
+                375
                 /
                 1027
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design.html
index 35af8fc15e3..99e42238fde 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        27.9%
+    
+        25.9%
     
     
-        356
+        328
     
     
-        1275
+        1265
     
 
       
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        59.2%
+    
+        58.6%
     
     
-        42
+        41
     
     
-        71
+        70
     
 
       
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    24.1%
+                    22.2%
                 
             
 
             
-                26
+                24
                 /
                 108
             
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    60.0%
+                    50.0%
                 
             
 
             
-                12
+                7
                 /
-                20
+                14
             
         
             
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.0%
+                    49.0%
                 
             
 
             
-                26
+                25
                 /
-                52
+                51
             
         
     
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    34.9%
+                    32.1%
                 
             
 
             
-                220
+                201
                 /
-                631
+                627
             
         
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    22.5%
+                    21.9%
                 
             
 
             
-                69
+                67
                 /
                 306
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dbg.html
index 3109abc5a7e..d566a397076 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dec.html
index 09f34356ab3..ee1f79924a4 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        44.8%
+    
+        39.0%
     
     
-        451
+        385
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    46.3%
+                    40.3%
                 
             
 
             
-                119
+                102
                 /
-                257
+                253
             
         
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    64.7%
+                    56.0%
                 
             
 
             
-                178
+                154
                 /
                 275
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    83.3%
+                    61.1%
                 
             
 
             
-                15
+                11
                 /
                 18
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    42.4%
+                    43.8%
                 
             
 
             
                 14
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.8%
+                    24.2%
                 
             
 
             
-                108
+                87
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dmi.html
index 35c0937f668..62a5e4c5dc2 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_exu.html
index 1208624dc6c..5e3672d1058 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_exu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        54.8%
+    
+        38.3%
     
     
-        189
+        132
     
     
         345
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    80.0%
+                    70.0%
                 
             
 
             
-                80
+                70
                 /
                 100
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.3%
+                    48.9%
                 
             
 
             
-                46
+                43
                 /
                 88
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
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+                    16.0%
                 
             
 
             
-                57
+                13
                 /
                 81
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_ifu.html
index b7a1894b6c5..66c289367a4 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        52.3%
+    
+        46.4%
     
     
-        530
+        470
     
     
         1014
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        74.8%
+    
+        72.8%
     
     
-        154
+        150
     
     
         206
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    44.2%
+                    40.7%
                 
             
 
             
-                76
+                70
                 /
                 172
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    76.0%
+                    58.4%
                 
             
 
             
-                95
+                73
                 /
                 125
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    82.7%
+                    63.6%
                 
             
 
             
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+                70
                 /
                 110
             
@@ -343,19 +343,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    97.4%
+                    81.6%
                 
             
 
             
-                37
+                31
                 /
                 38
             
@@ -547,19 +547,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    78.6%
+                    69.0%
                 
             
 
             
-                33
+                29
                 /
                 42
             
@@ -615,19 +615,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.0%
+                    44.7%
                 
             
 
             
-                158
+                157
                 /
                 351
             
@@ -643,19 +643,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
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+                    50.0%
                 
             
 
             
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+                55
                 /
                 110
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_include.html
index 853173be201..2383936600b 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        9.9%
+    
+        8.3%
     
     
-        10
+        7
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    9.9%
+                    8.3%
                 
             
 
             
-                10
+                7
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lib.html
index 7b357a9adbd..429e9aa4a84 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lib.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        32.6%
+    
+        30.5%
     
     
-        113
+        106
     
     
         347
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    56.6%
+                    51.5%
                 
             
 
             
-                77
+                70
                 /
                 136
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lsu.html
index 46b9dcd2b32..b384b691d15 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        43.8%
+    
+        36.5%
     
     
-        450
+        375
     
     
         1027
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.4%
+                    32.8%
                 
             
 
             
-                80
+                65
                 /
                 198
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    24.0%
+                    20.0%
                 
             
 
             
-                12
+                10
                 /
                 50
             
@@ -275,19 +275,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    61.3%
+                    48.0%
                 
             
 
             
-                157
+                123
                 /
                 256
             
@@ -343,19 +343,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    54.8%
+                    48.7%
                 
             
 
             
-                63
+                56
                 /
                 115
             
@@ -479,19 +479,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    24.1%
+                    19.6%
                 
             
 
             
-                27
+                22
                 /
                 112
             
@@ -683,19 +683,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    45.9%
+                    35.3%
                 
             
 
             
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+                30
                 /
                 85
             
@@ -751,19 +751,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    27.6%
+                    25.0%
                 
             
 
             
-                21
+                19
                 /
                 76
             
@@ -819,19 +819,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.0%
+                    30.0%
                 
             
 
             
-                4
+                3
                 /
                 10
             
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_ahb_to_axi4.sv.html
index b38b3f365f3..3b01c0f36ba 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : )
       29              : //   ,TAG  = 1)
       30              : (
-      31       583434 :    input                   clk,
+      31        12564 :    input                   clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -242,9 +242,9 @@
      138            2 :       buf_read_error_in = 1'b0;              // signal indicating that an error came back with the read from the core
      139            2 :       cmdbuf_wr_en      = 1'b0;              // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
      140            2 :       case (buf_state)
-     141       132192 :          IDLE: begin  // No commands recieved
-     142       132192 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
-     143       132192 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
+     141         3056 :          IDLE: begin  // No commands recieved
+     142         3056 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
+     143         3056 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
      144              :           end
      145            0 :          WR: begin // Write command recieved last cycle
      146            0 :                   buf_nxtstate      = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite  ? WR : RD;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_axi4_to_ahb.sv.html
index 342b7d5984d..c773a8c19fa 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : `include "el2_param.vh"
       28              : ,parameter TAG  = 1) (
       29              : 
-      30       528768 :    input                   clk,
-      31       528768 :    input                   free_clk,
+      30        12224 :    input                   clk,
+      31        12224 :    input                   free_clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -389,18 +389,18 @@
      285            2 :       rd_bypass_idle   = 1'b0;
      286              : 
      287            2 :       case (buf_state)
-     288       132192 :          IDLE: begin
-     289       132192 :                   master_ready   = 1'b1;
-     290       132192 :                   buf_write_in = (master_opc[2:1] == 2'b01);
-     291       132192 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
-     292       132192 :                   buf_state_en = master_valid & master_ready;
-     293       132192 :                   buf_wr_en    = buf_state_en;
-     294       132192 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
-     295       132192 :                   buf_cmd_byte_ptr_en   = buf_state_en;
-     296       132192 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
-     297       132192 :                   bypass_en       = buf_state_en;
-     298       132192 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
-     299       132192 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
+     288         3056 :          IDLE: begin
+     289         3056 :                   master_ready   = 1'b1;
+     290         3056 :                   buf_write_in = (master_opc[2:1] == 2'b01);
+     291         3056 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
+     292         3056 :                   buf_state_en = master_valid & master_ready;
+     293         3056 :                   buf_wr_en    = buf_state_en;
+     294         3056 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
+     295         3056 :                   buf_cmd_byte_ptr_en   = buf_state_en;
+     296         3056 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
+     297         3056 :                   bypass_en       = buf_state_en;
+     298         3056 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
+     299         3056 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
      300              :           end
      301            0 :          CMD_RD: begin
      302            0 :                   buf_nxtstate    = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_beh_lib.sv.html
index 34489395266..13c92f5d123 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_beh_lib.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        56.6%
+    
+        51.5%
     
     
-        77
+        70
     
     
         136
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22       528768 :      input logic           clk,
+      22        12224 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38       132190 :    always_ff @(posedge clk or negedge rst_l) begin
+      38         3054 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42       132180 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42         3044 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52            0 :      input logic             en,
-      53       528768 :      input logic           clk,
+      53        12224 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -171,10 +171,10 @@
       67              : // rvdff with en and clear
       68              : module rvdffsc #( parameter WIDTH=1, SHORT=0 )
       69              :    (
-      70         1384 :      input logic [WIDTH-1:0] din,
+      70            8 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73      2333736 :      input logic           clk,
+      73        50256 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -192,13 +192,13 @@
       88              : // _fpga versions
       89              : module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
       90              :    (
-      91        20544 :      input logic [WIDTH-1:0] din,
+      91          352 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94       583434 :      input logic           rawclk,
+      94        12564 :      input logic           rawclk,
       95            2 :      input logic           rst_l,
       96              : 
-      97        20544 :      output logic [WIDTH-1:0] dout
+      97          352 :      output logic [WIDTH-1:0] dout
       98              :      );
       99              : 
      100              : if (SHORT == 1) begin : genblock
@@ -220,7 +220,7 @@
      116            0 :      input logic             en,
      117            0 :      input logic           clk,
      118            6 :      input logic           clken,
-     119      1112202 :      input logic           rawclk,
+     119        24788 :      input logic           rawclk,
      120            6 :      input logic           rst_l,
      121              : 
      122            0 :      output logic [WIDTH-1:0] dout
@@ -243,14 +243,14 @@
      139              : module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
      140              :    (
      141           26 :      input logic [WIDTH-1:0] din,
-     142        89590 :      input logic             en,
+     142         2316 :      input logic             en,
      143            0 :      input logic             clear,
-     144       100818 :      input logic             clk,
+     144         4804 :      input logic             clk,
      145            6 :      input logic             clken,
-     146      1112202 :      input logic             rawclk,
+     146        24788 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
-     149         6344 :      output logic [WIDTH-1:0] dout
+     149          230 :      output logic [WIDTH-1:0] dout
      150              :      );
      151              : 
      152            0 :    logic [WIDTH-1:0]          din_new;
@@ -269,9 +269,9 @@
      165              : 
      166              : module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
      167              :    (
-     168        14976 :      input  logic [WIDTH-1:0] din,
+     168          688 :      input  logic [WIDTH-1:0] din,
      169            0 :      input  logic           en,
-     170       528768 :      input  logic           clk,
+     170        12224 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -309,12 +309,12 @@
      205              : 
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
-     208         1126 :      input  logic [WIDTH-1:0] din,
-     209      3172608 :      input  logic             clk,
+     208           28 :      input  logic [WIDTH-1:0] din,
+     209        73344 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
-     211       263768 :      input  logic             en,
+     211         6044 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
-     213         1126 :      output logic [WIDTH-1:0] dout
+     213           28 :      output logic [WIDTH-1:0] dout
      214              :      );
      215              : 
      216              : 
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            2 :      input  logic [WIDTH-1:0] din,
-     242       528768 :      input  logic             clk,
+     242        12224 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -397,12 +397,12 @@
      293              : // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
-     296         1360 :      input  logic [WIDTH-1:0] din,
-     297       583434 :      input  logic             clk,
+     296            0 :      input  logic [WIDTH-1:0] din,
+     297        12564 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
-     299        35128 :      input  logic             en,
+     299          816 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
-     301         1360 :      output logic [WIDTH-1:0] dout
+     301            0 :      output logic [WIDTH-1:0] dout
      302              :      );
      303              : 
      304              :    localparam integer RIGHT = 31;
@@ -440,16 +440,16 @@
      336              : 
      337              : module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
      338              :    (
-     339          268 :      input  logic [WIDTH-1:0] din,
+     339            8 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341       583434 :      input  logic           clk,
+     341        12564 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
-     344          268 :      output logic [WIDTH-1:0] dout
+     344            8 :      output logic [WIDTH-1:0] dout
      345              :      );
      346              : 
      347            0 :    logic                      l1clk;
-     348            4 :    logic                      en;
+     348           28 :    logic                      en;
      349              : 
      350              : 
      351              : 
@@ -519,7 +519,7 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418       583434 :      input  logic                 clk,
+     418        12564 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
      420            0 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434      8195904 :      input  logic                 rawclk,
+     434       189472 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -551,17 +551,17 @@
      447              : 
      448              : module rvlsadder
      449              :   (
-     450         2880 :     input logic [31:0] rs1,
-     451          400 :     input logic [11:0] offset,
+     450          104 :     input logic [31:0] rs1,
+     451            0 :     input logic [11:0] offset,
      452              : 
-     453         2496 :     output logic [31:0] dout
+     453          120 :     output logic [31:0] dout
      454              :     );
      455              : 
-     456          400 :    logic                cout;
-     457          480 :    logic                sign;
+     456            0 :    logic                cout;
+     457            0 :    logic                sign;
      458              : 
-     459         4128 :    logic [31:12]        rs1_inc;
-     460         3170 :    logic [31:12]        rs1_dec;
+     459          220 :    logic [31:12]        rs1_inc;
+     460           18 :    logic [31:12]        rs1_dec;
      461              : 
      462              :    assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
      463              : 
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480           16 :     input [31:1] pc,
-     481        11920 :     input [12:1] offset,
+     481          424 :     input [12:1] offset,
      482              : 
-     483         1126 :     output [31:1] dout
+     483           28 :     output [31:1] dout
      484              :     );
      485              : 
-     486        11864 :    logic          cout;
-     487        12838 :    logic          sign;
+     486          420 :    logic          cout;
+     487          448 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -615,10 +615,10 @@
      511              :    (
      512            0 :      input logic [WIDTH-1:0] din,
      513              : 
-     514           48 :      output logic [WIDTH-1:0] dout
+     514            0 :      output logic [WIDTH-1:0] dout
      515              :      );
      516              : 
-     517           48 :    logic [WIDTH-1:1]          dout_temp;   // holding for all other bits except for the lsb. LSB is always din
+     517            0 :    logic [WIDTH-1:1]          dout_temp;   // holding for all other bits except for the lsb. LSB is always din
      518              : 
      519              :    genvar                     i;
      520              : 
@@ -672,7 +672,7 @@
      568              : // find first starting from LSB. Skip that location and match the rest of the bits
      569              : module rvmaskandmatch #( parameter WIDTH=32 )
      570              :    (
-     571            0 :      input  logic [WIDTH-1:0] mask,     // this will have the mask in the lower bit positions
+     571            0 :      input  logic [WIDTH-1:0] mask,     // this will have the mask in the lower bit positions
      572            0 :      input  logic [WIDTH-1:0] data,     // this is what needs to be matched on the upper bits with the mask's upper bits
      573            0 :      input  logic             masken,   // when 1 : do mask. 0 : full match
      574           16 :      output logic             match
@@ -700,7 +700,7 @@
      596              : // Check if the S_ADDR <= addr < E_ADDR
      597              : module rvrangecheck  #(CCM_SADR = 32'h0,
      598              :                        CCM_SIZE  = 128) (
-     599         4992 :    input  logic [31:0]   addr,                             // Address to be checked for range
+     599          240 :    input  logic [31:0]   addr,                             // Address to be checked for range
      600            0 :    output logic          in_range,                            // S_ADDR <= start_addr < E_ADDR
      601            0 :    output logic          in_region
      602              : );
@@ -804,8 +804,8 @@
      700              : endmodule // rvecc_decode
      701              : 
      702              : module rvecc_encode_64  (
-     703         6906 :                       input [63:0] din,
-     704        20448 :                       output [6:0] ecc_out
+     703           20 :                       input [63:0] din,
+     704          108 :                       output [6:0] ecc_out
      705              :                       );
      706              :   assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
      707              : 
@@ -896,10 +896,10 @@
      792              : 
      793              : module rvoclkhdr
      794              :   (
-     795       159018 :    input  logic en,
-     796     15752718 :    input  logic clk,
+     795         4838 :    input  logic en,
+     796       339228 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798     15752718 :    output logic l1clk
+     798       339228 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_jtag_to_core_sync.v.html
index 57d3c60155c..887b9592c86 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32       583434 : input       clk,        // Core clock
+      32        12564 : input       clk,        // Core clock
       33              : 
       34            0 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35            0 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49       132190 : always @ ( posedge clk or negedge rst_n) begin
+      49         3054 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54       132186 :     else begin
-      55       132186 :         rden <= {rden[1:0], rd_en};
-      56       132186 :         wren <= {wren[1:0], wr_en};
+      54         3050 :     else begin
+      55         3050 :         rden <= {rden[1:0], rd_en};
+      56         3050 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_mux.v.html
index 19d982cc199..ac249053fd4 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_wrapper.v.html
index 8b5dcc1fac5..29d02b40440 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36       583434 :   input              core_clk,            // Core clock                  
+      36        12564 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38            0 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39            0 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dbg.sv.html
index dff22c46219..24c2e6975a9 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -140,7 +140,7 @@
       36            2 :    output logic                        dbg_core_rst_l,            // core reset from dm
       37              : 
       38              :    // inputs back from the core/dec
-      39           40 :    input logic [31:0]                  core_dbg_rddata,
+      39           12 :    input logic [31:0]                  core_dbg_rddata,
       40            0 :    input logic                         core_dbg_cmd_done,         // This will be treated like a valid signal
       41            0 :    input logic                         core_dbg_cmd_fail,         // Exception during command run
       42              : 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110       583434 :    input logic                         clk,
-     111       583434 :    input logic                         free_clk,
+     110        12564 :    input logic                         clk,
+     111        12564 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254            0 :    logic              dbg_free_clken;
-     255       583434 :    logic              dbg_free_clk;
+     255        12564 :    logic              dbg_free_clk;
      256              : 
      257            0 :    logic              sb_free_clken;
-     258       583434 :    logic              sb_free_clk;
+     258        12564 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474       132192 :             IDLE: begin
-     475       132192 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476       132192 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477       132192 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474         3056 :             IDLE: begin
+     475         3056 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476         3056 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477         3056 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604       132192 :             SBIDLE: begin
-     605       132192 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606       132192 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607       132192 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608       132192 :                      sbcs_sbbusy_din        = 1'b1;
-     609       132192 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610       132192 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604         3056 :             SBIDLE: begin
+     605         3056 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606         3056 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607         3056 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608         3056 :                      sbcs_sbbusy_din        = 1'b1;
+     609         3056 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610         3056 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec.sv.html
index e99e2d64d35..4dab1ea0902 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        46.3%
+    
+        40.3%
     
     
-        119
+        102
     
     
-        257
+        253
     
 
             
@@ -136,19 +136,19 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35       583434 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36       583434 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37       583434 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38       583434 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35        12564 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        12564 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37        12564 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38        12564 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
       42            0 :     output logic dec_extint_stall,  // Stall on external interrupt
       43              : 
-      44        35132 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
+      44          816 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
       45            0 :     output logic dec_pause_state_cg, // to top for active state clock gating
       46              : 
-      47         9576 :     output logic dec_tlu_core_empty,
+      47           92 :     output logic dec_tlu_core_empty,
       48              : 
       49            2 :     input logic        rst_l,   // reset, active low
       50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
@@ -174,27 +174,27 @@
       70            2 :     output logic mpc_debug_run_ack,   // Run ack
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
-      73         1360 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74         5836 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
-      75         7494 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
+      73           64 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
+      74          232 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      75          234 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
-      78         6024 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
-      79         2428 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
+      78          224 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
+      79          216 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
       80            0 :     input logic lsu_nonblock_load_inv_r,  // invalidate request for nonblock load r
-      81         2428 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
-      82         6192 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
+      81          216 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
+      82          224 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
       83            0 :     input logic lsu_nonblock_load_data_error,  // nonblock load bus error
-      84           48 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
-      85           24 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
+      84            0 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
+      85            0 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
       86              : 
-      87        12368 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
+      87          456 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
       88            0 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
       89            0 :     input logic lsu_pmu_bus_error,         // D side bus error
       90            0 :     input logic lsu_pmu_bus_busy,          // D side bus busy
       91            0 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
-      92         6024 :     input logic lsu_pmu_load_external_m,   // D side bus load
-      93         5848 :     input logic lsu_pmu_store_external_m,  // D side bus store
+      92          224 :     input logic lsu_pmu_load_external_m,   // D side bus load
+      93          228 :     input logic lsu_pmu_store_external_m,  // D side bus store
       94            0 :     input logic dma_pmu_dccm_read,         // DMA DCCM read
       95            0 :     input logic dma_pmu_dccm_write,        // DMA DCCM write
       96            0 :     input logic dma_pmu_any_read,          // DMA read
@@ -203,13 +203,13 @@
       99            0 :     input logic [31:1] lsu_fir_addr,  // Fast int address
      100            0 :     input logic [ 1:0] lsu_fir_error, // Fast int lookup error
      101              : 
-     102        35132 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
-     103         1286 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
-     104        35772 :     input logic ifu_pmu_ic_miss,        // icache miss
+     102          816 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
+     103           30 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
+     104          824 :     input logic ifu_pmu_ic_miss,        // icache miss
      105            0 :     input logic ifu_pmu_ic_hit,         // icache hit
      106            0 :     input logic ifu_pmu_bus_error,      // Instruction side bus error
      107            0 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
-     108        35770 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
+     108          824 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
      109              : 
      110            0 :     input logic ifu_ic_error_start,         // IC single bit error
      111            0 :     input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
@@ -228,11 +228,11 @@
      124            0 :     input logic ifu_i0_icaf_second,  // i0 has access fault on second 2B of 4B inst
      125            0 :     input logic ifu_i0_dbecc,        // icache/iccm double-bit error
      126              : 
-     127         8690 :     input logic lsu_idle_any,  // lsu idle for halting
+     127          232 :     input logic lsu_idle_any,  // lsu idle for halting
      128              : 
-     129          256 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
-     130         1124 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
-     131        11398 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
+     129            4 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
+     130           24 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
+     131           10 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
      132            0 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
      133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
      134              : 
@@ -244,31 +244,31 @@
      140            2 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
      141              : 
      142            0 :     input logic [31:0] exu_div_result,  // final div result
-     143           48 :     input logic        exu_div_wren,    // Divide write enable to GPR
+     143            0 :     input logic        exu_div_wren,    // Divide write enable to GPR
      144              : 
-     145            0 :     input logic [31:0] exu_csr_rs1_x,  // rs1 for csr instruction
+     145            0 :     input logic [31:0] exu_csr_rs1_x,  // rs1 for csr instruction
      146              : 
      147            0 :     input logic [31:0] lsu_result_m,      // load result
      148            0 :     input logic [31:0] lsu_result_corr_r, // load result - corrected load data
      149              : 
-     150           28 :     input logic lsu_load_stall_any,   // This is for blocking loads
-     151           28 :     input logic lsu_store_stall_any,  // This is for blocking stores
-     152            0 :     input logic dma_dccm_stall_any,   // stall any load/store at decode, pmu event
+     150            0 :     input logic lsu_load_stall_any,   // This is for blocking loads
+     151            0 :     input logic lsu_store_stall_any,  // This is for blocking stores
+     152            0 :     input logic dma_dccm_stall_any,   // stall any load/store at decode, pmu event
      153            0 :     input logic dma_iccm_stall_any,   // iccm stalled, pmu event
      154              : 
      155            0 :     input logic iccm_dma_sb_error,  // ICCM DMA single bit error
      156              : 
-     157         1596 :     input logic exu_flush_final,  // slot0 flush
+     157           68 :     input logic exu_flush_final,  // slot0 flush
      158              : 
      159            2 :     input logic [31:1] exu_npc_r,  // next PC
      160              : 
-     161          764 :     input logic [31:0] exu_i0_result_x,  // alu result x
+     161           16 :     input logic [31:0] exu_i0_result_x,  // alu result x
      162              : 
      163              : 
-     164        33540 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
-     165          760 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
+     164          608 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
+     165           12 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166           10 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167        17896 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167          310 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            2 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
@@ -290,7 +290,7 @@
      186              :     // Debug start
      187            0 :     input logic dbg_halt_req,        // DM requests a halt
      188            0 :     input logic dbg_resume_req,      // DM requests a resume
-     189        35772 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
+     189          824 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
      190              : 
      191            0 :     output logic        dec_tlu_dbg_halted,        // Core is halted and ready for debug command
      192            0 :     output logic        dec_tlu_debug_mode,        // Core is in debug mode
@@ -303,7 +303,7 @@
      199              : 
      200            0 :     output logic dec_debug_wdata_rs1_d,  // insert debug write data into rs1 at decode
      201              : 
-     202           40 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
+     202           12 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
      203              : 
      204            0 :     output logic dec_dbg_cmd_done,  // abstract command is done
      205            0 :     output logic dec_dbg_cmd_fail,  // abstract command failed (illegal reg address)
@@ -313,81 +313,81 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212         5352 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212          172 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215         7972 :     input  logic       exu_i0_br_valid_r,        // valid
-     216         1360 :     input  logic       exu_i0_br_mp_r,           // mispredict
-     217        10156 :     input  logic       exu_i0_br_middle_r,       // middle of bank
+     215          208 :     input  logic       exu_i0_br_valid_r,        // valid
+     216           64 :     input  logic       exu_i0_br_mp_r,           // mispredict
+     217          248 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
      219              :     // branch info from pipe1 for errors or counter updates
      220              : 
-     221         1914 :     input logic exu_i0_br_way_r,  // way hit or repl
+     221            4 :     input logic exu_i0_br_way_r,  // way hit or repl
      222              : 
-     223        28768 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
-     224        15504 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
-     225           80 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
-     226           12 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
+     223          548 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
+     224          232 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
+     225           12 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
+     226            8 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228         1752 :     output logic [31:0] dec_i0_immed_d,    // immediate data
-     229         1180 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
+     228           20 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     229           12 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
-     233        24544 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234        12188 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     233          376 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
+     234          448 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
-     236          936 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
+     236           24 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
      238           10 :     output logic [31:1] dec_i0_pc_d,             // pc's at decode
-     239         1072 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
+     239            4 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
      240            0 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
      241              : 
-     242           40 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
+     242           12 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
      243              : 
-     244         2612 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
-     245        25590 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
+     244           16 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
+     245          582 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
      246            0 :     output el2_mul_pkt_t mul_p,           // mul packet
-     247           24 :     output el2_div_pkt_t div_p,           // div packet
-     248            0 :     output logic         dec_div_cancel,  // cancel divide operation
+     247            0 :     output el2_div_pkt_t div_p,           // div packet
+     248            0 :     output logic         dec_div_cancel,  // cancel divide operation
      249              : 
-     250          400 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
+     250            0 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
-     252          172 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253            4 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     252            4 :     output logic        dec_csr_ren_d,    // CSR read enable
+     253            0 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
-     255           56 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
-     256           56 :     output logic dec_tlu_flush_lower_wb,
+     255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+     256            4 :     output logic dec_tlu_flush_lower_wb,
      257            0 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
      258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      259            0 :     output logic dec_tlu_fence_i_r,  // flush is a fence_i rfnpc, flush icache
      260              : 
-     261          922 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
+     261           28 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
      262              : 
-     263         1914 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
+     263            4 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
      264              : 
      265            0 :     output logic dec_tlu_perfcnt0,  // toggles when slot0 perf counter 0 has an event inc
      266            0 :     output logic dec_tlu_perfcnt1,  // toggles when slot0 perf counter 1 has an event inc
      267            0 :     output logic dec_tlu_perfcnt2,  // toggles when slot0 perf counter 2 has an event inc
      268            0 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
      269              : 
-     270         2738 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
-     271        11398 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
-     272         1124 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
+     270            4 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
+     271           10 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
+     272           24 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
      273            0 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
      274              : 
      275            0 :     output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index,  // Fully associt btb error index
      276              : 
-     277        11872 :     output logic dec_lsu_valid_raw_d,
+     277          452 :     output logic dec_lsu_valid_raw_d,
      278              : 
      279            0 :     output logic [31:0] dec_tlu_mrac_ff,  // CSR for memory region control
      280              : 
-     281        35132 :     output logic [1:0] dec_data_en,  // clock-gate control logic
-     282        35128 :     output logic [1:0] dec_ctl_en,
+     281          816 :     output logic [1:0] dec_data_en,  // clock-gate control logic
+     282          816 :     output logic [1:0] dec_ctl_en,
      283              : 
-     284         5200 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
+     284          166 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
      285              : 
-     286        35132 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
+     286          816 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
      287              : 
      288              :     // PMP signals
      289            0 :     output el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -396,12 +396,12 @@
      292              : `ifdef RV_USER_MODE
      293              : 
      294              :     // Privilege mode
-     295           18 :     output logic priv_mode,
-     296           26 :     output logic priv_mode_eff,
-     297           18 :     output logic priv_mode_ns,
+     295              :     output logic priv_mode,
+     296              :     output logic priv_mode_eff,
+     297              :     output logic priv_mode_ns,
      298              : 
      299              :     // mseccfg CSR content for PMP
-     300            0 :     output el2_mseccfg_pkt_t mseccfg,
+     300              :     output el2_mseccfg_pkt_t mseccfg,
      301              : 
      302              : `endif
      303              : 
@@ -423,7 +423,7 @@
      319            0 :     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
      320            0 :     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
      321              : 
-     322        35132 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+     322          816 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
      323            0 :     input  logic scan_mode               // Flop scan mode control
      324              : 
      325              : );
@@ -432,44 +432,44 @@
      328            0 :   logic dec_tlu_dec_clk_override;  // to and from dec blocks
      329            0 :   logic clk_override;
      330              : 
-     331        33540 :   logic dec_ib0_valid_d;
+     331          608 :   logic dec_ib0_valid_d;
      332              : 
-     333        35132 :   logic dec_pmu_instr_decoded;
-     334         1764 :   logic dec_pmu_decode_stall;
+     333          816 :   logic dec_pmu_instr_decoded;
+     334          208 :   logic dec_pmu_decode_stall;
      335            0 :   logic dec_pmu_presync_stall;
-     336            8 :   logic dec_pmu_postsync_stall;
+     336            0 :   logic dec_pmu_postsync_stall;
      337              : 
-     338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
+     338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
-     340         9336 :   logic [4:0] dec_i0_rs1_d;
-     341         9536 :   logic [4:0] dec_i0_rs2_d;
+     340           12 :   logic [4:0] dec_i0_rs1_d;
+     341           28 :   logic [4:0] dec_i0_rs2_d;
      342              : 
-     343          760 :   logic [31:0] dec_i0_instr_d;
+     343           12 :   logic [31:0] dec_i0_instr_d;
      344              : 
      345            0 :   logic dec_tlu_trace_disable;
      346            0 :   logic dec_tlu_pipelining_disable;
      347              : 
      348              : 
-     349        10592 :   logic [4:0] dec_i0_waddr_r;
-     350        17236 :   logic dec_i0_wen_r;
-     351           40 :   logic [31:0] dec_i0_wdata_r;
-     352           60 :   logic dec_csr_wen_r;  // csr write enable at wb
-     353         7568 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
-     354            4 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
+     349          216 :   logic [4:0] dec_i0_waddr_r;
+     350          308 :   logic dec_i0_wen_r;
+     351           12 :   logic [31:0] dec_i0_wdata_r;
+     352           12 :   logic dec_csr_wen_r;  // csr write enable at wb
+     353           24 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
+     354            8 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
      355            4 :   logic [31:0] dec_csr_wrdata_r;  // csr write data at wb
      356              : 
-     357            4 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
-     358          232 :   logic dec_csr_legal_d;  // csr indicates legal operation
+     357            8 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
+     358           16 :   logic dec_csr_legal_d;  // csr indicates legal operation
      359              : 
-     360           60 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
-     361          232 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
-     362           20 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
+     360           12 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
+     361           16 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
+     362            0 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
      363              : 
-     364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
+     364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366        17896 :   logic dec_i0_pc4_d;
+     366          310 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
-     368          148 :   logic dec_tlu_postsync_d;
+     368            4 :   logic dec_tlu_postsync_d;
      369            0 :   logic dec_tlu_debug_stall;
      370              : 
      371            0 :   logic [31:0] dec_illegal_inst;
@@ -480,18 +480,18 @@
      376            0 :   logic dec_i0_icaf_second_d;
      377            0 :   logic [3:0] dec_i0_trigger_match_d;
      378            0 :   logic dec_debug_fence_d;
-     379         6192 :   logic dec_nonblock_load_wen;
-     380          916 :   logic [4:0] dec_nonblock_load_waddr;
-     381            0 :   logic dec_tlu_flush_pause_r;
-     382          256 :   el2_br_pkt_t dec_i0_brp;
-     383         1124 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
-     384        11398 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
+     379          224 :   logic dec_nonblock_load_wen;
+     380            0 :   logic [4:0] dec_nonblock_load_waddr;
+     381            0 :   logic dec_tlu_flush_pause_r;
+     382            4 :   el2_br_pkt_t dec_i0_brp;
+     383           24 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
+     384           10 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
      385            0 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
      386            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
      387              : 
      388            2 :   logic [31:1] dec_tlu_i0_pc_r;
      389            0 :   logic dec_tlu_i0_kill_writeb_wb;
-     390        35132 :   logic dec_tlu_i0_valid_r;
+     390          816 :   logic dec_tlu_i0_valid_r;
      391              : 
      392            0 :   logic dec_pause_state;
      393              : 
@@ -499,17 +499,17 @@
      395              : 
      396            0 :   logic dec_tlu_flush_extint;  // Fast ext int started
      397              : 
-     398         4198 :   logic [31:0] dec_i0_inst_wb;
+     398            8 :   logic [31:0] dec_i0_inst_wb;
      399            2 :   logic [31:1] dec_i0_pc_wb;
-     400        35132 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
+     400          816 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
      401            0 :   logic [ 4:0] dec_tlu_exc_cause_wb1;
      402            0 :   logic [31:0] dec_tlu_mtval_wb1;
-     403           24 :   logic        dec_tlu_i0_exc_valid_wb1;
+     403            0 :   logic        dec_tlu_i0_exc_valid_wb1;
      404              : 
-     405            2 :   logic [ 4:0] div_waddr_wb;
-     406           48 :   logic        dec_div_active;
+     405            0 :   logic [ 4:0] div_waddr_wb;
+     406            0 :   logic        dec_div_active;
      407              : 
-     408            0 :   logic        dec_debug_valid_d;
+     408            0 :   logic        dec_debug_valid_d;
      409              : 
      410              :   assign clk_override = dec_tlu_dec_clk_override;
      411              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_csr_equ_m.svh.html
new file mode 100644
index 00000000000..d4c8752c6aa
--- /dev/null
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_csr_equ_m.svh.html
@@ -0,0 +1,573 @@
+
+
+
+
+    
+    
+        Full
+        coverage report
+    
+    
+    
+
+
+
+    
+        
+    

+            
+                
+                
+            

+                    Project
+                    Full
+                    coverage report
+                

+        

+    

+        
+            
+                
+                
+                
+                
+                
+                
+                
+            
+            
+                
+                
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+                
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+    
+
+            
+            
+                
+                
+                
+                
+    
+    
+    
+    
+
+            
+            
+        
Current view:
+                    Cores-VeeR-EL2—Cores-VeeR-EL2—design—include—el2_dec_csr_equ_m.svh
+                CoverageHitTotal
Test Date:
+                    25-09-2024
+                
+        Toggle
+    
+        8.3%
+    
+        7
+    
+        84
+    
Test:
+                    ahb_modesw
+                
+        Branch
+    
+        0.0%
+    
+        0
+    
+        0
+    

+    

+
+    
+
+
+
+
+
+
+


+
            Line data    Source code

+
+       1            4 : logic csr_misa;
+       2            0 : logic csr_mvendorid;
+       3            0 : logic csr_marchid;
+       4            0 : logic csr_mimpid;
+       5            0 : logic csr_mhartid;
+       6           18 : logic csr_mstatus;
+       7            4 : logic csr_mtvec;
+       8            0 : logic csr_mip;
+       9            0 : logic csr_mie;
+      10            0 : logic csr_mcyclel;
+      11            0 : logic csr_mcycleh;
+      12            0 : logic csr_minstretl;
+      13            0 : logic csr_minstreth;
+      14            0 : logic csr_mscratch;
+      15            0 : logic csr_mepc;
+      16            0 : logic csr_mcause;
+      17            0 : logic csr_mscause;
+      18            0 : logic csr_mtval;
+      19            0 : logic csr_mrac;
+      20            0 : logic csr_dmst;
+      21            0 : logic csr_mdseac;
+      22            0 : logic csr_meihap;
+      23            0 : logic csr_meivt;
+      24            0 : logic csr_meipt;
+      25            0 : logic csr_meicurpl;
+      26            0 : logic csr_meicidpl;
+      27            0 : logic csr_dcsr;
+      28            0 : logic csr_mcgc;
+      29            0 : logic csr_mfdc;
+      30            0 : logic csr_dpc;
+      31            0 : logic csr_mtsel;
+      32            0 : logic csr_mtdata1;
+      33            0 : logic csr_mtdata2;
+      34            0 : logic csr_mhpmc3;
+      35            0 : logic csr_mhpmc4;
+      36            0 : logic csr_mhpmc5;
+      37            0 : logic csr_mhpmc6;
+      38            0 : logic csr_mhpmc3h;
+      39            0 : logic csr_mhpmc4h;
+      40            0 : logic csr_mhpmc5h;
+      41            0 : logic csr_mhpmc6h;
+      42            0 : logic csr_mhpme3;
+      43            0 : logic csr_mhpme4;
+      44            0 : logic csr_mhpme5;
+      45            0 : logic csr_mhpme6;
+      46            0 : logic csr_mcountinhibit;
+      47            0 : logic csr_mitctl0;
+      48            0 : logic csr_mitctl1;
+      49            0 : logic csr_mitb0;
+      50            0 : logic csr_mitb1;
+      51            0 : logic csr_mitcnt0;
+      52            0 : logic csr_mitcnt1;
+      53            0 : logic csr_perfva;
+      54            0 : logic csr_perfvb;
+      55            0 : logic csr_perfvc;
+      56            0 : logic csr_perfvd;
+      57            0 : logic csr_perfve;
+      58            0 : logic csr_perfvf;
+      59            0 : logic csr_perfvg;
+      60            0 : logic csr_perfvh;
+      61            0 : logic csr_perfvi;
+      62            0 : logic csr_mpmc;
+      63            0 : logic csr_mcpc;
+      64            0 : logic csr_meicpct;
+      65            0 : logic csr_mdeau;
+      66            0 : logic csr_micect;
+      67            0 : logic csr_miccmect;
+      68            0 : logic csr_mdccmect;
+      69            0 : logic csr_mfdht;
+      70            0 : logic csr_mfdhs;
+      71            0 : logic csr_dicawics;
+      72            0 : logic csr_dicad0h;
+      73            0 : logic csr_dicad0;
+      74            0 : logic csr_dicad1;
+      75            0 : logic csr_dicago;
+      76            4 : logic csr_pmpcfg;
+      77            4 : logic csr_pmpaddr0;
+      78            0 : logic csr_pmpaddr16;
+      79            0 : logic csr_pmpaddr32;
+      80            0 : logic csr_pmpaddr48;
+      81            0 : logic valid_only;
+      82            0 : logic presync;
+      83           14 : logic postsync;
+      84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+      85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+      86              : 
+      87              : assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+      88              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+      89              : 
+      90              : assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+      91              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+      92              : 
+      93              : assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]
+      94              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+      95              : 
+      96              : assign csr_mhartid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+      97              :     &dec_csr_rdaddr_d[2]);
+      98              : 
+      99              : assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     100              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);
+     101              : 
+     102              : assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     103              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     104              : 
+     105              : assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]);
+     106              : 
+     107              : assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     108              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);
+     109              : 
+     110              : assign csr_mcyclel = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     111              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     112              :     &!dec_csr_rdaddr_d[1]);
+     113              : 
+     114              : assign csr_mcycleh = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     115              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     116              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     117              : 
+     118              : assign csr_minstretl = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     119              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     120              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     121              : 
+     122              : assign csr_minstreth = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     123              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     124              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     125              : 
+     126              : assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     127              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     128              : 
+     129              : assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     130              :     &dec_csr_rdaddr_d[0]);
+     131              : 
+     132              : assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     133              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     134              : 
+     135              : assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     136              :     &dec_csr_rdaddr_d[2]);
+     137              : 
+     138              : assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[1]
+     139              :     &dec_csr_rdaddr_d[0]);
+     140              : 
+     141              : assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     142              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     143              :     &!dec_csr_rdaddr_d[1]);
+     144              : 
+     145              : assign csr_dmst = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     146              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     147              : 
+     148              : assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     149              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]);
+     150              : 
+     151              : assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     152              :     &dec_csr_rdaddr_d[3]);
+     153              : 
+     154              : assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     155              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     156              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     157              : 
+     158              : assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     159              :     &dec_csr_rdaddr_d[0]);
+     160              : 
+     161              : assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     162              :     &dec_csr_rdaddr_d[2]);
+     163              : 
+     164              : assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     165              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     166              : 
+     167              : assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     168              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);
+     169              : 
+     170              : assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     171              :     &!dec_csr_rdaddr_d[0]);
+     172              : 
+     173              : assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     174              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     175              : 
+     176              : assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     177              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
+     178              : 
+     179              : assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     180              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     181              : 
+     182              : assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     183              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
+     184              : 
+     185              : assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     186              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);
+     187              : 
+     188              : assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     189              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     190              :     &dec_csr_rdaddr_d[0]);
+     191              : 
+     192              : assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     193              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     194              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     195              : 
+     196              : assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     197              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     198              :     &dec_csr_rdaddr_d[0]);
+     199              : 
+     200              : assign csr_mhpmc6 = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]
+     201              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     202              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     203              : 
+     204              : assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     205              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     206              :     &dec_csr_rdaddr_d[0]);
+     207              : 
+     208              : assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     209              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     210              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     211              : 
+     212              : assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     213              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     214              :     &dec_csr_rdaddr_d[0]);
+     215              : 
+     216              : assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
+     217              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     218              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     219              : 
+     220              : assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     221              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     222              :     &dec_csr_rdaddr_d[0]);
+     223              : 
+     224              : assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     225              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     226              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     227              : 
+     228              : assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     229              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     230              :     &dec_csr_rdaddr_d[0]);
+     231              : 
+     232              : assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     233              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
+     234              :     &!dec_csr_rdaddr_d[0]);
+     235              : 
+     236              : assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     237              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     238              :     &!dec_csr_rdaddr_d[0]);
+     239              : 
+     240              : assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     241              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
+     242              :     &!dec_csr_rdaddr_d[0]);
+     243              : 
+     244              : assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]
+     245              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     246              : 
+     247              : assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
+     248              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     249              : 
+     250              : assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
+     251              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     252              : 
+     253              : assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     254              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
+     255              :     &!dec_csr_rdaddr_d[0]);
+     256              : 
+     257              : assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[2]
+     258              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     259              : 
+     260              : assign csr_perfva  = 1'b0;
+     261              : 
+     262              : assign csr_perfvb  = 1'b0;
+     263              : 
+     264              : assign csr_perfvc  = 1'b0;
+     265              : 
+     266              : assign csr_perfvd  = 1'b0;
+     267              : 
+     268              : assign csr_perfve  = 1'b0;
+     269              : 
+     270              : assign csr_perfvf  = 1'b0;
+     271              : 
+     272              : assign csr_perfvg  = 1'b0;
+     273              : 
+     274              : assign csr_perfvh  = 1'b0;
+     275              : 
+     276              : assign csr_perfvi  = 1'b0;
+     277              : 
+     278              : assign csr_mpmc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     279              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     280              : 
+     281              : assign csr_mcpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     282              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     283              : 
+     284              : assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     285              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     286              : 
+     287              : assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     288              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
+     289              : 
+     290              : assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     291              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     292              : 
+     293              : assign csr_miccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     294              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
+     295              : 
+     296              : assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     297              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     298              : 
+     299              : assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     300              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     301              : 
+     302              : assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     303              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     304              : 
+     305              : assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     306              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     307              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     308              : 
+     309              : assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     310              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     311              : 
+     312              : assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     313              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     314              : 
+     315              : assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     316              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     317              : 
+     318              : assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     319              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     320              : 
+     321              : assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     322              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
+     323              : 
+     324              : assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     325              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
+     326              : 
+     327              : assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     328              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
+     329              : 
+     330              : assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     331              :     &dec_csr_rdaddr_d[4]);
+     332              : 
+     333              : assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     334              :     &!dec_csr_rdaddr_d[4]);
+     335              : 
+     336              : assign valid_only = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[2]
+     337              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[7]
+     338              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
+     339              :     !dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[4]) | (
+     340              :     !dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (
+     341              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+     342              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[3]);
+     343              : 
+     344              : assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     345              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     346              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     347              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
+     348              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     349              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     350              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | (
+     351              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     352              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]
+     353              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     354              :     &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
+     355              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     356              : 
+     357              : assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     358              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     359              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]
+     360              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     361              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     362              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     363              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | (
+     364              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]
+     365              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
+     366              :     dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
+     368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     369              : 
+     370           16 : logic legal;
+     371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     374              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
+     375              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     376              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     377              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     378              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     379              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     380              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     381              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     382              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     383              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     384              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
+     385              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     386              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (
+     387              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     388              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     389              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
+     390              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     391              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     392              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     393              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     394              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     395              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]
+     396              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     397              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     398              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     399              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     400              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     401              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     402              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
+     403              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     404              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     405              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     406              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
+     407              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     408              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     409              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     410              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     411              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     412              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     413              :     &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
+     414              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     415              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     416              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     417              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     418              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     419              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     420              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     421              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     422              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     423              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     424              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
+     425              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     426              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]
+     427              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     428              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     429              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     430              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     431              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     432              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[9]
+     433              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     434              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
+     435              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     436              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     437              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     438              :     &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     439              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     440              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
+     441              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     442              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     443              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     444              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     445              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     446              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
+     447              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     448              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     449              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
+     450              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     451              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     452              :     &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     453              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     454              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]
+     455              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     456              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
+     457              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     458              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     459              :     &dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     460              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     461              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);
+     462              : 
+        

+

+
+
+
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_csr_equ_mu.svh.html
deleted file mode 100644
index e83d323b9c7..00000000000
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_csr_equ_mu.svh.html
+++ /dev/null
@@ -1,666 +0,0 @@
-
-
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-    
-    
-        Full
-        coverage report
-    
-    
-    
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-    
-        
-    

-            
-                
-                
-            

-                    Project
-                    Full
-                    coverage report
-                

-        

-    

-        
-            
-                
-                
-                
-                
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-            
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-            
-            
-        
Current view:
-                    Cores-VeeR-EL2—Cores-VeeR-EL2—design—include—el2_dec_csr_equ_mu.svh
-                CoverageHitTotal
Test Date:
-                    19-09-2024
-                
-        Toggle
-    
-        9.9%
-    
-        10
-    
-        101
-    
Test:
-                    ahb_modesw
-                
-        Branch
-    
-        0.0%
-    
-        0
-    
-        0
-    

-    

-
-    
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-


-
            Line data    Source code

-
-       1            4 : logic csr_misa;
-       2            0 : logic csr_mvendorid;
-       3            0 : logic csr_marchid;
-       4            0 : logic csr_mimpid;
-       5            0 : logic csr_mhartid;
-       6          166 : logic csr_mstatus;
-       7            4 : logic csr_mtvec;
-       8            0 : logic csr_mip;
-       9            0 : logic csr_mie;
-      10            0 : logic csr_mcyclel;
-      11            0 : logic csr_mcycleh;
-      12            0 : logic csr_minstretl;
-      13            0 : logic csr_minstreth;
-      14            0 : logic csr_mscratch;
-      15           76 : logic csr_mepc;
-      16           72 : logic csr_mcause;
-      17            0 : logic csr_mscause;
-      18            0 : logic csr_mtval;
-      19            0 : logic csr_mrac;
-      20            0 : logic csr_dmst;
-      21            0 : logic csr_mdseac;
-      22            0 : logic csr_meihap;
-      23            0 : logic csr_meivt;
-      24            0 : logic csr_meipt;
-      25            0 : logic csr_meicurpl;
-      26            0 : logic csr_meicidpl;
-      27            0 : logic csr_dcsr;
-      28            0 : logic csr_mcgc;
-      29            0 : logic csr_mfdc;
-      30            0 : logic csr_dpc;
-      31            0 : logic csr_mtsel;
-      32            0 : logic csr_mtdata1;
-      33            0 : logic csr_mtdata2;
-      34            0 : logic csr_mhpmc3;
-      35            0 : logic csr_mhpmc4;
-      36            0 : logic csr_mhpmc5;
-      37            0 : logic csr_mhpmc6;
-      38            0 : logic csr_mhpmc3h;
-      39            0 : logic csr_mhpmc4h;
-      40            0 : logic csr_mhpmc5h;
-      41            0 : logic csr_mhpmc6h;
-      42            0 : logic csr_mhpme3;
-      43            0 : logic csr_mhpme4;
-      44            0 : logic csr_mhpme5;
-      45            0 : logic csr_mhpme6;
-      46            0 : logic csr_mcounteren;
-      47            0 : logic csr_mcountinhibit;
-      48            0 : logic csr_mitctl0;
-      49            0 : logic csr_mitctl1;
-      50            0 : logic csr_mitb0;
-      51            0 : logic csr_mitb1;
-      52            0 : logic csr_mitcnt0;
-      53            0 : logic csr_mitcnt1;
-      54            0 : logic csr_perfva;
-      55            0 : logic csr_perfvb;
-      56            0 : logic csr_perfvc;
-      57            0 : logic csr_perfvd;
-      58            0 : logic csr_perfve;
-      59            0 : logic csr_perfvf;
-      60            0 : logic csr_perfvg;
-      61            0 : logic csr_perfvh;
-      62            0 : logic csr_perfvi;
-      63            0 : logic csr_mpmc;
-      64            0 : logic csr_mcpc;
-      65            0 : logic csr_meicpct;
-      66            0 : logic csr_mdeau;
-      67            0 : logic csr_micect;
-      68            0 : logic csr_miccmect;
-      69            0 : logic csr_mdccmect;
-      70            0 : logic csr_mfdht;
-      71            0 : logic csr_mfdhs;
-      72            0 : logic csr_dicawics;
-      73            0 : logic csr_dicad0h;
-      74            0 : logic csr_dicad0;
-      75            0 : logic csr_dicad1;
-      76            0 : logic csr_dicago;
-      77            0 : logic csr_menvcfg;
-      78            0 : logic csr_menvcfgh;
-      79            4 : logic csr_pmpcfg;
-      80            4 : logic csr_pmpaddr0;
-      81            0 : logic csr_pmpaddr16;
-      82            0 : logic csr_pmpaddr32;
-      83            0 : logic csr_pmpaddr48;
-      84          234 : logic csr_cyclel;
-      85            0 : logic csr_cycleh;
-      86            0 : logic csr_instretl;
-      87            0 : logic csr_instreth;
-      88            0 : logic csr_hpmc3;
-      89            0 : logic csr_hpmc4;
-      90            0 : logic csr_hpmc5;
-      91            0 : logic csr_hpmc6;
-      92            0 : logic csr_hpmc3h;
-      93            0 : logic csr_hpmc4h;
-      94            0 : logic csr_hpmc5h;
-      95            0 : logic csr_hpmc6h;
-      96            0 : logic csr_mseccfgl;
-      97            0 : logic csr_mseccfgh;
-      98            0 : logic valid_only;
-      99            0 : logic presync;
-     100           86 : logic postsync;
-     101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     103              : 
-     104              : assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     105              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     106              : 
-     107              : assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     108              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     109              : 
-     110              : assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]
-     111              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     112              : 
-     113              : assign csr_mhartid = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     114              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]);
-     115              : 
-     116              : assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     117              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
-     118              :     &!dec_csr_rdaddr_d[0]);
-     119              : 
-     120              : assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     121              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     122              : 
-     123              : assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
-     124              :     &!dec_csr_rdaddr_d[0]);
-     125              : 
-     126              : assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     127              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     128              : 
-     129              : assign csr_mcyclel = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     130              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     131              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     132              : 
-     133              : assign csr_mcycleh = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     134              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     135              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     136              : 
-     137              : assign csr_minstretl = (dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     138              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     139              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     140              : 
-     141              : assign csr_minstreth = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     142              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     143              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     144              : 
-     145              : assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     146              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     147              : 
-     148              : assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     149              :     &dec_csr_rdaddr_d[0]);
-     150              : 
-     151              : assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     152              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     153              : 
-     154              : assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     155              :     &dec_csr_rdaddr_d[2]);
-     156              : 
-     157              : assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[2]
-     158              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     159              : 
-     160              : assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     161              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     162              :     &!dec_csr_rdaddr_d[1]);
-     163              : 
-     164              : assign csr_dmst = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
-     165              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     166              : 
-     167              : assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     168              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
-     169              : 
-     170              : assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     171              :     &dec_csr_rdaddr_d[3]);
-     172              : 
-     173              : assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     174              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     175              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     176              : 
-     177              : assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     178              :     &dec_csr_rdaddr_d[0]);
-     179              : 
-     180              : assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     181              :     &dec_csr_rdaddr_d[2]);
-     182              : 
-     183              : assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     184              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     185              : 
-     186              : assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     187              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);
-     188              : 
-     189              : assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     190              :     &!dec_csr_rdaddr_d[0]);
-     191              : 
-     192              : assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     193              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     194              : 
-     195              : assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     196              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
-     197              : 
-     198              : assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     199              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     200              : 
-     201              : assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     202              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
-     203              : 
-     204              : assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     205              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);
-     206              : 
-     207              : assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     208              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     209              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     210              : 
-     211              : assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     212              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     213              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     214              : 
-     215              : assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     216              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     217              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     218              : 
-     219              : assign csr_mhpmc6 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
-     220              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     221              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     222              : 
-     223              : assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     224              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     225              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     226              : 
-     227              : assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     228              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     229              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     230              : 
-     231              : assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     232              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     233              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     234              : 
-     235              : assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     236              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     237              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     238              : 
-     239              : assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     240              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     241              :     &dec_csr_rdaddr_d[0]);
-     242              : 
-     243              : assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     244              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     245              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     246              : 
-     247              : assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     248              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
-     249              :     &dec_csr_rdaddr_d[0]);
-     250              : 
-     251              : assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     252              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
-     253              :     &!dec_csr_rdaddr_d[0]);
-     254              : 
-     255              : assign csr_mcounteren = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     256              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     257              : 
-     258              : assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
-     259              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     260              :     &!dec_csr_rdaddr_d[0]);
-     261              : 
-     262              : assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     263              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
-     264              :     &!dec_csr_rdaddr_d[0]);
-     265              : 
-     266              : assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     267              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     268              :     &dec_csr_rdaddr_d[0]);
-     269              : 
-     270              : assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
-     271              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     272              : 
-     273              : assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
-     274              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     275              : 
-     276              : assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     277              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
-     278              :     &!dec_csr_rdaddr_d[0]);
-     279              : 
-     280              : assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]
-     281              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     282              : 
-     283              : assign csr_perfva  = 1'b0;
-     284              : 
-     285              : assign csr_perfvb  = 1'b0;
-     286              : 
-     287              : assign csr_perfvc  = 1'b0;
-     288              : 
-     289              : assign csr_perfvd  = 1'b0;
-     290              : 
-     291              : assign csr_perfve  = 1'b0;
-     292              : 
-     293              : assign csr_perfvf  = 1'b0;
-     294              : 
-     295              : assign csr_perfvg  = 1'b0;
-     296              : 
-     297              : assign csr_perfvh  = 1'b0;
-     298              : 
-     299              : assign csr_perfvi  = 1'b0;
-     300              : 
-     301              : assign csr_mpmc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     302              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     303              :     &dec_csr_rdaddr_d[1]);
-     304              : 
-     305              : assign csr_mcpc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
-     306              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     307              : 
-     308              : assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
-     309              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     310              : 
-     311              : assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     312              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
-     313              : 
-     314              : assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     315              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     316              : 
-     317              : assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     318              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
-     319              : 
-     320              : assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
-     321              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     322              : 
-     323              : assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     324              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     325              : 
-     326              : assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
-     327              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
-     328              : 
-     329              : assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     330              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     331              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     332              : 
-     333              : assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     334              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     335              : 
-     336              : assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
-     337              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     338              : 
-     339              : assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     340              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     341              : 
-     342              : assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
-     343              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     344              : 
-     345              : assign csr_menvcfg = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     346              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]);
-     347              : 
-     348              : assign csr_menvcfgh = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
-     349              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
-     350              : 
-     351              : assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     352              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
-     353              : 
-     354              : assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
-     355              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
-     356              : 
-     357              : assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     358              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
-     359              : 
-     360              : assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
-     361              :     &dec_csr_rdaddr_d[4]);
-     362              : 
-     363              : assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     364              :     &!dec_csr_rdaddr_d[4]);
-     365              : 
-     366              : assign csr_cyclel = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     367              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     368              : 
-     369              : assign csr_cycleh = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     370              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
-     371              : 
-     372              : assign csr_instretl = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     373              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     374              : 
-     375              : assign csr_instreth = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     376              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     377              : 
-     378              : assign csr_hpmc3 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     379              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     380              : 
-     381              : assign csr_hpmc4 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     382              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     383              : 
-     384              : assign csr_hpmc5 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     385              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     386              : 
-     387              : assign csr_hpmc6 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     388              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     389              : 
-     390              : assign csr_hpmc3h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     391              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     392              : 
-     393              : assign csr_hpmc4h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     394              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
-     395              : 
-     396              : assign csr_hpmc5h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     397              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
-     398              : 
-     399              : assign csr_hpmc6h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     400              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     401              : 
-     402              : assign csr_mseccfgl = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
-     403              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]);
-     404              : 
-     405              : assign csr_mseccfgh = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     406              :     &dec_csr_rdaddr_d[4]);
-     407              : 
-     408              : assign valid_only = (!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     409              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (
-     410              :     !dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
-     411              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
-     412              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[7]
-     413              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
-     414              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
-     415              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]);
-     416              : 
-     417              : assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     418              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
-     419              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     420              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
-     421              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
-     422              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     423              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
-     424              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
-     425              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
-     426              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
-     427              :     dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     428              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
-     429              : 
-     430              : assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
-     431              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     432              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]
-     433              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
-     434              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     435              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
-     436              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
-     437              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]
-     438              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
-     439              :     dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[4]
-     440              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
-     441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
-     442              :     &dec_csr_rdaddr_d[0]);
-     443              : 
-     444          232 : logic legal;
-     445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     448              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
-     449              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     450              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     451              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     452              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     453              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     454              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     455              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     456              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     457              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     458              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     459              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     460              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     461              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     462              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]
-     463              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     464              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
-     465              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     466              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     467              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
-     468              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     469              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (
-     470              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     471              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
-     472              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     473              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     474              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     475              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
-     476              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     477              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (
-     478              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]
-     479              :     &!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     480              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
-     481              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     482              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     483              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     484              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     485              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
-     486              :     &!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     487              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     488              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
-     489              :     &dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]
-     490              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     491              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     492              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     493              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     494              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
-     495              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     496              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     497              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
-     498              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     499              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     500              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (
-     501              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     502              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     503              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
-     504              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
-     505              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     506              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     507              :     &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
-     508              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
-     509              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
-     510              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
-     511              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     512              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
-     513              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     514              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     515              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     516              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
-     517              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     518              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     519              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
-     520              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
-     521              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-     522              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
-     523              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     524              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     525              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[9]
-     526              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
-     527              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
-     528              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
-     529              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     530              :     &!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     531              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
-     532              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     533              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     534              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
-     535              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
-     536              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-     537              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
-     538              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     539              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     540              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
-     541              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     542              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     543              :     &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     544              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     545              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]
-     546              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     547              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
-     548              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
-     549              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-     550              :     &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
-     551              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
-     552              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]
-     553              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
-     554              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);
-     555              : 
-        

-

-
-
-
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_decode_ctl.sv.html
index 9d955704bb7..0bb24da1055 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_decode_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        64.7%
+    
+        56.0%
     
     
-        178
+        154
     
     
         275
@@ -133,21 +133,21 @@
       29              : 
       30            0 :    output logic dec_extint_stall,            // Stall from external interrupt
       31              : 
-      32         5200 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
-      33         4198 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
+      32          166 :    input  logic [15:0] ifu_i0_cinst,         // 16b compressed instruction
+      33            8 :    output logic [31:0] dec_i0_inst_wb,       // 32b instruction at wb+1 for trace encoder
       34            2 :    output logic [31:1] dec_i0_pc_wb,         // 31b pc at wb+1 for trace encoder
       35              : 
       36              : 
-      37         6024 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
-      38         2428 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
+      37          224 :    input logic                                lsu_nonblock_load_valid_m,       // valid nonblock load at m
+      38          216 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_tag_m,         // -> corresponding tag
       39            0 :    input logic                                lsu_nonblock_load_inv_r,         // invalidate request for nonblock load r
-      40         2428 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
-      41         6192 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
+      40          216 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_inv_tag_r,     // -> corresponding tag
+      41          224 :    input logic                                lsu_nonblock_load_data_valid,    // valid nonblock load data back
       42            0 :    input logic                                lsu_nonblock_load_data_error,    // nonblock load bus error
-      43           48 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
+      43            0 :    input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]  lsu_nonblock_load_data_tag,      // -> corresponding tag
       44              : 
       45              : 
-      46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
+      46            0 :    input logic [3:0] dec_i0_trigger_match_d,          // i0 decode trigger matches
       47              : 
       48            0 :    input logic dec_tlu_wr_pause_r,                    // pause instruction at r
       49            0 :    input logic dec_tlu_pipelining_disable,            // pipeline disable - presync, i0 decode only
@@ -168,139 +168,139 @@
       64              : 
       65            0 :    input logic dec_i0_dbecc_d,                        // icache/iccm double-bit error
       66              : 
-      67          256 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
-      68         1124 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69        11398 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      67            4 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
+      68           24 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      69           10 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
-      73         8690 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
+      73          232 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
       74              : 
-      75           28 :    input logic lsu_load_stall_any,                    // stall any load at decode
-      76           28 :    input logic lsu_store_stall_any,                   // stall any store at decode
-      77            0 :    input logic dma_dccm_stall_any,                    // stall any load/store at decode
+      75            0 :    input logic lsu_load_stall_any,                    // stall any load at decode
+      76            0 :    input logic lsu_store_stall_any,                   // stall any store at decode
+      77            0 :    input logic dma_dccm_stall_any,                    // stall any load/store at decode
       78              : 
-      79           48 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
+      79            0 :    input logic exu_div_wren,                          // nonblocking divide write enable to GPR.
       80              : 
-      81            0 :    input logic dec_tlu_i0_kill_writeb_wb,             // I0 is flushed, don't writeback any results to arch state
-      82           56 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
+      81            0 :    input logic dec_tlu_i0_kill_writeb_wb,             // I0 is flushed, don't writeback any results to arch state
+      82            4 :    input logic dec_tlu_flush_lower_wb,                // trap lower flush
       83            0 :    input logic dec_tlu_i0_kill_writeb_r,              // I0 is flushed, don't writeback any results to arch state
-      84           56 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
+      84            4 :    input logic dec_tlu_flush_lower_r,                 // trap lower flush
       85            0 :    input logic dec_tlu_flush_pause_r,                 // don't clear pause state on initial lower flush
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
-      87          148 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
+      87            4 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89        17896 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89          310 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91            4 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
-      92          232 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
+      91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
       95              : 
       96            0 :    input logic [31:0] lsu_result_m,                   // load result
       97            0 :    input logic [31:0] lsu_result_corr_r,              // load result - corrected data for writing gpr's, not for bypassing
       98              : 
-      99         1596 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
+      99           68 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
      100              : 
      101            2 :    input logic [31:1] exu_i0_pc_x,                    // pcs at e1
      102              : 
-     103          760 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
+     103           12 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
      104              : 
-     105        33540 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
+     105          608 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
      106              : 
-     107          764 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
+     107           16 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109       583434 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110       583434 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111       583434 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109        12564 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110        12564 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111        12564 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
      115              : 
      116              : 
      117              : 
-     118        28768 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
-     119        15504 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
+     118          548 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
+     119          232 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
-     121         9336 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122         9536 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     121           12 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
+     122           28 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124         1752 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124           20 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
-     127         1180 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
+     127           12 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
      128              : 
      129            0 :    output el2_alu_pkt_t i0_ap,                       // alu packets
      130              : 
-     131        35132 :    output logic        dec_i0_decode_d,               // i0 decode
+     131          816 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
-     133        24544 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134        12188 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     133          376 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
+     134          448 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
-     136        10592 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137        17236 :    output logic        dec_i0_wen_r,                  // i0 write enable
-     138           40 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
+     136          216 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
+     137          308 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     138           12 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
-     140          936 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
+     140           24 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
      141              : 
-     142         1072 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
+     142            4 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
      143            0 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
-     144           40 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
+     144           12 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
      145              : 
-     146         2612 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
-     147        25590 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
+     146           16 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
+     147          582 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
      148              : 
      149            0 :    output el2_mul_pkt_t    mul_p,                    // multiply packet
      150              : 
-     151           24 :    output el2_div_pkt_t    div_p,                    // divide packet
-     152            2 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
-     153            0 :    output logic             dec_div_cancel,           // cancel the divide operation
+     151            0 :    output el2_div_pkt_t    div_p,                    // divide packet
+     152            0 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
+     153            0 :    output logic             dec_div_cancel,           // cancel the divide operation
      154              : 
-     155        11872 :    output logic        dec_lsu_valid_raw_d,
-     156          400 :    output logic [11:0] dec_lsu_offset_d,
+     155          452 :    output logic        dec_lsu_valid_raw_d,
+     156            0 :    output logic [11:0] dec_lsu_offset_d,
      157              : 
-     158          172 :    output logic        dec_csr_ren_d,                 // valid csr decode
-     159           60 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
-     160          232 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
-     161            4 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
-     162           60 :    output logic        dec_csr_wen_r,                 // csr write enable at r
-     163         7568 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
-     164            4 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
+     158            4 :    output logic        dec_csr_ren_d,                 // valid csr decode
+     159           12 :    output logic        dec_csr_wen_unq_d,             // valid csr with write - for csr legal
+     160           16 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
+     161            8 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
+     162           12 :    output logic        dec_csr_wen_r,                 // csr write enable at r
+     163           24 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
+     164            8 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
      165            4 :    output logic [31:0] dec_csr_wrdata_r,              // csr write data at r
-     166           20 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
+     166            0 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
      167              : 
-     168        35132 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
+     168          816 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
      169              : 
      170            0 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
      171              : 
      172            2 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
      173              : 
      174            0 :    output logic [31:0] dec_illegal_inst,              // illegal inst
-     175          922 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
+     175           28 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
-     177         2738 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178        11398 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
-     179         1124 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
+     177            4 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
+     178           10 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     179           24 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      183              : 
-     184        35132 :    output logic [1:0] dec_data_en,                    // clock-gating logic
-     185        35128 :    output logic [1:0] dec_ctl_en,
+     184          816 :    output logic [1:0] dec_data_en,                    // clock-gating logic
+     185          816 :    output logic [1:0] dec_ctl_en,
      186              : 
-     187        35132 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
-     188         1764 :    output logic       dec_pmu_decode_stall,           // decode is stalled
+     187          816 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
+     188          208 :    output logic       dec_pmu_decode_stall,           // decode is stalled
      189            0 :    output logic       dec_pmu_presync_stall,          // decode has presync stall
-     190            8 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
+     190            0 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
      191              : 
-     192         6192 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
-     193          916 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
-     194            0 :    output logic       dec_pause_state,                // core in pause state
+     192          224 :    output logic       dec_nonblock_load_wen,          // write enable for nonblock load
+     193            0 :    output logic [4:0] dec_nonblock_load_waddr,        // logical write addr for nonblock load
+     194            0 :    output logic       dec_pause_state,                // core in pause state
      195            0 :    output logic       dec_pause_state_cg,             // pause state for clock-gating
      196              : 
-     197           48 :    output logic       dec_div_active,                 // non-block divide is active
+     197            0 :    output logic       dec_div_active,                 // non-block divide is active
      198              : 
-     199            0 :    input  logic       scan_mode
+     199            0 :    input  logic       scan_mode
      200              :    );
      201              : 
      202              : 
@@ -308,27 +308,27 @@
      204              : 
      205            0 :    el2_dec_pkt_t           i0_dp_raw, i0_dp;
      206              : 
-     207          760 :    logic [31:0]        i0;
-     208        33540 :    logic               i0_valid_d;
+     207           12 :    logic [31:0]        i0;
+     208          608 :    logic               i0_valid_d;
      209              : 
-     210           40 :    logic [31:0]        i0_result_r;
+     210           12 :    logic [31:0]        i0_result_r;
      211              : 
-     212          140 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
+     212            0 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
      213              : 
-     214          760 :    logic               i0_jalimm20;
-     215          720 :    logic               i0_uiimm20;
+     214           12 :    logic               i0_jalimm20;
+     215           24 :    logic               i0_uiimm20;
      216              : 
-     217        11872 :    logic               lsu_decode_d;
-     218         1752 :    logic [31:0]        i0_immed_d;
+     217          452 :    logic               lsu_decode_d;
+     218           20 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
-     220         2292 :    logic               i0_postsync;
+     220          208 :    logic               i0_postsync;
      221              : 
-     222          200 :    logic               postsync_stall;
-     223          200 :    logic               ps_stall;
+     222            4 :    logic               postsync_stall;
+     223            4 :    logic               ps_stall;
      224              : 
-     225        35128 :    logic               prior_inflight, prior_inflight_wb;
+     225          816 :    logic               prior_inflight, prior_inflight_wb;
      226              : 
-     227           60 :    logic               csr_clr_d, csr_set_d, csr_write_d;
+     227           12 :    logic               csr_clr_d, csr_set_d, csr_write_d;
      228              : 
      229            0 :    logic               csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
      230            0 :    logic [31:0]        csr_mask_x;
@@ -342,58 +342,58 @@
      238            0 :    logic [31:0]        csr_rddata_x;
      239              : 
      240            0 :    logic               mul_decode_d;
-     241           48 :    logic               div_decode_d;
-     242           48 :    logic               div_e1_to_r;
-     243            0 :    logic               div_flush;
-     244           48 :    logic               div_active_in;
-     245           48 :    logic               div_active;
-     246            0 :    logic               i0_nonblock_div_stall;
+     241            0 :    logic               div_decode_d;
+     242            0 :    logic               div_e1_to_r;
+     243            0 :    logic               div_flush;
+     244            0 :    logic               div_active_in;
+     245            0 :    logic               div_active;
+     246            0 :    logic               i0_nonblock_div_stall;
      247            0 :    logic               i0_div_prior_div_stall;
      248            0 :    logic               nonblock_div_cancel;
      249              : 
-     250        31564 :    logic               i0_legal;
+     250          404 :    logic               i0_legal;
      251            0 :    logic               shift_illegal;
      252            0 :    logic               illegal_inst_en;
      253            0 :    logic               illegal_lockout_in, illegal_lockout;
-     254        35132 :    logic               i0_legal_decode_d;
-     255         1956 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
+     254          816 :    logic               i0_legal_decode_d;
+     255          212 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
-     257         6256 :    logic [12:1]        last_br_immed_d;
-     258         1588 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
+     257          176 :    logic [12:1]        last_br_immed_d;
+     258          208 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
-     261           48 :    logic               i0_div_decode_d;
-     262            0 :    logic               i0_load_block_d;
+     261            0 :    logic               i0_div_decode_d;
+     262            0 :    logic               i0_load_block_d;
      263            0 :    logic [1:0]         i0_rs1_depth_d, i0_rs2_depth_d;
      264              : 
-     265           28 :    logic               i0_load_stall_d;
-     266            0 :    logic               i0_store_stall_d;
+     265            0 :    logic               i0_load_stall_d;
+     266            0 :    logic               i0_store_stall_d;
      267              : 
-     268         4864 :    logic               i0_predict_nt, i0_predict_t;
+     268           68 :    logic               i0_predict_nt, i0_predict_t;
      269              : 
-     270         1980 :    logic               i0_notbr_error, i0_br_toffset_error;
+     270          172 :    logic               i0_notbr_error, i0_br_toffset_error;
      271            0 :    logic               i0_ret_error;
-     272         2092 :    logic               i0_br_error;
-     273         2092 :    logic               i0_br_error_all;
-     274         7628 :    logic [11:0]        i0_br_offset;
+     272          204 :    logic               i0_br_error;
+     273          204 :    logic               i0_br_error_all;
+     274          224 :    logic [11:0]        i0_br_offset;
      275              : 
-     276         4560 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
-     277        29810 :    logic               i0_pcall_12b_offset;
-     278          284 :    logic               i0_pcall_raw;
-     279          288 :    logic               i0_pcall_case;
-     280          284 :    logic               i0_pcall;
+     276           12 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
+     277          578 :    logic               i0_pcall_12b_offset;
+     278            8 :    logic               i0_pcall_raw;
+     279           12 :    logic               i0_pcall_case;
+     280            8 :    logic               i0_pcall;
      281              : 
-     282          476 :    logic               i0_pja_raw;
-     283          480 :    logic               i0_pja_case;
-     284          476 :    logic               i0_pja;
+     282            4 :    logic               i0_pja_raw;
+     283            8 :    logic               i0_pja_case;
+     284            4 :    logic               i0_pja;
      285              : 
-     286          280 :    logic               i0_pret_case;
-     287          280 :    logic               i0_pret_raw, i0_pret;
+     286            8 :    logic               i0_pret_case;
+     287            8 :    logic               i0_pret_raw, i0_pret;
      288              : 
-     289          168 :    logic               i0_jal;                                // jal's that are not predicted
+     289            0 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292         9928 :    logic               i0_predict_br;
+     292          244 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301        17896 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301          310 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303        22752 :    logic               i0_rd_en_d;
+     303          528 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -412,43 +412,43 @@
      308            0 :    logic               leak1_i1_stall_in, leak1_i1_stall;
      309            0 :    logic               leak1_mode;
      310              : 
-     311           60 :    logic               i0_csr_write_only_d;
+     311           12 :    logic               i0_csr_write_only_d;
      312              : 
-     313        35128 :    logic               prior_inflight_x, prior_inflight_eff;
-     314          232 :    logic               any_csr_d;
+     313          816 :    logic               prior_inflight_x, prior_inflight_eff;
+     314           16 :    logic               any_csr_d;
      315              : 
-     316           60 :    logic               prior_csr_write;
+     316           12 :    logic               prior_csr_write;
      317              : 
-     318        35132 :    logic [3:0]        i0_pipe_en;
-     319        35128 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
-     320        35132 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
+     318          816 :    logic [3:0]        i0_pipe_en;
+     319          816 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
+     320          816 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
      321              : 
      322            0 :    logic              debug_fence_i;
      323            0 :    logic              debug_fence;
      324              : 
-     325           60 :    logic              i0_csr_write;
+     325           12 :    logic              i0_csr_write;
      326            0 :    logic              presync_stall;
      327              : 
      328            0 :    logic              i0_instr_error;
      329            0 :    logic              i0_icaf_d;
      330              : 
-     331           56 :    logic              clear_pause;
+     331            4 :    logic              clear_pause;
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335        10064 :    logic              i0_brp_valid;
-     336         4164 :    logic              nonblock_load_cancel;
-     337         8690 :    logic              lsu_idle;
+     335          412 :    logic              i0_brp_valid;
+     336           12 :    logic              nonblock_load_cancel;
+     337          232 :    logic              lsu_idle;
      338            0 :    logic              lsu_pmu_misaligned_r;
-     339          172 :    logic              csr_ren_qual_d;
-     340          172 :    logic              csr_read_x;
-     341         1984 :    logic              i0_block_d;
-     342         1956 :    logic              i0_block_raw_d;  // This is use to create the raw valid
-     343          200 :    logic              ps_stall_in;
-     344         1040 :    logic [31:0]       i0_result_x;
+     339            4 :    logic              csr_ren_qual_d;
+     340            4 :    logic              csr_read_x;
+     341          212 :    logic              i0_block_d;
+     342          212 :    logic              i0_block_raw_d;  // This is use to create the raw valid
+     343            4 :    logic              ps_stall_in;
+     344           16 :    logic [31:0]       i0_result_x;
      345              : 
-     346           48 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
-     347           48 :    el2_dest_pkt_t         x_d_in, r_d_in;
+     346          216 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
+     347          216 :    el2_dest_pkt_t         x_d_in, r_d_in;
      348              : 
      349            0 :    el2_trap_pkt_t         d_t, x_t, x_t_in, r_t_in, r_t;
      350              : 
@@ -456,16 +456,16 @@
      352              : 
      353            2 :    logic [31:1]       dec_i0_pc_r;
      354              : 
-     355           60 :    logic csr_read, csr_write;
-     356          168 :    logic i0_br_unpred;
+     355            4 :    logic csr_read, csr_write;
+     356            0 :    logic i0_br_unpred;
      357              : 
-     358         6024 :    logic nonblock_load_valid_m_delay;
-     359        22748 :    logic i0_wen_r;
+     358          224 :    logic nonblock_load_valid_m_delay;
+     359          528 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
      363              : 
-     364         1596 :    logic flush_final_r;
+     364           68 :    logic flush_final_r;
      365              : 
      366            2 :    logic bitmanip_zbb_legal;
      367            2 :    logic bitmanip_zbs_legal;
@@ -489,24 +489,24 @@
      385              :    localparam NBLOAD_TAG_MSB  = pt.LSU_NUM_NBLOAD_WIDTH-1;
      386              : 
      387              : 
-     388         6192 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
-     389           48 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
-     390            0 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
+     388          224 :    logic                     cam_write, cam_inv_reset, cam_data_reset;
+     389            0 :    logic [NBLOAD_TAG_MSB:0]  cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
+     390            0 :    logic [NBLOAD_SIZE_MSB:0] cam_wen;
      391              : 
-     392           48 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
-     393            0 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
+     392            0 :    logic [NBLOAD_TAG_MSB:0]  load_data_tag;
+     393            0 :    logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
      394              : 
      395            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
      396            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
      397            0 :    el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
      398              : 
-     399          932 :    logic [4:0] nonblock_load_rd;
-     400         1756 :    logic i0_nonblock_load_stall;
-     401         1588 :    logic i0_nonblock_boundary_stall;
+     399            0 :    logic [4:0] nonblock_load_rd;
+     400          208 :    logic i0_nonblock_load_stall;
+     401          208 :    logic i0_nonblock_boundary_stall;
      402              : 
      403            0 :    logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
      404              : 
-     405         6024 :    logic i0_load_kill_wen_r;
+     405          224 :    logic i0_load_kill_wen_r;
      406              : 
      407            2 :    logic found;
      408              : 
@@ -514,27 +514,27 @@
      410              : 
      411            0 :    logic debug_fence_raw;
      412              : 
-     413           40 :    logic [31:0] i0_result_r_raw;
-     414           40 :    logic [31:0] i0_result_corr_r;
+     413           12 :    logic [31:0] i0_result_r_raw;
+     414           12 :    logic [31:0] i0_result_corr_r;
      415              : 
-     416         5866 :    logic [12:1] last_br_immed_x;
+     416          176 :    logic [12:1] last_br_immed_x;
      417              : 
-     418         4556 :    logic [31:0]        i0_inst_d;
-     419         4198 :    logic [31:0]        i0_inst_x;
-     420         4198 :    logic [31:0]        i0_inst_r;
-     421         4198 :    logic [31:0]        i0_inst_wb_in;
-     422         4198 :    logic [31:0]        i0_inst_wb;
+     418            8 :    logic [31:0]        i0_inst_d;
+     419            8 :    logic [31:0]        i0_inst_x;
+     420            8 :    logic [31:0]        i0_inst_r;
+     421            8 :    logic [31:0]        i0_inst_wb_in;
+     422            8 :    logic [31:0]        i0_inst_wb;
      423              : 
      424            2 :    logic [31:1]        i0_pc_wb;
      425              : 
-     426        35132 :    logic               i0_wb_en;
+     426          816 :    logic               i0_wb_en;
      427              : 
      428            2 :    logic               trace_enable;
      429              : 
      430            0 :    logic               debug_valid_x;
      431              : 
-     432        10148 :    el2_inst_pkt_t i0_itype;
-     433         9336 :    el2_reg_pkt_t i0r;
+     432          244 :    el2_inst_pkt_t i0_itype;
+     433           12 :    el2_reg_pkt_t i0r;
      434              : 
      435              : 
      436              :    rvdffie  #(8) misc1ff (.*,
@@ -631,14 +631,14 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530         4892 :       if (i0_br_error_all | i0_instr_error) begin
-     531         4892 :          i0_dp          =   '0;
-     532         4892 :          i0_dp.alu      = 1'b1;
-     533         4892 :          i0_dp.rs1      = 1'b1;
-     534         4892 :          i0_dp.rs2      = 1'b1;
-     535         4892 :          i0_dp.lor      = 1'b1;
-     536         4892 :          i0_dp.legal    = 1'b1;
-     537         4892 :          i0_dp.postsync = 1'b1;
+     530          408 :       if (i0_br_error_all | i0_instr_error) begin
+     531          408 :          i0_dp          =   '0;
+     532          408 :          i0_dp.alu      = 1'b1;
+     533          408 :          i0_dp.rs1      = 1'b1;
+     534          408 :          i0_dp.rs2      = 1'b1;
+     535          408 :          i0_dp.lor      = 1'b1;
+     536          408 :          i0_dp.legal    = 1'b1;
+     537          408 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -709,16 +709,16 @@
      605            2 :       found = 0;
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
-     608        21954 :             if (~cam[i].valid) begin
-     609       122590 :                cam_wen[i] = cam_write;
-     610       122590 :                found = 1'b1;
+     608          892 :             if (~cam[i].valid) begin
+     609         2620 :                cam_wen[i] = cam_write;
+     610         2620 :                found = 1'b1;
      611              :             end
-     612        21954 :             else begin
-     613        21954 :                cam_wen[i] = 0;
+     612          892 :             else begin
+     613          892 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617       507084 :             cam_wen[i] = 0;
+     617        13224 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,28 +756,28 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655         3162 :          if (cam_data_reset_val[i])
-     656         3162 :            cam[i].valid = 1'b0;
+     655          114 :          if (cam_data_reset_val[i])
+     656          114 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
      659              : 
-     660         9486 :          if (cam_wen[i]) begin
-     661         9486 :             cam_in[i].valid    = 1'b1;
-     662         9486 :             cam_in[i].wb       = 1'b0;
-     663         9486 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
-     664         9486 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
+     660          342 :          if (cam_wen[i]) begin
+     661          342 :             cam_in[i].valid    = 1'b1;
+     662          342 :             cam_in[i].wb       = 1'b0;
+     663          342 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
+     664          342 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666          222 :          else if ( (cam_inv_reset_val[i]) |
+     666            2 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
-     668          222 :            cam_in[i].valid = 1'b0;
+     668            2 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670       666404 :            cam_in[i] = cam[i];
+     670        17288 :            cam_in[i] = cam[i];
      671              : 
-     672         9486 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
-     673         9486 :            cam_in[i].wb = 1'b1;
+     672          342 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     673          342 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676       528768 :          if (dec_tlu_force_halt)
+     676        12224 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746        26580 :       if (i0_legal_decode_d) begin
-     747        26580 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748         3778 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749         3760 :          if (i0_dp.store)                i0_itype = STORE;
-     750        11168 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751        26580 :          if (i0_dp.zbb | i0_dp.zbs |
+     746          736 :       if (i0_legal_decode_d) begin
+     747          736 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748          118 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749          120 :          if (i0_dp.store)                i0_itype = STORE;
+     750          152 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751          736 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756           86 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757           30 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758        26580 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759        26580 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760           12 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761        26580 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762        26580 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763           14 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764         6576 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765         1132 :          if (i0_dp.jal)                  i0_itype = JAL;
+     756            2 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757            6 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758          736 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759          736 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760          736 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761          736 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762          736 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763          736 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764          320 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765           18 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862       132192 :       if (dec_extint_stall) begin
+     862         3056 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868       132192 :       else begin
-     869       132192 :          lsu_p.valid = lsu_decode_d;
+     868         3056 :       else begin
+     869         3056 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871       132192 :          lsu_p.load                         =  i0_dp.load ;
-     872       132192 :          lsu_p.store                        =  i0_dp.store;
-     873       132192 :          lsu_p.by                           =  i0_dp.by   ;
-     874       132192 :          lsu_p.half                         =  i0_dp.half ;
-     875       132192 :          lsu_p.word                         =  i0_dp.word ;
-     876       132192 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871         3056 :          lsu_p.load                         =  i0_dp.load ;
+     872         3056 :          lsu_p.store                        =  i0_dp.store;
+     873         3056 :          lsu_p.by                           =  i0_dp.by   ;
+     874         3056 :          lsu_p.half                         =  i0_dp.half ;
+     875         3056 :          lsu_p.word                         =  i0_dp.word ;
+     876         3056 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878       132192 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879       132192 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880       132192 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878         3056 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879         3056 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880         3056 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882       132192 :          lsu_p.unsign  =  i0_dp.unsign;
+     882         3056 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1380,7 +1380,7 @@
     1276            2 :       r_t_in.i0trigger[3:0]              = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
     1277            2 :       r_t_in.pmu_lsu_misaligned          = lsu_pmu_misaligned_r;   // only valid if a load/store is valid in DC3 stage
     1278              : 
-    1279           28 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
+    1279            2 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
     1280              : 
     1281              :    end
     1282              : 
@@ -1614,11 +1614,11 @@
     1510              : module el2_dec_dec_ctl
     1511              :   import el2_pkg::*;
     1512              : (
-    1513          760 :     input logic [31:0] inst,
+    1513           12 :     input logic [31:0] inst,
     1514            0 :     output el2_dec_pkt_t out
     1515              : );
     1516              : 
-    1517          760 :   logic [31:0] i;
+    1517           12 :   logic [31:0] i;
     1518              : 
     1519              :   assign i[31:0] = inst[31:0];
     1520              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_gpr_ctl.sv.html
index b8bee3fa1a2..f21a79ae4f8 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_gpr_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        83.3%
+    
+        61.1%
     
     
-        15
+        11
     
     
         18
@@ -122,26 +122,26 @@
       18              : #(
       19              :    `include "el2_param.vh"
       20              :  )  (
-      21         9336 :     input logic [4:0]  raddr0,       // logical read addresses
-      22         9536 :     input logic [4:0]  raddr1,
+      21           12 :     input logic [4:0]  raddr0,       // logical read addresses
+      22           28 :     input logic [4:0]  raddr1,
       23              : 
-      24        17236 :     input logic        wen0,         // write enable
-      25        10592 :     input logic [4:0]  waddr0,       // write address
-      26           40 :     input logic [31:0] wd0,          // write data
+      24          308 :     input logic        wen0,         // write enable
+      25          216 :     input logic [4:0]  waddr0,       // write address
+      26           12 :     input logic [31:0] wd0,          // write data
       27              : 
-      28         6192 :     input logic        wen1,         // write enable
-      29          916 :     input logic [4:0]  waddr1,       // write address
-      30           24 :     input logic [31:0] wd1,          // write data
+      28          224 :     input logic        wen1,         // write enable
+      29            0 :     input logic [4:0]  waddr1,       // write address
+      30            0 :     input logic [31:0] wd1,          // write data
       31              : 
-      32           48 :     input logic        wen2,         // write enable
-      33            2 :     input logic [4:0]  waddr2,       // write address
-      34            0 :     input logic [31:0] wd2,          // write data
+      32            0 :     input logic        wen2,         // write enable
+      33            0 :     input logic [4:0]  waddr2,       // write address
+      34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36       583434 :     input logic        clk,
+      36        12564 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
-      39           80 :     output logic [31:0] rd0,         // read data
-      40           12 :     output logic [31:0] rd1,
+      39           12 :     output logic [31:0] rd0,         // read data
+      40            8 :     output logic [31:0] rd1,
       41              : 
       42            0 :     input  logic        scan_mode
       43              : );
@@ -149,7 +149,7 @@
       45              :    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
       46              :    logic [31:1] [31:0] gpr_in;
       47            0 :    logic [31:1] w0v,w1v,w2v;
-      48           96 :    logic [31:1] gpr_wr_en;
+      48            4 :    logic [31:1] gpr_wr_en;
       49              : 
       50              :    // GPR Write Enables
       51              :    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_ib_ctl.sv.html
index c3cb667414f..b40c655ba3b 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,36 +129,36 @@
       25            0 :    input logic [1:0]           dbg_cmd_type,                       // dbg type
       26            0 :    input logic [31:0]          dbg_cmd_addr,                       // expand to 31:0
       27              : 
-      28          256 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
-      29         1124 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30        11398 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      28            4 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
+      29           24 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
+      30           10 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34        17896 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
-      35        33540 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
+      34          310 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      35          608 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
       38              : 
       39            0 :    input logic   ifu_i0_icaf_second,                               // i0 has access fault on second 2B of 4B inst
       40            0 :    input logic   ifu_i0_dbecc,                                     // i0 double-bit error
-      41          760 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
+      41           12 :    input logic [31:0]  ifu_i0_instr,                               // i0 instruction from the aligner
       42           10 :    input logic [31:1]  ifu_i0_pc,                                  // i0 pc from the aligner
       43              : 
       44              : 
-      45        33540 :    output logic dec_ib0_valid_d,                                   // ib0 valid
+      45          608 :    output logic dec_ib0_valid_d,                                   // ib0 valid
       46            0 :    output logic dec_debug_valid_d,                                 // Debug read or write at D-stage
       47              : 
       48              : 
-      49          760 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
+      49           12 :    output logic [31:0] dec_i0_instr_d,                             // i0 inst at decode
       50              : 
       51           10 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53        17896 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53          310 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
-      55          256 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
-      56         1124 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57        11398 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      55            4 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
+      56           24 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
+      57           10 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
@@ -185,7 +185,7 @@
       81            0 :    logic         debug_read_csr;
       82            0 :    logic         debug_write_csr;
       83              : 
-      84         1068 :    logic [34:0]  ifu_i0_pcdata, pc0;
+      84           22 :    logic [34:0]  ifu_i0_pcdata, pc0;
       85              : 
       86              :    assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
       87              :                                   ifu_i0_pc[31:1], ifu_i0_pc4 };
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_pmp_ctl.sv.html
index ca10f05fcee..c4dd603e86d 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        42.4%
+    
+        43.8%
     
     
         14
     
     
-        33
+        32
     
 
             
@@ -133,14 +133,14 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32       583434 :    input logic clk,
-      33       583434 :    input logic free_l2clk,
-      34       583434 :    input logic csr_wr_clk,
+      32        12564 :    input logic clk,
+      33        12564 :    input logic free_l2clk,
+      34        12564 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
-      36           60 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
-      37            4 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
+      36           12 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+      37            8 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
       38            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
-      39            4 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
+      39            8 :    input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
       40              : 
       41            4 :    input logic csr_pmpcfg,
       42            4 :    input logic csr_pmpaddr0,
@@ -153,7 +153,7 @@
       49            0 :    input logic internal_dbg_halt_timers, // debug halted
       50              : 
       51              : `ifdef RV_SMEPMP
-      52            0 :    input el2_mseccfg_pkt_t mseccfg,
+      52              :    input el2_mseccfg_pkt_t mseccfg,
       53              : `endif
       54              : 
       55            0 :    output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_tlu_ctl.sv.html
index ba163040187..2e72f6c7ca5 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.8%
+    
+        24.2%
     
     
-        108
+        87
     
     
-        375
+        360
     
 
             
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32       583434 :    input logic clk,
-      33       583434 :    input logic free_clk,
-      34       583434 :    input logic free_l2clk,
+      32        12564 :    input logic clk,
+      33        12564 :    input logic free_clk,
+      34        12564 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
@@ -149,29 +149,29 @@
       45              : 
       46              : 
       47              :    // perf counter inputs
-      48        35132 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
-      49         1286 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
-      50        35772 :    input logic       ifu_pmu_ic_miss, // icache miss
+      48          816 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
+      49           30 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
+      50          824 :    input logic       ifu_pmu_ic_miss, // icache miss
       51            0 :    input logic       ifu_pmu_ic_hit, // icache hit
       52            0 :    input logic       ifu_pmu_bus_error, // Instruction side bus error
       53            0 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
-      54        35770 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
-      55        35132 :    input logic       dec_pmu_instr_decoded, // decoded instructions
-      56         1764 :    input logic       dec_pmu_decode_stall, // decode stall
+      54          824 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
+      55          816 :    input logic       dec_pmu_instr_decoded, // decoded instructions
+      56          208 :    input logic       dec_pmu_decode_stall, // decode stall
       57            0 :    input logic       dec_pmu_presync_stall, // decode stall due to presync'd inst
-      58            8 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
-      59           28 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
-      60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
+      58            0 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
+      59            0 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
+      60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
-      62         1360 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63         5836 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64         7494 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
-      65        12368 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
+      62           64 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
+      63          232 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64          234 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      65          456 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
       66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
       68            0 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
-      69         6024 :    input logic       lsu_pmu_load_external_m, // D side bus load
-      70         5848 :    input logic       lsu_pmu_store_external_m, // D side bus store
+      69          224 :    input logic       lsu_pmu_load_external_m, // D side bus load
+      70          228 :    input logic       lsu_pmu_store_external_m, // D side bus store
       71            0 :    input logic       dma_pmu_dccm_read,          // DMA DCCM read
       72            0 :    input logic       dma_pmu_dccm_write,         // DMA DCCM write
       73            0 :    input logic       dma_pmu_any_read,           // DMA read
@@ -190,18 +190,18 @@
       86            0 :    input logic         lsu_imprecise_error_load_any,      // store bus error
       87            2 :    input logic [31:0]  lsu_imprecise_error_addr_any, // store bus error address
       88              : 
-      89           60 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
-      90          232 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
-      91            4 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
+      89           12 :    input logic        dec_csr_wen_unq_d,       // valid csr with write - for csr legal
+      90           16 :    input logic        dec_csr_any_unq_d,       // valid csr - for csr legal
+      91            8 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
       92              : 
-      93           60 :    input logic        dec_csr_wen_r,      // csr write enable at wb
-      94         7568 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
-      95            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+      93           12 :    input logic        dec_csr_wen_r,      // csr write enable at wb
+      94           24 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
+      95            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
       96            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       97              : 
-      98           20 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
+      98            0 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
       99              : 
-     100        35132 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
+     100          816 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
      101              : 
      102            2 :    input logic [31:1] exu_npc_r, // for NPC tracking
      103              : 
@@ -210,21 +210,21 @@
      106            0 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
      107              : 
      108            0 :    input logic [31:0] dec_illegal_inst, // For mtval
-     109        35132 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
+     109          816 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112         5352 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112          172 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115         7972 :    input logic        exu_i0_br_valid_r, // valid
-     116         1360 :    input logic        exu_i0_br_mp_r, // mispredict
-     117        10156 :    input logic        exu_i0_br_middle_r, // middle of bank
+     115          208 :    input logic        exu_i0_br_valid_r, // valid
+     116           64 :    input logic        exu_i0_br_mp_r, // mispredict
+     117          248 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
      119              :    // branch info from pipe1 for errors or counter updates
      120              : 
-     121         1914 :    input logic             exu_i0_br_way_r, // way hit or repl
+     121            4 :    input logic             exu_i0_br_way_r, // way hit or repl
      122              : 
-     123         9576 :    output logic dec_tlu_core_empty,  // core is empty
+     123           92 :    output logic dec_tlu_core_empty,  // core is empty
      124              :    // Debug start
      125            0 :    output logic dec_dbg_cmd_done, // abstract command done
      126            0 :    output logic dec_dbg_cmd_fail, // abstract command failed
@@ -243,10 +243,10 @@
      139              : 
      140            0 :    input  logic dbg_halt_req, // DM requests a halt
      141            0 :    input  logic dbg_resume_req, // DM requests a resume
-     142        35772 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
-     143         8690 :    input  logic lsu_idle_any, // lsu is idle
-     144           48 :    input  logic dec_div_active, // oop div is active
-     145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
+     142          824 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
+     143          232 :    input  logic lsu_idle_any, // lsu is idle
+     144            0 :    input  logic dec_div_active, // oop div is active
+     145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
      146              : 
      147            0 :    input logic  ifu_ic_error_start,     // IC single bit error
      148            0 :    input logic  ifu_iccm_rd_ecc_single_err, // ICCM single bit error
@@ -284,24 +284,24 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183            4 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
-     184          232 :    output logic dec_csr_legal_d,              // csr indicates legal operation
+     183            0 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
-     186         1914 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
+     186            4 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
      188            0 :    output logic dec_tlu_i0_kill_writeb_wb,    // I0 is flushed, don't writeback any results to arch state
-     189           56 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
-     190        35132 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
+     189            4 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
+     190          816 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
      191              : 
      192            0 :    output logic dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
-     193           56 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
+     193            4 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
      194            0 :    output logic [31:1] dec_tlu_flush_path_r, // flush pc
      195            0 :    output logic dec_tlu_fence_i_r,           // flush is a fence_i rfnpc, flush icache
      196            0 :    output logic dec_tlu_wr_pause_r,           // CSR write to pause reg is at R.
      197            0 :    output logic dec_tlu_flush_pause_r,        // Flush is due to pause
      198              : 
      199            0 :    output logic dec_tlu_presync_d,            // CSR read needs to be presync'd
-     200          148 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
+     200            4 :    output logic dec_tlu_postsync_d,           // CSR needs to be presync'd
      201              : 
      202              : 
      203            0 :    output logic [31:0] dec_tlu_mrac_ff,        // CSR for memory region control
@@ -313,8 +313,8 @@
      209            0 :    output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc
      210            0 :    output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
      211              : 
-     212           24 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
-     213        35132 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
+     212            0 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
+     213          816 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
      214            0 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
      215            0 :    output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
      216            0 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
@@ -344,12 +344,12 @@
      240              : 
      241              :    // Privilege mode
      242              :    // 0 - machine, 1 - user
-     243           18 :    output logic  priv_mode,
-     244           26 :    output logic  priv_mode_eff,
-     245           18 :    output logic  priv_mode_ns,
+     243              :    output logic  priv_mode,
+     244              :    output logic  priv_mode_eff,
+     245              :    output logic  priv_mode_ns,
      246              : 
      247              :    // mseccfg CSR content for PMP
-     248            0 :    output logic [2:0] mseccfg,
+     248              :    output logic [2:0] mseccfg,
      249              : 
      250              : `endif
      251              : 
@@ -376,12 +376,12 @@
      272            0 :    logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
      273            0 :    logic wr_mcountinhibit_r;
      274              : `ifdef RV_USER_MODE
-     275            0 :    logic wr_mcounteren_r;
-     276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
-     277            0 :    logic wr_mseccfg_r;
-     278            8 :    logic [2:0] mseccfg_ns;
+     275              :    logic wr_mcounteren_r;
+     276              :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
+     277              :    logic wr_mseccfg_r;
+     278              :    logic [2:0] mseccfg_ns;
      279              : `endif
-     280            0 :    logic [6:0] mcountinhibit;
+     280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
      282            0 :    logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
      283            0 :    logic [9:0]  mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
@@ -389,23 +389,23 @@
      285            0 :    logic [1:0] mtsel_ns, mtsel;
      286            0 :    logic tlu_i0_kill_writeb_r;
      287              : `ifdef RV_USER_MODE
-     288            6 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
+     288              :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
-     292            0 :    logic [1:0] mfdhs_ns, mfdhs;
+     292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
      294            0 :    logic        force_halt;
      295            0 :    logic [5:0]  mfdht, mfdht_ns;
-     296           18 :    logic mstatus_mie_ns;
-     297            0 :    logic [30:0] mtvec_ns, mtvec;
+     296            0 :    logic mstatus_mie_ns;
+     297            0 :    logic [30:0] mtvec_ns, mtvec;
      298            0 :    logic [15:2] dcsr_ns, dcsr;
      299            0 :    logic [5:0] mip_ns, mip;
      300            0 :    logic [5:0] mie_ns, mie;
-     301          258 :    logic [31:0] mcyclel_ns, mcyclel;
+     301            4 :    logic [31:0] mcyclel_ns, mcyclel;
      302            0 :    logic [31:0] mcycleh_ns, mcycleh;
-     303           40 :    logic [31:0] minstretl_ns, minstretl;
-     304            0 :    logic [31:0] minstreth_ns, minstreth;
+     303            0 :    logic [31:0] minstretl_ns, minstretl;
+     304            0 :    logic [31:0] minstreth_ns, minstreth;
      305            0 :    logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;
      306            0 :    logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;
      307            0 :    logic [31:0] mscratch;
@@ -426,10 +426,10 @@
      322            0 :    logic [3:0] mscause_ns, mscause, mscause_type;
      323            0 :    logic [31:0] mtval_ns, mtval;
      324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
-     325           56 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
+     325            4 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
      326            0 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
-     327        35132 :    logic i0_valid_wb;
-     328        35132 :    logic tlu_i0_commit_cmt;
+     327          816 :    logic i0_valid_wb;
+     328          816 :    logic tlu_i0_commit_cmt;
      329            0 :    logic [31:1] vectored_path, interrupt_path;
      330            0 :    logic [16:0] dicawics_ns, dicawics;
      331            0 :    logic        wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
@@ -441,25 +441,25 @@
      337            0 :                 ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r;
      338            0 :    logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready,
      339            0 :          take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible;
-     340           24 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
-     341           24 :    logic synchronous_flush_r;
-     342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
-     343         1032 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
-     344          258 :    logic [31:0] mcyclel_inc;
+     340            0 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
+     341            0 :    logic synchronous_flush_r;
+     342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
+     343           20 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
+     344            4 :    logic [31:0] mcyclel_inc;
      345            0 :    logic [31:0] mcycleh_inc;
      346              : 
-     347          164 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
+     347            0 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
      348              : 
-     349           40 :    logic [31:0] minstretl_inc, minstretl_read;
-     350            0 :    logic [31:0] minstreth_inc, minstreth_read;
+     349            0 :    logic [31:0] minstretl_inc, minstretl_read;
+     350            0 :    logic [31:0] minstreth_inc, minstreth_read;
      351            2 :    logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;
-     352          232 :    logic valid_csr;
+     352           16 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355         7260 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355          176 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
-     357           52 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
-     358        35132 :    logic i0_trigger_eval_r;
+     357            0 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
+     358          816 :    logic i0_trigger_eval_r;
      359              : 
      360            0 :    logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
      361            4 :    logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
@@ -506,17 +506,17 @@
      402            8 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405       583434 :    logic csr_wr_clk;
+     405        12564 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
-     407         5848 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
+     407          224 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
      409            0 :    logic lsu_single_ecc_error_r;
      410            0 :    logic [31:0] lsu_error_pkt_addr_r;
      411            2 :    logic mcyclel_cout_in;
-     412        35108 :    logic i0_valid_no_ebreak_ecall_r;
-     413        35108 :    logic minstret_enable_f;
-     414           56 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
-     415        35132 :    logic pc0_valid_r;
+     412          816 :    logic i0_valid_no_ebreak_ecall_r;
+     413          816 :    logic minstret_enable_f;
+     414            4 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
+     415          816 :    logic pc0_valid_r;
      416            4 :    logic [15:0] mfdc_int, mfdc_ns;
      417            4 :    logic [31:0] mrac_in;
      418            4 :    logic [31:27] csr_sat;
@@ -535,13 +535,13 @@
      431            0 :    logic            mhpmc5h_wr_en0, mhpmc5h_wr_en;
      432            0 :    logic            mhpmc6h_wr_en0, mhpmc6h_wr_en;
      433            0 :    logic [63:0]     mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;
-     434           56 :    logic perfcnt_halted_d1, zero_event_r;
+     434            8 :    logic perfcnt_halted_d1, zero_event_r;
      435            0 :    logic [3:0] perfcnt_during_sleep;
      436            0 :    logic [9:0] event_r;
      437              : 
-     438        10148 :    el2_inst_pkt_t pmu_i0_itype_qual;
+     438          244 :    el2_inst_pkt_t pmu_i0_itype_qual;
      439              : 
-     440           60 :    logic dec_csr_wen_r_mod;
+     440           12 :    logic dec_csr_wen_r_mod;
      441              : 
      442            4 :    logic flush_clkvalid;
      443            0 :    logic sel_fir_addr;
@@ -550,8 +550,8 @@
      446            0 :    logic mtval_capture_pc_plus2_r;
      447            0 :    logic mtval_capture_inst_r;
      448            0 :    logic mtval_capture_lsu_r;
-     449           24 :    logic mtval_clear_r;
-     450            0 :    logic wr_mcgc_r;
+     449            0 :    logic mtval_clear_r;
+     450            0 :    logic wr_mcgc_r;
      451            0 :    logic wr_mfdc_r;
      452            0 :    logic wr_mdeau_r;
      453            0 :    logic trigger_hit_for_dscr_cause_r_d1;
@@ -584,9 +584,9 @@
      480              : 
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
-     483            0 :    logic  csr_acc_r;    // CSR access error
-     484           62 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         8266 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     483              :    logic  csr_acc_r;    // CSR access error
+     484              :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485              :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -1095,8 +1095,8 @@
      991              : 
      992              :    // CSR access error
      993              :    // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
-     994            0 :    logic csr_wr_acc_r;
-     995            0 :    logic csr_rd_acc_r;
+     994              :    logic csr_wr_acc_r;
+     995              :    logic csr_rd_acc_r;
      996              : 
      997              :    assign csr_wr_acc_r = csr_wr_usr_r & (
      998              :                              ((dec_csr_wraddr_r[11:0] == CYCLEL)   & mcounteren[MCOUNTEREN_CY]) |
@@ -1664,12 +1664,12 @@
     1560              : 
     1561              :    // Detect if any PMP region is locked regardless of being enabled. This is
     1562              :    // necessary for mseccfg.RLB bit write behavior
-    1563            0 :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
+    1563              :    logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
     1564              :    for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
     1565              :      assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
     1566              :    end
     1567              : 
-    1568            0 :    logic  pmp_any_region_locked;
+    1568              :    logic  pmp_any_region_locked;
     1569              :    assign pmp_any_region_locked = |pmp_region_locked;
     1570              : 
     1571              :    // mseccfg
@@ -2828,12 +2828,12 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727       583434 :    input logic clk,
-    2728       583434 :    input logic free_l2clk,
-    2729       583434 :    input logic csr_wr_clk,
+    2727        12564 :    input logic clk,
+    2728        12564 :    input logic free_l2clk,
+    2729        12564 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
-    2731           60 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
-    2732            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
+    2731           12 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
+    2732            8 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
     2733            4 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
     2734              : 
     2735            0 :    input logic csr_mitctl0,
@@ -2859,12 +2859,12 @@
     2755              :    localparam MITCTL_ENABLE_HALTED      = 1;
     2756              :    localparam MITCTL_ENABLE_PAUSED      = 2;
     2757              : 
-    2758          258 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
+    2758            4 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
     2759            0 :    logic [2:0] mitctl0_ns, mitctl0;
     2760            0 :    logic [3:0] mitctl1_ns, mitctl1;
     2761            0 :    logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
     2762            2 :    logic mitcnt0_inc_ok, mitcnt1_inc_ok;
-    2763         1032 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
+    2763           20 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
     2764            0 :  logic mit0_match_ns;
     2765            0 :  logic mit1_match_ns;
     2766            0 :  logic mitctl0_0_b_ns;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_trigger.sv.html
index 150de15a419..219ebc86a70 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dma_ctrl.sv.html
index f5754a0a46e..e1e6dcb5059 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29       583434 :    input logic         clk,
-      30       583434 :    input logic         free_clk,
+      29        12564 :    input logic         clk,
+      30        12564 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -173,8 +173,8 @@
       69            0 :    output logic        dma_active,         // DMA is busy
       70            0 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
       71            0 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
-      72        11874 :    input logic         dccm_ready, // dccm ready to accept DMA request
-      73         1594 :    input logic         iccm_ready, // iccm ready to accept DMA request
+      72          454 :    input logic         dccm_ready, // dccm ready to accept DMA request
+      73           66 :    input logic         iccm_ready, // iccm ready to accept DMA request
       74            2 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
       75              : 
       76              :    // PMU signals
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185       583434 :    logic                    dma_buffer_c1_clk;
-     186       583434 :    logic                    dma_free_clk;
+     185        12564 :    logic                    dma_buffer_c1_clk;
+     186        12564 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu.sv.html
index 9c0463159bb..35e70986322 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        80.0%
+    
+        70.0%
     
     
-        80
+        70
     
     
         100
@@ -124,48 +124,48 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       583434 :    input logic          clk,                                           // Top level clock
+      23        12564 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
-      27        35132 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
-      28        35128 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
+      27          816 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
+      28          816 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
       29            0 :    input logic  [31:0]  dbg_cmd_wrdata,                                // Debug data   to primary I0 RS1
       30            0 :    input el2_alu_pkt_t i0_ap,                                         // DEC alu {valid,predecodes}
       31              : 
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
-      34         2738 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35        11398 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
-      36         1124 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
+      34            4 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
+      35           10 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      36           24 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
       39            0 :    input logic  [31:0]  lsu_result_m,                                  // Load result M-stage
-      40           24 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
-      41        28768 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
-      42        15504 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
-      43           80 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
-      44           12 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45         1752 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
-      46           40 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
-      47         1180 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
-      48        24544 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49        12188 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
-      50          936 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
+      40            0 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
+      41          548 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
+      42          232 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
+      43           12 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
+      44            8 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
+      45           20 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      46           12 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
+      47           12 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
+      48          376 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
+      49          448 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      50           24 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51           10 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
-      52         1072 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
+      52            4 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
-      54          172 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55            4 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      54            4 :    input logic          dec_csr_ren_d,                                 // CSR read select
+      55            0 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57        25590 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57          582 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
-      59           24 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
-      60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
+      59            0 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
+      60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
       61              : 
-      62          922 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
+      62           28 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
       63              : 
-      64           56 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
+      64            4 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
       65            0 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
       66              : 
       67              : 
@@ -173,90 +173,90 @@
       69            0 :    input logic [31:2]  dec_tlu_meihap,                                 // External stall mux data
       70              : 
       71              : 
-      72         2880 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
-      73           72 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
+      72          104 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
+      73            0 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
       74              : 
-      75         1596 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
-      76          680 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
+      75           68 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
+      76            8 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
       77              : 
-      78          764 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
+      78           16 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
       79            2 :    output logic [31:1]  exu_i0_pc_x,                                   // Primary PC  result to DEC
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            2 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83         5352 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83          172 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
-      86          236 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87         7972 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
-      88         1360 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
-      89        10156 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90         2402 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
-      91         1914 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
+      86            4 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
+      87          208 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      88           64 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
+      89          248 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
+      90            2 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      91            4 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
-      93           44 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
-      94          940 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95         2402 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      96          548 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      93            0 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
+      94           20 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
+      95            2 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      96            8 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
-     100         1360 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101         5836 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102         7494 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     100           64 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
+     101          232 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102          234 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105            0 :    output logic [31:0]  exu_div_result,                                // Divide result
-     106           48 :    output logic         exu_div_wren                                   // Divide write enable to GPR
+     106            0 :    output logic         exu_div_wren                                   // Divide write enable to GPR
      107              :   );
      108              : 
      109              : 
      110              : 
      111              : 
-     112            8 :    logic [31:0]                i0_rs1_bypass_data_d;
-     113           40 :    logic [31:0]                i0_rs2_bypass_data_d;
-     114         4492 :    logic                       i0_rs1_bypass_en_d;
-     115          140 :    logic                       i0_rs2_bypass_en_d;
-     116           80 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
-     117           80 :    logic [31:0]                muldiv_rs1_d;
-     118          922 :    logic [31:1]                pred_correct_npc_r;
-     119         7876 :    logic                       i0_pred_correct_upper_r;
+     112            0 :    logic [31:0]                i0_rs1_bypass_data_d;
+     113            0 :    logic [31:0]                i0_rs2_bypass_data_d;
+     114          420 :    logic                       i0_rs1_bypass_en_d;
+     115            0 :    logic                       i0_rs2_bypass_en_d;
+     116           12 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
+     117           12 :    logic [31:0]                muldiv_rs1_d;
+     118           28 :    logic [31:1]                pred_correct_npc_r;
+     119          180 :    logic                       i0_pred_correct_upper_r;
      120            2 :    logic [31:1]                i0_flush_path_upper_r;
-     121          172 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
-     122        35128 :    logic                       x_ctl_en,  r_ctl_en;
+     121            4 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
+     122          816 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124         2402 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125         2402 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126         5848 :    logic                       i0_taken_d;
-     127         5848 :    logic                       i0_taken_x;
-     128         7972 :    logic                       i0_valid_d;
-     129         7972 :    logic                       i0_valid_x;
-     130         2402 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124            2 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125            2 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126          232 :    logic                       i0_taken_d;
+     127          232 :    logic                       i0_taken_x;
+     128          208 :    logic                       i0_valid_d;
+     129          208 :    logic                       i0_valid_x;
+     130            2 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
-     132           44 :    el2_predict_pkt_t          final_predict_mp;
-     133         2738 :    el2_predict_pkt_t          i0_predict_newp_d;
+     132            0 :    el2_predict_pkt_t          final_predict_mp;
+     133            4 :    el2_predict_pkt_t          i0_predict_newp_d;
      134              : 
      135            0 :    logic                       flush_in_d;
-     136          764 :    logic [31:0]                alu_result_x;
+     136           16 :    logic [31:0]                alu_result_x;
      137              : 
      138            0 :    logic                       mul_valid_x;
      139            0 :    logic [31:0]                mul_result_x;
      140              : 
-     141         1420 :    el2_predict_pkt_t          i0_pp_r;
+     141            4 :    el2_predict_pkt_t          i0_pp_r;
      142              : 
-     143         1540 :    logic                       i0_flush_upper_d;
+     143           64 :    logic                       i0_flush_upper_d;
      144           10 :    logic [31:1]                i0_flush_path_d;
-     145         2738 :    el2_predict_pkt_t          i0_predict_p_d;
-     146         7876 :    logic                       i0_pred_correct_upper_d;
+     145            4 :    el2_predict_pkt_t          i0_predict_p_d;
+     146          180 :    logic                       i0_pred_correct_upper_d;
      147              : 
-     148         1540 :    logic                       i0_flush_upper_x;
+     148           64 :    logic                       i0_flush_upper_x;
      149            2 :    logic [31:1]                i0_flush_path_x;
-     150         1420 :    el2_predict_pkt_t          i0_predict_p_x;
-     151         7876 :    logic                       i0_pred_correct_upper_x;
-     152        12188 :    logic                       i0_branch_x;
+     150            4 :    el2_predict_pkt_t          i0_predict_p_x;
+     151          180 :    logic                       i0_pred_correct_upper_x;
+     152          448 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
-     155          548 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
+     155           20 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
      156              : 
      157              : 
      158              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_alu_ctl.sv.html
index 0cb5eb7bd7b..46a39fcf72a 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_alu_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        52.3%
+    
+        48.9%
     
     
-        46
+        43
     
     
         88
@@ -124,52 +124,52 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       583434 :    input  logic                  clk,                // Top level clock
+      23        12564 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
-      27         1540 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
-      28           56 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
-      29        35132 :    input  logic                  enable,             // Clock enable
-      30        24544 :    input  logic                  valid_in,           // Valid
+      27           64 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
+      28            4 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
+      29          816 :    input  logic                  enable,             // Clock enable
+      30          376 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
-      32          172 :    input  logic                  csr_ren_in,         // CSR select
-      33            4 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34           80 :    input  logic signed [31:0]    a_in,               // A operand
-      35         1916 :    input  logic        [31:0]    b_in,               // B operand
+      32            4 :    input  logic                  csr_ren_in,         // CSR select
+      33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34           12 :    input  logic signed [31:0]    a_in,               // A operand
+      35           24 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
-      37         2738 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
-      38         1180 :    input  logic        [12:1]    brimm_in,           // Branch offset
+      37            4 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
+      38           12 :    input  logic        [12:1]    brimm_in,           // Branch offset
       39              : 
       40              : 
-      41          764 :    output logic        [31:0]    result_ff,          // final result
-      42         1540 :    output logic                  flush_upper_out,    // Branch flush
-      43         1596 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
+      41           16 :    output logic        [31:0]    result_ff,          // final result
+      42           64 :    output logic                  flush_upper_out,    // Branch flush
+      43           68 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
       44           10 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            2 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46         7876 :    output logic                  pred_correct_out,   // NPC control
-      47         2738 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
+      46          180 :    output logic                  pred_correct_out,   // NPC control
+      47            4 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
       50              : 
-      51           80 :    logic               [31:0]    zba_a_in;
-      52          848 :    logic               [31:0]    aout;
-      53          528 :    logic                         cout,ov,neg;
-      54           28 :    logic               [31:0]    lout;
-      55           80 :    logic               [31:0]    sout;
-      56          808 :    logic                         sel_shift;
-      57        21812 :    logic                         sel_adder;
+      51           12 :    logic               [31:0]    zba_a_in;
+      52           20 :    logic               [31:0]    aout;
+      53            4 :    logic                         cout,ov,neg;
+      54            0 :    logic               [31:0]    lout;
+      55           12 :    logic               [31:0]    sout;
+      56            0 :    logic                         sel_shift;
+      57          328 :    logic                         sel_adder;
       58            0 :    logic                         slt_one;
-      59         5936 :    logic                         actual_taken;
+      59          236 :    logic                         actual_taken;
       60           10 :    logic               [31:1]    pcout;
-      61         2720 :    logic                         cond_mispredict;
-      62          172 :    logic                         target_mispredict;
-      63        22180 :    logic                         eq, ne, lt, ge;
-      64         1208 :    logic                         any_jal;
-      65         9816 :    logic               [1:0]     newhist;
-      66         1208 :    logic                         sel_pc;
-      67           80 :    logic               [31:0]    csr_write_data;
-      68          844 :    logic               [31:0]    result;
+      61          240 :    logic                         cond_mispredict;
+      62            8 :    logic                         target_mispredict;
+      63          740 :    logic                         eq, ne, lt, ge;
+      64           20 :    logic                         any_jal;
+      65          404 :    logic               [1:0]     newhist;
+      66           20 :    logic                         sel_pc;
+      67           12 :    logic               [31:0]    csr_write_data;
+      68           20 :    logic               [31:0]    result;
       69              : 
       70              : 
       71              : 
@@ -348,7 +348,7 @@
      244              :                                 ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |
      245              :                                 ( {32{~ap_zba   }} &  a_in[31:0]       );
      246              : 
-     247        10660 :    logic        [31:0]    bm;
+     247          248 :    logic        [31:0]    bm;
      248              : 
      249              :    assign bm[31:0]            = ( ap.sub )  ?  ~b_in[31:0]  :  b_in[31:0];
      250              : 
@@ -383,8 +383,8 @@
      279              : 
      280            0 :    logic        [5:0]     shift_amount;
      281            2 :    logic        [31:0]    shift_mask;
-     282         6172 :    logic        [62:0]    shift_extend;
-     283         6100 :    logic        [62:0]    shift_long;
+     282          444 :    logic        [62:0]    shift_extend;
+     283          444 :    logic        [62:0]    shift_long;
      284              : 
      285              : 
      286              :    assign shift_amount[5:0]            = ( { 6{ap.sll}}   & (6'd32 - {1'b0,b_in[4:0]}) ) |   // [5] unused
@@ -416,7 +416,7 @@
      312              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CLZ,CTZ      * * * * * * * * * * * * * * * * * *
      313              : 
      314            0 :    logic                  bitmanip_clz_ctz_sel;
-     315           80 :    logic        [31:0]    bitmanip_a_reverse_ff;
+     315           12 :    logic        [31:0]    bitmanip_a_reverse_ff;
      316            0 :    logic        [31:0]    bitmanip_lzd_in;
      317            2 :    logic        [5:0]     bitmanip_dw_lzd_enc;
      318            0 :    logic        [5:0]     bitmanip_clz_ctz_result;
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342      5408896 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343      5408896 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342       141056 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343       141056 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
@@ -460,7 +460,7 @@
      356              : 
      357              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CPOP         * * * * * * * * * * * * * * * * * *
      358              : 
-     359            4 :    logic        [5:0]     bitmanip_cpop;
+     359           12 :    logic        [5:0]     bitmanip_cpop;
      360            0 :    logic        [5:0]     bitmanip_cpop_result;
      361              : 
      362              : 
@@ -499,7 +499,7 @@
      395              : 
      396              :    assign bitmanip_minmax_sel          =  ap_min | ap_max;
      397              : 
-     398        22182 :    logic                  bitmanip_minmax_sel_a;
+     398          742 :    logic                  bitmanip_minmax_sel_a;
      399              : 
      400              :    assign bitmanip_minmax_sel_a        =  ge  ^ ap_min;
      401              : 
@@ -557,7 +557,7 @@
      453              : 
      454              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  ZBSET, ZBCLR, ZBINV  * * * * * * * * * * * * * *
      455              : 
-     456           72 :    logic        [31:0]    bitmanip_sb_1hot;
+     456            4 :    logic        [31:0]    bitmanip_sb_1hot;
      457            0 :    logic        [31:0]    bitmanip_sb_data;
      458              : 
      459              :    assign bitmanip_sb_1hot[31:0]       = ( 32'h00000001 << b_in[4:0] );
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_div_ctl.sv.html
index 7b8e31e1000..f8127260493 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_div_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        70.4%
+    
+        16.0%
     
     
-        57
+        13
     
     
         81
@@ -124,19 +124,19 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23       583434 :    input logic           clk,                       // Top level clock
+      23        12564 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
-      27           24 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
-      28           80 :    input logic  [31:0]   dividend,                  // Numerator
-      29         1916 :    input logic  [31:0]   divisor,                   // Denominator
+      27            0 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
+      28           12 :    input logic  [31:0]   dividend,                  // Numerator
+      29           24 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
       33              : 
-      34           48 :    output logic          finish_dly,                // Finish to match data
-      35            0 :    output logic [31:0]   out                        // Result
+      34            0 :    output logic          finish_dly,                // Finish to match data
+      35            0 :    output logic [31:0]   out                        // Result
       36              :   );
       37              : 
       38              : 
@@ -1414,81 +1414,81 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313       583434 :    input  logic            clk,                       // Top level clock
+    1313        12564 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
     1317            0 :    input  logic            cancel,                    // Flush pipeline
-    1318           48 :    input  logic            valid_in,
-    1319         5238 :    input  logic            signed_in,
-    1320           24 :    input  logic            rem_in,
-    1321           80 :    input  logic [31:0]     dividend_in,
-    1322         1916 :    input  logic [31:0]     divisor_in,
+    1318            0 :    input  logic            valid_in,
+    1319          218 :    input  logic            signed_in,
+    1320            0 :    input  logic            rem_in,
+    1321           12 :    input  logic [31:0]     dividend_in,
+    1322           24 :    input  logic [31:0]     divisor_in,
     1323              : 
-    1324           48 :    output logic            valid_out,
-    1325            0 :    output logic [31:0]     data_out
+    1324            0 :    output logic            valid_out,
+    1325            0 :    output logic [31:0]     data_out
     1326              :   );
     1327              : 
     1328              : 
-    1329           48 :    logic                   valid_ff_in, valid_ff;
-    1330           48 :    logic                   finish_raw, finish, finish_ff;
-    1331           44 :    logic                   running_state;
-    1332           48 :    logic                   misc_enable;
-    1333            0 :    logic         [2:0]     control_in, control_ff;
-    1334           24 :    logic                   dividend_sign_ff, divisor_sign_ff, rem_ff;
-    1335           24 :    logic                   count_enable;
-    1336            0 :    logic         [6:0]     count_in, count_ff;
+    1329            0 :    logic                   valid_ff_in, valid_ff;
+    1330            0 :    logic                   finish_raw, finish, finish_ff;
+    1331            0 :    logic                   running_state;
+    1332            0 :    logic                   misc_enable;
+    1333            0 :    logic         [2:0]     control_in, control_ff;
+    1334            0 :    logic                   dividend_sign_ff, divisor_sign_ff, rem_ff;
+    1335            0 :    logic                   count_enable;
+    1336            0 :    logic         [6:0]     count_in, count_ff;
     1337              : 
-    1338           24 :    logic                   smallnum_case;
-    1339            0 :    logic         [3:0]     smallnum;
+    1338            0 :    logic                   smallnum_case;
+    1339            0 :    logic         [3:0]     smallnum;
     1340              : 
-    1341           24 :    logic                   a_enable, a_shift;
-    1342            0 :    logic        [31:0]     a_in, a_ff;
+    1341            0 :    logic                   a_enable, a_shift;
+    1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
-    1344           48 :    logic                   b_enable, b_twos_comp;
-    1345         1964 :    logic        [32:0]     b_in;
-    1346            2 :    logic        [37:0]     b_ff;
+    1344            0 :    logic                   b_enable, b_twos_comp;
+    1345           24 :    logic        [32:0]     b_in;
+    1346            0 :    logic        [37:0]     b_ff;
     1347              : 
-    1348            0 :    logic        [31:0]     q_in, q_ff;
+    1348            0 :    logic        [31:0]     q_in, q_ff;
     1349              : 
-    1350           48 :    logic                   rq_enable;
-    1351            0 :    logic                   r_sign_sel;
-    1352           24 :    logic                   r_restore_sel;
-    1353            0 :    logic                   r_adder01_sel, r_adder02_sel, r_adder03_sel;
+    1350            0 :    logic                   rq_enable;
+    1351            0 :    logic                   r_sign_sel;
+    1352            0 :    logic                   r_restore_sel;
+    1353            0 :    logic                   r_adder01_sel, r_adder02_sel, r_adder03_sel;
     1354            0 :    logic                   r_adder04_sel, r_adder05_sel, r_adder06_sel, r_adder07_sel;
     1355            0 :    logic                   r_adder08_sel, r_adder09_sel, r_adder10_sel, r_adder11_sel;
-    1356            4 :    logic                   r_adder12_sel, r_adder13_sel, r_adder14_sel, r_adder15_sel;
-    1357            0 :    logic        [32:0]     r_in, r_ff;
+    1356            0 :    logic                   r_adder12_sel, r_adder13_sel, r_adder14_sel, r_adder15_sel;
+    1357            0 :    logic        [32:0]     r_in, r_ff;
     1358              : 
-    1359           48 :    logic                   twos_comp_q_sel, twos_comp_b_sel;
-    1360           48 :    logic        [31:0]     twos_comp_in, twos_comp_out;
+    1359            0 :    logic                   twos_comp_q_sel, twos_comp_b_sel;
+    1360            0 :    logic        [31:0]     twos_comp_in, twos_comp_out;
     1361              : 
-    1362           48 :    logic        [15:1]     quotient_raw;
-    1363           52 :    logic         [3:0]     quotient_new;
-    1364           18 :    logic        [34:0]     adder01_out;
-    1365           16 :    logic        [35:0]     adder02_out;
-    1366           18 :    logic        [36:0]     adder03_out;
-    1367            2 :    logic        [37:0]     adder04_out;
-    1368           18 :    logic        [37:0]     adder05_out;
-    1369           16 :    logic        [37:0]     adder06_out;
-    1370           18 :    logic        [37:0]     adder07_out;
-    1371           14 :    logic        [37:0]     adder08_out;
-    1372           18 :    logic        [37:0]     adder09_out;
-    1373           16 :    logic        [37:0]     adder10_out;
-    1374           18 :    logic        [37:0]     adder11_out;
-    1375            2 :    logic        [37:0]     adder12_out;
-    1376           18 :    logic        [37:0]     adder13_out;
-    1377           16 :    logic        [37:0]     adder14_out;
-    1378           18 :    logic        [37:0]     adder15_out;
+    1362            2 :    logic        [15:1]     quotient_raw;
+    1363            2 :    logic         [3:0]     quotient_new;
+    1364            0 :    logic        [34:0]     adder01_out;
+    1365            0 :    logic        [35:0]     adder02_out;
+    1366            0 :    logic        [36:0]     adder03_out;
+    1367            0 :    logic        [37:0]     adder04_out;
+    1368            0 :    logic        [37:0]     adder05_out;
+    1369            0 :    logic        [37:0]     adder06_out;
+    1370            0 :    logic        [37:0]     adder07_out;
+    1371            0 :    logic        [37:0]     adder08_out;
+    1372            0 :    logic        [37:0]     adder09_out;
+    1373            0 :    logic        [37:0]     adder10_out;
+    1374            0 :    logic        [37:0]     adder11_out;
+    1375            0 :    logic        [37:0]     adder12_out;
+    1376            0 :    logic        [37:0]     adder13_out;
+    1377            0 :    logic        [37:0]     adder14_out;
+    1378            0 :    logic        [37:0]     adder15_out;
     1379              : 
-    1380            0 :    logic        [64:0]     ar_shifted;
+    1380            0 :    logic        [64:0]     ar_shifted;
     1381            0 :    logic         [5:0]     shortq;
-    1382           40 :    logic         [4:0]     shortq_shift;
-    1383           26 :    logic         [4:0]     shortq_decode;
-    1384           40 :    logic         [4:0]     shortq_shift_ff;
-    1385           40 :    logic                   shortq_enable;
-    1386           40 :    logic                   shortq_enable_ff;
-    1387            0 :    logic        [32:0]     shortq_dividend;
+    1382            0 :    logic         [4:0]     shortq_shift;
+    1383            2 :    logic         [4:0]     shortq_decode;
+    1384            0 :    logic         [4:0]     shortq_shift_ff;
+    1385            0 :    logic                   shortq_enable;
+    1386            0 :    logic                   shortq_enable_ff;
+    1387            0 :    logic        [32:0]     shortq_dividend;
     1388              : 
     1389            0 :    logic                   by_zero_case;
     1390            0 :    logic                   by_zero_case_ff;
@@ -1746,7 +1746,7 @@
     1642              : 
     1643            0 :    logic [5:0]  dw_a_enc;
     1644            0 :    logic [5:0]  dw_b_enc;
-    1645           18 :    logic [6:0]  dw_shortq_raw;
+    1645            0 :    logic [6:0]  dw_shortq_raw;
     1646              : 
     1647              : 
     1648              : 
@@ -1821,14 +1821,14 @@
     1717              : 
     1718              : module el2_exu_div_cls
     1719              :   (
-    1720           18 :    input  logic [32:0] operand,
+    1720            0 :    input  logic [32:0] operand,
     1721              : 
-    1722           42 :    output logic [4:0]  cls                  // Count leading sign bits - "n" format ignoring [32]
+    1722            0 :    output logic [4:0]  cls                  // Count leading sign bits - "n" format ignoring [32]
     1723              :    );
     1724              : 
     1725              : 
-    1726           16 :    logic [4:0]   cls_zeros;
-    1727           46 :    logic [4:0]   cls_ones;
+    1726            0 :    logic [4:0]   cls_zeros;
+    1727            0 :    logic [4:0]   cls_ones;
     1728              : 
     1729              : 
     1730              : assign cls_zeros[4:0]             = ({5{operand[31]    ==  {           1'b1} }} & 5'd00) |
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_mul_ctl.sv.html
index 44f78298272..0294ae57976 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23       583434 :    input logic          clk,              // Top level clock
+      23        12564 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209      5408896 :              if (bcompress_test_bit_d)
+     209       141056 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236      5408896 :              if (bdecompress_test_bit_d)
+     236       141056 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu.sv.html
index bf9cc22bc73..73220454d1b 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        44.2%
+    
+        40.7%
     
     
-        76
+        70
     
     
         172
@@ -129,18 +129,18 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28       583434 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29       583434 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30       583434 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28        12564 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        12564 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        12564 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
-      33        35132 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
+      33          816 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
       34              : 
-      35         1596 :    input logic exu_flush_final, // flush, includes upper and lower
-      36        35132 :    input logic dec_tlu_i0_commit_cmt , // committed i0
+      35           68 :    input logic exu_flush_final, // flush, includes upper and lower
+      36          816 :    input logic dec_tlu_i0_commit_cmt , // committed i0
       37            0 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
       38            0 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
-      39          680 :    input logic [31:1] exu_flush_path_final, // flush fetch address
+      39            8 :    input logic [31:1] exu_flush_path_final, // flush fetch address
       40              : 
       41            0 :    input logic [31:0]  dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
       42            0 :    input logic         dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
@@ -172,10 +172,10 @@
       68            0 :    output logic                            ifu_axi_bready,
       69              : 
       70              :    // AXI Read Channels
-      71        35770 :    output logic                            ifu_axi_arvalid,
-      72        35770 :    input  logic                            ifu_axi_arready,
-      73        23272 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      74        14112 :    output logic [31:0]                     ifu_axi_araddr,
+      71          824 :    output logic                            ifu_axi_arvalid,
+      72          824 :    input  logic                            ifu_axi_arready,
+      73          104 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      74           16 :    output logic [31:0]                     ifu_axi_araddr,
       75            2 :    output logic [3:0]                      ifu_axi_arregion,
       76            0 :    output logic [7:0]                      ifu_axi_arlen,
       77            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -185,10 +185,10 @@
       81            2 :    output logic [2:0]                      ifu_axi_arprot,
       82            0 :    output logic [3:0]                      ifu_axi_arqos,
       83              : 
-      84        71536 :    input  logic                            ifu_axi_rvalid,
+      84         1644 :    input  logic                            ifu_axi_rvalid,
       85            2 :    output logic                            ifu_axi_rready,
-      86         7408 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-      87         3454 :    input  logic [63:0]                     ifu_axi_rdata,
+      86           32 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+      87           12 :    input  logic [63:0]                     ifu_axi_rdata,
       88            0 :    input  logic [1:0]                      ifu_axi_rresp,
       89              : 
       90            2 :    input  logic                      ifu_bus_clk_en,
@@ -206,10 +206,10 @@
      102            0 :    output logic                      iccm_dma_rvalid,
      103            0 :    output logic [63:0]               iccm_dma_rdata,
      104            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     105         1594 :    output logic                      iccm_ready,
+     105           66 :    output logic                      iccm_ready,
      106              : 
-     107        35132 :    output logic       ifu_pmu_instr_aligned,
-     108         1286 :    output logic       ifu_pmu_fetch_stall,
+     107          816 :    output logic       ifu_pmu_instr_aligned,
+     108           30 :    output logic       ifu_pmu_fetch_stall,
      109            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
      110              : 
      111              : //   I$ & ITAG Ports
@@ -217,8 +217,8 @@
      113            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      114            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      115              : 
-     116         2004 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     117         7972 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     116           38 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     117           38 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      118            0 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      119            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
      120            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
@@ -227,8 +227,8 @@
      123              : 
      124            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
      125            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     126         7972 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     127        28098 :    output logic                      ic_sel_premux_data, // Select the premux data.
+     126           38 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     127          594 :    output logic                      ic_sel_premux_data, // Select the premux data.
      128              : 
      129            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      130            0 :    output logic                      ic_debug_rd_en,     // Icache debug rd
@@ -244,7 +244,7 @@
      140              : 
      141              : 
      142              :    // ICCM ports
-     143          268 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
+     143            8 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
      144            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
      145            0 :    output logic                      iccm_rden,          // ICCM read enable.
      146            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
@@ -259,46 +259,46 @@
      155            0 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
      156              : 
      157              : // Perf counter sigs
-     158        35772 :    output logic       ifu_pmu_ic_miss, // ic miss
+     158          824 :    output logic       ifu_pmu_ic_miss, // ic miss
      159            0 :    output logic       ifu_pmu_ic_hit, // ic hit
      160            0 :    output logic       ifu_pmu_bus_error, // iside bus error
      161            0 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
-     162        35770 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
+     162          824 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
      163              : 
      164              : 
      165            0 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
      166            0 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
      167              : 
-     168        33540 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
+     168          608 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
      169            0 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
      170            0 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
-     172          760 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
+     172           12 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173           10 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174        17896 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174          310 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
-     176        35772 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
+     176          824 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
-     178          256 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
-     179         1124 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180        11398 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     178            4 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
+     179           24 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
+     180           10 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
-     184           44 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
-     185          940 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186         2402 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-     187          548 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+     184            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+     185           20 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
+     186            2 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     187            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
-     190         1914 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191         2402 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-     192          236 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+     190            4 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
+     191            2 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     192            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
-     195           56 :    input dec_tlu_flush_lower_wb,
+     195            4 :    input dec_tlu_flush_lower_wb,
      196              : 
-     197         5200 :    output logic [15:0] ifu_i0_cinst,
+     197          166 :    output logic [15:0] ifu_i0_cinst,
      198              : 
      199            2 :     output logic [31:1] ifu_pmp_addr,
      200            0 :     input  logic        ifu_pmp_error,
@@ -315,12 +315,12 @@
      211              :    localparam TAGWIDTH = 2 ;
      212              :    localparam IDWIDTH  = 2 ;
      213              : 
-     214         2100 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
-     215            2 :    logic [31:1]            ifc_fetch_addr_f;
+     214            0 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
+     215            2 :    logic [31:1]            ifc_fetch_addr_f;
      216            2 :    logic [31:1]            ifc_fetch_addr_bf;
      217              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
      218              : 
-     219        32400 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
+     219          786 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
      220            2 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
      221              : 
      222            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
@@ -329,33 +329,33 @@
      225              :    assign ifu_ic_error_start = ic_error_start;
      226              : 
      227              : 
-     228        13832 :    logic        ic_write_stall;
+     228          312 :    logic        ic_write_stall;
      229            0 :    logic        ic_dma_active;
-     230         1598 :    logic        ifc_dma_access_ok;
+     230           70 :    logic        ifc_dma_access_ok;
      231            0 :    logic [1:0]  ic_access_fault_f;
      232            0 :    logic [1:0]  ic_access_fault_type_f;
-     233        35808 :    logic        ifu_ic_mb_empty;
+     233          824 :    logic        ifu_ic_mb_empty;
      234              : 
-     235        35640 :    logic ic_hit_f;
+     235          790 :    logic ic_hit_f;
      236              : 
-     237         4996 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238         6092 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
-     239         2224 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240         2930 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
-     241         5484 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
-     242         5968 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243         2760 :    logic [11:0] ifu_bp_poffset_f; // predicted target
-     244          164 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
-     245         2152 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
-     246         4480 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247         2402 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     237            0 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
+     238          176 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     239            0 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
+     240            2 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     241          184 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
+     242          176 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
+     243          208 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     244            0 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
+     245            0 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
+     246          208 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
+     247            2 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
-     251        32400 :    logic [1:0]   ic_fetch_val_f;
-     252         7972 :    logic [31:0] ic_data_f;
-     253         7972 :    logic [31:0] ifu_fetch_data_f;
-     254        17874 :    logic ifc_fetch_req_f;
+     251          786 :    logic [1:0]   ic_fetch_val_f;
+     252           38 :    logic [31:0] ic_data_f;
+     253           38 :    logic [31:0] ifu_fetch_data_f;
+     254          314 :    logic ifc_fetch_req_f;
      255            0 :    logic ifc_fetch_req_f_raw;
      256            0 :    logic iccm_dma_rd_ecc_double_err;
      257            0 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
@@ -369,7 +369,7 @@
      265              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
      266              : 
      267            2 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
-     268        17874 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
+     268          314 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
      269            2 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
      270            0 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
      271            0 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_aln_ctl.sv.html
index bb83b601e03..2f21d404cf2 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_aln_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        76.0%
+    
+        58.4%
     
     
-        95
+        73
     
     
         125
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30       583434 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31       583434 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        12564 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        12564 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -141,166 +141,166 @@
       37            0 :    input logic [1:0]                              ic_access_fault_f,        // Instruction access fault for the current fetch.
       38            0 :    input logic [1:0]                              ic_access_fault_type_f,   // Instruction access fault types
       39              : 
-      40         1596 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
+      40           68 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
       41              : 
-      42        35132 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
+      42          816 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
       43              : 
-      44         7972 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
+      44           38 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
       45              : 
-      46        32400 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
+      46          786 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
       47            2 :    input logic [31:1]                             ifu_fetch_pc,             // starting pc of fetch
       48              : 
       49              : 
       50              : 
-      51        33540 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
+      51          608 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
       52            0 :    output logic                                   ifu_i0_icaf,              // Instruction 0 has access fault
       53            0 :    output logic [1:0]                             ifu_i0_icaf_type,         // Instruction 0 access fault type
       54            0 :    output logic                                   ifu_i0_icaf_second,       // Instruction 0 has access fault on second 2B of 4B inst
       55              : 
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
-      57          760 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
+      57           12 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58           10 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59        17896 :    output logic                                   ifu_i0_pc4,
+      59          310 :    output logic                                   ifu_i0_pc4,
       60              : 
-      61        27644 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62         2100 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      61          708 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
+      62            0 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65         2402 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
-      66         2224 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67         2760 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      65            2 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      66            0 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
+      67          208 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
-      70         5968 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
-      71         5484 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
-      72         2152 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
-      73         4996 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
-      74         4480 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
-      75          164 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
+      70          176 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
+      71          184 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
+      72            0 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
+      73            0 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
+      74          208 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
+      75            0 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
       76              : 
       77              : 
-      78          256 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
-      79         1124 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80        11398 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      78            4 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
+      79           24 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
+      80           10 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
       84              : 
-      85        35132 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
+      85          816 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
       86              : 
-      87         5200 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
+      87          166 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
       88              :    );
       89              : 
       90              : 
       91              : 
-      92        35640 :    logic                                          ifvalid;
+      92          790 :    logic                                          ifvalid;
       93            0 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
       94            0 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
       95              : 
       96            0 :    logic [1:0]                                    f2val_in, f2val;
-      97        11836 :    logic [1:0]                                    f1val_in, f1val;
-      98        21612 :    logic [1:0]                                    f0val_in, f0val;
-      99          168 :    logic [1:0]                                    sf1val, sf0val;
+      97          604 :    logic [1:0]                                    f1val_in, f1val;
+      98          182 :    logic [1:0]                                    f0val_in, f0val;
+      99            0 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
-     101         5200 :    logic [31:0]                                   aligndata;
-     102        17896 :    logic                                          first4B, first2B;
+     101          122 :    logic [31:0]                                   aligndata;
+     102          310 :    logic                                          first4B, first2B;
      103              : 
-     104          668 :    logic [31:0]                                   uncompress0;
-     105        35132 :    logic                                          i0_shift;
-     106        12408 :    logic                                          shift_2B, shift_4B;
-     107        12536 :    logic                                          f1_shift_2B;
-     108        11836 :    logic                                          f2_valid, sf1_valid, sf0_valid;
+     104            4 :    logic [31:0]                                   uncompress0;
+     105          816 :    logic                                          i0_shift;
+     106          300 :    logic                                          shift_2B, shift_4B;
+     107          428 :    logic                                          f1_shift_2B;
+     108          604 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
-     110         5200 :    logic [31:0]                                   ifirst;
-     111        21612 :    logic [1:0]                                    alignval;
-     112         6380 :    logic [31:1]                                   firstpc, secondpc;
+     110          122 :    logic [31:0]                                   ifirst;
+     111          182 :    logic [1:0]                                    alignval;
+     112           16 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114         3192 :    logic [11:0]                                   f1poffset;
-     115         2524 :    logic [11:0]                                   f0poffset;
-     116         3606 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117         9166 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
-     118         4954 :    logic [1:0]                                    f1hist1;
-     119         3444 :    logic [1:0]                                    f0hist1;
-     120         4554 :    logic [1:0]                                    f1hist0;
-     121         5244 :    logic [1:0]                                    f0hist0;
+     114          212 :    logic [11:0]                                   f1poffset;
+     115          212 :    logic [11:0]                                   f0poffset;
+     116            6 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117            2 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     118          180 :    logic [1:0]                                    f1hist1;
+     119            4 :    logic [1:0]                                    f0hist1;
+     120          172 :    logic [1:0]                                    f1hist0;
+     121            0 :    logic [1:0]                                    f0hist0;
      122              : 
-     123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
+     123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
      124              : 
      125            0 :    logic [1:0]                                    f1ictype;
      126            0 :    logic [1:0]                                    f0ictype;
      127              : 
-     128         1932 :    logic [1:0]                                    f1pc4;
-     129         3732 :    logic [1:0]                                    f0pc4;
+     128            0 :    logic [1:0]                                    f1pc4;
+     129            0 :    logic [1:0]                                    f0pc4;
      130              : 
-     131            0 :    logic [1:0]                                    f1ret;
-     132           96 :    logic [1:0]                                    f0ret;
-     133         1852 :    logic [1:0]                                    f1way;
-     134         2896 :    logic [1:0]                                    f0way;
+     131            0 :    logic [1:0]                                    f1ret;
+     132            0 :    logic [1:0]                                    f0ret;
+     133            0 :    logic [1:0]                                    f1way;
+     134            0 :    logic [1:0]                                    f0way;
      135              : 
-     136         3748 :    logic [1:0]                                    f1brend;
-     137         3024 :    logic [1:0]                                    f0brend;
+     136          208 :    logic [1:0]                                    f1brend;
+     137            0 :    logic [1:0]                                    f0brend;
      138              : 
-     139         2812 :    logic [1:0]                                    alignbrend;
-     140         5160 :    logic [1:0]                                    alignpc4;
+     139          208 :    logic [1:0]                                    alignbrend;
+     140            0 :    logic [1:0]                                    alignpc4;
      141              : 
-     142          180 :    logic [1:0]                                    alignret;
-     143         4324 :    logic [1:0]                                    alignway;
-     144         6856 :    logic [1:0]                                    alignhist1;
-     145         6496 :    logic [1:0]                                    alignhist0;
-     146        10744 :    logic [1:1]                                    alignfromf1;
-     147         5920 :    logic                                          i0_ends_f1;
+     142            0 :    logic [1:0]                                    alignret;
+     143            0 :    logic [1:0]                                    alignway;
+     144          184 :    logic [1:0]                                    alignhist1;
+     145          172 :    logic [1:0]                                    alignhist0;
+     146          242 :    logic [1:1]                                    alignfromf1;
+     147          218 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
-     150         2024 :    logic [31:1]                                   f1prett;
-     151         1550 :    logic [31:1]                                   f0prett;
-     152            0 :    logic [1:0]                                    f1dbecc;
+     150            0 :    logic [31:1]                                   f1prett;
+     151            0 :    logic [31:1]                                   f0prett;
+     152            0 :    logic [1:0]                                    f1dbecc;
      153            0 :    logic [1:0]                                    f0dbecc;
      154            0 :    logic [1:0]                                    f1icaf;
      155            0 :    logic [1:0]                                    f0icaf;
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159         5160 :    logic                                          i0_brp_pc4;
+     159            0 :    logic                                          i0_brp_pc4;
      160              : 
-     161         1068 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
+     161           16 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165        11864 :    logic [1:0]                                    wrptr, wrptr_in;
-     166        10712 :    logic [1:0]                                    rdptr, rdptr_in;
-     167        11356 :    logic [2:0]                                    qwen;
-     168          942 :    logic [31:0]                                   q2,q1,q0;
-     169         7680 :    logic                                          q2off_in, q2off;
-     170         7904 :    logic                                          q1off_in, q1off;
-     171         7994 :    logic                                          q0off_in, q0off;
-     172        23156 :    logic                                          f0_shift_2B;
+     165          258 :    logic [1:0]                                    wrptr, wrptr_in;
+     166          252 :    logic [1:0]                                    rdptr, rdptr_in;
+     167          258 :    logic [2:0]                                    qwen;
+     168            4 :    logic [31:0]                                   q2,q1,q0;
+     169          232 :    logic                                          q2off_in, q2off;
+     170          226 :    logic                                          q1off_in, q1off;
+     171          230 :    logic                                          q0off_in, q0off;
+     172          724 :    logic                                          f0_shift_2B;
      173              : 
-     174         5430 :    logic [31:0]                                   q0eff;
-     175         3148 :    logic [31:0]                                   q0final;
-     176        17538 :    logic                                          q0ptr;
-     177        17538 :    logic [1:0]                                    q0sel;
+     174           16 :    logic [31:0]                                   q0eff;
+     175           28 :    logic [31:0]                                   q0final;
+     176          286 :    logic                                          q0ptr;
+     177          286 :    logic [1:0]                                    q0sel;
      178              : 
-     179         5024 :    logic [31:0]                                   q1eff;
-     180         6816 :    logic [15:0]                                   q1final;
-     181        13360 :    logic                                          q1ptr;
-     182        13360 :    logic [1:0]                                    q1sel;
+     179            8 :    logic [31:0]                                   q1eff;
+     180           14 :    logic [15:0]                                   q1final;
+     181          612 :    logic                                          q1ptr;
+     182          612 :    logic [1:0]                                    q1sel;
      183              : 
-     184        10712 :    logic [2:0]                                    qren;
+     184          252 :    logic [2:0]                                    qren;
      185              : 
-     186         2192 :    logic                                          consume_fb1, consume_fb0;
+     186          752 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
      190              :    localparam                                     BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
-     191           40 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
-     192          172 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
-     193           96 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
+     191            0 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
+     192          212 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
+     193            0 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
      194              : 
      195              :    localparam                                     MHI   = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
-     198          876 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199         6280 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     198            0 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
+     199            2 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201            0 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_bp_ctl.sv.html
index 58fb182c71e..926a2527c41 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_bp_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        82.7%
+    
+        63.6%
     
     
-        91
+        70
     
     
         110
@@ -135,47 +135,47 @@
       31              :  )
       32              :   (
       33              : 
-      34       583434 :    input logic clk,
+      34        12564 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
-      37        35640 :    input logic ic_hit_f,      // Icache hit, enables F address capture
+      37          790 :    input logic ic_hit_f,      // Icache hit, enables F address capture
       38              : 
       39            2 :    input logic [31:1] ifc_fetch_addr_f, // look up btb address
-      40        17874 :    input logic ifc_fetch_req_f,  // F1 valid
+      40          314 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
-      42         1914 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43         2402 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
-      44          236 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
+      42            4 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
+      43            2 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      44            4 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
       47              : 
-      48           56 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
+      48            4 :    input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F
       49            0 :    input logic dec_tlu_flush_leak_one_wb, // don't hit for leak one fetches
       50              : 
       51            0 :    input logic dec_tlu_bpred_disable, // disable all branch prediction
       52              : 
-      53           44 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
+      53            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
-      55          940 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56         2402 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
-      57          548 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
+      55           20 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
+      56            2 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      57            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
-      60         1596 :    input logic exu_flush_final, // all flushes
+      60           68 :    input logic exu_flush_final, // all flushes
       61              : 
-      62         6092 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
-      63         2224 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64         2930 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      62          176 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      63            0 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      64            2 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66         2402 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66            2 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
-      68         4996 :    output logic [1:0] ifu_bp_way_f, // way
-      69          164 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
-      70         5484 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
-      71         5968 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
-      72         2152 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
-      73         4480 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74         2760 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      68            0 :    output logic [1:0] ifu_bp_way_f, // way
+      69            0 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
+      70          184 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
+      71          176 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
+      72            0 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
+      73          208 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
+      74          208 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -205,95 +205,95 @@
      101              :    localparam BHT_NO_ADDR_MATCH  = ( pt.BHT_ARRAY_DEPTH <= 16 );
      102              : 
      103              : 
-     104          356 :    logic exu_mp_valid_write;
-     105         1236 :    logic exu_mp_ataken;
-     106         1372 :    logic exu_mp_valid; // conditional branch mispredict
-     107          760 :    logic exu_mp_boffset; // branch offsett
-     108          732 :    logic exu_mp_pc4; // branch is a 4B inst
-     109          136 :    logic exu_mp_call; // branch is a call inst
-     110          172 :    logic exu_mp_ret; // branch is a ret inst
-     111           52 :    logic exu_mp_ja; // branch is a jump always
-     112          208 :    logic [1:0] exu_mp_hist; // new history
-     113          524 :    logic [11:0] exu_mp_tgt; // target offset
-     114          548 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115         7260 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116         5352 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
-     117          236 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
+     104           28 :    logic exu_mp_valid_write;
+     105           60 :    logic exu_mp_ataken;
+     106           64 :    logic exu_mp_valid; // conditional branch mispredict
+     107           16 :    logic exu_mp_boffset; // branch offsett
+     108            4 :    logic exu_mp_pc4; // branch is a 4B inst
+     109            8 :    logic exu_mp_call; // branch is a call inst
+     110            8 :    logic exu_mp_ret; // branch is a ret inst
+     111            4 :    logic exu_mp_ja; // branch is a jump always
+     112           64 :    logic [1:0] exu_mp_hist; // new history
+     113           16 :    logic [11:0] exu_mp_tgt; // target offset
+     114            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
+     115          176 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116          172 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     117            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120         2402 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120            2 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122            0 :    logic use_mp_way, use_mp_way_p1;
-     123            6 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
-     124          300 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
+     123            0 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
+     124            0 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127         2760 :    logic [11:0]       btb_rd_tgt_f;
-     128          920 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
-     129         3368 :    logic [1:1]        bp_total_branch_offset_f;
+     127          208 :    logic [11:0]       btb_rd_tgt_f;
+     128            0 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
+     129           14 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
      131            2 :    logic [31:1]       bp_btb_target_adder_f;
      132            2 :    logic [31:1]       bp_rs_call_target_f;
-     133          300 :    logic              rs_push, rs_pop, rs_hold;
-     134          244 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
+     133            2 :    logic              rs_push, rs_pop, rs_hold;
+     134            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;
      135            0 :    logic [pt.BTB_BTAG_SIZE-1:0] btb_wr_tag, fetch_rd_tag_f, fetch_rd_tag_p1_f;
-     136          188 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
-     137           44 :    logic               btb_wr_en_way0, btb_wr_en_way1;
+     136            4 :    logic [BTB_DWIDTH-1:0]        btb_wr_data;
+     137            0 :    logic               btb_wr_en_way0, btb_wr_en_way1;
      138              : 
      139              : 
-     140         1372 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
-     141          236 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
+     140           64 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
+     141            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
      142            0 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144            0 :    logic  branch_error_bank_conflict_f;
-     145         2402 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145            2 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146            0 :    logic [1:0] num_valids;
      147            2 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
      148            0 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
      149            4 :                         mp_wrindex_dec, mp_wrlru_b0;
-     150         7082 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
-     151           44 :    logic  tag_match_way0_f, tag_match_way1_f;
-     152         2928 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
-     153          456 :    logic [1:0] bht_valid_f, bht_force_taken_f;
+     150           40 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
+     151            0 :    logic  tag_match_way0_f, tag_match_way1_f;
+     152            0 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
+     153            0 :    logic [1:0] bht_valid_f, bht_force_taken_f;
      154              : 
-     155            0 :    logic leak_one_f, leak_one_f_d1;
+     155            0 :    logic leak_one_f, leak_one_f_d1;
      156              : 
      157              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way0_out ;
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161         1264 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
-     162           68 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
+     161            4 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     162            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
-     164         1052 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
-     165           60 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
+     164          208 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
+     165            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;
      166              : 
-     167          628 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
+     167          208 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169         6092 :    logic                                         final_h;
-     170          776 :    logic                                         btb_fg_crossing_f;
-     171          628 :    logic                                         middle_of_bank;
+     169          176 :    logic                                         final_h;
+     170            0 :    logic                                         btb_fg_crossing_f;
+     171           12 :    logic                                         middle_of_bank;
      172              : 
      173              : 
-     174         5360 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
+     174          176 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
      175            0 :    logic                                         branch_error_bank_conflict_p1_f;
-     176           40 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
+     176            0 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
      177              : 
-     178            0 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
+     178            0 :    logic [1:0]                                   btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;
      179            2 :    logic [31:2] fetch_addr_p1_f;
      180              : 
      181              : 
-     182           44 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
-     183          164 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
+     182            4 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
+     183          208 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185          692 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
-     187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
+     187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
-     190         4816 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191         5648 :     logic [1:0]                                  bht_bank1_rd_data_f;
-     192         5268 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
+     190           12 :     logic [1:0]                                  bht_bank0_rd_data_f;
+     191            0 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     192          176 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
      195              :    assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict
@@ -348,7 +348,7 @@
      244              :    // set on leak one, hold until next flush without leak one
      245              :    assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
      246              : 
-     247         1596 : logic exu_flush_final_d1;
+     247           68 : logic exu_flush_final_d1;
      248              : 
      249              :  if(!pt.BTB_FULLYA) begin : genblock1
      250              :    assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
@@ -461,8 +461,8 @@
      357              : 
      358              :  end // if (!pt.BTB_FULLYA)
      359              :    // Detect end of cache line and mask as needed
-     360         1578 :    logic eoc_near;
-     361          724 :    logic eoc_mask;
+     360           20 :    logic eoc_near;
+     361            6 :    logic eoc_mask;
      362              :    assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];
      363              :    assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));
      364              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372          920 :    logic [16:1] btb_sel_data_f;
+     372          208 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -484,7 +484,7 @@
      380              :                                     ({16{btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]) );
      381              : 
      382              : 
-     383          164 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
+     383            0 :    logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;
      384              : 
      385              :    // a valid taken target needs to kill the next fetch as we compute the target address
      386              :    assign ifu_bp_hit_taken_f = |(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f & ~leak_one_f_d1 & ~dec_tlu_bpred_disable;
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460         2402 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460            2 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500         3590 : logic [1:0] bloc_f;
-     501         4622 : logic use_fa_plus;
+     500           12 : logic [1:0] bloc_f;
+     501           12 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -719,8 +719,8 @@
      615              :                                                 exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
-     618          208 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619          416 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     618           64 :    logic [1:0] bht_wr_data0, bht_wr_data2;
+     619            0 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -732,9 +732,9 @@
      628              : 
      629              : 
      630              : 
-     631          756 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
+     631            6 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
      632              : 
-     633          756 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
+     633            6 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
      634              :    el2_btb_ghr_hash #(.pt(pt)) mpghrhs  (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      635              :    el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      636              :    el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676       132192 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676         3056 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678       132192 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679       132192 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678         3056 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679         3056 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684       132192 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684         3056 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686       132192 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687       132192 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686         3056 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687         3056 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -933,8 +933,8 @@
      829              : 
      830              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0]      bht_bank_wr_data ;
      831              :    logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0]                bht_bank_rd_data_out ;
-     832           12 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
-     833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
+     832            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
+     833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
      834              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0]           bht_bank_sel   ;
      835              : 
      836              :    for ( i=0; i<2; i++) begin : BANKS
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877       132192 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878       132192 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879       132192 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877         3056 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878         3056 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879         3056 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881       132192 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882       132192 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881         3056 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882         3056 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_compress_ctl.sv.html
index 06dd8241ccc..9718aa7a431 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_compress_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        97.4%
+    
+        81.6%
     
     
-        37
+        31
     
     
         38
@@ -127,14 +127,14 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26         3104 :    input  logic [15:0] din,        // 16-bit   compressed instruction
-      27          668 :    output logic [31:0] dout        // 32-bit uncompressed instruction
+      26           24 :    input  logic [15:0] din,        // 16-bit   compressed instruction
+      27            4 :    output logic [31:0] dout        // 32-bit uncompressed instruction
       28              :    );
       29              : 
       30              : 
-      31        12412 :    logic               legal;
+      31          300 :    logic               legal;
       32              : 
-      33         3104 :    logic [15:0]  i;
+      33           24 :    logic [15:0]  i;
       34              : 
       35            2 :    logic [31:0]  o,l1,l2,l3;
       36              : 
@@ -144,27 +144,27 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43         9736 :    logic rdrd;
-      44         6100 :    logic rdrs1;
-      45         6184 :    logic rs2rs2;
-      46          468 :    logic rdprd;
-      47         2816 :    logic rdprs1;
-      48          116 :    logic rs2prs2;
-      49        12390 :    logic rs2prd;
-      50        12414 :    logic uimm9_2;
-      51          316 :    logic ulwimm6_2;
-      52          464 :    logic ulwspimm7_2;
-      53          288 :    logic rdeq2;
-      54          220 :    logic rdeq1;
-      55        11290 :    logic rs1eq2;
-      56         2380 :    logic sbroffset8_1;
-      57          288 :    logic simm9_4;
-      58         5396 :    logic simm5_0;
-      59          668 :    logic sjaloffset11_1;
-      60           52 :    logic sluimm17_12;
-      61          664 :    logic uimm5_0;
-      62           24 :    logic uswimm6_2;
-      63          888 :    logic uswspimm7_2;
+      43          236 :    logic rdrd;
+      44          228 :    logic rdrs1;
+      45            8 :    logic rs2rs2;
+      46            4 :    logic rdprd;
+      47          220 :    logic rdprs1;
+      48            4 :    logic rs2prs2;
+      49          302 :    logic rs2prd;
+      50          302 :    logic uimm9_2;
+      51            0 :    logic ulwimm6_2;
+      52            8 :    logic ulwspimm7_2;
+      53            0 :    logic rdeq2;
+      54            8 :    logic rdeq1;
+      55          294 :    logic rs1eq2;
+      56          216 :    logic sbroffset8_1;
+      57            0 :    logic simm9_4;
+      58          232 :    logic simm5_0;
+      59           12 :    logic sjaloffset11_1;
+      60            0 :    logic sluimm17_12;
+      61            0 :    logic uimm5_0;
+      62            0 :    logic uswimm6_2;
+      63            8 :    logic uswspimm7_2;
       64              : 
       65              : 
       66              : 
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115         4300 :    logic [5:0] simm5d;
-     116         4300 :    logic [9:2] uimm9d;
+     115          220 :    logic [5:0] simm5d;
+     116          220 :    logic [9:2] uimm9d;
      117              : 
-     118         4300 :    logic [9:4] simm9d;
-     119         4300 :    logic [6:2] ulwimm6d;
-     120         4300 :    logic [7:2] ulwspimm7d;
-     121         4300 :    logic [5:0] uimm5d;
-     122         4300 :    logic [20:1] sjald;
+     118          220 :    logic [9:4] simm9d;
+     119          220 :    logic [6:2] ulwimm6d;
+     120          220 :    logic [7:2] ulwspimm7d;
+     121          220 :    logic [5:0] uimm5d;
+     122          220 :    logic [20:1] sjald;
      123              : 
-     124         4300 :    logic [31:12] sluimmd;
+     124          220 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,9 +272,9 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171         4300 :    logic [8:1]   sbr8d;
-     172         4300 :    logic [6:2]   uswimm6d;
-     173         5032 :    logic [7:2]   uswspimm7d;
+     171          220 :    logic [8:1]   sbr8d;
+     172          220 :    logic [6:2]   uswimm6d;
+     173          220 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
      176              :    assign sbr8d[8:1] =   { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ic_mem.sv.html
index de2aeb578c2..8566bf6d1fd 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26       583434 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27       583434 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26        12564 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27        12564 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -141,11 +141,11 @@
       37            0 :       input logic                                   ic_debug_wr_en,     // Icache debug wr
       38            0 :       input logic                                   ic_debug_tag_array, // Debug tag array
       39            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_debug_way,       // Debug way. Rd or Wr.
-      40         7972 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-      41        28098 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
+      40           38 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+      41          594 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
       42              : 
-      43         2004 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
-      44         7972 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      43           38 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
+      44           38 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       45            0 :       output logic [70:0]                           ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       46            0 :       output logic [25:0]                           ictag_debug_rd_data,// Debug icache tag.
       47            0 :       input logic  [70:0]                           ic_debug_wr_data,   // Debug wr cache.
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91       583434 :       input logic clk,
-      92       583434 :       input logic active_clk,
+      91        12564 :       input logic clk,
+      92        12564 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -201,8 +201,8 @@
       97            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en,
       98            0 :       input logic                          ic_rd_en,           // Read enable
       99              : 
-     100         2004 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
-     101         7972 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     100           38 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
+     101           38 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      102            0 :       input  logic [70:0]                             ic_debug_wr_data,   // Debug wr cache.
      103            0 :       output logic [70:0]                             ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      104            0 :       output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
@@ -212,8 +212,8 @@
      108            0 :       input logic                            ic_debug_wr_en,      // Icache debug wr
      109            0 :       input logic                            ic_debug_tag_array,  // Debug tag array
      110            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way,        // Debug way. Rd or Wr.
-     111         7972 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-     112        28098 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
+     111           38 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+     112          594 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
      113              : 
      114            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
      115            0 :       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
@@ -221,7 +221,7 @@
      117              : 
      118              :       ) ;
      119              : 
-     120         1142 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
+     120           12 :    logic [pt.ICACHE_TAG_INDEX_LO-1:1]                                             ic_rw_addr_ff;
      121            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_wren;    //bank x ways
      122            0 :    logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0]                        ic_b_sb_rden;    //bank x ways
      123              : 
@@ -231,9 +231,9 @@
      127            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                ic_debug_sel_sb;
      128              : 
      129              :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0]                  wb_dout ;       //  ways x bank
-     130         2004 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
+     130           38 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
      131              :    logic [pt.ICACHE_NUM_WAYS-1:0] [141:0]                                         wb_dout_way_pre;
-     132         7972 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
+     132           38 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
      133            0 :    logic [141:0]                                                                  wb_dout_ecc;
      134              : 
      135            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                bank_check_en;
@@ -245,11 +245,11 @@
      141            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en;    // debug wr_way
      142            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_rd_way_en_ff; // debug wr_way
      143            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_debug_wr_way_en;    // debug wr_way
-     144          268 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
+     144            8 :    logic [pt.ICACHE_INDEX_HI:1]                                                   ic_rw_addr_q;
      145              : 
-     146          268 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
+     146            8 :    logic [pt.ICACHE_BANKS_WAY-1:0]       [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
      147              : 
-     148          244 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
+     148            8 :    logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO]                           ic_rw_addr_q_inc;
      149            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                                 ic_rd_hit_q;
      150              : 
      151              : 
@@ -278,7 +278,7 @@
      174              : 
      175              : 
      176            2 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr;
-     177          268 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
+     177            8 :    logic [pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;
      178              : 
      179            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_up;
      180            0 :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]                 [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only_up;
@@ -296,7 +296,7 @@
      192              :    assign  ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      193              :    assign  ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] =  {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;
      194              : 
-     195         3526 :    logic end_of_cache_line;
+     195           16 :    logic end_of_cache_line;
      196              :    assign end_of_cache_line = (pt.ICACHE_LN_SZ==7'h40) ? (&ic_rw_addr_q[5:4]) : ic_rw_addr_q[4];
      197            2 :    always_comb begin : clkens
      198            2 :       ic_bank_way_clken  = '0;
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803       583434 :       input logic                                                   clk,
-     804       583434 :       input logic                                                   active_clk,
+     803        12564 :       input logic                                                   clk,
+     804        12564 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
@@ -945,7 +945,7 @@
      841            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en ;
      842            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_debug_rd_way_en_ff ;
      843              : 
-     844          268 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
+     844            8 :    logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO]              ic_rw_addr_q;
      845            2 :    logic [31:pt.ICACHE_TAG_LO]                                     ic_rw_addr_ff;
      846            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_rden_q;          // way
      847            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]                                  ic_tag_wren;          // way
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_iccm_mem.sv.html
index b8ca258cee4..be4c5614566 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,14 +129,14 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28       583434 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29       583434 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28        12564 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29        12564 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
       33            0 :    input logic                                        iccm_wren,                           // ICCM write enable
       34            0 :    input logic                                        iccm_rden,                           // ICCM read enable
-      35          268 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
+      35            8 :    input logic [pt.ICCM_BITS-1:1]                     iccm_rw_addr,                        // ICCM read/write address
       36            0 :    input logic                                        iccm_buf_correct_ecc,                // ICCM is doing a single bit error correct cycle
       37            0 :    input logic                                        iccm_correction_state,               // ICCM under a correction - This is needed to guard replacements when hit
       38            0 :    input logic [2:0]                                  iccm_wr_size,                        // ICCM write size
@@ -154,13 +154,13 @@
       50            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                wren_bank;
       51            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                rden_bank;
       52            0 :    logic [pt.ICCM_NUM_BANKS-1:0]                                                iccm_clken;
-      53          268 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
+      53            8 :    logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
       54              : 
       55            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
-      57          244 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58         9876 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
-      59         1142 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
+      57            8 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
+      58          260 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      59           12 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
       60            0 :    logic             [63:0]              iccm_rd_data_pre;
       61            0 :    logic             [63:0]              iccm_data;
       62            0 :    logic [1:0]                           addr_incr;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ifc_ctl.sv.html
index f26cb836fff..c9fa7147be3 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_ifc_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        78.6%
+    
+        69.0%
     
     
-        33
+        29
     
     
         42
@@ -130,27 +130,27 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29       583434 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30       583434 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        12564 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        12564 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
       34              : 
-      35        35640 :    input logic ic_hit_f,      // Icache hit
-      36        35808 :    input logic ifu_ic_mb_empty, // Miss buffer empty
+      35          790 :    input logic ic_hit_f,      // Icache hit
+      36          824 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
-      38        27644 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39         2100 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      38          708 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
+      39            0 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
-      41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
-      42         1596 :    input logic exu_flush_final, // FLush
-      43          680 :    input logic [31:1] exu_flush_path_final, // Flush path
+      41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
+      42           68 :    input logic exu_flush_final, // FLush
+      43            8 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45         6092 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
-      46         2224 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
+      45          176 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      46            0 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
-      48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
-      49        13832 :    input logic ic_write_stall, // IC is writing, stop fetching
+      48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
+      49          312 :    input logic ic_write_stall, // IC is writing, stop fetching
       50            0 :    input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
       51              : 
       52            0 :    input logic [31:0]  dec_tlu_mrac_ff ,   // side_effect and cacheable for each region
@@ -158,34 +158,34 @@
       54            2 :    output logic [31:1] ifc_fetch_addr_f, // fetch addr F
       55            2 :    output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
       56              : 
-      57        17874 :    output logic  ifc_fetch_req_f,  // fetch request valid F
+      57          314 :    output logic  ifc_fetch_req_f,  // fetch request valid F
       58              : 
-      59         1286 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
+      59           30 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
       60              : 
       61            2 :    output logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. BF stage
-      62        17874 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
+      62          314 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
       63            2 :    output logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. BF stage
       64            0 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       65            0 :    output logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       66              : 
-      67         1598 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
+      67           70 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
       68              : 
       69              : 
       70              :    );
       71              : 
       72            2 :    logic [31:1]  fetch_addr_bf;
       73            2 :    logic [31:1]  fetch_addr_next;
-      74         4040 :    logic [3:0]   fb_write_f, fb_write_ns;
+      74            0 :    logic [3:0]   fb_write_f, fb_write_ns;
       75              : 
-      76         4040 :    logic     fb_full_f_ns, fb_full_f;
-      77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
-      78        30576 :    logic     sel_last_addr_bf, sel_next_addr_bf;
-      79        49754 :    logic     miss_f, miss_a;
+      76            0 :    logic     fb_full_f_ns, fb_full_f;
+      77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
+      78          614 :    logic     sel_last_addr_bf, sel_next_addr_bf;
+      79         1138 :    logic     miss_f, miss_a;
       80            0 :    logic     flush_fb, dma_iccm_stall_any_f;
       81            4 :    logic     mb_empty_mod, goto_idle, leave_idle;
-      82        17778 :    logic     fetch_bf_en;
-      83         1342 :    logic         line_wrap;
-      84         1032 :    logic         fetch_addr_next_1;
+      82          318 :    logic     fetch_bf_en;
+      83           12 :    logic         line_wrap;
+      84           12 :    logic         fetch_addr_next_1;
       85              : 
       86              :    // FSM assignment
       87              :     typedef enum logic [1:0] { IDLE  = 2'b00 ,
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_mem_ctl.sv.html
index 229838fa544..71219f4f817 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_ifu_mem_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        45.0%
+    
+        44.7%
     
     
-        158
+        157
     
     
         351
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        53.6%
+    
+        50.0%
     
     
-        59
+        55
     
     
         110
@@ -131,40 +131,40 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30       583434 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31       583434 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32       583434 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30        12564 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        12564 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32        12564 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
-      35         1596 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
-      36           56 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
+      35           68 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
+      36            4 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
       37            0 :    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
-      38        35132 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
+      38          816 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
       39            0 :    input logic                       dec_tlu_force_halt,            // force halt.
       40              : 
       41            2 :    input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
       42            2 :    input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
-      43        17874 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
+      43          314 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
       44            2 :    input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
       45            0 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
-      47         1598 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
+      47           70 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49         6092 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49          176 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51         2930 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51            2 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
-      53        35772 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
-      54        35808 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
+      53          824 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
+      54          824 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
       55            0 :    output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
-      56        13832 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
+      56          312 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
       57              : 
       58              : /// PMU signals
-      59        35772 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
+      59          824 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
       60            0 :    output logic                      ifu_pmu_ic_hit,                // IC hit event
       61            0 :    output logic                      ifu_pmu_bus_error,             // Bus error event
       62            0 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
-      63        35770 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
+      63          824 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
       64              : 
       65              :   //-------------------------- IFU AXI signals--------------------------
       66              :    // AXI Write Channels
@@ -188,10 +188,10 @@
       84            0 :    output logic                            ifu_axi_bready,
       85              : 
       86              :    // AXI Read Channels
-      87        35770 :    output logic                            ifu_axi_arvalid,
-      88        35770 :    input  logic                            ifu_axi_arready,
-      89        23272 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-      90        14112 :    output logic [31:0]                     ifu_axi_araddr,
+      87          824 :    output logic                            ifu_axi_arvalid,
+      88          824 :    input  logic                            ifu_axi_arready,
+      89          104 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      90           16 :    output logic [31:0]                     ifu_axi_araddr,
       91            2 :    output logic [3:0]                      ifu_axi_arregion,
       92            0 :    output logic [7:0]                      ifu_axi_arlen,
       93            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -201,10 +201,10 @@
       97            2 :    output logic [2:0]                      ifu_axi_arprot,
       98            0 :    output logic [3:0]                      ifu_axi_arqos,
       99              : 
-     100        71536 :    input  logic                            ifu_axi_rvalid,
+     100         1644 :    input  logic                            ifu_axi_rvalid,
      101            2 :    output logic                            ifu_axi_rready,
-     102         7408 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     103         3454 :    input  logic [63:0]                     ifu_axi_rdata,
+     102           32 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     103           12 :    input  logic [63:0]                     ifu_axi_rdata,
      104            0 :    input  logic [1:0]                      ifu_axi_rresp,
      105              : 
      106            2 :     input  logic                     ifu_bus_clk_en,
@@ -221,7 +221,7 @@
      117            0 :    output logic                      iccm_dma_rvalid,   //   Data read from iccm is valid
      118            0 :    output logic [63:0]               iccm_dma_rdata,    //   dma data read from iccm
      119            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     120         1594 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
+     120           66 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
      121              : 
      122              : 
      123              : //   I$ & ITAG Ports
@@ -229,8 +229,8 @@
      125            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
      126            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      127              : 
-     128         2004 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
-     129         7972 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     128           38 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
+     129           38 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      130            0 :    input  logic [70:0]               ic_debug_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      131            0 :    input  logic [25:0]               ictag_debug_rd_data,  // Debug icache tag.
      132            0 :    output logic [70:0]               ic_debug_wr_data,     // Debug wr cache.
@@ -253,7 +253,7 @@
      149            0 :    input  logic                      ic_tag_perr,        // Icache Tag parity error
      150              : 
      151              :    // ICCM ports
-     152          268 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
+     152            8 :    output logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,       // ICCM read/write address.
      153            0 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
      154            0 :    output logic                      iccm_rden,          // ICCM read enable.
      155            0 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
@@ -261,9 +261,9 @@
      157              : 
      158            0 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
      159            0 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
-     160        32400 :    input  logic [1:0]                ifu_fetch_val,
+     160          786 :    input  logic [1:0]                ifu_fetch_val,
      161              :    // IFU control signals
-     162        35640 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
+     162          790 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
      163            0 :    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
      164            0 :    output logic [1:0]                ic_access_fault_type_f, // Access fault types
      165            0 :    output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
@@ -274,10 +274,10 @@
      170              : 
      171            0 :    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
      172            0 :    output logic                      iccm_dma_sb_error,      // Single Bit ECC error from a DMA access
-     173        32400 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
-     174         7972 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
-     175         7972 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
-     176        28098 :    output logic                      ic_sel_premux_data,     // Select premux data.
+     173          786 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
+     174           38 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
+     175           38 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
+     176          594 :    output logic                      ic_sel_premux_data,     // Select premux data.
      177              : 
      178              : /////  Debug
      179            0 :    input  el2_cache_debug_pkt_t     dec_tlu_ic_diag_pkt ,       // Icache/tag debug read/write packet
@@ -304,8 +304,8 @@
      200              : 
      201              : 
      202              : 
-     203        71536 :    logic           bus_ifu_wr_en     ;
-     204        71536 :    logic           bus_ifu_wr_en_ff  ;
+     203         1644 :    logic           bus_ifu_wr_en     ;
+     204         1642 :    logic           bus_ifu_wr_en_ff  ;
      205            0 :    logic           bus_ifu_wr_en_ff_q  ;
      206            0 :    logic           bus_ifu_wr_en_ff_wo_err  ;
      207            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     bus_ic_wr_en ;
@@ -333,36 +333,36 @@
      229            0 :    logic           scnd_miss_index_match ;
      230              : 
      231              : 
-     232         1594 :    logic           ifc_dma_access_q_ok;
+     232           66 :    logic           ifc_dma_access_q_ok;
      233            0 :    logic           ifc_iccm_access_f ;
      234            0 :    logic           ifc_region_acc_fault_f;
      235            0 :    logic           ifc_region_acc_fault_final_f;
      236            0 :    logic  [1:0]    ifc_bus_acc_fault_f;
-     237        35772 :    logic           ic_act_miss_f;
+     237          824 :    logic           ic_act_miss_f;
      238            0 :    logic           ic_miss_under_miss_f;
-     239         1064 :    logic           ic_ignore_2nd_miss_f;
+     239           52 :    logic           ic_ignore_2nd_miss_f;
      240            0 :    logic           ic_act_hit_f;
-     241        35770 :    logic           miss_pending;
+     241          822 :    logic           miss_pending;
      242            2 :    logic [31:1]    imb_in , imb_ff  ;
      243            2 :    logic [31:pt.ICACHE_BEAT_ADDR_HI+1]    miss_addr_in , miss_addr  ;
-     244         2360 :    logic           miss_wrap_f ;
-     245         1596 :    logic           flush_final_f;
-     246        19150 :    logic           ifc_fetch_req_f;
-     247        17874 :    logic           ifc_fetch_req_f_raw;
-     248        35640 :    logic           fetch_req_f_qual   ;
-     249        17874 :    logic           ifc_fetch_req_qual_bf ;
+     244            8 :    logic           miss_wrap_f ;
+     245           68 :    logic           flush_final_f;
+     246          378 :    logic           ifc_fetch_req_f;
+     247          314 :    logic           ifc_fetch_req_f_raw;
+     248          790 :    logic           fetch_req_f_qual   ;
+     249          314 :    logic           ifc_fetch_req_qual_bf ;
      250            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     replace_way_mb_any;
-     251        35768 :    logic           last_beat;
-     252        49736 :    logic           reset_beat_cnt  ;
-     253        13136 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
-     254        35220 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
+     251          820 :    logic           last_beat;
+     252         1144 :    logic           reset_beat_cnt  ;
+     253          320 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
+     254          172 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
      255            2 :    logic [31:1]    ifu_fetch_addr_int_f ;
      256            2 :    logic [31:1]    ifu_ic_rw_int_addr ;
-     257        35770 :    logic           crit_wd_byp_ok_ff ;
-     258        35640 :    logic           ic_crit_wd_rdy_new_ff;
-     259         3542 :    logic   [79:0]  ic_byp_data_only_pre_new;
-     260         3204 :    logic   [79:0]  ic_byp_data_only_new;
-     261        35640 :    logic           ic_byp_hit_f ;
+     257          822 :    logic           crit_wd_byp_ok_ff ;
+     258          790 :    logic           ic_crit_wd_rdy_new_ff;
+     259           36 :    logic   [79:0]  ic_byp_data_only_pre_new;
+     260           12 :    logic   [79:0]  ic_byp_data_only_new;
+     261          790 :    logic           ic_byp_hit_f ;
      262            2 :    logic           ic_valid ;
      263            2 :    logic           ic_valid_ff;
      264            0 :    logic           reset_all_tags;
@@ -380,94 +380,94 @@
      276              : 
      277            0 :    logic           reset_ic_in ;
      278            0 :    logic           reset_ic_ff ;
-     279         1142 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
+     279           12 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]     vaddr_f ;
      280            2 :    logic [31:1]    ifu_status_wr_addr;
      281            0 :    logic           sel_mb_addr ;
      282            0 :    logic           sel_mb_addr_ff ;
      283            0 :    logic           sel_mb_status_addr ;
-     284         7972 :    logic [63:0]    ic_final_data;
+     284           38 :    logic [63:0]    ic_final_data;
      285              : 
      286            0 :    logic [pt.ICACHE_STATUS_BITS-1:0]                              way_status_new_ff ;
      287            0 :    logic                                    way_status_wr_en_ff ;
      288            0 :    logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0]        way_status_out ;
      289            0 :    logic [1:0]                              ic_debug_way_enc;
      290              : 
-     291         7408 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
+     291           32 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
      292              : 
-     293        19150 :    logic         fetch_req_icache_f;
+     293          378 :    logic         fetch_req_icache_f;
      294            0 :    logic         fetch_req_iccm_f;
      295            0 :    logic         ic_iccm_hit_f;
      296            2 :    logic         fetch_uncacheable_ff;
      297            0 :    logic         way_status_wr_en;
-     298        28098 :    logic         sel_byp_data;
-     299        28100 :    logic         sel_ic_data;
+     298          594 :    logic         sel_byp_data;
+     299          596 :    logic         sel_ic_data;
      300            0 :    logic         sel_iccm_data;
      301            0 :    logic         ic_rd_parity_final_err;
-     302        35772 :    logic         ic_act_miss_f_delayed;
+     302          824 :    logic         ic_act_miss_f_delayed;
      303            0 :    logic         bus_ifu_wr_data_error;
      304            0 :    logic         bus_ifu_wr_data_error_ff;
      305            0 :    logic         way_status_wr_en_w_debug;
      306            0 :    logic         ic_debug_tag_val_rd_out;
-     307        35772 :    logic         ifu_pmu_ic_miss_in;
+     307          824 :    logic         ifu_pmu_ic_miss_in;
      308            0 :    logic         ifu_pmu_ic_hit_in;
      309            0 :    logic         ifu_pmu_bus_error_in;
-     310        35770 :    logic         ifu_pmu_bus_trxn_in;
+     310          824 :    logic         ifu_pmu_bus_trxn_in;
      311            0 :    logic         ifu_pmu_bus_busy_in;
      312            0 :    logic         ic_debug_ict_array_sel_in;
      313            0 :    logic         ic_debug_ict_array_sel_ff;
      314            0 :    logic         debug_data_clken;
-     315        35768 :    logic         last_data_recieved_in ;
-     316        35768 :    logic         last_data_recieved_ff ;
+     315          820 :    logic         last_data_recieved_in ;
+     316          820 :    logic         last_data_recieved_ff ;
      317              : 
-     318        71536 :    logic                          ifu_bus_rvalid           ;
-     319        71536 :    logic                          ifu_bus_rvalid_ff        ;
-     320        71536 :    logic                          ifu_bus_rvalid_unq_ff    ;
-     321        35770 :    logic                          ifu_bus_arready_unq       ;
-     322        35770 :    logic                          ifu_bus_arready_unq_ff    ;
-     323        35770 :    logic                          ifu_bus_arvalid           ;
-     324        35770 :    logic                          ifu_bus_arvalid_ff        ;
-     325        35770 :    logic                          ifu_bus_arready           ;
-     326        35770 :    logic                          ifu_bus_arready_ff        ;
-     327         3454 :    logic [63:0]                   ifu_bus_rdata_ff        ;
+     318         1644 :    logic                          ifu_bus_rvalid           ;
+     319         1642 :    logic                          ifu_bus_rvalid_ff        ;
+     320         1642 :    logic                          ifu_bus_rvalid_unq_ff    ;
+     321          824 :    logic                          ifu_bus_arready_unq       ;
+     322          822 :    logic                          ifu_bus_arready_unq_ff    ;
+     323          824 :    logic                          ifu_bus_arvalid           ;
+     324          824 :    logic                          ifu_bus_arvalid_ff        ;
+     325          824 :    logic                          ifu_bus_arready           ;
+     326          822 :    logic                          ifu_bus_arready_ff        ;
+     327           12 :    logic [63:0]                   ifu_bus_rdata_ff        ;
      328            0 :    logic [1:0]                    ifu_bus_rresp_ff          ;
-     329        71536 :    logic                          ifu_bus_rsp_valid ;
+     329         1644 :    logic                          ifu_bus_rsp_valid ;
      330            2 :    logic                          ifu_bus_rsp_ready ;
-     331         7408 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
-     332         3454 :    logic [63:0]                   ifu_bus_rsp_rdata;
+     331           32 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
+     332           12 :    logic [63:0]                   ifu_bus_rsp_rdata;
      333            0 :    logic [1:0]                    ifu_bus_rsp_opc;
      334              : 
-     335         5224 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
+     335           36 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
      336            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    wr_data_c1_clk;
-     337         5224 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
-     338         5224 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
+     337           36 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
+     338           36 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
      339            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error_in;
      340            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error;
-     341         1142 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
-     342         3686 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
+     341           12 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
+     342           12 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
      343            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_1;
-     344         1824 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
-     345         1824 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
+     344           24 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
+     345           24 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
      346            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_1;
-     347        50604 :    logic          miss_buff_hit_unq_f ;
+     347         1090 :    logic          miss_buff_hit_unq_f ;
      348            0 :    logic          stream_hit_f ;
      349            0 :    logic          stream_miss_f ;
      350            0 :    logic          stream_eol_f ;
-     351        35640 :    logic          crit_byp_hit_f ;
-     352         7408 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
+     351          790 :    logic          crit_byp_hit_f ;
+     352           32 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
      353              :    logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;
-     354         3452 :    logic [63:0] ic_miss_buff_half;
+     354            8 :    logic [63:0] ic_miss_buff_half;
      355            0 :    logic        scnd_miss_req, scnd_miss_req_q;
      356            0 :    logic        scnd_miss_req_in;
      357              : 
      358              : 
      359            0 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_ff;
-     360          244 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
+     360            8 :    logic [pt.ICCM_BITS-1:2]                iccm_ecc_corr_index_in;
      361            0 :    logic [38:0]                         iccm_ecc_corr_data_ff;
      362            0 :    logic                                iccm_ecc_write_status     ;
      363            0 :    logic                                iccm_rd_ecc_single_err_ff   ;
      364            0 :    logic                                iccm_error_start;     // start the error fsm
      365            0 :    logic                                perr_state_en;
-     366        76628 :    logic                                miss_state_en;
+     366         1678 :    logic                                miss_state_en;
      367              : 
      368            0 :    logic        busclk;
      369            0 :    logic        busclk_force;
@@ -475,46 +475,46 @@
      371            2 :    logic        bus_ifu_bus_clk_en_ff;
      372            2 :    logic        bus_ifu_bus_clk_en ;
      373              : 
-     374        35772 :    logic        ifc_bus_ic_req_ff_in;
-     375        35770 :    logic        ifu_bus_cmd_valid ;
-     376        35770 :    logic        ifu_bus_cmd_ready ;
+     374          824 :    logic        ifc_bus_ic_req_ff_in;
+     375          824 :    logic        ifu_bus_cmd_valid ;
+     376          824 :    logic        ifu_bus_cmd_ready ;
      377              : 
-     378        35768 :    logic        bus_inc_data_beat_cnt     ;
-     379        49736 :    logic        bus_reset_data_beat_cnt   ;
-     380        85506 :    logic        bus_hold_data_beat_cnt    ;
+     378          822 :    logic        bus_inc_data_beat_cnt     ;
+     379         1144 :    logic        bus_reset_data_beat_cnt   ;
+     380         1968 :    logic        bus_hold_data_beat_cnt    ;
      381              : 
-     382        35770 :    logic        bus_inc_cmd_beat_cnt     ;
+     382          824 :    logic        bus_inc_cmd_beat_cnt     ;
      383            0 :    logic        bus_reset_cmd_beat_cnt_0   ;
-     384        35772 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
-     385        35772 :    logic        bus_hold_cmd_beat_cnt    ;
+     384          824 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
+     385          826 :    logic        bus_hold_cmd_beat_cnt    ;
      386              : 
      387            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_data_beat_count  ;
      388            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_data_beat_count      ;
      389              : 
-     390        35772 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
-     391        35770 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
+     390          824 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
+     391          824 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
      392              : 
      393              : 
-     394        13136 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
-     395        13136 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
+     394          320 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
+     395          320 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
      396              : 
      397              : 
-     398        35770 :    logic        bus_cmd_sent           ;
-     399        35768 :    logic        bus_last_data_beat     ;
+     398          824 :    logic        bus_cmd_sent           ;
+     399          820 :    logic        bus_last_data_beat     ;
      400              : 
      401              : 
      402            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren            ;
      403              : 
      404            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren_last       ;
      405            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       wren_reset_miss      ;
-     406         1598 :    logic        ifc_dma_access_ok_d;
-     407         1598 :    logic        ifc_dma_access_ok_prev;
+     406           70 :    logic        ifc_dma_access_ok_d;
+     407           70 :    logic        ifc_dma_access_ok_prev;
      408              : 
-     409        35772 :    logic   bus_cmd_req_in ;
-     410        35772 :    logic   bus_cmd_req_hold ;
+     409          824 :    logic   bus_cmd_req_in ;
+     410          824 :    logic   bus_cmd_req_hold ;
      411              : 
-     412        16180 :    logic   second_half_available ;
-     413        16180 :    logic   write_ic_16_bytes ;
+     412          328 :    logic   second_half_available ;
+     413          328 :    logic   write_ic_16_bytes ;
      414              : 
      415            0 :    logic   ifc_region_acc_fault_final_bf;
      416            0 :    logic   ifc_region_acc_fault_memory_bf;
@@ -523,21 +523,21 @@
      419              : 
      420            0 :    logic   iccm_correct_ecc;
      421            0 :    logic   dma_sb_err_state, dma_sb_err_state_ff;
-     422        19952 :    logic   two_byte_instr;
+     422          542 :    logic   two_byte_instr;
      423              : 
      424              :    typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;
-     425           36 :    miss_state_t miss_state, miss_nxtstate;
+     425            0 :    miss_state_t miss_state, miss_nxtstate;
      426              : 
      427              :    typedef enum logic [1:0] {ERR_STOP_IDLE=2'b00, ERR_FETCH1=2'b01 , ERR_FETCH2=2'b10 , ERR_STOP_FETCH=2'b11} err_stop_state_t;
-     428            0 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
+     428            0 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
      429            0 :    logic   err_stop_state_en ;
      430            0 :    logic   err_stop_fetch ;
      431              : 
-     432        35640 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
+     432          790 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434         5064 :    logic   ifu_bp_hit_taken_q_f;
-     435        71536 :    logic   ifu_bus_rvalid_unq;
-     436        35770 :    logic   bus_cmd_beat_en;
+     434          176 :    logic   ifu_bp_hit_taken_q_f;
+     435         1644 :    logic   ifu_bus_rvalid_unq;
+     436          824 :    logic   bus_cmd_beat_en;
      437              : 
      438              : 
      439              : // ---- Clock gating section -----
@@ -587,21 +587,21 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486        24884 :          IDLE: begin : idle
-     487        24884 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488        24884 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486          588 :          IDLE: begin : idle
+     487          588 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488          588 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490        79380 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491        79380 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492        79380 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493        79380 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494        79380 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495        79380 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496        79380 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497        79380 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498        79380 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499        79380 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500        79380 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490         1900 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491         1900 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492         1900 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493         1900 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494         1900 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495         1900 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496         1900 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497         1900 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498         1900 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499         1900 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500         1900 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,26 +611,26 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510        27336 :          MISS_WAIT: begin : miss_wait
-     511        27336 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512        27336 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510          542 :          MISS_WAIT: begin : miss_wait
+     511          542 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512          542 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514          532 :          HIT_U_MISS: begin : hit_u_miss
-     515          532 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516          532 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517          532 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514           26 :          HIT_U_MISS: begin : hit_u_miss
+     515           26 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516           26 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517           26 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
      521            0 :                                     exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;
      522            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      523              :          end
-     524           60 :          STALL_SCND_MISS: begin : stall_scnd_miss
-     525           60 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
-     526           60 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
-     527           60 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
+     524            0 :          STALL_SCND_MISS: begin : stall_scnd_miss
+     525            0 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
+     526            0 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
+     527            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      528              :          end
-     529            0 :          default: begin : def_case
+     529            0 :          default: begin : def_case
      530            0 :                   miss_nxtstate   = IDLE;
      531            0 :                   miss_state_en   = 1'b0;
      532              :          end
@@ -638,7 +638,7 @@
      534              :    end
      535              :    rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en),   .*);
      536              : 
-     537        35770 :   logic    sel_hold_imb     ;
+     537          822 :   logic    sel_hold_imb     ;
      538              : 
      539              :    assign miss_pending       =  (miss_state != IDLE) ;
      540              :    assign crit_wd_byp_ok_ff  =  (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
@@ -902,7 +902,7 @@
      798              : /////////////////////////////////////////////////////////////////////////////////////
      799              : //  Create full buffer...                                                          //
      800              : /////////////////////////////////////////////////////////////////////////////////////
-     801         3454 :      logic [63:0]       ic_miss_buff_data_in;
+     801           12 :      logic [63:0]       ic_miss_buff_data_in;
      802              :      assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
      803              : 
      804              :      for (genvar i=0; i<pt.ICACHE_NUM_BEATS; i++) begin :  wr_flop
@@ -939,10 +939,10 @@
      835              : /////////////////////////////////////////////////////////////////////////////////////
      836              : // New bypass ready                                                                //
      837              : /////////////////////////////////////////////////////////////////////////////////////
-     838         1106 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
-     839         1572 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
-     840        35768 :    logic   bypass_data_ready_in;
-     841        35640 :    logic   ic_crit_wd_rdy_new_in;
+     838            8 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
+     839           16 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
+     840          822 :    logic   bypass_data_ready_in;
+     841          790 :    logic   ic_crit_wd_rdy_new_in;
      842              : 
      843              :    assign bypass_index[pt.ICACHE_BEAT_ADDR_HI:1] = imb_ff[pt.ICACHE_BEAT_ADDR_HI:1] ;
      844              :    assign bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3] = bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] + 1 ;
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945       132192 :       ERR_IDLE: begin : err_idle
-     946       132192 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947       132192 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948       132192 :         perr_sb_write_status = perr_state_en;
+     945         3056 :       ERR_IDLE: begin : err_idle
+     946         3056 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947         3056 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948         3056 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990       132192 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991       132192 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992       132192 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990         3056 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991         3056 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992         3056 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1469,7 +1469,7 @@
     1365              :                               ((miss_state == CRIT_BYP_OK) &  miss_state_en &  (miss_nxtstate == MISS_WAIT))  ))  |
     1366              :                              ( ifc_fetch_req_bf & exu_flush_final  & ~ifc_fetch_uncacheable_bf & ~ifc_iccm_access_bf )     ;
     1367              : 
-    1368        36540 : logic   ic_real_rd_wp_unused;
+    1368          868 : logic   ic_real_rd_wp_unused;
     1369              : assign  ic_real_rd_wp_unused  =  (ifc_fetch_req_bf &  ~ifc_iccm_access_bf  &  ~ifc_region_acc_fault_final_bf & ~dec_tlu_fence_i_wb & ~stream_miss_f & ~ic_act_miss_f &
     1370              :                             ~(((miss_state == STREAM) & ~miss_state_en) |
     1371              :                               ((miss_state == CRIT_BYP_OK) & ~miss_state_en & ~(miss_nxtstate == MISS_WAIT)) |
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446       132192 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447       132192 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446         3056 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447         3056 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509       132192 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510       132192 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511       264384 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509         3056 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510         3056 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511         6112 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lib.sv.html
index 65c836c0eba..f727fb8761e 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35         8892 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
-      36         8892 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
+      35           56 :                         input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
+      36           56 :                         output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
       37              :                         );
       38              : 
       39              : 
@@ -158,9 +158,9 @@
       54              : #(
       55              : `include "el2_param.vh"
       56              :  )(
-      57         1684 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58         8190 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59         8306 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      57           32 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
+      58           26 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59           50 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu.sv.html
index 3be584dcd06..14e00bf0fc8 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        40.4%
+    
+        32.8%
     
     
-        80
+        65
     
     
         198
@@ -137,7 +137,7 @@
       33              : (
       34              : 
       35            0 :    input logic                             clk_override,             // Override non-functional clock gating
-      36           56 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
+      36            4 :    input logic                             dec_tlu_flush_lower_r,    // I0/I1 writeback flush. This is used to flush the old packets only
       37            0 :    input logic                             dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
       38            0 :    input logic                             dec_tlu_force_halt,       // This will be high till TLU goes to debug halt
       39              : 
@@ -147,21 +147,21 @@
       43            0 :    input logic                             dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
       44            0 :    input logic                             dec_tlu_core_ecc_disable,          // disable the generation of the ecc
       45              : 
-      46         2880 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
-      47           72 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
-      48          400 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
+      46          104 :    input logic [31:0]                      exu_lsu_rs1_d,        // address rs operand
+      47            0 :    input logic [31:0]                      exu_lsu_rs2_d,        // store data
+      48            0 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
       49              : 
-      50         2612 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
-      51        11872 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
+      50           16 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
+      51          452 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
       52            0 :    input logic [31:0]                      dec_tlu_mrac_ff,       // CSR for memory region control
       53              : 
       54            0 :    output logic [31:0]                     lsu_result_m,          // lsu load data
       55            0 :    output logic [31:0]                     lsu_result_corr_r,     // This is the ECC corrected data going to RF
-      56           28 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
-      57           28 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
-      58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
-      59         8690 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
-      60         8688 :    output logic                            lsu_active,            // Used to turn off top level clk
+      56            0 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
+      57            0 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
+      58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
+      59          232 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
+      60          230 :    output logic                            lsu_active,            // Used to turn off top level clk
       61              : 
       62            0 :    output logic [31:1]                     lsu_fir_addr,        // fast interrupt address
       63            0 :    output logic [1:0]                      lsu_fir_error,       // Error during fast interrupt lookup
@@ -173,19 +173,19 @@
       69            2 :    output logic [31:0]                     lsu_imprecise_error_addr_any,  // bus store imprecise error address
       70              : 
       71              :    // Non-blocking loads
-      72         6024 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
-      73         2428 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
+      72          224 :    output logic                               lsu_nonblock_load_valid_m,      // there is an external load -> put in the cam
+      73          216 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,        // the tag of the external non block load
       74            0 :    output logic                               lsu_nonblock_load_inv_r,        // invalidate signal for the cam entry for non block loads
-      75         2428 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
-      76         6192 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
+      75          216 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,    // tag of the enrty which needs to be invalidated
+      76          224 :    output logic                               lsu_nonblock_load_data_valid,   // the non block is valid - sending information back to the cam
       77            0 :    output logic                               lsu_nonblock_load_data_error,   // non block load has an error
-      78           48 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
-      79           24 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
+      78            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,     // the tag of the non block load sending the data/error
+      79            0 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
       80              : 
-      81         6024 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
-      82         5848 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
+      81          224 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
+      82          228 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
       83            0 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
-      84        12368 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
+      84          456 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
       85            0 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
       86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
       87            0 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
@@ -199,8 +199,8 @@
       95            0 :    output logic                            dccm_rden,       // DCCM read enable
       96            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo, // DCCM write address low bank
       97            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi, // DCCM write address hi bank
-      98         2336 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
-      99         2496 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
+      98          104 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo, // DCCM read address low bank
+      99          120 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
      100            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo, // DCCM write data for lo bank
      101            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi, // DCCM write data for hi bank
      102              : 
@@ -213,12 +213,12 @@
      109            0 :    output logic                            picm_mken,    // Need to read the mask for stores to determine which bits to write/forward
      110            2 :    output logic [31:0]                     picm_rdaddr,  // address for pic read access
      111            2 :    output logic [31:0]                     picm_wraddr,  // address for pic write access
-     112           24 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
-     113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
+     112            0 :    output logic [31:0]                     picm_wr_data, // PIC memory write data
+     113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
      114              : 
      115              :    // AXI Write Channels
-     116         6344 :    output logic                            lsu_axi_awvalid,
-     117        12370 :    input  logic                            lsu_axi_awready,
+     116          232 :    output logic                            lsu_axi_awvalid,
+     117          456 :    input  logic                            lsu_axi_awready,
      118            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      119            2 :    output logic [31:0]                     lsu_axi_awaddr,
      120            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -230,20 +230,20 @@
      126            0 :    output logic [2:0]                      lsu_axi_awprot,
      127            0 :    output logic [3:0]                      lsu_axi_awqos,
      128              : 
-     129         6344 :    output logic                            lsu_axi_wvalid,
-     130        12370 :    input  logic                            lsu_axi_wready,
-     131           20 :    output logic [63:0]                     lsu_axi_wdata,
-     132          792 :    output logic [7:0]                      lsu_axi_wstrb,
+     129          232 :    output logic                            lsu_axi_wvalid,
+     130          456 :    input  logic                            lsu_axi_wready,
+     131            0 :    output logic [63:0]                     lsu_axi_wdata,
+     132            4 :    output logic [7:0]                      lsu_axi_wstrb,
      133            2 :    output logic                            lsu_axi_wlast,
      134              : 
-     135         6344 :    input  logic                            lsu_axi_bvalid,
+     135          228 :    input  logic                            lsu_axi_bvalid,
      136            2 :    output logic                            lsu_axi_bready,
      137            0 :    input  logic [1:0]                      lsu_axi_bresp,
      138            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      139              : 
      140              :    // AXI Read Channels
-     141         6024 :    output logic                            lsu_axi_arvalid,
-     142        12370 :    input  logic                            lsu_axi_arready,
+     141          224 :    output logic                            lsu_axi_arvalid,
+     142          456 :    input  logic                            lsu_axi_arready,
      143            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      144            2 :    output logic [31:0]                     lsu_axi_araddr,
      145            2 :    output logic [3:0]                      lsu_axi_arregion,
@@ -255,10 +255,10 @@
      151            0 :    output logic [2:0]                      lsu_axi_arprot,
      152            0 :    output logic [3:0]                      lsu_axi_arqos,
      153              : 
-     154         6192 :    input  logic                            lsu_axi_rvalid,
+     154          224 :    input  logic                            lsu_axi_rvalid,
      155            2 :    output logic                            lsu_axi_rready,
      156            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     157          120 :    input  logic [63:0]                     lsu_axi_rdata,
+     157            4 :    input  logic [63:0]                     lsu_axi_rdata,
      158            0 :    input  logic [1:0]                      lsu_axi_rresp,
      159            2 :    input  logic                            lsu_axi_rlast,
      160              : 
@@ -276,33 +276,33 @@
      172            0 :    output logic                            dccm_dma_ecc_error,  // DMA load had ecc error
      173            0 :    output logic [2:0]                      dccm_dma_rtag,       // DMA request tag
      174            0 :    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
-     175        11874 :    output logic                            dccm_ready,          // lsu ready for DMA access
+     175          454 :    output logic                            dccm_ready,          // lsu ready for DMA access
      176              : 
      177              :    // DCCM ECC status
      178            0 :    output logic                            lsu_dccm_rd_ecc_single_err,
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182       583434 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183       583434 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182        12564 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183        12564 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
-     186         2496 :     output logic [31:0] lsu_pmp_addr_start,
-     187         2496 :     output logic [31:0] lsu_pmp_addr_end,
-     188         4970 :     input  logic        lsu_pmp_error_start,
-     189         4970 :     input  logic        lsu_pmp_error_end,
-     190         5848 :     output logic        lsu_pmp_we,
-     191         6024 :     output logic        lsu_pmp_re
+     186          120 :     output logic [31:0] lsu_pmp_addr_start,
+     187          120 :     output logic [31:0] lsu_pmp_addr_end,
+     188            0 :     input  logic        lsu_pmp_error_start,
+     189            0 :     input  logic        lsu_pmp_error_end,
+     190          228 :     output logic        lsu_pmp_we,
+     191          224 :     output logic        lsu_pmp_re
      192              : 
      193              :    );
      194              : 
      195            0 :    logic        lsu_dccm_rden_m;
      196            0 :    logic        lsu_dccm_rden_r;
-     197           72 :    logic [31:0] store_data_m;
-     198           72 :    logic [31:0] store_data_r;
-     199           24 :    logic [31:0] store_data_hi_r, store_data_lo_r;
-     200           24 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
-     201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
+     197            0 :    logic [31:0] store_data_m;
+     198            0 :    logic [31:0] store_data_r;
+     199            0 :    logic [31:0] store_data_hi_r, store_data_lo_r;
+     200            0 :    logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
+     201            0 :    logic [31:0] sec_data_lo_m, sec_data_hi_m;
      202            0 :    logic [31:0] sec_data_lo_r, sec_data_hi_r;
      203              : 
      204            0 :    logic [31:0] lsu_ld_data_m;
@@ -324,12 +324,12 @@
      220              : 
      221            0 :    logic [31:0] picm_mask_data_m;
      222              : 
-     223         2496 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
-     224         2496 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
+     223          120 :    logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
+     224          120 :    logic [31:0] end_addr_d, end_addr_m, end_addr_r;
      225              :   assign lsu_pmp_addr_start = lsu_addr_d;
      226              :   assign lsu_pmp_addr_end   = end_addr_d;
      227              : 
-     228         2612 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
+     228           16 :    el2_lsu_pkt_t    lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
      229            0 :    logic        lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
      230              :   assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
      231              :   assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
@@ -338,7 +338,7 @@
      234            0 :    logic        store_stbuf_reqvld_r;
      235            0 :    logic        ldst_stbuf_reqvld_r;
      236              : 
-     237        11872 :    logic        lsu_commit_r;
+     237          452 :    logic        lsu_commit_r;
      238            0 :    logic        lsu_exc_m;
      239              : 
      240            0 :    logic        addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
@@ -365,11 +365,11 @@
      261            0 :    logic        lsu_stbuf_full_any;
      262              : 
      263              :     // Bus signals
-     264        11872 :    logic        lsu_busreq_r;
-     265         6040 :    logic        lsu_bus_buffer_pend_any;
-     266         9798 :    logic        lsu_bus_buffer_empty_any;
-     267           28 :    logic        lsu_bus_buffer_full_any;
-     268        11872 :    logic        lsu_busreq_m;
+     264          452 :    logic        lsu_busreq_r;
+     265          228 :    logic        lsu_bus_buffer_pend_any;
+     266          244 :    logic        lsu_bus_buffer_empty_any;
+     267            0 :    logic        lsu_bus_buffer_full_any;
+     268          452 :    logic        lsu_busreq_m;
      269            0 :    logic [31:0] bus_read_data_m;
      270              : 
      271            0 :    logic        flush_m_up, flush_r;
@@ -381,16 +381,16 @@
      277            0 :    logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
      278              : 
      279              :    // Clocks
-     280         9144 :    logic        lsu_busm_clken;
-     281        17720 :    logic        lsu_bus_obuf_c1_clken;
-     282       583434 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283       583434 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284       583434 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     280          234 :    logic        lsu_busm_clken;
+     281          680 :    logic        lsu_bus_obuf_c1_clken;
+     282        12564 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283        12564 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284        12564 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286       583434 :    logic        lsu_stbuf_c1_clk;
-     287       583434 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286        12564 :    logic        lsu_stbuf_c1_clk;
+     287        12564 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289       583434 :    logic        lsu_free_c2_clk;
+     289        12564 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_addrcheck.sv.html
index 77e4bb5b296..548b921d761 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_addrcheck.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        24.0%
+    
+        20.0%
     
     
-        12
+        10
     
     
         50
@@ -131,16 +131,16 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30       583434 :    input logic          lsu_c2_m_clk,              // clock
+      30        12564 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
-      33         2496 :    input logic [31:0]   start_addr_d,              // start address for lsu
-      34         2496 :    input logic [31:0]   end_addr_d,                // end address for lsu
-      35         2612 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
+      33          120 :    input logic [31:0]   start_addr_d,              // start address for lsu
+      34          120 :    input logic [31:0]   end_addr_d,                // end address for lsu
+      35           16 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
       36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
-      37         4128 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
+      37          220 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
       38              : 
-      39         2880 :    input logic [31:0]   rs1_d,                     // address rs operand
+      39          104 :    input logic [31:0]   rs1_d,                     // address rs operand
       40              : 
       41            0 :    output logic         is_sideeffects_m,          // is sideffects space
       42            0 :    output logic         addr_in_dccm_d,            // address in dccm
@@ -154,10 +154,10 @@
       50            0 :    output logic         fir_dccm_access_error_d,   // Fast interrupt dccm access error
       51            0 :    output logic         fir_nondccm_access_error_d,// Fast interrupt dccm access error
       52              : 
-      53         4970 :     input logic lsu_pmp_error_start,
-      54         4970 :     input logic lsu_pmp_error_end,
+      53            0 :     input logic lsu_pmp_error_start,
+      54            0 :     input logic lsu_pmp_error_end,
       55              : 
-      56            0 :    input  logic         scan_mode                  // Scan mode
+      56            0 :    input  logic         scan_mode                  // Scan mode
       57              : );
       58              : 
       59              : 
@@ -167,7 +167,7 @@
       63            0 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
       64            0 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
       65            0 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
-      66         4128 :    logic [4:0]  csr_idx;
+      66          220 :    logic [4:0]  csr_idx;
       67            0 :    logic        addr_in_iccm;
       68            0 :    logic        start_addr_dccm_or_pic;
       69            0 :    logic        base_reg_dccm_or_pic;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_buffer.sv.html
index 071695351a9..03019b954d6 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_buffer.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        61.3%
+    
+        48.0%
     
     
-        157
+        123
     
     
         256
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31       583434 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        12564 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -142,34 +142,34 @@
       38            0 :    input logic                          dec_tlu_force_halt,
       39              : 
       40              :    // various clocks needed for the bus reads and writes
-      41        17720 :    input logic                          lsu_bus_obuf_c1_clken,
-      42         9144 :    input logic                          lsu_busm_clken,
-      43       583434 :    input logic                          lsu_c2_r_clk,
-      44       583434 :    input logic                          lsu_bus_ibuf_c1_clk,
+      41          680 :    input logic                          lsu_bus_obuf_c1_clken,
+      42          234 :    input logic                          lsu_busm_clken,
+      43        12564 :    input logic                          lsu_c2_r_clk,
+      44        12564 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46       583434 :    input logic                          lsu_bus_buf_c1_clk,
-      47       583434 :    input logic                          lsu_free_c2_clk,
+      46        12564 :    input logic                          lsu_bus_buf_c1_clk,
+      47        12564 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
-      51        11872 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
-      52         2612 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
-      53         2612 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
+      51          452 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
+      52           16 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
+      53           16 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
       54              : 
-      55         2496 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
-      56         2496 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
-      57         2496 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
-      58         2496 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
-      59           72 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
+      55          120 :    input logic [31:0]                   lsu_addr_m,                     // lsu address flowing down the pipe
+      56          120 :    input logic [31:0]                   end_addr_m,                     // lsu address flowing down the pipe
+      57          120 :    input logic [31:0]                   lsu_addr_r,                     // lsu address flowing down the pipe
+      58          120 :    input logic [31:0]                   end_addr_r,                     // lsu address flowing down the pipe
+      59            0 :    input logic [31:0]                   store_data_r,                   // store data flowing down the pipe
       60              : 
-      61          796 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
-      62          604 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
-      63        11872 :    input logic                          lsu_busreq_m,                   // bus request is in m
-      64        11872 :    output logic                         lsu_busreq_r,                   // bus request is in r
+      61            8 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
+      62            8 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
+      63          452 :    input logic                          lsu_busreq_m,                   // bus request is in m
+      64          452 :    output logic                         lsu_busreq_r,                   // bus request is in r
       65            0 :    input logic                          ld_full_hit_m,                  // load can get all its byte from a write buffer entry
-      66           56 :    input logic                          flush_m_up,                     // flush
+      66            4 :    input logic                          flush_m_up,                     // flush
       67            0 :    input logic                          flush_r,                        // flush
-      68        11872 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
+      68          452 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
       69            0 :    input logic                          is_sideeffects_r,               // lsu attribute is side_effects
       70            0 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
       71            0 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
@@ -177,9 +177,9 @@
       73              : 
       74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
       75              : 
-      76         6040 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
-      77           28 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
-      78         9798 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
+      76          228 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
+      77            0 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
+      78          244 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
       79              : 
       80            0 :    output logic [3:0]                   ld_byte_hit_buf_lo, ld_byte_hit_buf_hi,    // Byte enables for forwarding data
       81            0 :    output logic [31:0]                  ld_fwddata_buf_lo, ld_fwddata_buf_hi,      // load forwarding data
@@ -189,24 +189,24 @@
       85            2 :    output logic [31:0]                  lsu_imprecise_error_addr_any,     // address of the imprecise error
       86              : 
       87              :    // Non-blocking loads
-      88         6024 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
-      89         2428 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
+      88          224 :    output logic                               lsu_nonblock_load_valid_m,     // there is an external load -> put in the cam
+      89          216 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,       // the tag of the external non block load
       90            0 :    output logic                               lsu_nonblock_load_inv_r,       // invalidate signal for the cam entry for non block loads
-      91         2428 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
-      92         6192 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
+      91          216 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,   // tag of the enrty which needs to be invalidated
+      92          224 :    output logic                               lsu_nonblock_load_data_valid,  // the non block is valid - sending information back to the cam
       93            0 :    output logic                               lsu_nonblock_load_data_error,  // non block load has an error
-      94           48 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
-      95           24 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
+      94            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,    // the tag of the non block load sending the data/error
+      95            0 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
       96              : 
       97              :    // PMU events
-      98        12368 :    output logic                         lsu_pmu_bus_trxn,
+      98          456 :    output logic                         lsu_pmu_bus_trxn,
       99            0 :    output logic                         lsu_pmu_bus_misaligned,
      100            0 :    output logic                         lsu_pmu_bus_error,
      101            0 :    output logic                         lsu_pmu_bus_busy,
      102              : 
      103              :    // AXI Write Channels
-     104         6344 :    output logic                            lsu_axi_awvalid,
-     105        12370 :    input  logic                            lsu_axi_awready,
+     104          232 :    output logic                            lsu_axi_awvalid,
+     105          456 :    input  logic                            lsu_axi_awready,
      106            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      107            2 :    output logic [31:0]                     lsu_axi_awaddr,
      108            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -218,20 +218,20 @@
      114            0 :    output logic [2:0]                      lsu_axi_awprot,
      115            0 :    output logic [3:0]                      lsu_axi_awqos,
      116              : 
-     117         6344 :    output logic                            lsu_axi_wvalid,
-     118        12370 :    input  logic                            lsu_axi_wready,
-     119           20 :    output logic [63:0]                     lsu_axi_wdata,
-     120          792 :    output logic [7:0]                      lsu_axi_wstrb,
+     117          232 :    output logic                            lsu_axi_wvalid,
+     118          456 :    input  logic                            lsu_axi_wready,
+     119            0 :    output logic [63:0]                     lsu_axi_wdata,
+     120            4 :    output logic [7:0]                      lsu_axi_wstrb,
      121            2 :    output logic                            lsu_axi_wlast,
      122              : 
-     123         6344 :    input  logic                            lsu_axi_bvalid,
+     123          228 :    input  logic                            lsu_axi_bvalid,
      124            2 :    output logic                            lsu_axi_bready,
      125            0 :    input  logic [1:0]                      lsu_axi_bresp,
      126            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      127              : 
      128              :    // AXI Read Channels
-     129         6024 :    output logic                            lsu_axi_arvalid,
-     130        12370 :    input  logic                            lsu_axi_arready,
+     129          224 :    output logic                            lsu_axi_arvalid,
+     130          456 :    input  logic                            lsu_axi_arready,
      131            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      132            2 :    output logic [31:0]                     lsu_axi_araddr,
      133            2 :    output logic [3:0]                      lsu_axi_arregion,
@@ -243,10 +243,10 @@
      139            0 :    output logic [2:0]                      lsu_axi_arprot,
      140            0 :    output logic [3:0]                      lsu_axi_arqos,
      141              : 
-     142         6192 :    input  logic                            lsu_axi_rvalid,
+     142          224 :    input  logic                            lsu_axi_rvalid,
      143            2 :    output logic                            lsu_axi_rready,
      144            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
-     145          120 :    input  logic [63:0]                     lsu_axi_rdata,
+     145            4 :    input  logic [63:0]                     lsu_axi_rdata,
      146            0 :    input  logic [1:0]                      lsu_axi_rresp,
      147              : 
      148            2 :    input logic                             lsu_bus_clk_en,
@@ -264,7 +264,7 @@
      160              :    localparam TIMER_MAX = TIMER - 1;  // Maximum value of timer
      161              :    localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);
      162              : 
-     163         3638 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
+     163           68 :    logic [3:0]                          ldst_byteen_hi_m, ldst_byteen_lo_m;
      164            0 :    logic [DEPTH-1:0]                    ld_addr_hitvec_lo, ld_addr_hitvec_hi;
      165            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvec_lo, ld_byte_hitvec_hi;
      166            0 :    logic [3:0][DEPTH-1:0]               ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;
@@ -273,152 +273,152 @@
      169            0 :    logic [3:0]                          ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;
      170              : 
      171            2 :    logic [3:0]                          ldst_byteen_r;
-     172         3638 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
-     173           24 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
-     174            2 :    logic                                is_aligned_r;                   // Aligned load/store
+     172           68 :    logic [3:0]                          ldst_byteen_hi_r, ldst_byteen_lo_r;
+     173            0 :    logic [31:0]                         store_data_hi_r, store_data_lo_r;
+     174            2 :    logic                                is_aligned_r;                   // Aligned load/store
      175            2 :    logic                                ldst_samedw_r;
      176              : 
-     177         6024 :    logic                                lsu_nonblock_load_valid_r;
-     178          228 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
-     179         2048 :    logic [1:0]                          lsu_nonblock_addr_offset;
-     180          360 :    logic [1:0]                          lsu_nonblock_sz;
-     181         4204 :    logic                                lsu_nonblock_unsign;
-     182         6192 :    logic                                lsu_nonblock_load_data_ready;
+     177          224 :    logic                                lsu_nonblock_load_valid_r;
+     178           68 :    logic [31:0]                         lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
+     179          104 :    logic [1:0]                          lsu_nonblock_addr_offset;
+     180            8 :    logic [1:0]                          lsu_nonblock_sz;
+     181          216 :    logic                                lsu_nonblock_unsign;
+     182          224 :    logic                                lsu_nonblock_load_data_ready;
      183              : 
      184            0 :    logic [DEPTH-1:0]                    CmdPtr0Dec, CmdPtr1Dec;
-     185           28 :    logic [DEPTH-1:0]                    RspPtrDec;
-     186            0 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
-     187           28 :    logic [DEPTH_LOG2-1:0]               RspPtr;
-     188         2428 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
-     189         2832 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
+     185            0 :    logic [DEPTH-1:0]                    RspPtrDec;
+     186            0 :    logic [DEPTH_LOG2-1:0]               CmdPtr0, CmdPtr1;
+     187            0 :    logic [DEPTH_LOG2-1:0]               RspPtr;
+     188          216 :    logic [DEPTH_LOG2-1:0]               WrPtr0_m, WrPtr0_r;
+     189          220 :    logic [DEPTH_LOG2-1:0]               WrPtr1_m, WrPtr1_r;
      190            0 :    logic                                found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;
      191            0 :    logic [3:0]                          buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;
-     192          132 :    logic                                any_done_wait_state;
+     192            4 :    logic                                any_done_wait_state;
      193            0 :    logic                                bus_sideeffect_pend;
      194            2 :    logic                                bus_coalescing_disable;
      195              : 
-     196          324 :    logic                                bus_addr_match_pending;
-     197        12368 :    logic                                bus_cmd_sent, bus_cmd_ready;
-     198         6344 :    logic                                bus_wcmd_sent, bus_wdata_sent;
-     199         6192 :    logic                                bus_rsp_read, bus_rsp_write;
+     196            4 :    logic                                bus_addr_match_pending;
+     197          456 :    logic                                bus_cmd_sent, bus_cmd_ready;
+     198          232 :    logic                                bus_wcmd_sent, bus_wdata_sent;
+     199          224 :    logic                                bus_rsp_read, bus_rsp_write;
      200            0 :    logic [pt.LSU_BUS_TAG-1:0]           bus_rsp_read_tag, bus_rsp_write_tag;
      201            0 :    logic                                bus_rsp_read_error, bus_rsp_write_error;
-     202          120 :    logic [63:0]                         bus_rsp_rdata;
+     202            4 :    logic [63:0]                         bus_rsp_rdata;
      203              : 
      204              :    // Bus buffer signals
-     205           28 :    state_t [DEPTH-1:0]                  buf_state;
-     206            2 :    logic   [DEPTH-1:0][1:0]             buf_sz;
-     207            0 :    logic   [DEPTH-1:0][31:0]            buf_addr;
-     208            2 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
-     209            0 :    logic   [DEPTH-1:0]                  buf_sideeffect;
+     205            0 :    state_t [DEPTH-1:0]                  buf_state;
+     206            0 :    logic   [DEPTH-1:0][1:0]             buf_sz;
+     207            0 :    logic   [DEPTH-1:0][31:0]            buf_addr;
+     208            0 :    logic   [DEPTH-1:0][3:0]             buf_byteen;
+     209            0 :    logic   [DEPTH-1:0]                  buf_sideeffect;
      210            0 :    logic   [DEPTH-1:0]                  buf_write;
      211            0 :    logic   [DEPTH-1:0]                  buf_unsign;
      212            0 :    logic   [DEPTH-1:0]                  buf_dual;
-     213            2 :    logic   [DEPTH-1:0]                  buf_samedw;
-     214            0 :    logic   [DEPTH-1:0]                  buf_nomerge;
+     213            0 :    logic   [DEPTH-1:0]                  buf_samedw;
+     214            0 :    logic   [DEPTH-1:0]                  buf_nomerge;
      215            0 :    logic   [DEPTH-1:0]                  buf_dualhi;
-     216            2 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
-     217           28 :    logic   [DEPTH-1:0]                  buf_ldfwd;
-     218           28 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
-     219            0 :    logic   [DEPTH-1:0]                  buf_error;
+     216            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag;
+     217            0 :    logic   [DEPTH-1:0]                  buf_ldfwd;
+     218            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag;
+     219            0 :    logic   [DEPTH-1:0]                  buf_error;
      220            0 :    logic   [DEPTH-1:0][31:0]            buf_data;
      221            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age, buf_age_younger;
      222            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage, buf_rsp_pickage;
      223              : 
-     224           28 :    state_t [DEPTH-1:0]                  buf_nxtstate;
-     225           28 :    logic   [DEPTH-1:0]                  buf_rst;
-     226           56 :    logic   [DEPTH-1:0]                  buf_state_en;
-     227           28 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
-     228           28 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
-     229           56 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
-     230            0 :    logic   [DEPTH-1:0]                  buf_dual_in;
+     224            0 :    state_t [DEPTH-1:0]                  buf_nxtstate;
+     225            0 :    logic   [DEPTH-1:0]                  buf_rst;
+     226            0 :    logic   [DEPTH-1:0]                  buf_state_en;
+     227            0 :    logic   [DEPTH-1:0]                  buf_cmd_state_bus_en;
+     228            0 :    logic   [DEPTH-1:0]                  buf_resp_state_bus_en;
+     229            0 :    logic   [DEPTH-1:0]                  buf_state_bus_en;
+     230            0 :    logic   [DEPTH-1:0]                  buf_dual_in;
      231            2 :    logic   [DEPTH-1:0]                  buf_samedw_in;
-     232          604 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
+     232            8 :    logic   [DEPTH-1:0]                  buf_nomerge_in;
      233            0 :    logic   [DEPTH-1:0]                  buf_sideeffect_in;
-     234         4732 :    logic   [DEPTH-1:0]                  buf_unsign_in;
-     235         2612 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
-     236         5848 :    logic   [DEPTH-1:0]                  buf_write_in;
-     237           28 :    logic   [DEPTH-1:0]                  buf_wr_en;
-     238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
-     239         2832 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
-     240           48 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
-     241           28 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
-     242           28 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
-     243         3638 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
-     244         2496 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
-     245           24 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
-     246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
-     247           56 :    logic   [DEPTH-1:0]                  buf_data_en;
-     248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
+     234          216 :    logic   [DEPTH-1:0]                  buf_unsign_in;
+     235           16 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
+     236          228 :    logic   [DEPTH-1:0]                  buf_write_in;
+     237            0 :    logic   [DEPTH-1:0]                  buf_wr_en;
+     238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
+     239          220 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
+     240            0 :    logic   [DEPTH-1:0]                  buf_ldfwd_en;
+     241            0 :    logic   [DEPTH-1:0]                  buf_ldfwd_in;
+     242            0 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_ldfwdtag_in;
+     243           68 :    logic   [DEPTH-1:0][3:0]             buf_byteen_in;
+     244          120 :    logic   [DEPTH-1:0][31:0]            buf_addr_in;
+     245            0 :    logic   [DEPTH-1:0][31:0]            buf_data_in;
+     246            0 :    logic   [DEPTH-1:0]                  buf_error_en;
+     247            0 :    logic   [DEPTH-1:0]                  buf_data_en;
+     248            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_age_in;
      249            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_ageQ;
      250            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage_set;
      251            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspage_in;
      252            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspageQ;
      253              : 
      254              :    // Input buffer signals
-     255         5848 :    logic                               ibuf_valid;
+     255          228 :    logic                               ibuf_valid;
      256            0 :    logic                               ibuf_dual;
      257            2 :    logic                               ibuf_samedw;
      258            0 :    logic                               ibuf_nomerge;
-     259          220 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
-     260          220 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
-     261            0 :    logic                               ibuf_sideeffect;
+     259            0 :    logic [DEPTH_LOG2-1:0]              ibuf_tag;
+     260            0 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag;
+     261            0 :    logic                               ibuf_sideeffect;
      262            0 :    logic                               ibuf_unsign;
      263            2 :    logic                               ibuf_write;
-     264           80 :    logic [1:0]                         ibuf_sz;
-     265           98 :    logic [3:0]                         ibuf_byteen;
-     266            2 :    logic [31:0]                        ibuf_addr;
-     267           24 :    logic [31:0]                        ibuf_data;
-     268         5850 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
+     264            4 :    logic [1:0]                         ibuf_sz;
+     265            2 :    logic [3:0]                         ibuf_byteen;
+     266            0 :    logic [31:0]                        ibuf_addr;
+     267            0 :    logic [31:0]                        ibuf_data;
+     268          230 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
      269              : 
-     270         6520 :    logic                               ibuf_byp;
-     271         5848 :    logic                               ibuf_wr_en;
-     272         5848 :    logic                               ibuf_rst;
+     270          228 :    logic                               ibuf_byp;
+     271          228 :    logic                               ibuf_wr_en;
+     272          228 :    logic                               ibuf_rst;
      273            0 :    logic                               ibuf_force_drain;
-     274         5848 :    logic                               ibuf_drain_vld;
+     274          228 :    logic                               ibuf_drain_vld;
      275            0 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
-     276         2428 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
-     277         2428 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
-     278         2612 :    logic [1:0]                         ibuf_sz_in;
-     279         2496 :    logic [31:0]                        ibuf_addr_in;
-     280         3638 :    logic [3:0]                         ibuf_byteen_in;
-     281           24 :    logic [31:0]                        ibuf_data_in;
-     282         5850 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
-     283           98 :    logic [3:0]                         ibuf_byteen_out;
-     284           24 :    logic [31:0]                        ibuf_data_out;
-     285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
+     276          216 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
+     277          216 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
+     278           16 :    logic [1:0]                         ibuf_sz_in;
+     279          120 :    logic [31:0]                        ibuf_addr_in;
+     280           68 :    logic [3:0]                         ibuf_byteen_in;
+     281            0 :    logic [31:0]                        ibuf_data_in;
+     282          230 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
+     283            2 :    logic [3:0]                         ibuf_byteen_out;
+     284            0 :    logic [31:0]                        ibuf_data_out;
+     285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
      286              : 
      287              :    // Output buffer signals
-     288        12368 :    logic                               obuf_valid;
-     289         4258 :    logic                               obuf_write;
-     290          132 :    logic                               obuf_nosend;
-     291         6024 :    logic                               obuf_rdrsp_pend;
+     288          456 :    logic                               obuf_valid;
+     289          222 :    logic                               obuf_write;
+     290            4 :    logic                               obuf_nosend;
+     291          224 :    logic                               obuf_rdrsp_pend;
      292            0 :    logic                               obuf_sideeffect;
      293            2 :    logic [31:0]                        obuf_addr;
-     294           20 :    logic [63:0]                        obuf_data;
-     295          360 :    logic [1:0]                         obuf_sz;
-     296         1952 :    logic [7:0]                         obuf_byteen;
+     294            0 :    logic [63:0]                        obuf_data;
+     295            8 :    logic [1:0]                         obuf_sz;
+     296           36 :    logic [7:0]                         obuf_byteen;
      297            0 :    logic                               obuf_merge;
      298            0 :    logic                               obuf_cmd_done, obuf_data_done;
      299            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0;
      300            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag1;
      301            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag;
      302              : 
-     303         6328 :    logic                               ibuf_buf_byp;
+     303          228 :    logic                               ibuf_buf_byp;
      304            0 :    logic                               obuf_force_wr_en;
      305            0 :    logic                               obuf_wr_wait;
-     306        12368 :    logic                               obuf_wr_en, obuf_wr_enQ;
-     307        12368 :    logic                               obuf_rst;
-     308         4258 :    logic                               obuf_write_in;
-     309         4072 :    logic                               obuf_nosend_in;
+     306          456 :    logic                               obuf_wr_en, obuf_wr_enQ;
+     307          456 :    logic                               obuf_rst;
+     308          222 :    logic                               obuf_write_in;
+     309           12 :    logic                               obuf_nosend_in;
      310            2 :    logic                               obuf_rdrsp_pend_en;
-     311         6024 :    logic                               obuf_rdrsp_pend_in;
+     311          224 :    logic                               obuf_rdrsp_pend_in;
      312            0 :    logic                               obuf_sideeffect_in;
      313            2 :    logic                               obuf_aligned_in;
      314            2 :    logic [31:0]                        obuf_addr_in;
-     315          212 :    logic [63:0]                        obuf_data_in;
-     316          360 :    logic [1:0]                         obuf_sz_in;
-     317         2080 :    logic [7:0]                         obuf_byteen_in;
+     315            4 :    logic [63:0]                        obuf_data_in;
+     316            8 :    logic [1:0]                         obuf_sz_in;
+     317           36 :    logic [7:0]                         obuf_byteen_in;
      318            0 :    logic                               obuf_merge_in;
      319            0 :    logic                               obuf_cmd_done_in, obuf_data_done_in;
      320            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_tag0_in;
@@ -427,33 +427,33 @@
      323              : 
      324            0 :    logic                               obuf_merge_en;
      325            0 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
-     326         1400 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
-     327          210 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
+     326           16 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
+     327            4 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
      328              : 
-     329         6344 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
-     330         6344 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
-     331         6024 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
+     329          232 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
+     330          232 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
+     331          224 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
      332            2 :    logic                               lsu_axi_bvalid_q, lsu_axi_bready_q;
      333            2 :    logic                               lsu_axi_rvalid_q, lsu_axi_rready_q;
      334            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_axi_bid_q, lsu_axi_rid_q;
      335            0 :    logic [1:0]                         lsu_axi_bresp_q, lsu_axi_rresp_q;
      336            0 :    logic [pt.LSU_BUS_TAG-1:0]          lsu_imprecise_error_store_tag;
-     337          120 :    logic [63:0]                        lsu_axi_rdata_q;
+     337            4 :    logic [63:0]                        lsu_axi_rdata_q;
      338              : 
      339              :    //------------------------------------------------------------------------------
      340              :    // Load forwarding logic start
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344       446728 :    function automatic logic [2:0] f_Enc8to3;
+     344        10984 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348       446728 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349       446728 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350       446728 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348        10984 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349        10984 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350        10984 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352       446728 :       return Enc_value[2:0];
+     352        10984 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -672,11 +672,11 @@
      568              : 
      569              :       // Find second write pointer
      570            2 :       for (int i=0; i<DEPTH; i++) begin
-     571           44 :          if (~found_wrptr1) begin
-     572           44 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     573           44 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     574           44 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
-     575           44 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     571            2 :          if (~found_wrptr1) begin
+     572            2 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     573            2 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     574            2 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
+     575            2 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      576              :          end
      577              :       end
      578              :    end
@@ -758,51 +758,51 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657       496348 :             IDLE: begin
-     658       496348 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659       496348 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660       496348 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661       496348 :                      buf_wr_en[i]    = buf_state_en[i];
-     662       496348 :                      buf_data_en[i]  = buf_state_en[i];
-     663       496348 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664       496348 :                      buf_cmd_state_bus_en[i]  = '0;
+     657        10974 :             IDLE: begin
+     658        10974 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659        10974 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660        10974 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661        10974 :                      buf_wr_en[i]    = buf_state_en[i];
+     662        10974 :                      buf_data_en[i]  = buf_state_en[i];
+     663        10974 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664        10974 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         9354 :             CMD: begin
-     672         9354 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         9354 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         9354 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         9354 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         9354 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         9354 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         9354 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         9354 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         9354 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         9354 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671          344 :             CMD: begin
+     672          344 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673          344 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674          344 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675          344 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676          344 :                      buf_ldfwd_in[i]          = 1'b1;
+     677          344 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678          344 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679          344 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680          344 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681          344 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683        19838 :             RESP: begin
-     684        19838 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685        19838 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686        19838 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687        19838 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688        19838 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689        19838 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690        19838 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691        19838 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692        19838 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693        19838 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694        19838 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695        19838 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683          790 :             RESP: begin
+     684          790 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685          790 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686          790 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687          790 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688          790 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689          790 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690          790 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691          790 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692          790 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693          790 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694          790 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695          790 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697        19838 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698        19838 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699        19838 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700        19838 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701        19838 :                      buf_cmd_state_bus_en[i]  = '0;
+     697          790 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698          790 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699          790 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700          790 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701          790 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
      703            0 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
      704            0 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
@@ -811,18 +811,18 @@
      707            0 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
      708            0 :                      buf_cmd_state_bus_en[i]  = '0;
      709              :             end
-     710           66 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
-     711           66 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
-     712           66 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
-     713           66 :                       buf_cmd_state_bus_en[i]  = '0;
+     710            2 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
+     711            2 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
+     712            2 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
+     713            2 :                       buf_cmd_state_bus_en[i]  = '0;
      714              :             end
-     715         3162 :             DONE: begin
-     716         3162 :                      buf_nxtstate[i]           = IDLE;
-     717         3162 :                      buf_rst[i]                = 1'b1;
-     718         3162 :                      buf_state_en[i]           = 1'b1;
-     719         3162 :                      buf_ldfwd_in[i]           = 1'b0;
-     720         3162 :                      buf_ldfwd_en[i]           = buf_state_en[i];
-     721         3162 :                      buf_cmd_state_bus_en[i]  = '0;
+     715          114 :             DONE: begin
+     716          114 :                      buf_nxtstate[i]           = IDLE;
+     717          114 :                      buf_rst[i]                = 1'b1;
+     718          114 :                      buf_state_en[i]           = 1'b1;
+     719          114 :                      buf_ldfwd_in[i]           = 1'b0;
+     720          114 :                      buf_ldfwd_en[i]           = buf_state_en[i];
+     721          114 :                      buf_cmd_state_bus_en[i]  = '0;
      722              :             end
      723            0 :             default : begin
      724            0 :                      buf_nxtstate[i]          = IDLE;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_intf.sv.html
index 0a9279ebc3e..21079e0a966 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_bus_intf.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        54.8%
+    
+        48.7%
     
     
-        63
+        56
     
     
         115
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30       583434 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        12564 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -140,43 +140,43 @@
       36            0 :    input logic                          dec_tlu_sideeffect_posted_disable,  // disable the posted sideeffect load store to the bus
       37              : 
       38              :    // various clocks needed for the bus reads and writes
-      39        17720 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
-      40         9144 :    input logic                          lsu_busm_clken,                     // bus clock enable
+      39          680 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
+      40          234 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42       583434 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43       583434 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44       583434 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42        12564 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43        12564 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44        12564 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46       583434 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47       583434 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48       583434 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46        12564 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47        12564 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48        12564 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
-      51        11872 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
-      52        11872 :    input logic                          lsu_busreq_m,                      // bus request is in m
+      51          452 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
+      52          452 :    input logic                          lsu_busreq_m,                      // bus request is in m
       53              : 
-      54         2612 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
-      55         2612 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
+      54           16 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
+      55           16 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
       56              : 
-      57         2496 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
-      58         2496 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
+      57          120 :    input logic [31:0]                   lsu_addr_m,                        // lsu address flowing down the pipe
+      58          120 :    input logic [31:0]                   lsu_addr_r,                        // lsu address flowing down the pipe
       59              : 
-      60         2496 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
-      61         2496 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
+      60          120 :    input logic [31:0]                   end_addr_m,                        // lsu address flowing down the pipe
+      61          120 :    input logic [31:0]                   end_addr_r,                        // lsu address flowing down the pipe
       62              : 
-      63           72 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
-      64            0 :    input logic                          dec_tlu_force_halt,
+      63            0 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
+      64            0 :    input logic                          dec_tlu_force_halt,
       65              : 
-      66        11872 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
+      66          452 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
       67            0 :    input logic                          is_sideeffects_m,                  // lsu attribute is side_effects
-      68           56 :    input logic                          flush_m_up,                        // flush
+      68            4 :    input logic                          flush_m_up,                        // flush
       69            0 :    input logic                          flush_r,                           // flush
       70            0 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71              : 
-      72        11872 :    output logic                         lsu_busreq_r,                      // bus request is in r
-      73         6040 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      74           28 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
-      75         9798 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
+      72          452 :    output logic                         lsu_busreq_r,                      // bus request is in r
+      73          228 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      74            0 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
+      75          244 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
       76            0 :    output logic [31:0]                  bus_read_data_m,                   // the bus return data
       77              : 
       78              : 
@@ -185,24 +185,24 @@
       81            2 :    output logic [31:0]                  lsu_imprecise_error_addr_any,      // address of the imprecise error
       82              : 
       83              :    // Non-blocking loads
-      84         6024 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
-      85         2428 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
+      84          224 :    output logic                               lsu_nonblock_load_valid_m,   // there is an external load -> put in the cam
+      85          216 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,     // the tag of the external non block load
       86            0 :    output logic                               lsu_nonblock_load_inv_r,     // invalidate signal for the cam entry for non block loads
-      87         2428 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
-      88         6192 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
+      87          216 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
+      88          224 :    output logic                               lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
       89            0 :    output logic                               lsu_nonblock_load_data_error,// non block load has an error
-      90           48 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
-      91           24 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
+      90            0 :    output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // the tag of the non block load sending the data/error
+      91            0 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
       92              : 
       93              :    // PMU events
-      94        12368 :    output logic                         lsu_pmu_bus_trxn,
+      94          456 :    output logic                         lsu_pmu_bus_trxn,
       95            0 :    output logic                         lsu_pmu_bus_misaligned,
       96            0 :    output logic                         lsu_pmu_bus_error,
       97            0 :    output logic                         lsu_pmu_bus_busy,
       98              : 
       99              :    // AXI Write Channels
-     100         6344 :    output logic                        lsu_axi_awvalid,
-     101        12370 :    input  logic                        lsu_axi_awready,
+     100          232 :    output logic                        lsu_axi_awvalid,
+     101          456 :    input  logic                        lsu_axi_awready,
      102            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_awid,
      103            2 :    output logic [31:0]                 lsu_axi_awaddr,
      104            2 :    output logic [3:0]                  lsu_axi_awregion,
@@ -214,20 +214,20 @@
      110            0 :    output logic [2:0]                  lsu_axi_awprot,
      111            0 :    output logic [3:0]                  lsu_axi_awqos,
      112              : 
-     113         6344 :    output logic                        lsu_axi_wvalid,
-     114        12370 :    input  logic                        lsu_axi_wready,
-     115           20 :    output logic [63:0]                 lsu_axi_wdata,
-     116          792 :    output logic [7:0]                  lsu_axi_wstrb,
+     113          232 :    output logic                        lsu_axi_wvalid,
+     114          456 :    input  logic                        lsu_axi_wready,
+     115            0 :    output logic [63:0]                 lsu_axi_wdata,
+     116            4 :    output logic [7:0]                  lsu_axi_wstrb,
      117            2 :    output logic                        lsu_axi_wlast,
      118              : 
-     119         6344 :    input  logic                        lsu_axi_bvalid,
+     119          228 :    input  logic                        lsu_axi_bvalid,
      120            2 :    output logic                        lsu_axi_bready,
      121            0 :    input  logic [1:0]                  lsu_axi_bresp,
      122            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_bid,
      123              : 
      124              :    // AXI Read Channels
-     125         6024 :    output logic                        lsu_axi_arvalid,
-     126        12370 :    input  logic                        lsu_axi_arready,
+     125          224 :    output logic                        lsu_axi_arvalid,
+     126          456 :    input  logic                        lsu_axi_arready,
      127            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_arid,
      128            2 :    output logic [31:0]                 lsu_axi_araddr,
      129            2 :    output logic [3:0]                  lsu_axi_arregion,
@@ -239,10 +239,10 @@
      135            0 :    output logic [2:0]                  lsu_axi_arprot,
      136            0 :    output logic [3:0]                  lsu_axi_arqos,
      137              : 
-     138         6192 :    input  logic                        lsu_axi_rvalid,
+     138          224 :    input  logic                        lsu_axi_rvalid,
      139            2 :    output logic                        lsu_axi_rready,
      140            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_rid,
-     141          120 :    input  logic [63:0]                 lsu_axi_rdata,
+     141            4 :    input  logic [63:0]                 lsu_axi_rdata,
      142            0 :    input  logic [1:0]                  lsu_axi_rresp,
      143              : 
      144            2 :    input logic                         lsu_bus_clk_en
@@ -256,16 +256,16 @@
      152            2 :    logic [3:0]        ldst_byteen_m, ldst_byteen_r;
      153            0 :    logic [7:0]        ldst_byteen_ext_m, ldst_byteen_ext_r;
      154            0 :    logic [3:0]        ldst_byteen_hi_m, ldst_byteen_hi_r;
-     155         3638 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
+     155           68 :    logic [3:0]        ldst_byteen_lo_m, ldst_byteen_lo_r;
      156            0 :    logic              is_sideeffects_r;
      157              : 
-     158           96 :    logic [63:0]       store_data_ext_r;
-     159            0 :    logic [31:0]       store_data_hi_r;
-     160           24 :    logic [31:0]       store_data_lo_r;
+     158            0 :    logic [63:0]       store_data_ext_r;
+     159            0 :    logic [31:0]       store_data_hi_r;
+     160            0 :    logic [31:0]       store_data_lo_r;
      161              : 
-     162        12198 :    logic              addr_match_dw_lo_r_m;
-     163        11874 :    logic              addr_match_word_lo_r_m;
-     164          604 :    logic              no_word_merge_r, no_dword_merge_r;
+     162          458 :    logic              addr_match_dw_lo_r_m;
+     163          454 :    logic              addr_match_word_lo_r_m;
+     164            8 :    logic              no_word_merge_r, no_dword_merge_r;
      165              : 
      166            0 :    logic              ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
      167            0 :    logic [3:0]        ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_clkdomain.sv.html
index 635b7fb35b8..f58fb541e4a 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31       583434 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32       583434 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31        12564 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32        12564 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -144,52 +144,52 @@
       40              : 
       41            0 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
       42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
-      43        11872 :    input logic      lsu_busreq_r,                      // busreq in r
-      44         6040 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      45         9798 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
+      43          452 :    input logic      lsu_busreq_r,                      // busreq in r
+      44          228 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      45          244 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
       46            2 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
       47              : 
       48            2 :    input logic      lsu_bus_clk_en,                    // bus clock enable
       49              : 
-      50         2612 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
-      51         2612 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
-      52         2612 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
-      53         2612 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
+      50           16 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
+      51           16 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
+      52           16 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
+      53           16 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
       54              : 
       55              :    // Outputs
-      56        17720 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
-      57         9144 :    output logic     lsu_busm_clken,                    // bus clock enable
+      56          680 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
+      57          234 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59       583434 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60       583434 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59        12564 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60        12564 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62       583434 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63       583434 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62        12564 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63        12564 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65       583434 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66       583434 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65        12564 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66        12564 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68       583434 :    output logic     lsu_stbuf_c1_clk,
+      68        12564 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70       583434 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71       583434 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70        12564 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71        12564 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74       583434 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74        12564 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
       78              : 
-      79        11872 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
-      80        11872 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
-      81        11872 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
-      82         5848 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
+      79          452 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
+      80          452 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
+      81          452 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
+      82          228 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
       83              : 
       84              : 
       85            0 :    logic lsu_stbuf_c1_clken;
-      86         9144 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
+      86          234 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
       87              : 
-      88         8488 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
+      88          230 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
       89              : 
       90              :    //-------------------------------------------------------------------------------------------
       91              :    // Clock Enable logic
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_ctl.sv.html
index 06618666571..aad2b034283 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        24.1%
+    
+        19.6%
     
     
-        27
+        22
     
     
         112
@@ -136,37 +136,37 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35       583434 :    input logic                             lsu_c2_m_clk,            // clocks
-      36       583434 :    input logic                             lsu_c2_r_clk,            // clocks
-      37       583434 :    input logic                             lsu_c1_r_clk,            // clocks
-      38       583434 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39       583434 :    input logic                             lsu_free_c2_clk,         // clocks
+      35        12564 :    input logic                             lsu_c2_m_clk,            // clocks
+      36        12564 :    input logic                             lsu_c2_r_clk,            // clocks
+      37        12564 :    input logic                             lsu_c1_r_clk,            // clocks
+      38        12564 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39        12564 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41       583434 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41        12564 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
-      45         2612 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
-      46         2612 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
-      47         2612 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
+      45           16 :    input                                   el2_lsu_pkt_t lsu_pkt_r,// lsu packets
+      46           16 :    input                                   el2_lsu_pkt_t lsu_pkt_m,// lsu packets
+      47           16 :    input                                   el2_lsu_pkt_t lsu_pkt_d,// lsu packets
       48            0 :    input logic                             addr_in_dccm_d,          // address maps to dccm
       49            0 :    input logic                             addr_in_pic_d,           // address maps to pic
       50            0 :    input logic                             addr_in_pic_m,           // address maps to pic
       51            0 :    input logic                             addr_in_dccm_m, addr_in_dccm_r,   // address in dccm per pipe stage
       52            0 :    input logic                             addr_in_pic_r,                    // address in pic  per pipe stage
       53            0 :    input logic                             lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
-      54        11872 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
+      54          452 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
       55            0 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
       56              : 
       57              :    // lsu address down the pipe
-      58         2496 :    input logic [31:0]                      lsu_addr_d,
-      59         2336 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
-      60         2496 :    input logic [31:0]                      lsu_addr_r,
+      58          120 :    input logic [31:0]                      lsu_addr_d,
+      59          104 :    input logic [pt.DCCM_BITS-1:0]          lsu_addr_m,
+      60          120 :    input logic [31:0]                      lsu_addr_r,
       61              : 
       62              :    // lsu address down the pipe - needed to check unaligned
-      63         2496 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
-      64         2496 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
-      65         2496 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
+      63          120 :    input logic [pt.DCCM_BITS-1:0]          end_addr_d,
+      64          120 :    input logic [pt.DCCM_BITS-1:0]          end_addr_m,
+      65          120 :    input logic [pt.DCCM_BITS-1:0]          end_addr_r,
       66              : 
       67              : 
       68            0 :    input logic                             stbuf_reqvld_any,        // write enable
@@ -206,8 +206,8 @@
      102            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_hi_m,           // corrected dccm data
      103            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]    sec_data_lo_m,           // corrected dccm data
      104              : 
-     105           72 :    input logic [31:0]                      store_data_m,            // Store data M-stage
-     106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
+     105            0 :    input logic [31:0]                      store_data_m,            // Store data M-stage
+     106            0 :    input logic                             dma_dccm_wen,            // Perform DMA writes only for word/dword
      107            0 :    input logic                             dma_pic_wen,             // Perform PIC writes
      108            0 :    input logic [2:0]                       dma_mem_tag_m,           // DMA Buffer entry number M-stage
      109            0 :    input logic [31:0]                      dma_mem_addr,            // DMA request address
@@ -218,11 +218,11 @@
      114            0 :    input logic [pt.DCCM_ECC_WIDTH-1:0]     dma_dccm_wdata_ecc_lo,   // ECC bits for the DMA wdata
      115              : 
      116            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_hi_r,
-     117           24 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
-     118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
-     119           24 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
-     120           72 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
-     121            0 :    output logic                            ld_single_ecc_error_r,
+     117            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_data_lo_r,
+     118            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_hi_r,       // data from the dccm
+     119            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0]   store_datafn_lo_r,       // data from the dccm
+     120            0 :    output logic [31:0]                     store_data_r,            // raw store data to be sent to bus
+     121            0 :    output logic                            ld_single_ecc_error_r,
      122            0 :    output logic                            ld_single_ecc_error_r_ff,
      123              : 
      124            0 :    output logic [31:0]                     picm_mask_data_m,        // pic data to stbuf
@@ -240,8 +240,8 @@
      136            0 :    output logic                            dccm_rden,               // dccm interface -- write
      137            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo,         // dccm interface -- wr addr for lo bank
      138            0 :    output logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi,         // dccm interface -- wr addr for hi bank
-     139         2336 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
-     140         2496 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
+     139          104 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo,         // dccm interface -- read address for lo bank
+     140          120 :    output logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi,         // dccm interface -- read address for hi bank
      141            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,         // dccm write data for lo bank
      142            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,         // dccm write data for hi bank
      143              : 
@@ -254,8 +254,8 @@
      150            0 :    output logic                            picm_mken,               // write to pic need a mask
      151            2 :    output logic [31:0]                     picm_rdaddr,             // address for pic read access
      152            2 :    output logic [31:0]                     picm_wraddr,             // address for pic write access
-     153           24 :    output logic [31:0]                     picm_wr_data,            // write data
-     154            0 :    input logic [31:0]                      picm_rd_data,            // read data
+     153            0 :    output logic [31:0]                     picm_wr_data,            // write data
+     154            0 :    input logic [31:0]                      picm_rd_data,            // read data
      155              : 
      156            0 :    input logic                             scan_mode                // scan mode
      157              : );
@@ -277,7 +277,7 @@
      173            0 :    logic                           kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;
      174              : 
      175              :     // byte_en flowing down
-     176         1320 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
+     176            8 :    logic [3:0]                     store_byteen_m ,store_byteen_r;
      177            0 :    logic [7:0]                     store_byteen_ext_m, store_byteen_ext_r;
      178              : 
      179              :    if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_mem.sv.html
index 58dad47e3cd..3972df199f1 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35       583434 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36       583434 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35        12564 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        12564 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
@@ -145,8 +145,8 @@
       41            0 :    input logic         dccm_rden,                                       // read enable
       42            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,                     // write address
       43            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,                     // write address
-      44         2336 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
-      45         2496 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
+      44          104 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,                     // read address
+      45          120 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,                     // read address for the upper bank in case of a misaligned access
       46            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,              // write data
       47            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,              // write data
       48              :    el2_mem_if.veer_dccm                   dccm_mem_export,              // RAM repositioned in testbench and connected by this interface
@@ -164,7 +164,7 @@
       60              : 
       61            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        wren_bank;
       62            0 :    logic [pt.DCCM_NUM_BANKS-1:0]                                        rden_bank;
-      63         2496 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
+      63          120 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;
       64            0 :    logic [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+DCCM_WIDTH_BITS)]           rd_addr_even, rd_addr_odd;
       65            0 :    logic                                                                rd_unaligned, wr_unaligned;
       66            0 :    logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0]              dccm_bank_dout;
@@ -172,8 +172,8 @@
       68              : 
       69            0 :    logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0]               wr_data_bank;
       70              : 
-      71         4260 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
-      72         4260 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
+      71          120 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_lo_q;
+      72          120 :    logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS]        dccm_rd_addr_hi_q;
       73              : 
       74            0 :    logic [pt.DCCM_NUM_BANKS-1:0]            dccm_clken;
       75              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_ecc.sv.html
index b96f4791c2c..8f74d68871e 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,22 +135,22 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34       583434 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35       583434 :    input logic                           lsu_c2_r_clk,       // clock
+      34        12564 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        12564 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
       39              : 
-      40         2612 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
-      41         2612 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
+      40           16 :    input el2_lsu_pkt_t                  lsu_pkt_m,          // packet in m
+      41           16 :    input el2_lsu_pkt_t                  lsu_pkt_r,          // packet in r
       42            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  stbuf_data_any,
       43              : 
       44            0 :    input logic                           dec_tlu_core_ecc_disable,  // disables the ecc computation and error flagging
       45              : 
       46            0 :    input logic                           lsu_dccm_rden_r,          // dccm rden
       47            0 :    input logic                           addr_in_dccm_r,           // address in dccm
-      48         2336 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
-      49         2496 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
+      48          104 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_r,               // start address
+      49          120 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_r,               // end address
       50            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r,          // data from the dccm
       51            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r,          // data from the dccm
       52            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_r,       // data from the dccm + ecc
@@ -164,8 +164,8 @@
       60            0 :    input logic                           ld_single_ecc_error_r_ff,  // ld has a single ecc error
       61            0 :    input logic                           lsu_dccm_rden_m,           // dccm rden
       62            0 :    input logic                           addr_in_dccm_m,            // address in dccm
-      63         2336 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
-      64         2496 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
+      63          104 :    input logic  [pt.DCCM_BITS-1:0]       lsu_addr_m,                // start address
+      64          120 :    input logic  [pt.DCCM_BITS-1:0]       end_addr_m,                // end address
       65            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m,           // raw data from mem
       66            0 :    input logic  [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m,           // raw data from mem
       67            0 :    input logic  [pt.DCCM_ECC_WIDTH-1:0]  dccm_data_ecc_hi_m,        // ecc read out from mem
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_lsc_ctl.sv.html
index fbafa9361f1..6c530ee8d17 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_lsc_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        45.9%
+    
+        35.3%
     
     
-        39
+        30
     
     
         85
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35       583434 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        12564 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38       583434 :    input logic                lsu_c1_m_clk,
-      39       583434 :    input logic                lsu_c1_r_clk,
-      40       583434 :    input logic                lsu_c2_m_clk,
-      41       583434 :    input logic                lsu_c2_r_clk,
-      42       583434 :    input logic                lsu_store_c1_m_clk,
+      38        12564 :    input logic                lsu_c1_m_clk,
+      39        12564 :    input logic                lsu_c1_r_clk,
+      40        12564 :    input logic                lsu_c2_m_clk,
+      41        12564 :    input logic                lsu_c2_r_clk,
+      42        12564 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
@@ -154,38 +154,38 @@
       50            0 :    input logic                lsu_single_ecc_error_m,    // ECC single bit error M-stage
       51            0 :    input logic                lsu_double_ecc_error_m,    // ECC double bit error M-stage
       52              : 
-      53           56 :    input logic                flush_m_up,                // Flush M and D stage
+      53            4 :    input logic                flush_m_up,                // Flush M and D stage
       54            0 :    input logic                flush_r,                   // Flush R-stage
       55            0 :    input logic                ldst_dual_d,               // load/store is unaligned at 32 bit boundary D-stage
       56            0 :    input logic                ldst_dual_m,               // load/store is unaligned at 32 bit boundary M-stage
       57            0 :    input logic                ldst_dual_r,               // load/store is unaligned at 32 bit boundary R-stage
       58              : 
-      59         2880 :    input logic [31:0]         exu_lsu_rs1_d,             // address
-      60           72 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
+      59          104 :    input logic [31:0]         exu_lsu_rs1_d,             // address
+      60            0 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
       61              : 
-      62         2612 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
-      63        11872 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
-      64          400 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
+      62           16 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
+      63          452 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
+      64            0 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
       65              : 
-      66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
+      66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
       67            0 :    input  logic [31:0]        bus_read_data_m,           // the bus return data
       68            0 :    output logic [31:0]        lsu_result_m,              // lsu load data
       69            0 :    output logic [31:0]        lsu_result_corr_r,         // This is the ECC corrected data going to RF
       70              :    // lsu address down the pipe
-      71         2496 :    output logic [31:0]        lsu_addr_d,
-      72         2496 :    output logic [31:0]        lsu_addr_m,
-      73         2496 :    output logic [31:0]        lsu_addr_r,
+      71          120 :    output logic [31:0]        lsu_addr_d,
+      72          120 :    output logic [31:0]        lsu_addr_m,
+      73          120 :    output logic [31:0]        lsu_addr_r,
       74              :    // lsu address down the pipe - needed to check unaligned
-      75         2496 :    output logic [31:0]        end_addr_d,
-      76         2496 :    output logic [31:0]        end_addr_m,
-      77         2496 :    output logic [31:0]        end_addr_r,
+      75          120 :    output logic [31:0]        end_addr_d,
+      76          120 :    output logic [31:0]        end_addr_m,
+      77          120 :    output logic [31:0]        end_addr_r,
       78              :    // store data down the pipe
-      79           72 :    output logic [31:0]        store_data_m,
+      79            0 :    output logic [31:0]        store_data_m,
       80              : 
-      81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
+      81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
       82            0 :    output logic                lsu_exc_m,                // Access or misaligned fault
       83            0 :    output logic                is_sideeffects_m,         // is sideffects space
-      84        11872 :    output logic                lsu_commit_r,             // lsu instruction in r commits
+      84          452 :    output logic                lsu_commit_r,             // lsu instruction in r commits
       85            0 :    output logic                lsu_single_ecc_error_incr,// LSU inc SB error counter
       86            0 :    output el2_lsu_error_pkt_t lsu_error_pkt_r,          // lsu exception packet
       87              : 
@@ -211,26 +211,26 @@
      107            0 :    input logic [63:0]         dma_mem_wdata,
      108              : 
      109              :    // Store buffer related signals
-     110         2612 :    output el2_lsu_pkt_t      lsu_pkt_d,
-     111         2612 :    output el2_lsu_pkt_t      lsu_pkt_m,
-     112         2612 :    output el2_lsu_pkt_t      lsu_pkt_r,
+     110           16 :    output el2_lsu_pkt_t      lsu_pkt_d,
+     111           16 :    output el2_lsu_pkt_t      lsu_pkt_m,
+     112           16 :    output el2_lsu_pkt_t      lsu_pkt_r,
      113              : 
-     114         4970 :     input logic lsu_pmp_error_start,
-     115         4970 :     input logic lsu_pmp_error_end,
+     114            0 :     input logic lsu_pmp_error_start,
+     115            0 :     input logic lsu_pmp_error_end,
      116              : 
-     117            0 :    input  logic               scan_mode                  // Scan mode
+     117            0 :    input  logic               scan_mode                  // Scan mode
      118              : 
      119              :    );
      120              : 
      121            0 :    logic [31:3]        end_addr_pre_m, end_addr_pre_r;
-     122         2496 :    logic [31:0]        full_addr_d;
-     123         2496 :    logic [31:0]        full_end_addr_d;
-     124         2880 :    logic [31:0]        lsu_rs1_d;
-     125          400 :    logic [11:0]        lsu_offset_d;
-     126         2880 :    logic [31:0]        rs1_d;
-     127          400 :    logic [11:0]        offset_d;
-     128          400 :    logic [12:0]        end_addr_offset_d;
-     129            0 :    logic [2:0]         addr_offset_d;
+     122          120 :    logic [31:0]        full_addr_d;
+     123          120 :    logic [31:0]        full_end_addr_d;
+     124          104 :    logic [31:0]        lsu_rs1_d;
+     125            0 :    logic [11:0]        lsu_offset_d;
+     126          104 :    logic [31:0]        rs1_d;
+     127            0 :    logic [11:0]        offset_d;
+     128            0 :    logic [12:0]        end_addr_offset_d;
+     129            0 :    logic [2:0]         addr_offset_d;
      130              : 
      131            0 :    logic [63:0]        dma_mem_wdata_shifted;
      132            2 :    logic               addr_external_d;
@@ -242,12 +242,12 @@
      138            0 :    logic               fir_dccm_access_error_m, fir_nondccm_access_error_m;
      139              : 
      140            0 :    logic [3:0]         exc_mscause_d, exc_mscause_m;
-     141         2880 :    logic [31:0]        rs1_d_raw;
-     142           72 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
-     143            0 :    logic [31:0]        bus_read_data_r;
+     141          104 :    logic [31:0]        rs1_d_raw;
+     142            0 :    logic [31:0]        store_data_d, store_data_pre_m, store_data_m_in;
+     143            0 :    logic [31:0]        bus_read_data_r;
      144              : 
      145            0 :    el2_lsu_pkt_t           dma_pkt_d;
-     146         2612 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
+     146           16 :    el2_lsu_pkt_t           lsu_pkt_m_in, lsu_pkt_r_in;
      147            0 :    el2_lsu_error_pkt_t     lsu_error_pkt_m;
      148              : 
      149              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_stbuf.sv.html
index de000d46bb3..0a14f89c36b 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_stbuf.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        27.6%
+    
+        25.0%
     
     
-        21
+        19
     
     
         76
@@ -137,23 +137,23 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36       583434 :    input logic                           clk,                         // core clock
+      36        12564 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39       583434 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40       583434 :    input logic                           lsu_free_c2_clk,             // free clk
+      39        12564 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40        12564 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
-      44        11872 :    input logic                           lsu_commit_r,                // lsu commits
-      45        11872 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
+      44          452 :    input logic                           lsu_commit_r,                // lsu commits
+      45          452 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
       46            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_hi_r,             // merged data from the dccm for stores. This is used for fwding
-      47           24 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
-      48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
-      49           24 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
+      47            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
+      48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
+      49            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_lo_r,           // merged data from the dccm for stores
       50              : 
       51              :    // Store Buffer output
-      52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
+      52            0 :    output logic                          stbuf_reqvld_any,            // stbuf is draining
       53            0 :    output logic                          stbuf_reqvld_flushed_any,    // Top entry is flushed
       54            0 :    output logic [pt.LSU_SB_BITS-1:0]     stbuf_addr_any,              // address
       55            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any,              // stbuf data
@@ -163,13 +163,13 @@
       59            2 :    output logic                          lsu_stbuf_empty_any,         // stbuf is empty
       60            0 :    output logic                          ldst_stbuf_reqvld_r,         // needed for clocking
       61              : 
-      62         2336 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
-      63         2496 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
-      64         2496 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
+      62          104 :    input logic [pt.LSU_SB_BITS-1:0]      lsu_addr_d,                  // lsu address D-stage
+      63          120 :    input logic [31:0]                    lsu_addr_m,                  // lsu address M-stage
+      64          120 :    input logic [31:0]                    lsu_addr_r,                  // lsu address R-stage
       65              : 
-      66         2496 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
-      67         2496 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
-      68         2496 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
+      66          120 :    input logic [pt.LSU_SB_BITS-1:0]      end_addr_d,                  // lsu end address D-stage - needed to check unaligned
+      67          120 :    input logic [31:0]                    end_addr_m,                  // lsu end address M-stage - needed to check unaligned
+      68          120 :    input logic [31:0]                    end_addr_r,                  // lsu end address R-stage - needed to check unaligned
       69              : 
       70            0 :    input logic                           ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71            0 :    input logic                           addr_in_dccm_m,              // address is in dccm
@@ -177,8 +177,8 @@
       73              : 
       74              :    // Forwarding signals
       75            0 :    input logic                           lsu_cmpen_m,                 // needed for forwarding stbuf - load
-      76         2612 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
-      77         2612 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
+      76           16 :    input el2_lsu_pkt_t                  lsu_pkt_m,                   // LSU packet M-stage
+      77           16 :    input el2_lsu_pkt_t                  lsu_pkt_r,                   // LSU packet R-stage
       78              : 
       79            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m,          // stbuf data
       80            0 :    output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m,          // stbuf data
@@ -206,13 +206,13 @@
      102            0 :    logic [DEPTH-1:0]                     stbuf_wr_en;
      103            0 :    logic [DEPTH-1:0]                     stbuf_dma_kill_en;
      104            0 :    logic [DEPTH-1:0]                     stbuf_reset;
-     105         2496 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
+     105          120 :    logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
      106            0 :    logic [DEPTH-1:0][DATA_WIDTH-1:0]     stbuf_datain;
      107            0 :    logic [DEPTH-1:0][BYTE_WIDTH-1:0]     stbuf_byteenin;
      108              : 
      109            0 :    logic [7:0]             store_byteen_ext_r;
      110            0 :    logic [BYTE_WIDTH-1:0]  store_byteen_hi_r;
-     111         1384 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
+     111            8 :    logic [BYTE_WIDTH-1:0]  store_byteen_lo_r;
      112              : 
      113            0 :    logic                   WrPtrEn, RdPtrEn;
      114            0 :    logic [DEPTH_LOG2-1:0]  WrPtr, RdPtr;
@@ -225,7 +225,7 @@
      121            0 :    logic [3:0]             stbuf_numvld_any, stbuf_specvld_any;
      122            0 :    logic [1:0]             stbuf_specvld_m, stbuf_specvld_r;
      123              : 
-     124         2496 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
+     124          120 :    logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
      125              : 
      126              :    // variables to detect matching from the store queue
      127            0 :    logic [DEPTH-1:0]                 stbuf_match_hi, stbuf_match_lo;
@@ -241,7 +241,7 @@
      137            0 :    logic [BYTE_WIDTH-1:0]  ld_byte_hit_hi, ld_byte_rhit_hi;
      138              : 
      139            0 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_hi_r;
-     140         3638 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
+     140           68 :    logic [BYTE_WIDTH-1:0]  ldst_byteen_lo_r;
      141              :    // byte_en flowing down
      142            0 :    logic [7:0]             ldst_byteen_r;
      143            0 :    logic [7:0]             ldst_byteen_ext_r;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_trigger.sv.html
index 9fbd0b0ffb1..7262b9adba6 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_lsu_trigger.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        40.0%
+    
+        30.0%
     
     
-        4
+        3
     
     
         10
@@ -132,11 +132,11 @@
       28              : `include "el2_param.vh"
       29              :  )(
       30            0 :    input el2_trigger_pkt_t [3:0] trigger_pkt_any,            // trigger packet from dec
-      31         2612 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
-      32         2496 :    input logic [31:0]             lsu_addr_m,                 // address
-      33           72 :    input logic [31:0]             store_data_m,               // store data
+      31           16 :    input el2_lsu_pkt_t           lsu_pkt_m,                  // lsu packet
+      32          120 :    input logic [31:0]             lsu_addr_m,                 // address
+      33            0 :    input logic [31:0]             store_data_m,               // store data
       34              : 
-      35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
+      35            0 :    output logic [3:0]             lsu_trigger_match_m         // match result
       36              : );
       37              : 
       38            0 :    logic               trigger_enable;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem.sv.html
index 472c572e82f..a371be4c112 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25       583434 :    input logic         clk,
+      25        12564 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -137,8 +137,8 @@
       33            0 :    input logic         dccm_rden,
       34            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,
       35            0 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,
-      36         2336 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
-      37         2496 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
+      36          104 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
+      37          120 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
       38            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
       39            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
       40              : 
@@ -147,7 +147,7 @@
       43            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
       44              : 
       45              :    //ICCM ports
-      46          268 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
+      46            8 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
       47            0 :    input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
       48            0 :    input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
       49            0 :    input logic         iccm_wren,
@@ -164,12 +164,12 @@
       60            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
       61            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
       62            0 :    input  logic         ic_rd_en,
-      63         7972 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-      64        28098 :    input  logic         ic_sel_premux_data, // Premux data sel
+      63           38 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+      64          594 :    input  logic         ic_sel_premux_data, // Premux data sel
       65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
       66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
       67              : 
-      68         2004 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+      68           38 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
       69            0 :    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
       70            0 :    output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       71            0 :    input  logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -178,7 +178,7 @@
       74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
       75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
       76              : 
-      77         7972 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      77           38 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
       79              : 
       80              : 
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92       583434 :    logic active_clk;
+      92        12564 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem_if.sv.html
index 19b39dd9ad5..de0e249e61d 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,14 +130,14 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29       793152 :   logic                                                               clk;
+      29        18336 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
       33              :   // ICCM
       34            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
       35            0 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_wren_bank;
-      36          804 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
+      36           24 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
       37              : 
       38            0 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_wr_data;
       39            0 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
@@ -149,7 +149,7 @@
       45              :   // DCCM
       46            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_clken;
       47            0 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
-      48         7488 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
+      48          360 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
       49            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
       50            0 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
       51            0 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pic_ctrl.sv.html
index 676a591a8c9..6b36240a496 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pic_ctrl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        24.1%
+    
+        22.2%
     
     
-        26
+        24
     
     
         108
@@ -131,16 +131,16 @@
       27              :  )
       28              :                   (
       29              : 
-      30       583434 :                      input  logic                   clk,                  // Core clock
-      31       583434 :                      input  logic                   free_clk,             // free clock
+      30        12564 :                      input  logic                   clk,                  // Core clock
+      31        12564 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
       35            0 :                      input  logic [pt.PIC_TOTAL_INT_PLUS1-1:0]   extintsrc_req,  // Interrupt requests
       36            2 :                      input  logic [31:0]            picm_rdaddr,          // Address of the register
       37            2 :                      input  logic [31:0]            picm_wraddr,          // Address of the register
-      38           24 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
-      39            0 :                      input  logic                   picm_wren,            // Write enable to the register
+      38            0 :                      input  logic [31:0]            picm_wr_data,         // Data to be written to the register
+      39            0 :                      input  logic                   picm_wren,            // Write enable to the register
       40            0 :                      input  logic                   picm_rden,            // Read enable for the register
       41            0 :                      input  logic                   picm_mken,            // Read the Mask for the register
       42            0 :                      input  logic [3:0]             meicurpl,             // Current Priority Level
@@ -185,11 +185,11 @@
       81              : 
       82            0 : logic  raddr_config_pic_match ;
       83            0 : logic  raddr_intenable_base_match;
-      84         7746 : logic  raddr_intpriority_base_match;
+      84          234 : logic  raddr_intpriority_base_match;
       85            0 : logic  raddr_config_gw_base_match ;
       86              : 
       87            0 : logic  waddr_config_pic_match ;
-      88         7746 : logic  waddr_intpriority_base_match;
+      88          234 : logic  waddr_intpriority_base_match;
       89            0 : logic  waddr_intenable_base_match;
       90            0 : logic  waddr_config_gw_base_match ;
       91            0 : logic  addr_clear_gw_base_match ;
@@ -228,7 +228,7 @@
      124            0 : logic                                        intpriord;
      125            0 : logic                                        config_reg_we ;
      126            0 : logic                                        config_reg_re ;
-     127         2100 : logic                                        config_reg_in ;
+     127          100 : logic                                        config_reg_in ;
      128            0 : logic                                        prithresh_reg_write , prithresh_reg_read;
      129            0 : logic                                        intpriority_reg_read ;
      130            0 : logic                                        intenable_reg_read   ;
@@ -236,8 +236,8 @@
      132            0 : logic                                        picm_wren_ff , picm_rden_ff ;
      133            2 : logic [31:0]                                 picm_raddr_ff;
      134            2 : logic [31:0]                                 picm_waddr_ff;
-     135           24 : logic [31:0]                                 picm_wr_data_ff;
-     136            0 : logic [3:0]                                  mask;
+     135            0 : logic [31:0]                                 picm_wr_data_ff;
+     136            0 : logic [3:0]                                  mask;
      137            0 : logic                                        picm_mken_ff;
      138            0 : logic [ID_BITS-1:0]                          claimid_in ;
      139            0 : logic [INTPRIORITY_BITS-1:0]                 pl_in ;
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155       583434 :    logic                                     pic_raddr_c1_clk;
-     156       583434 :    logic                                     pic_data_c1_clk;
-     157       583434 :    logic                                     pic_pri_c1_clk;
-     158       583434 :    logic                                     pic_int_c1_clk;
-     159       583434 :    logic                                     gw_config_c1_clk;
+     155        12564 :    logic                                     pic_raddr_c1_clk;
+     156        12564 :    logic                                     pic_data_c1_clk;
+     157        12564 :    logic                                     pic_pri_c1_clk;
+     158        12564 :    logic                                     pic_int_c1_clk;
+     159        12564 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500      4230144 :               if (intenable_reg_re[i]) begin
+     500        97792 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503      4230144 :               if (intpriority_reg_re[i]) begin
+     503        97792 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506      4230144 :               if (gw_config_reg_re[i]) begin
+     506        97792 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -627,7 +627,7 @@
      523              : 
      524              : assign picm_rd_data[31:0] = picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0] ;
      525              : 
-     526         2336 : logic [14:0] address;
+     526          104 : logic [14:0] address;
      527              : 
      528              : assign address[14:0] = picm_raddr_ff[14:0];
      529              : 
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562      8195904 :                              input logic rawclk,
+     562       189472 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pmp.sv.html
index d8b97cb1075..5b869dcfb80 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        60.0%
+    
+        50.0%
     
     
-        12
+        7
     
     
-        20
+        14
     
 
             
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        50.0%
+    
+        49.0%
     
     
-        26
+        25
     
     
-        52
+        51
     
 
             
@@ -127,29 +127,29 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26       583434 :     input logic clk,       // Top level clock
+      26        12564 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
       30              : `ifdef RV_SMEPMP
-      31            0 :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
+      31              :     input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits
       32              : `endif
       33              : 
       34              : `ifdef RV_USER_MODE
-      35           18 :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
-      36           26 :     input logic priv_mode_eff,  // operating effective privilege mode
+      35              :     input logic priv_mode_ns,   // operating privilege mode (next clock cycle)
+      36              :     input logic priv_mode_eff,  // operating effective privilege mode
       37              : `endif
       38              : 
-      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
+      39            0 :     input el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
       40              :     input logic             [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],
       41              : 
-      42         2496 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
+      42          120 :     input  logic              [31:0] pmp_chan_addr[PMP_CHANNELS],
       43            0 :     input  el2_pmp_type_pkt_t        pmp_chan_type[PMP_CHANNELS],
-      44         4970 :     output logic                     pmp_chan_err [PMP_CHANNELS]
+      44            0 :     output logic                     pmp_chan_err [PMP_CHANNELS]
       45              : );
       46              : 
       47              :   logic [                33:0]                     csr_pmp_addr_i          [pt.PMP_ENTRIES];
-      48         2496 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
+      48          120 :   logic [                33:0]                     pmp_req_addr_i          [  PMP_CHANNELS];
       49              : 
       50              :   logic [                33:0]                     region_start_addr       [pt.PMP_ENTRIES];
       51              :   logic [33:PMP_GRANULARITY+2]                     region_addr_mask        [pt.PMP_ENTRIES];
@@ -161,7 +161,7 @@
       57            2 :   logic [    PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
       58              : 
       59              : `ifdef RV_USER_MODE
-      60            2 :   logic any_region_enabled;
+      60              :   logic any_region_enabled;
       61              : `endif
       62              : 
       63              :   ///////////////////////
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133      8113344 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133       211584 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139      8113344 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139       211584 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       513840 :       if (!matched && match_all[r]) begin
-     170       513840 :         access_fail = ~final_perm_check[r];
-     171       513840 :         matched = 1'b1;
+     169        12816 :       if (!matched && match_all[r]) begin
+     170        12816 :         access_fail = ~final_perm_check[r];
+     171        12816 :         matched = 1'b1;
      172              :       end
      173              :     end
      174            6 :     return access_fail;
@@ -283,7 +283,7 @@
      179              :   // ---------------
      180              : 
      181              : `ifdef RV_USER_MODE
-     182            0 :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
+     182              :   logic [pt.PMP_ENTRIES-1:0] region_enabled;
      183              :   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena
      184              :     assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;
      185              :   end
@@ -324,7 +324,7 @@
      220              :   end
      221              : 
      222              : `ifdef RV_USER_MODE
-     223           18 :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
+     223              :   logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;
      224              :   for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff
      225              :     assign pmp_priv_mode_eff[c] = (
      226              :       ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |
@@ -348,12 +348,12 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247      5949096 :           OFF:     region_match_all[c][r] = 1'b0;
+     247       137976 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250       396120 :           TOR: begin
-     251       396120 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252       396120 :                                      region_match_lt[c][r];
+     250         8712 :           TOR: begin
+     251         8712 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252         8712 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer.sv.html
index 0ffd54aec50..0a8b13f3a5c 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        34.9%
+    
+        32.1%
     
     
-        220
+        201
     
     
-        631
+        627
     
 
             
@@ -130,7 +130,7 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29       583434 :    input logic                  clk,
+      29        12564 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
@@ -138,14 +138,14 @@
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37       583434 :    output logic                 active_l2clk,
-      38       583434 :    output logic                 free_l2clk,
+      37        12564 :    output logic                 active_l2clk,
+      38        12564 :    output logic                 free_l2clk,
       39              : 
-      40         4198 :    output logic [31:0] trace_rv_i_insn_ip,
+      40            8 :    output logic [31:0] trace_rv_i_insn_ip,
       41            2 :    output logic [31:0] trace_rv_i_address_ip,
-      42        35132 :    output logic   trace_rv_i_valid_ip,
-      43           24 :    output logic   trace_rv_i_exception_ip,
-      44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
+      42          816 :    output logic   trace_rv_i_valid_ip,
+      43            0 :    output logic   trace_rv_i_exception_ip,
+      44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
       45            0 :    output logic   trace_rv_i_interrupt_ip,
       46            0 :    output logic [31:0] trace_rv_i_tval_ip,
       47              : 
@@ -182,8 +182,8 @@
       78            0 :    output logic                          dccm_rden,
       79            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_lo,
       80            0 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_hi,
-      81         2336 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
-      82         2496 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
+      81          104 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
+      82          120 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
       83            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
       84            0 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_hi,
       85              : 
@@ -191,7 +191,7 @@
       87            0 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_hi,
       88              : 
       89              :    // ICCM ports
-      90          268 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
+      90            8 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
       91            0 :    output logic                  iccm_wren,
       92            0 :    output logic                  iccm_rden,
       93            0 :    output logic [2:0]            iccm_wr_size,
@@ -208,16 +208,16 @@
      104            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_wr_en,
      105            0 :    output logic                  ic_rd_en,
      106              : 
-     107         2004 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     108         7972 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     107           38 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
+     108           38 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      109            0 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      112              : 
      113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
      114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     115         7972 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     116        28098 :    output logic                      ic_sel_premux_data, // Select premux data
+     115           38 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     116          594 :    output logic                      ic_sel_premux_data, // Select premux data
      117              : 
      118              : 
      119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -233,7 +233,7 @@
      129              : 
      130              :    //-------------------------- LSU AXI signals--------------------------
      131              :    // AXI Write Channels
-     132         6344 :    output logic                            lsu_axi_awvalid,
+     132          232 :    output logic                            lsu_axi_awvalid,
      133            0 :    input  logic                            lsu_axi_awready,
      134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      135            2 :    output logic [31:0]                     lsu_axi_awaddr,
@@ -246,10 +246,10 @@
      142            0 :    output logic [2:0]                      lsu_axi_awprot,
      143            0 :    output logic [3:0]                      lsu_axi_awqos,
      144              : 
-     145         6344 :    output logic                            lsu_axi_wvalid,
+     145          232 :    output logic                            lsu_axi_wvalid,
      146            0 :    input  logic                            lsu_axi_wready,
-     147           20 :    output logic [63:0]                     lsu_axi_wdata,
-     148          792 :    output logic [7:0]                      lsu_axi_wstrb,
+     147            0 :    output logic [63:0]                     lsu_axi_wdata,
+     148            4 :    output logic [7:0]                      lsu_axi_wstrb,
      149            2 :    output logic                            lsu_axi_wlast,
      150              : 
      151            0 :    input  logic                            lsu_axi_bvalid,
@@ -258,7 +258,7 @@
      154            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      155              : 
      156              :    // AXI Read Channels
-     157         6024 :    output logic                            lsu_axi_arvalid,
+     157          224 :    output logic                            lsu_axi_arvalid,
      158            0 :    input  logic                            lsu_axi_arready,
      159            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      160            2 :    output logic [31:0]                     lsu_axi_araddr,
@@ -305,10 +305,10 @@
      201            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      202              : 
      203              :    // AXI Read Channels
-     204        35770 :    output logic                            ifu_axi_arvalid,
+     204          824 :    output logic                            ifu_axi_arvalid,
      205            0 :    input  logic                            ifu_axi_arready,
-     206        23272 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
-     207        14112 :    output logic [31:0]                     ifu_axi_araddr,
+     206          104 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     207           16 :    output logic [31:0]                     ifu_axi_araddr,
      208            2 :    output logic [3:0]                      ifu_axi_arregion,
      209            0 :    output logic [7:0]                      ifu_axi_arlen,
      210            0 :    output logic [2:0]                      ifu_axi_arsize,
@@ -419,10 +419,10 @@
      315            0 :    output logic                  hmastlock,
      316            0 :    output logic [3:0]            hprot,
      317            0 :    output logic [2:0]            hsize,
-     318        35770 :    output logic [1:0]            htrans,
+     318          824 :    output logic [1:0]            htrans,
      319            0 :    output logic                  hwrite,
      320              : 
-     321         3456 :    input  logic [63:0]           hrdata,
+     321           12 :    input  logic [63:0]           hrdata,
      322            2 :    input  logic                  hready,
      323            0 :    input  logic                  hresp,
      324              : 
@@ -432,11 +432,11 @@
      328            0 :    output logic                 lsu_hmastlock,
      329            0 :    output logic [3:0]           lsu_hprot,
      330            0 :    output logic [2:0]           lsu_hsize,
-     331        12368 :    output logic [1:0]           lsu_htrans,
-     332         4258 :    output logic                 lsu_hwrite,
-     333          254 :    output logic [63:0]          lsu_hwdata,
+     331          456 :    output logic [1:0]           lsu_htrans,
+     332          222 :    output logic                 lsu_hwrite,
+     333           32 :    output logic [63:0]          lsu_hwdata,
      334              : 
-     335          120 :    input  logic [63:0]          lsu_hrdata,
+     335            4 :    input  logic [63:0]          lsu_hrdata,
      336            2 :    input  logic                 lsu_hready,
      337            0 :    input  logic                 lsu_hresp,
      338              : 
@@ -496,12 +496,12 @@
      392              : 
      393              : 
      394              : 
-     395         3266 :    logic [63:0]                  hwdata_nc;
+     395           16 :    logic [63:0]                  hwdata_nc;
      396              :    //----------------------------------------------------------------------
      397              :    //
      398              :    //----------------------------------------------------------------------
      399              : 
-     400        35132 :    logic                         ifu_pmu_instr_aligned;
+     400          816 :    logic                         ifu_pmu_instr_aligned;
      401            0 :    logic                         ifu_ic_error_start;
      402            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
      403            0 :    logic                         ifu_iccm_rd_ecc_single_err;
@@ -509,55 +509,55 @@
      405            0 :    logic                         lsu_dccm_rd_ecc_single_err;
      406            0 :    logic                         lsu_dccm_rd_ecc_double_err;
      407              : 
-     408        12370 :    logic                         lsu_axi_awready_ahb;
-     409        12370 :    logic                         lsu_axi_wready_ahb;
-     410         6344 :    logic                         lsu_axi_bvalid_ahb;
+     408          456 :    logic                         lsu_axi_awready_ahb;
+     409          456 :    logic                         lsu_axi_wready_ahb;
+     410          228 :    logic                         lsu_axi_bvalid_ahb;
      411            0 :    logic                         lsu_axi_bready_ahb;
      412            0 :    logic [1:0]                   lsu_axi_bresp_ahb;
      413            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
-     414        12370 :    logic                         lsu_axi_arready_ahb;
-     415         6192 :    logic                         lsu_axi_rvalid_ahb;
+     414          456 :    logic                         lsu_axi_arready_ahb;
+     415          224 :    logic                         lsu_axi_rvalid_ahb;
      416            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
-     417          120 :    logic [63:0]                  lsu_axi_rdata_ahb;
+     417            4 :    logic [63:0]                  lsu_axi_rdata_ahb;
      418            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
      419            2 :    logic                         lsu_axi_rlast_ahb;
      420              : 
-     421        12370 :    logic                         lsu_axi_awready_int;
-     422        12370 :    logic                         lsu_axi_wready_int;
-     423         6344 :    logic                         lsu_axi_bvalid_int;
+     421          456 :    logic                         lsu_axi_awready_int;
+     422          456 :    logic                         lsu_axi_wready_int;
+     423          228 :    logic                         lsu_axi_bvalid_int;
      424            0 :    logic                         lsu_axi_bready_int;
      425            0 :    logic [1:0]                   lsu_axi_bresp_int;
      426            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
-     427        12370 :    logic                         lsu_axi_arready_int;
-     428         6192 :    logic                         lsu_axi_rvalid_int;
+     427          456 :    logic                         lsu_axi_arready_int;
+     428          224 :    logic                         lsu_axi_rvalid_int;
      429            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
-     430          120 :    logic [63:0]                  lsu_axi_rdata_int;
+     430            4 :    logic [63:0]                  lsu_axi_rdata_int;
      431            0 :    logic [1:0]                   lsu_axi_rresp_int;
      432            2 :    logic                         lsu_axi_rlast_int;
      433              : 
-     434        35770 :    logic                         ifu_axi_awready_ahb;
-     435        35770 :    logic                         ifu_axi_wready_ahb;
+     434          824 :    logic                         ifu_axi_awready_ahb;
+     435          824 :    logic                         ifu_axi_wready_ahb;
      436            0 :    logic                         ifu_axi_bvalid_ahb;
      437            0 :    logic                         ifu_axi_bready_ahb;
      438            0 :    logic [1:0]                   ifu_axi_bresp_ahb;
-     439         7408 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
-     440        35770 :    logic                         ifu_axi_arready_ahb;
-     441        71536 :    logic                         ifu_axi_rvalid_ahb;
-     442         7408 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
-     443         3454 :    logic [63:0]                  ifu_axi_rdata_ahb;
+     439           32 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
+     440          824 :    logic                         ifu_axi_arready_ahb;
+     441         1644 :    logic                         ifu_axi_rvalid_ahb;
+     442           32 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
+     443           12 :    logic [63:0]                  ifu_axi_rdata_ahb;
      444            0 :    logic [1:0]                   ifu_axi_rresp_ahb;
      445            2 :    logic                         ifu_axi_rlast_ahb;
      446              : 
-     447        35770 :    logic                         ifu_axi_awready_int;
-     448        35770 :    logic                         ifu_axi_wready_int;
+     447          824 :    logic                         ifu_axi_awready_int;
+     448          824 :    logic                         ifu_axi_wready_int;
      449            0 :    logic                         ifu_axi_bvalid_int;
      450            0 :    logic                         ifu_axi_bready_int;
      451            0 :    logic [1:0]                   ifu_axi_bresp_int;
-     452         7408 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
-     453        35770 :    logic                         ifu_axi_arready_int;
-     454        71536 :    logic                         ifu_axi_rvalid_int;
-     455         7408 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
-     456         3454 :    logic [63:0]                  ifu_axi_rdata_int;
+     452           32 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
+     453          824 :    logic                         ifu_axi_arready_int;
+     454         1644 :    logic                         ifu_axi_rvalid_int;
+     455           32 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
+     456           12 :    logic [63:0]                  ifu_axi_rdata_int;
      457            0 :    logic [1:0]                   ifu_axi_rresp_int;
      458            2 :    logic                         ifu_axi_rlast_int;
      459              : 
@@ -636,13 +636,13 @@
      532            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
      533              : 
      534              : 
-     535        28768 :    logic         dec_i0_rs1_en_d;
-     536        15504 :    logic         dec_i0_rs2_en_d;
-     537           80 :    logic  [31:0] gpr_i0_rs1_d;
-     538           12 :    logic  [31:0] gpr_i0_rs2_d;
+     535          548 :    logic         dec_i0_rs1_en_d;
+     536          232 :    logic         dec_i0_rs2_en_d;
+     537           12 :    logic  [31:0] gpr_i0_rs1_d;
+     538            8 :    logic  [31:0] gpr_i0_rs2_d;
      539              : 
-     540           40 :    logic [31:0] dec_i0_result_r;
-     541          764 :    logic [31:0] exu_i0_result_x;
+     540           12 :    logic [31:0] dec_i0_result_r;
+     541           16 :    logic [31:0] exu_i0_result_x;
      542            2 :    logic [31:1] exu_i0_pc_x;
      543            2 :    logic [31:1] exu_npc_r;
      544              : 
@@ -653,112 +653,112 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552         1752 :    logic [31:0] dec_i0_immed_d;
-     553         1180 :    logic [12:1] dec_i0_br_immed_d;
-     554          936 :    logic         dec_i0_select_pc_d;
+     552           20 :    logic [31:0] dec_i0_immed_d;
+     553           12 :    logic [12:1] dec_i0_br_immed_d;
+     554           24 :    logic         dec_i0_select_pc_d;
      555              : 
      556           10 :    logic [31:1] dec_i0_pc_d;
-     557         1072 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
+     557            4 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
      558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
-     560        24544 :    logic         dec_i0_alu_decode_d;
-     561        12188 :    logic         dec_i0_branch_d;
+     560          376 :    logic         dec_i0_alu_decode_d;
+     561          448 :    logic         dec_i0_branch_d;
      562              : 
-     563        35772 :    logic         ifu_miss_state_idle;
+     563          824 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
      565            0 :    logic         dec_tlu_flush_leak_one_r;
      566            0 :    logic         dec_tlu_flush_err_r;
-     567        33540 :    logic         ifu_i0_valid;
-     568          760 :    logic [31:0]  ifu_i0_instr;
+     567          608 :    logic         ifu_i0_valid;
+     568           12 :    logic [31:0]  ifu_i0_instr;
      569           10 :    logic [31:1]  ifu_i0_pc;
      570              : 
-     571         1596 :    logic        exu_flush_final;
+     571           68 :    logic        exu_flush_final;
      572              : 
-     573          680 :    logic [31:1] exu_flush_path_final;
+     573            8 :    logic [31:1] exu_flush_path_final;
      574              : 
-     575         2880 :    logic [31:0] exu_lsu_rs1_d;
-     576           72 :    logic [31:0] exu_lsu_rs2_d;
+     575          104 :    logic [31:0] exu_lsu_rs1_d;
+     576            0 :    logic [31:0] exu_lsu_rs2_d;
      577              : 
      578              : 
-     579         2612 :    el2_lsu_pkt_t    lsu_p;
-     580        25590 :    logic             dec_qual_lsu_d;
+     579           16 :    el2_lsu_pkt_t    lsu_p;
+     580          582 :    logic             dec_qual_lsu_d;
      581              : 
-     582        11872 :    logic        dec_lsu_valid_raw_d;
-     583          400 :    logic [11:0] dec_lsu_offset_d;
+     582          452 :    logic        dec_lsu_valid_raw_d;
+     583            0 :    logic [11:0] dec_lsu_offset_d;
      584              : 
-     585            0 :    logic [31:0]  lsu_result_m;
+     585            0 :    logic [31:0]  lsu_result_m;
      586            0 :    logic [31:0]  lsu_result_corr_r;     // This is the ECC corrected data going to RF
      587            0 :    logic         lsu_single_ecc_error_incr;     // Increment the ecc counter
      588            0 :    el2_lsu_error_pkt_t lsu_error_pkt_r;
      589            0 :    logic         lsu_imprecise_error_load_any;
      590            0 :    logic         lsu_imprecise_error_store_any;
      591            2 :    logic [31:0]  lsu_imprecise_error_addr_any;
-     592           28 :    logic         lsu_load_stall_any;       // This is for blocking loads
-     593           28 :    logic         lsu_store_stall_any;      // This is for blocking stores
-     594         8690 :    logic         lsu_idle_any;             // doesn't include DMA
-     595         8688 :    logic         lsu_active;               // lsu is active. used for clock
+     592            0 :    logic         lsu_load_stall_any;       // This is for blocking loads
+     593            0 :    logic         lsu_store_stall_any;      // This is for blocking stores
+     594          232 :    logic         lsu_idle_any;             // doesn't include DMA
+     595          230 :    logic         lsu_active;               // lsu is active. used for clock
      596              : 
      597              : 
      598            0 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
      599            0 :    logic [1:0]   lsu_fir_error;       // Error during fast interrupt lookup
      600              : 
      601              :    // Non-blocking loads
-     602         6024 :    logic                                 lsu_nonblock_load_valid_m;
-     603         2428 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
+     602          224 :    logic                                 lsu_nonblock_load_valid_m;
+     603          216 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
      604            0 :    logic                                 lsu_nonblock_load_inv_r;
-     605         2428 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
-     606         6192 :    logic                                 lsu_nonblock_load_data_valid;
-     607           48 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
-     608           24 :    logic [31:0]                          lsu_nonblock_load_data;
+     605          216 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
+     606          224 :    logic                                 lsu_nonblock_load_data_valid;
+     607            0 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
+     608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
-     610          172 :    logic        dec_csr_ren_d;
-     611            4 :    logic [31:0] dec_csr_rddata_d;
+     610            4 :    logic        dec_csr_ren_d;
+     611            0 :    logic [31:0] dec_csr_rddata_d;
      612              : 
-     613            0 :    logic [31:0] exu_csr_rs1_x;
+     613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
-     615        35132 :    logic        dec_tlu_i0_commit_cmt;
-     616           56 :    logic        dec_tlu_flush_lower_r;
-     617           56 :    logic        dec_tlu_flush_lower_wb;
+     615          816 :    logic        dec_tlu_i0_commit_cmt;
+     616            4 :    logic        dec_tlu_flush_lower_r;
+     617            4 :    logic        dec_tlu_flush_lower_wb;
      618            0 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
      619            0 :    logic        dec_tlu_fence_i_r;            // flush is a fence_i rfnpc, flush icache
      620              : 
      621            0 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624        17896 :    logic        ifu_i0_pc4;
+     624          310 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
-     628           24 :    el2_div_pkt_t  div_p;
-     629            0 :    logic           dec_div_cancel;
+     628            0 :    el2_div_pkt_t  div_p;
+     629            0 :    logic           dec_div_cancel;
      630              : 
      631            0 :    logic [31:0] exu_div_result;
-     632           48 :    logic exu_div_wren;
+     632            0 :    logic exu_div_wren;
      633              : 
-     634        35132 :    logic dec_i0_decode_d;
+     634          816 :    logic dec_i0_decode_d;
      635              : 
      636              : 
-     637          922 :    logic [31:1] pred_correct_npc_x;
+     637           28 :    logic [31:1] pred_correct_npc_x;
      638              : 
-     639         1914 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
+     639            4 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
      640              : 
-     641           44 :    el2_predict_pkt_t  exu_mp_pkt;
-     642          940 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643         2402 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
-     644          548 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
+     641            0 :    el2_predict_pkt_t  exu_mp_pkt;
+     642           20 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
+     643            2 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     644            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647         2402 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648         5352 :    logic [1:0]  exu_i0_br_hist_r;
+     647            2 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648          172 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651         7972 :    logic        exu_i0_br_valid_r;
-     652         1360 :    logic        exu_i0_br_mp_r;
-     653        10156 :    logic        exu_i0_br_middle_r;
+     651          208 :    logic        exu_i0_br_valid_r;
+     652           64 :    logic        exu_i0_br_mp_r;
+     653          248 :    logic        exu_i0_br_middle_r;
      654              : 
-     655         1914 :    logic        exu_i0_br_way_r;
+     655            4 :    logic        exu_i0_br_way_r;
      656              : 
-     657          236 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
+     657            4 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
      658              : 
      659            0 :    logic        dma_dccm_req;
      660            0 :    logic        dma_iccm_req;
@@ -779,8 +779,8 @@
      675              : 
      676            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
      677            0 :    logic        dma_iccm_stall_any;       // Stall the fetch
-     678        11874 :    logic        dccm_ready;
-     679         1594 :    logic        iccm_ready;
+     678          454 :    logic        dccm_ready;
+     679           66 :    logic        iccm_ready;
      680              : 
      681            0 :    logic        dma_pmu_dccm_read;
      682            0 :    logic        dma_pmu_dccm_write;
@@ -795,19 +795,19 @@
      691            0 :    logic        ifu_i0_dbecc;
      692            0 :    logic        iccm_dma_sb_error;
      693              : 
-     694          256 :    el2_br_pkt_t i0_brp;
-     695         1124 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696        11398 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     694            4 :    el2_br_pkt_t i0_brp;
+     695           24 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
+     696           10 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697            0 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
      700            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
      701              : 
      702              : 
-     703         2738 :    el2_predict_pkt_t dec_i0_predict_p_d;
+     703            4 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705        11398 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
-     706         1124 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
+     705           10 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     706           24 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707            0 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
      709              :    // PIC ports
@@ -816,8 +816,8 @@
      712            0 :    logic                  picm_mken;
      713            2 :    logic [31:0]           picm_rdaddr;
      714            2 :    logic [31:0]           picm_wraddr;
-     715           24 :    logic [31:0]           picm_wr_data;
-     716            0 :    logic [31:0]           picm_rd_data;
+     715            0 :    logic [31:0]           picm_wr_data;
+     716            0 :    logic [31:0]           picm_rd_data;
      717              : 
      718              :    // feature disable from mfdc
      719            0 :    logic  dec_tlu_external_ldfwd_disable; // disable external load forwarding
@@ -843,18 +843,18 @@
      739              :   // PMP Signals
      740            0 :   el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
      741              :   logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
-     742         2496 :   logic [31:0]            pmp_chan_addr [3];
+     742          120 :   logic [31:0]            pmp_chan_addr [3];
      743            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
-     744         4970 :   logic                   pmp_chan_err  [3];
+     744            0 :   logic                   pmp_chan_err  [3];
      745              : 
-     746            2 :   logic [31:1] ifu_pmp_addr;
+     746            2 :   logic [31:1] ifu_pmp_addr;
      747            0 :   logic        ifu_pmp_error;
-     748         2496 :   logic [31:0] lsu_pmp_addr_start;
-     749         4970 :   logic        lsu_pmp_error_start;
-     750         2496 :   logic [31:0] lsu_pmp_addr_end;
-     751         4970 :   logic        lsu_pmp_error_end;
-     752         5848 :   logic        lsu_pmp_we;
-     753         6024 :   logic        lsu_pmp_re;
+     748          120 :   logic [31:0] lsu_pmp_addr_start;
+     749            0 :   logic        lsu_pmp_error_start;
+     750          120 :   logic [31:0] lsu_pmp_addr_end;
+     751            0 :   logic        lsu_pmp_error_end;
+     752          228 :   logic        lsu_pmp_we;
+     753          224 :   logic        lsu_pmp_re;
      754              : 
      755              :    // -----------------------DEBUG  START -------------------------------
      756              : 
@@ -870,7 +870,7 @@
      766              : 
      767            0 :    logic                   core_dbg_cmd_done;         // Final muxed cmd done to debug
      768            0 :    logic                   core_dbg_cmd_fail;         // Final muxed cmd done to debug
-     769           40 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
+     769           12 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
      770              : 
      771            0 :    logic                   dma_dbg_cmd_done;          // Abstarct memory command sent to dma is done
      772            0 :    logic                   dma_dbg_cmd_fail;          // Abstarct memory command sent to dma failed
@@ -879,7 +879,7 @@
      775            0 :    logic                   dbg_dma_bubble;            // Debug needs a bubble to send a valid
      776            0 :    logic                   dma_dbg_ready;             // DMA is ready to accept debug request
      777              : 
-     778           40 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
+     778           12 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
      779            0 :    logic                   dec_dbg_cmd_done;          // This will be treated like a valid signal
      780            0 :    logic                   dec_dbg_cmd_fail;          // Abstract command failed
      781            0 :    logic                   dec_tlu_mpc_halted_only;   // Only halted due to MPC
@@ -889,43 +889,43 @@
      785            0 :    logic                   dec_debug_wdata_rs1_d;
      786            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
      787              : 
-     788        35132 :    logic [1:0]             dec_data_en;
-     789        35128 :    logic [1:0]             dec_ctl_en;
+     788          816 :    logic [1:0]             dec_data_en;
+     789          816 :    logic [1:0]             dec_ctl_en;
      790              : 
      791              :    // PMU Signals
-     792         1360 :    logic                   exu_pmu_i0_br_misp;
-     793         5836 :    logic                   exu_pmu_i0_br_ataken;
-     794         7494 :    logic                   exu_pmu_i0_pc4;
+     792           64 :    logic                   exu_pmu_i0_br_misp;
+     793          232 :    logic                   exu_pmu_i0_br_ataken;
+     794          234 :    logic                   exu_pmu_i0_pc4;
      795              : 
-     796         6024 :    logic                   lsu_pmu_load_external_m;
-     797         5848 :    logic                   lsu_pmu_store_external_m;
+     796          224 :    logic                   lsu_pmu_load_external_m;
+     797          228 :    logic                   lsu_pmu_store_external_m;
      798            0 :    logic                   lsu_pmu_misaligned_m;
-     799        12368 :    logic                   lsu_pmu_bus_trxn;
+     799          456 :    logic                   lsu_pmu_bus_trxn;
      800            0 :    logic                   lsu_pmu_bus_misaligned;
      801            0 :    logic                   lsu_pmu_bus_error;
      802            0 :    logic                   lsu_pmu_bus_busy;
      803              : 
-     804         1286 :    logic                   ifu_pmu_fetch_stall;
-     805        35772 :    logic                   ifu_pmu_ic_miss;
+     804           30 :    logic                   ifu_pmu_fetch_stall;
+     805          824 :    logic                   ifu_pmu_ic_miss;
      806            0 :    logic                   ifu_pmu_ic_hit;
      807            0 :    logic                   ifu_pmu_bus_error;
      808            0 :    logic                   ifu_pmu_bus_busy;
-     809        35770 :    logic                   ifu_pmu_bus_trxn;
+     809          824 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812       583434 :    logic                   free_clk;
-     813       583434 :    logic                   active_clk;
+     812        12564 :    logic                   free_clk;
+     813        12564 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
      817              : 
-     818         5200 :    logic [15:0]            ifu_i0_cinst;
+     818          166 :    logic [15:0]            ifu_i0_cinst;
      819              : 
      820              : // fast interrupt
      821            0 :    logic [31:2]            dec_tlu_meihap;
      822            0 :    logic                   dec_extint_stall;
      823              : 
-     824        35132 :    el2_trace_pkt_t  trace_rv_trace_pkt;
+     824          816 :    el2_trace_pkt_t  trace_rv_trace_pkt;
      825              : 
      826              : 
      827            0 :    logic                   lsu_fastint_stall_any;
@@ -941,7 +941,7 @@
      837            0 :    logic        pause_state;
      838            0 :    logic        halt_state;
      839              : 
-     840         9576 :    logic        dec_tlu_core_empty;
+     840           92 :    logic        dec_tlu_core_empty;
      841              : 
      842              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
      843              : 
@@ -991,13 +991,13 @@
      887              : `ifdef RV_USER_MODE
      888              : 
      889              :    // Operating privilege mode, 0 - machine, 1 - user
-     890           18 :    logic priv_mode;
+     890              :    logic priv_mode;
      891              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
-     892           26 :    logic priv_mode_eff;
+     892              :    logic priv_mode_eff;
      893              :    // Next privilege mode
-     894           18 :    logic priv_mode_ns;
+     894              :    logic priv_mode_ns;
      895              : 
-     896            0 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
+     896              :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
      897              : 
      898              : `endif
      899              : 
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer_wrapper.sv.html
index 16301858747..af31ad14872 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_el2_veer_wrapper.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        22.5%
+    
+        21.9%
     
     
-        69
+        67
     
     
         306
@@ -131,7 +131,7 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30       583434 :    input logic                             clk,
+      30        12564 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
@@ -140,11 +140,11 @@
       36            0 :    input logic [31:1]                      jtag_id,
       37              : 
       38              : 
-      39         4198 :    output logic [31:0]                     trace_rv_i_insn_ip,
+      39            8 :    output logic [31:0]                     trace_rv_i_insn_ip,
       40            2 :    output logic [31:0]                     trace_rv_i_address_ip,
-      41        35132 :    output logic                            trace_rv_i_valid_ip,
-      42           24 :    output logic                            trace_rv_i_exception_ip,
-      43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
+      41          816 :    output logic                            trace_rv_i_valid_ip,
+      42            0 :    output logic                            trace_rv_i_exception_ip,
+      43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
       44            0 :    output logic                            trace_rv_i_interrupt_ip,
       45            0 :    output logic [31:0]                     trace_rv_i_tval_ip,
       46              : 
@@ -339,10 +339,10 @@
      235            0 :    output logic                            hmastlock,
      236            0 :    output logic [3:0]                      hprot,
      237            0 :    output logic [2:0]                      hsize,
-     238        35770 :    output logic [1:0]                      htrans,
+     238          824 :    output logic [1:0]                      htrans,
      239            0 :    output logic                            hwrite,
      240              : 
-     241         3456 :    input logic [63:0]                      hrdata,
+     241           12 :    input logic [63:0]                      hrdata,
      242            2 :    input logic                             hready,
      243            0 :    input logic                             hresp,
      244              : 
@@ -352,11 +352,11 @@
      248            0 :    output logic                            lsu_hmastlock,
      249            0 :    output logic [3:0]                      lsu_hprot,
      250            0 :    output logic [2:0]                      lsu_hsize,
-     251        12368 :    output logic [1:0]                      lsu_htrans,
-     252         4258 :    output logic                            lsu_hwrite,
-     253          254 :    output logic [63:0]                     lsu_hwdata,
+     251          456 :    output logic [1:0]                      lsu_htrans,
+     252          222 :    output logic                            lsu_hwrite,
+     253           32 :    output logic [63:0]                     lsu_hwdata,
      254              : 
-     255          120 :    input logic [63:0]                      lsu_hrdata,
+     255            4 :    input logic [63:0]                      lsu_hrdata,
      256            2 :    input logic                             lsu_hready,
      257            0 :    input logic                             lsu_hresp,
      258              :    // Debug Syster Bus AHB
@@ -454,16 +454,16 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353       583434 :    logic                             active_l2clk;
-     354       583434 :    logic                             free_l2clk;
+     353        12564 :    logic                             active_l2clk;
+     354        12564 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
      358            0 :    logic         dccm_rden;
      359            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo;
      360            0 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi;
-     361         2336 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
-     362         2496 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
+     361          104 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
+     362          120 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
      363            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
      364            0 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi;
      365              : 
@@ -490,19 +490,19 @@
      386            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way;   // Debug way. Rd or Wr.
      387              : 
      388            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
-     389         2004 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
-     390         7972 :    logic [63:0]  ic_rd_data;
+     389           38 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
+     390           38 :    logic [63:0]  ic_rd_data;
      391            0 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      392            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
      393              : 
      394            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
      395            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
      396              : 
-     397         7972 :    logic [63:0]  ic_premux_data;
-     398        28098 :    logic         ic_sel_premux_data;
+     397           38 :    logic [63:0]  ic_premux_data;
+     398          594 :    logic         ic_sel_premux_data;
      399              : 
      400              :    // ICCM ports
-     401          268 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
+     401            8 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
      402            0 :    logic           iccm_wren;
      403            0 :    logic           iccm_rden;
      404            0 :    logic [2:0]     iccm_wr_size;
@@ -610,7 +610,7 @@
      506              : 
      507              : 
      508              : `ifdef RV_BUILD_AHB_LITE
-     509         6344 :    wire                            lsu_axi_awvalid;
+     509          232 :    wire                            lsu_axi_awvalid;
      510            0 :    wire                            lsu_axi_awready;
      511            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid;
      512            2 :    wire [31:0]                     lsu_axi_awaddr;
@@ -624,10 +624,10 @@
      520            0 :    wire [3:0]                      lsu_axi_awqos;
      521              : 
      522              : 
-     523         6344 :    wire                            lsu_axi_wvalid;
+     523          232 :    wire                            lsu_axi_wvalid;
      524            0 :    wire                            lsu_axi_wready;
-     525           20 :    wire [63:0]                     lsu_axi_wdata;
-     526          792 :    wire [7:0]                      lsu_axi_wstrb;
+     525            0 :    wire [63:0]                     lsu_axi_wdata;
+     526            4 :    wire [7:0]                      lsu_axi_wstrb;
      527            2 :    wire                            lsu_axi_wlast;
      528              : 
      529            0 :    wire                            lsu_axi_bvalid;
@@ -636,7 +636,7 @@
      532            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid;
      533              : 
      534              :    // AXI Read Channels
-     535         6024 :    wire                            lsu_axi_arvalid;
+     535          224 :    wire                            lsu_axi_arvalid;
      536            0 :    wire                            lsu_axi_arready;
      537            0 :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid;
      538            2 :    wire [31:0]                     lsu_axi_araddr;
@@ -694,10 +694,10 @@
      590            0 :    wire [pt.IFU_BUS_TAG-1:0]      ifu_axi_bid;
      591              : 
      592              :    // AXI Read Channels
-     593        35770 :    wire                            ifu_axi_arvalid;
+     593          824 :    wire                            ifu_axi_arvalid;
      594            0 :    wire                            ifu_axi_arready;
-     595        23272 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
-     596        14112 :    wire [31:0]                     ifu_axi_araddr;
+     595          104 :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
+     596           16 :    wire [31:0]                     ifu_axi_araddr;
      597            2 :    wire [3:0]                      ifu_axi_arregion;
      598            0 :    wire [7:0]                      ifu_axi_arlen;
      599            0 :    wire [2:0]                      ifu_axi_arsize;
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_modesw/index_mem_lib.sv.html
index 6c384485975..8d0d6b267e4 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111      2115040 : `EL2_RAM(4096, 39)
+     111        48864 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175       528760 : `EL2_RAM_BE(512, 142)
+     175        12216 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208       264380 : `EL2_RAM_BE(128, 52)
+     208         6108 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_ahb_modesw/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_modesw/index_rvjtag_tap.v.html
index 6146115fea9..34363012fac 100644
--- a/html/main/coverage_dashboard/all_ahb_modesw/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_modesw/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index.html
index 072923ae001..c06e5136b47 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design.html
index f549d56c867..0cb6518f474 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dbg.html
index c022478c45d..41bd415c675 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dec.html
index b40c78beb1e..7dc5f61dbe6 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dmi.html
index 3ed145606e4..5dd52c08ab2 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_exu.html
index 988c61c511d..22d6e1f475c 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_ifu.html
index 0da362fdcfe..0efab287311 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_include.html
index 543e0c0886d..5bb4f0f30ca 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lib.html
index f1aaf5f543d..bdf6b3aac7d 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lsu.html
index bd645d98287..3739b79c606 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_ahb_to_axi4.sv.html
index acad0e76d0d..93913a89978 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_axi4_to_ahb.sv.html
index 139ae0b0bdd..26e8904c0aa 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_beh_lib.sv.html
index ef767c5c07e..9d7572e0b76 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_jtag_to_core_sync.v.html
index 0261861722f..835c68fabcf 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_mux.v.html
index 6e1260ef54b..759417e91bc 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_wrapper.v.html
index 0026b9f90f3..40b1a992b61 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dbg.sv.html
index f43a3df278c..47d0510d9bd 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec.sv.html
index f8543219f67..02b98bade55 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_csr_equ_mu.svh.html
index 67ad7bb9b3d..692b72b72e6 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_decode_ctl.sv.html
index 3f1a887224f..3535e1dbd65 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_gpr_ctl.sv.html
index 39959782ece..8e02ba823fc 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_ib_ctl.sv.html
index 7cf14360798..dd2e5fa331a 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_pmp_ctl.sv.html
index c1aa9d88277..108c983a9e8 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_tlu_ctl.sv.html
index e8300612baf..f263c6164e5 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_trigger.sv.html
index f187487732a..f05e1cee016 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dma_ctrl.sv.html
index 783f4afcbcf..39a71c834c0 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu.sv.html
index 6c3fa932e59..2cdee2b53ad 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_alu_ctl.sv.html
index af1054abcd4..0bb201b3ba8 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_div_ctl.sv.html
index 9f300eca0e1..6ea7da40820 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_mul_ctl.sv.html
index 040ddf357a0..e14a08be6a2 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu.sv.html
index 2a25ce71f94..586daf53861 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_aln_ctl.sv.html
index fdc8fc9cf0b..c99646e4220 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_bp_ctl.sv.html
index b404cc19589..ebcdd8cd7b7 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_compress_ctl.sv.html
index 4166f043ddc..834ef9bd973 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ic_mem.sv.html
index c72b449561e..43b53a0bcd4 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_iccm_mem.sv.html
index be06c18053b..8f00befad5a 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ifc_ctl.sv.html
index 214ef151dc0..2e982f57817 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_mem_ctl.sv.html
index 33ee761919a..d5cbec3e153 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lib.sv.html
index 8a98f725007..4853ebefc3b 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu.sv.html
index a281d17f147..dbe28e4cb02 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_addrcheck.sv.html
index 8f0767f2a25..ac5d4c359b9 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_buffer.sv.html
index 3b50faaf69a..e3de5ffab63 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_intf.sv.html
index c6e8705548c..e057012c4a1 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_clkdomain.sv.html
index 8fa160e1373..a6feeebf5da 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_ctl.sv.html
index f80f6639b5f..3443b46d04a 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_mem.sv.html
index 3ba84eaa507..2a672bf1b35 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_ecc.sv.html
index 36de60e2f7b..0281b258f3d 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_lsc_ctl.sv.html
index 91c9b42de52..9f11e797fe5 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_stbuf.sv.html
index 11a48ca0547..759c760c8fd 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_trigger.sv.html
index 73641df0fc5..f4699011384 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem.sv.html
index 72cf856a468..5e3005c1a81 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem_if.sv.html
index d1d317fc938..c6cbb082617 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pic_ctrl.sv.html
index e8c44993678..a65d88756b1 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pmp.sv.html
index dd6612aba26..b120bfd0c4a 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer.sv.html
index 01481b15d5e..2ba5ee3eff5 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer_wrapper.sv.html
index df6ab3f17dd..fd23d99b18e 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_mem_lib.sv.html
index e85ac065dd2..bf0f78fd34e 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_perf_counters/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_perf_counters/index_rvjtag_tap.v.html
index 22e0f7bf828..8414d251abc 100644
--- a/html/main/coverage_dashboard/all_ahb_perf_counters/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_perf_counters/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index.html b/html/main/coverage_dashboard/all_ahb_pmp/index.html
index 5f95ae2c447..7cbd43398c6 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design.html
index f75de8c3296..b70d581c6d2 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dbg.html
index fcad9ff4e82..2aaa5a63e95 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dec.html
index bba3c3155fd..7c832a00b03 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dmi.html
index 1c5c9cd2630..788809beaf1 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_exu.html
index 8426a542d57..c176d2416e8 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_ifu.html
index cc39b25dfca..7f3ca34a4ba 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_include.html
index dc557e60863..f05efddc512 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lib.html
index a5fc18300c3..49b3ed74013 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lsu.html
index 93d926254db..1d71aefa892 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_ahb_to_axi4.sv.html
index f6e626a6da4..ba078d0e3be 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_axi4_to_ahb.sv.html
index 9e54fdfdacc..4b9f47bd1a8 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_beh_lib.sv.html
index bf3faca52e8..647ea31e844 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_jtag_to_core_sync.v.html
index f779ab902de..26b6e7b0211 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_mux.v.html
index ddcf8f31ea0..4fd755115ac 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_wrapper.v.html
index 477fbf0aa58..3479f46ec14 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dbg.sv.html
index bc3af6fe30c..16daab44c48 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec.sv.html
index 84879fca8a2..6a329179c8b 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_csr_equ_mu.svh.html
index cda13045390..e6352b51b8f 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_decode_ctl.sv.html
index f826d87a0b2..8e23a2d4d9e 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_gpr_ctl.sv.html
index c9f1ed650fa..0f4c97c6462 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_ib_ctl.sv.html
index 06a7fe1783f..4ef9ec5f133 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_pmp_ctl.sv.html
index b361f6b9cba..61b47deaa2d 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_tlu_ctl.sv.html
index 7076dcaa421..5df0730a943 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_trigger.sv.html
index 8e906c6bb73..7f7495e7444 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dma_ctrl.sv.html
index c4a1f45fcc2..f48dba1056b 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu.sv.html
index 0c03f044596..bfe7b83e698 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_alu_ctl.sv.html
index 2ca074421b8..f0e7a0b0581 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_div_ctl.sv.html
index 0a60d378988..4b4c51aa5f9 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_mul_ctl.sv.html
index 24c6044f097..5bcc15a840e 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu.sv.html
index 48b6dc7c552..716b1563cdd 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_aln_ctl.sv.html
index 86c13224b4b..57f86defc4c 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_bp_ctl.sv.html
index 220504991c8..c6e2a281f0d 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_compress_ctl.sv.html
index d6eac2b0718..c03ae4a2083 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ic_mem.sv.html
index 61d3d91f36b..a60e86bf20d 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_iccm_mem.sv.html
index a35e9cf69ab..89accd39db9 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ifc_ctl.sv.html
index 3823f09b928..cbc101f92fe 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_mem_ctl.sv.html
index de9ca37951c..4cc81889dac 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lib.sv.html
index 43a826dce0d..7d51c31a5a2 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu.sv.html
index 2d30c90ad7c..f208035f9fe 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_addrcheck.sv.html
index 669ebc6c778..63567577a9f 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_buffer.sv.html
index 3daabc628d0..447538d1993 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_intf.sv.html
index 6200665c3e0..4544fd92e54 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_clkdomain.sv.html
index 4e53fb92bd8..56f77251bdc 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_ctl.sv.html
index 3e7084165f2..5b3ae6a24b5 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_mem.sv.html
index 54a2da2bb48..fb896b87971 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_ecc.sv.html
index 13cc37e3b42..2acb29e4273 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_lsc_ctl.sv.html
index c7af806b32b..e0ba3479634 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_stbuf.sv.html
index 7a03a12e9a1..197f603f6c7 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_trigger.sv.html
index 06b0ada2fa6..dea579d61bb 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem.sv.html
index 5b5eef48dcc..d6b8bee0e35 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem_if.sv.html
index 1cfc2dc1959..d5d9e83c4bf 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pic_ctrl.sv.html
index 5739541d0d5..bdf0d080ab5 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pmp.sv.html
index b7ffec89374..38f83fd0807 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer.sv.html
index d2745bafcc7..aa9413563ca 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer_wrapper.sv.html
index 601551d7fb5..b3ae39d89c6 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_ahb_pmp/index_mem_lib.sv.html
index d07ba7755f3..4aa25e3bbbb 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ahb_pmp/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_ahb_pmp/index_rvjtag_tap.v.html
index 092478bfb4a..486d5b9b1db 100644
--- a/html/main/coverage_dashboard/all_ahb_pmp/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_ahb_pmp/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index.html b/html/main/coverage_dashboard/all_axi_cmark/index.html
index 328c4394286..5ae419fa20e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        45.8%
+    
+        45.4%
     
     
-        2348
+        2352
     
     
-        5131
+        5178
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.1%
+                    27.8%
                 
             
 
             
                 355
                 /
-                1265
+                1275
             
         
             
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    48.3%
+                    47.7%
                 
             
 
             
-                477
+                480
                 /
-                987
+                1007
             
         
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.1%
+                    6.9%
                 
             
 
             
-                6
+                7
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design.html
index d09bad07d7e..921ddd0001a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        28.1%
+    
+        27.8%
     
     
         355
     
     
-        1265
+        1275
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.0%
+                    35.0%
                 
             
 
             
                 7
                 /
-                14
+                20
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    33.2%
+                    33.0%
                 
             
 
             
                 208
                 /
-                627
+                631
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dbg.html
index fbcb8653a3a..aab55ff549c 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dec.html
index 298a640ef63..4839becc5d1 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        48.3%
+    
+        47.7%
     
     
-        477
+        480
     
     
-        987
+        1007
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.6%
+                    49.8%
                 
             
 
             
                 128
                 /
-                253
+                257
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.9%
+                    21.2%
                 
             
 
             
                 7
                 /
-                32
+                33
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.9%
+                    28.5%
                 
             
 
             
-                104
+                107
                 /
-                360
+                375
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dmi.html
index a500f94d793..829d52613c2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_exu.html
index 6d807c0e541..12c9d96b5de 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_ifu.html
index fdddcef81d0..6a4e2133bab 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_include.html
index f1ad9d97ebd..26eb053dcbe 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        7.1%
+    
+        6.9%
     
     
-        6
+        7
     
     
-        84
+        101
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_m.svh
+            
+                el2_dec_csr_equ_mu.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    7.1%
+                    6.9%
                 
             
 
             
-                6
+                7
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lib.html
index 895aabf563d..798c738426e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lsu.html
index 585ed5fe42e..d5e7afa39c2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_beh_lib.sv.html
index 5f1679ce561..109ba76db21 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_cmark/index_dmi_jtag_to_core_sync.v.html
index 2aea611890a..76b3bf4f9e9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_cmark/index_dmi_mux.v.html
index adf56e0fe45..fe9cf6ffa7d 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_cmark/index_dmi_wrapper.v.html
index 034288cb33f..6aef81940d3 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dbg.sv.html
index 96c6a1eff26..b24d7ce34c3 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec.sv.html
index 078ee26f360..85813192fd2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.6%
+    
+        49.8%
     
     
         128
     
     
-        253
+        257
     
 
             
@@ -354,7 +354,7 @@
      250        16572 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252           24 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253         2414 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253         2833 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255          736 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256          736 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_csr_equ_mu.svh.html
new file mode 100644
index 00000000000..271ee1c626b
--- /dev/null
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_csr_equ_mu.svh.html
@@ -0,0 +1,666 @@
+
+
+
+
+    
+    
+        Full
+        coverage report
+    
+    
+    
+
+
+
+    
+        
+    

+            
+                
+                
+            

+                    Project
+                    Full
+                    coverage report
+                

+        

+    

+        
+            
+                
+                
+                
+                
+                
+                
+                
+            
+            
+                
+                
+                
+                
+    
+    
+    
+    
+
+            
+            
+                
+                
+                
+                
+    
+    
+    
+    
+
+            
+            
+        
Current view:
+                    Cores-VeeR-EL2—Cores-VeeR-EL2—design—include—el2_dec_csr_equ_mu.svh
+                CoverageHitTotal
Test Date:
+                    25-09-2024
+                
+        Toggle
+    
+        6.9%
+    
+        7
+    
+        101
+    
Test:
+                    axi_cmark
+                
+        Branch
+    
+        0.0%
+    
+        0
+    
+        0
+    

+    

+
+    
+
+
+
+
+
+
+


+
            Line data    Source code

+
+       1            0 : logic csr_misa;
+       2            0 : logic csr_mvendorid;
+       3            0 : logic csr_marchid;
+       4            0 : logic csr_mimpid;
+       5            0 : logic csr_mhartid;
+       6           36 : logic csr_mstatus;
+       7            8 : logic csr_mtvec;
+       8            0 : logic csr_mip;
+       9            0 : logic csr_mie;
+      10           16 : logic csr_mcyclel;
+      11            0 : logic csr_mcycleh;
+      12            0 : logic csr_minstretl;
+      13            0 : logic csr_minstreth;
+      14            0 : logic csr_mscratch;
+      15            0 : logic csr_mepc;
+      16            0 : logic csr_mcause;
+      17            0 : logic csr_mscause;
+      18            0 : logic csr_mtval;
+      19            8 : logic csr_mrac;
+      20            0 : logic csr_dmst;
+      21            0 : logic csr_mdseac;
+      22            0 : logic csr_meihap;
+      23            0 : logic csr_meivt;
+      24            0 : logic csr_meipt;
+      25            0 : logic csr_meicurpl;
+      26            0 : logic csr_meicidpl;
+      27            0 : logic csr_dcsr;
+      28            0 : logic csr_mcgc;
+      29            0 : logic csr_mfdc;
+      30            0 : logic csr_dpc;
+      31            0 : logic csr_mtsel;
+      32            0 : logic csr_mtdata1;
+      33            0 : logic csr_mtdata2;
+      34            0 : logic csr_mhpmc3;
+      35            0 : logic csr_mhpmc4;
+      36            0 : logic csr_mhpmc5;
+      37            0 : logic csr_mhpmc6;
+      38            0 : logic csr_mhpmc3h;
+      39            0 : logic csr_mhpmc4h;
+      40            0 : logic csr_mhpmc5h;
+      41            0 : logic csr_mhpmc6h;
+      42            0 : logic csr_mhpme3;
+      43            0 : logic csr_mhpme4;
+      44            0 : logic csr_mhpme5;
+      45            0 : logic csr_mhpme6;
+      46            0 : logic csr_mcounteren;
+      47            0 : logic csr_mcountinhibit;
+      48            0 : logic csr_mitctl0;
+      49            0 : logic csr_mitctl1;
+      50            0 : logic csr_mitb0;
+      51            0 : logic csr_mitb1;
+      52            0 : logic csr_mitcnt0;
+      53            0 : logic csr_mitcnt1;
+      54            0 : logic csr_perfva;
+      55            0 : logic csr_perfvb;
+      56            0 : logic csr_perfvc;
+      57            0 : logic csr_perfvd;
+      58            0 : logic csr_perfve;
+      59            0 : logic csr_perfvf;
+      60            0 : logic csr_perfvg;
+      61            0 : logic csr_perfvh;
+      62            0 : logic csr_perfvi;
+      63            0 : logic csr_mpmc;
+      64            0 : logic csr_mcpc;
+      65            0 : logic csr_meicpct;
+      66            0 : logic csr_mdeau;
+      67            0 : logic csr_micect;
+      68            0 : logic csr_miccmect;
+      69            0 : logic csr_mdccmect;
+      70            0 : logic csr_mfdht;
+      71            0 : logic csr_mfdhs;
+      72            0 : logic csr_dicawics;
+      73            0 : logic csr_dicad0h;
+      74            0 : logic csr_dicad0;
+      75            0 : logic csr_dicad1;
+      76            0 : logic csr_dicago;
+      77            0 : logic csr_menvcfg;
+      78            0 : logic csr_menvcfgh;
+      79            0 : logic csr_pmpcfg;
+      80            0 : logic csr_pmpaddr0;
+      81            0 : logic csr_pmpaddr16;
+      82            0 : logic csr_pmpaddr32;
+      83            0 : logic csr_pmpaddr48;
+      84           36 : logic csr_cyclel;
+      85            0 : logic csr_cycleh;
+      86            0 : logic csr_instretl;
+      87            0 : logic csr_instreth;
+      88            0 : logic csr_hpmc3;
+      89            0 : logic csr_hpmc4;
+      90            0 : logic csr_hpmc5;
+      91            0 : logic csr_hpmc6;
+      92            0 : logic csr_hpmc3h;
+      93            0 : logic csr_hpmc4h;
+      94            0 : logic csr_hpmc5h;
+      95            0 : logic csr_hpmc6h;
+      96            0 : logic csr_mseccfgl;
+      97            0 : logic csr_mseccfgh;
+      98            0 : logic valid_only;
+      99            0 : logic presync;
+     100           20 : logic postsync;
+     101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     103              : 
+     104              : assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+     105              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     106              : 
+     107              : assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+     108              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     109              : 
+     110              : assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]
+     111              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     112              : 
+     113              : assign csr_mhartid = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     114              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]);
+     115              : 
+     116              : assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     117              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
+     118              :     &!dec_csr_rdaddr_d[0]);
+     119              : 
+     120              : assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     121              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     122              : 
+     123              : assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
+     124              :     &!dec_csr_rdaddr_d[0]);
+     125              : 
+     126              : assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     127              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     128              : 
+     129              : assign csr_mcyclel = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
+     130              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     131              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     132              : 
+     133              : assign csr_mcycleh = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     134              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     135              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     136              : 
+     137              : assign csr_minstretl = (dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     138              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     139              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     140              : 
+     141              : assign csr_minstreth = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     142              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     143              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     144              : 
+     145              : assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     146              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     147              : 
+     148              : assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     149              :     &dec_csr_rdaddr_d[0]);
+     150              : 
+     151              : assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     152              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     153              : 
+     154              : assign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     155              :     &dec_csr_rdaddr_d[2]);
+     156              : 
+     157              : assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[2]
+     158              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     159              : 
+     160              : assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     161              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     162              :     &!dec_csr_rdaddr_d[1]);
+     163              : 
+     164              : assign csr_dmst = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
+     165              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     166              : 
+     167              : assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     168              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
+     169              : 
+     170              : assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     171              :     &dec_csr_rdaddr_d[3]);
+     172              : 
+     173              : assign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     174              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     175              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     176              : 
+     177              : assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     178              :     &dec_csr_rdaddr_d[0]);
+     179              : 
+     180              : assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     181              :     &dec_csr_rdaddr_d[2]);
+     182              : 
+     183              : assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     184              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     185              : 
+     186              : assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     187              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);
+     188              : 
+     189              : assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     190              :     &!dec_csr_rdaddr_d[0]);
+     191              : 
+     192              : assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     193              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     194              : 
+     195              : assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     196              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
+     197              : 
+     198              : assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     199              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     200              : 
+     201              : assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     202              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);
+     203              : 
+     204              : assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     205              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);
+     206              : 
+     207              : assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
+     208              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     209              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     210              : 
+     211              : assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
+     212              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     213              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     214              : 
+     215              : assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
+     216              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     217              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     218              : 
+     219              : assign csr_mhpmc6 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]
+     220              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     221              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     222              : 
+     223              : assign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     224              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     225              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     226              : 
+     227              : assign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     228              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     229              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     230              : 
+     231              : assign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     232              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     233              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     234              : 
+     235              : assign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     236              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     237              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     238              : 
+     239              : assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     240              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     241              :     &dec_csr_rdaddr_d[0]);
+     242              : 
+     243              : assign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     244              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     245              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     246              : 
+     247              : assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     248              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     249              :     &dec_csr_rdaddr_d[0]);
+     250              : 
+     251              : assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     252              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
+     253              :     &!dec_csr_rdaddr_d[0]);
+     254              : 
+     255              : assign csr_mcounteren = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     256              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     257              : 
+     258              : assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+     259              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     260              :     &!dec_csr_rdaddr_d[0]);
+     261              : 
+     262              : assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     263              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
+     264              :     &!dec_csr_rdaddr_d[0]);
+     265              : 
+     266              : assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     267              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+     268              :     &dec_csr_rdaddr_d[0]);
+     269              : 
+     270              : assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
+     271              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     272              : 
+     273              : assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
+     274              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     275              : 
+     276              : assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     277              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
+     278              :     &!dec_csr_rdaddr_d[0]);
+     279              : 
+     280              : assign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]
+     281              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     282              : 
+     283              : assign csr_perfva  = 1'b0;
+     284              : 
+     285              : assign csr_perfvb  = 1'b0;
+     286              : 
+     287              : assign csr_perfvc  = 1'b0;
+     288              : 
+     289              : assign csr_perfvd  = 1'b0;
+     290              : 
+     291              : assign csr_perfve  = 1'b0;
+     292              : 
+     293              : assign csr_perfvf  = 1'b0;
+     294              : 
+     295              : assign csr_perfvg  = 1'b0;
+     296              : 
+     297              : assign csr_perfvh  = 1'b0;
+     298              : 
+     299              : assign csr_perfvi  = 1'b0;
+     300              : 
+     301              : assign csr_mpmc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     302              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     303              :     &dec_csr_rdaddr_d[1]);
+     304              : 
+     305              : assign csr_mcpc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]
+     306              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     307              : 
+     308              : assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]
+     309              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     310              : 
+     311              : assign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     312              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);
+     313              : 
+     314              : assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     315              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     316              : 
+     317              : assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     318              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);
+     319              : 
+     320              : assign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]
+     321              :     &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     322              : 
+     323              : assign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     324              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     325              : 
+     326              : assign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     327              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+     328              : 
+     329              : assign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     330              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     331              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     332              : 
+     333              : assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     334              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     335              : 
+     336              : assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
+     337              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     338              : 
+     339              : assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     340              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     341              : 
+     342              : assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
+     343              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     344              : 
+     345              : assign csr_menvcfg = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     346              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]);
+     347              : 
+     348              : assign csr_menvcfgh = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
+     349              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
+     350              : 
+     351              : assign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     352              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
+     353              : 
+     354              : assign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]
+     355              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);
+     356              : 
+     357              : assign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     358              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);
+     359              : 
+     360              : assign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
+     361              :     &dec_csr_rdaddr_d[4]);
+     362              : 
+     363              : assign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     364              :     &!dec_csr_rdaddr_d[4]);
+     365              : 
+     366              : assign csr_cyclel = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     367              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     368              : 
+     369              : assign csr_cycleh = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     370              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
+     371              : 
+     372              : assign csr_instretl = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     373              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     374              : 
+     375              : assign csr_instreth = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     376              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     377              : 
+     378              : assign csr_hpmc3 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     379              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     380              : 
+     381              : assign csr_hpmc4 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     382              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     383              : 
+     384              : assign csr_hpmc5 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     385              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     386              : 
+     387              : assign csr_hpmc6 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     388              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     389              : 
+     390              : assign csr_hpmc3h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     391              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     392              : 
+     393              : assign csr_hpmc4h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     394              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+     395              : 
+     396              : assign csr_hpmc5h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     397              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
+     398              : 
+     399              : assign csr_hpmc6h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     400              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     401              : 
+     402              : assign csr_mseccfgl = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]
+     403              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]);
+     404              : 
+     405              : assign csr_mseccfgh = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     406              :     &dec_csr_rdaddr_d[4]);
+     407              : 
+     408              : assign valid_only = (!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     409              :     &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (
+     410              :     !dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]
+     411              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
+     412              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[7]
+     413              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
+     414              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]
+     415              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]);
+     416              : 
+     417              : assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     418              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
+     419              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     420              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     421              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
+     422              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     423              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
+     424              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]
+     425              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
+     426              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
+     427              :     dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     428              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
+     429              : 
+     430              : assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
+     431              :     &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     432              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]
+     433              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]
+     434              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     435              :     &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]
+     436              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (
+     437              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]
+     438              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
+     439              :     dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[4]
+     440              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
+     441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
+     442              :     &dec_csr_rdaddr_d[0]);
+     443              : 
+     444           32 : logic legal;
+     445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     448              :     &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
+     449              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     450              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     451              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     452              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     453              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     454              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+     455              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     456              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     457              :     &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     458              :     !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     459              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     460              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     461              :     &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     462              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]
+     463              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     464              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]
+     465              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     466              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     467              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
+     468              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     469              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (
+     470              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     471              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     472              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     473              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     474              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     475              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     476              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     477              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (
+     478              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]
+     479              :     &!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     480              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+     481              :     &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     482              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     483              :     &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     484              :     &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+     485              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]
+     486              :     &!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     487              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     488              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
+     489              :     &dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]
+     490              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     491              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     492              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     493              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     494              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
+     495              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     496              :     &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     497              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
+     498              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     499              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     500              :     &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (
+     501              :     dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     502              :     &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     503              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
+     504              :     &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
+     505              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     506              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     507              :     &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]
+     508              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]
+     509              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+     510              :     &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (
+     511              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     512              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]
+     513              :     &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     514              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     515              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     516              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]
+     517              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     518              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     519              :     &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]
+     520              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]
+     521              :     &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
+     522              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
+     523              :     !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     524              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     525              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[9]
+     526              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
+     527              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]
+     528              :     &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
+     529              :     &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     530              :     &!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     531              :     &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+     532              :     &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     533              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     534              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]
+     535              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]
+     536              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
+     537              :     &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (
+     538              :     !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     539              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     540              :     &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (
+     541              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     542              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     543              :     &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     544              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     545              :     &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]
+     546              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     547              :     &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (
+     548              :     dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
+     549              :     &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
+     550              :     &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]
+     551              :     &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]
+     552              :     &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]
+     553              :     &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]
+     554              :     &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);
+     555              : 
+        

+

+
+
+
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_decode_ctl.sv.html
index a7bb5beca0b..5531e1bc81e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89       594670 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91         2414 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91         2833 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           48 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_gpr_ctl.sv.html
index 7f4684c31cf..0734e64fdda 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_ib_ctl.sv.html
index e190451d78c..22a67e20c57 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_pmp_ctl.sv.html
index e32acb2bb86..2269c7d1bfb 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.9%
+    
+        21.2%
     
     
         7
     
     
-        32
+        33
     
 
             
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_tlu_ctl.sv.html
index 9981b2ded24..1c5a2686223 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.9%
+    
+        28.5%
     
     
-        104
+        107
     
     
-        360
+        375
     
 
             
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183         2414 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183         2833 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           48 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186          352 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -586,7 +586,7 @@
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
      484           20 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485       272116 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     485       273938 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_trigger.sv.html
index a89693d2813..90d56b9b474 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dma_ctrl.sv.html
index 62bdfbddaec..aeebd30c9ea 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu.sv.html
index a9afc3190a4..b3085484081 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52        76204 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53         3768 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54           24 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55         2414 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55         2833 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57       646786 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_alu_ctl.sv.html
index 785acbbcc35..2f9c6650cc1 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30       776740 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32           24 :    input  logic                  csr_ren_in,         // CSR select
-      33         2414 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33         2833 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        84044 :    input  logic signed [31:0]    a_in,               // A operand
       35       205340 :    input  logic        [31:0]    b_in,               // B operand
       36           24 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_div_ctl.sv.html
index f48d08394ff..d5f6890771b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_mul_ctl.sv.html
index 0d1372a964d..79428c9af1a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu.sv.html
index 38caeb320e0..3e2656ecedf 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_aln_ctl.sv.html
index 157f4eeda71..0f2b10f7668 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_bp_ctl.sv.html
index b888ba6be53..042be52a431 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_compress_ctl.sv.html
index a502151cadb..c0c653c29fb 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ic_mem.sv.html
index 31e090247ee..7116d27896e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_iccm_mem.sv.html
index a34fc393d09..a203f9231f0 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ifc_ctl.sv.html
index f28854949ac..94929ddbe23 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_mem_ctl.sv.html
index 10322bd7d28..c3d427799ca 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lib.sv.html
index 10db9b5afa9..b3670645c73 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu.sv.html
index aa0fcf102ab..9740823c798 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_addrcheck.sv.html
index da6a4f6a895..d6338c4be7b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_buffer.sv.html
index 2101c559677..514ccd82c97 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_intf.sv.html
index aef384f3221..ca64d9f80a4 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_clkdomain.sv.html
index faf7b74897d..76beb23aaf8 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_ctl.sv.html
index 2bfee5e87ef..b0eb91e2ae2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_mem.sv.html
index e1ee58e0241..8f40b7d7da9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_ecc.sv.html
index aeddeb959d4..8a9fb4f95da 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_lsc_ctl.sv.html
index 5f186225b27..74989fa776b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_stbuf.sv.html
index 7579ef4be4d..ad56c1be3e7 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_trigger.sv.html
index 1c7ddab7d91..f0a55324673 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem.sv.html
index 5ceab1a367d..1079ed72c98 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem_if.sv.html
index 2303cd9d3a0..ec431e46140 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_pic_ctrl.sv.html
index 3e009ababd1..398bcd65f3f 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_pmp.sv.html
index 547bbb2e18a..a46ade18ffb 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.0%
+    
+        35.0%
     
     
         7
     
     
-        14
+        20
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            9 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            9 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154           12 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155           12 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            9 :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164           18 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer.sv.html
index 249a76ef97b..22db58cc928 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        33.2%
+    
+        33.0%
     
     
         208
     
     
-        627
+        631
     
 
             
@@ -712,7 +712,7 @@
      608         2940 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610           24 :    logic        dec_csr_ren_d;
-     611         2414 :    logic [31:0] dec_csr_rddata_d;
+     611         2833 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer_wrapper.sv.html
index ae1de838082..c74a84aed4e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark/index_mem_lib.sv.html
index 5471f4e919e..6d784da22b6 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_cmark/index_rvjtag_tap.v.html
index cb48f17117a..a5ed4a09003 100644
--- a/html/main/coverage_dashboard/all_axi_cmark/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index.html
index 06853be6d1c..df5396a9000 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        44.9%
+    
+        45.2%
     
     
-        2324
+        2320
     
     
-        5178
+        5131
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    26.3%
+                    26.5%
                 
             
 
             
                 335
                 /
-                1275
+                1265
             
         
             
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    44.1%
+                    44.7%
                 
             
 
             
-                444
+                441
                 /
-                1007
+                987
             
         
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    6.9%
+                    7.1%
                 
             
 
             
-                7
+                6
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design.html
index 1fb0090c742..366b7e97de8 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        26.3%
+    
+        26.5%
     
     
         335
     
     
-        1275
+        1265
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    35.0%
+                    50.0%
                 
             
 
             
                 7
                 /
-                20
+                14
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    30.1%
+                    30.3%
                 
             
 
             
                 190
                 /
-                631
+                627
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html
index 4064681a393..024e6e29606 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html
index 1ff1b838bd0..08446dadf71 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        44.1%
+    
+        44.7%
     
     
-        444
+        441
     
     
-        1007
+        987
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    46.3%
+                    47.0%
                 
             
 
             
                 119
                 /
-                257
+                253
             
         
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.2%
+                    21.9%
                 
             
 
             
                 7
                 /
-                33
+                32
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    28.0%
+                    28.3%
                 
             
 
             
-                105
+                102
                 /
-                375
+                360
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html
index c55e35547b3..e896a2469f0 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html
index 6888870bb53..d61835188e8 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html
index 9a055f444db..87372c771cd 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_include.html
index 2204b64139c..d5ea1a4ae5d 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        6.9%
+    
+        7.1%
     
     
-        7
+        6
     
     
-        101
+        84
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_mu.svh
+            
+                el2_dec_csr_equ_m.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    6.9%
+                    7.1%
                 
             
 
             
-                7
+                6
                 /
-                101
+                84
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html
index cb9d06090fe..76aea1ae754 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html
index b52de3fcae5..e4cb1d0fd85 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_beh_lib.sv.html
index 5f576142dc5..ad7eb1f51ef 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_jtag_to_core_sync.v.html
index 48178b58974..39e50d51537 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_mux.v.html
index 5c3088c4881..f24a2c470c2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_wrapper.v.html
index abf19d4026c..03d98482534 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dbg.sv.html
index fdf556b3f43..5a3b516ca34 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec.sv.html
index 092fad9f798..d514a1b07f2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        46.3%
+    
+        47.0%
     
     
         119
     
     
-        257
+        253
     
 
             
@@ -354,7 +354,7 @@
      250         6908 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            8 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253         1176 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253          592 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255          344 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256          344 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_csr_equ_m.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_csr_equ_m.svh.html
rename to html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_csr_equ_m.svh.html
index 3756d004852..8243b3b815a 100644
--- a/html/main/coverage_dashboard/all_ahb_cmark_iccm/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    ahb_cmark_iccm
+                    axi_cmark_dccm
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_decode_ctl.sv.html
index 64331e38e5f..ee0e434702a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89       190020 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91         1176 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91          592 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_gpr_ctl.sv.html
index a4fd4c77b59..74653e751ce 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_ib_ctl.sv.html
index eaa5927cf98..1957eb6881a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_pmp_ctl.sv.html
index 4a64dfb5b86..e0c2eb1058c 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.2%
+    
+        21.9%
     
     
         7
     
     
-        33
+        32
     
 
             
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_tlu_ctl.sv.html
index 7aa32cbd259..3a7e6fb5fbb 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        28.0%
+    
+        28.3%
     
     
-        105
+        102
     
     
-        375
+        360
     
 
             
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183         1176 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183          592 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186          172 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -379,7 +379,7 @@
      275            0 :    logic wr_mcounteren_r;
      276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277            0 :    logic wr_mseccfg_r;
-     278            4 :    logic [2:0] mseccfg_ns;
+     278            2 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -391,7 +391,7 @@
      287              : `ifdef RV_USER_MODE
      288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484           10 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485       137900 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484            5 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485        68950 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_trigger.sv.html
index 9a9910d8167..489a311686b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dma_ctrl.sv.html
index 31003d9bab3..2d1674f9dcb 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu.sv.html
index a8801c4d802..18032b3c42f 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            8 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55         1176 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55          592 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57       210432 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_alu_ctl.sv.html
index e873d9a28d9..1723b228f16 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30       235890 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            8 :    input  logic                  csr_ren_in,         // CSR select
-      33         1176 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33          592 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        26480 :    input  logic signed [31:0]    a_in,               // A operand
       35        65376 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_div_ctl.sv.html
index 6eb77e3f9d6..7ea1848785a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_mul_ctl.sv.html
index d34648d14b5..65619381d21 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu.sv.html
index f715d27e744..06f2f8898db 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_aln_ctl.sv.html
index ca43a0b47a0..066566b86ed 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_bp_ctl.sv.html
index 039f3c7f19a..51346795df0 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_compress_ctl.sv.html
index a1d19c06cc9..f8aa83d73f3 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ic_mem.sv.html
index 244d137816d..471df71268e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_iccm_mem.sv.html
index 469423aea4b..669dd1712d1 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html
index 008c766ac44..3f104855bca 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_mem_ctl.sv.html
index b1e60b59d21..2af965739e0 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lib.sv.html
index 058752187ba..795ac55d8f1 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu.sv.html
index c13a8f65876..e8560bb2bf9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_addrcheck.sv.html
index ff338938f7a..eca3ea6d690 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_buffer.sv.html
index adb3f4bd0d3..1c31041e370 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_intf.sv.html
index 7f97b584a40..88e44f29ec0 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_clkdomain.sv.html
index 17ce6b894ce..f3ab14f89c1 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html
index 205ad7fa638..59287e79071 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_mem.sv.html
index 53bdc852f64..0abc26d5c81 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_ecc.sv.html
index 3a0028e32e7..c5fb0651d57 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html
index fea01055d8b..876040cbdb2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_stbuf.sv.html
index 29f3bc959cf..33de69b2b53 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_trigger.sv.html
index 678dae0057d..71356c008ad 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem.sv.html
index eebdc50ddb1..d04f1b341d2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem_if.sv.html
index 1224782f17c..d7ebd235e44 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pic_ctrl.sv.html
index 7f1d7259abc..cfe595f624e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pmp.sv.html
index f4fab55b060..920ca74c71c 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        35.0%
+    
+        50.0%
     
     
         7
     
     
-        20
+        14
     
 
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer.sv.html
index ab3b3879034..27a659d721b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        30.1%
+    
+        30.3%
     
     
         190
     
     
-        631
+        627
     
 
             
@@ -712,7 +712,7 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            8 :    logic        dec_csr_ren_d;
-     611         1176 :    logic [31:0] dec_csr_rddata_d;
+     611          592 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer_wrapper.sv.html
index 637a8e2c3c5..1dc46d93307 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_mem_lib.sv.html
index 9fe6cf62d55..df370b2b64c 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_rvjtag_tap.v.html
index 7449df03abe..d13383e25b9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_dccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_dccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index.html
index 0ec00df332e..299d22dce22 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        67.4%
+    
+        67.5%
     
     
-        617
+        618
     
     
-        915
+        916
     
 
       
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    51.4%
+                    52.1%
                 
             
 
             
-                36
+                37
                 /
-                70
+                71
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design.html
index 6c413ce9af1..97f1165d55f 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        51.4%
+    
+        52.1%
     
     
-        36
+        37
     
     
-        70
+        71
     
 
       
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    39.2%
+                    40.4%
                 
             
 
             
-                20
+                21
                 /
-                51
+                52
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html
index fae7679e219..4d1593fa93b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html
index 9101403c5a7..c61ee4ec9b2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html
index 7625029d7be..9d186cd7c5b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html
index 823f904197e..9cb95383155 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html
index 1b3e5a837c8..2e165896e93 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_include.html
index 54b7f79501f..64e2986f3c3 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html
index 7346bd946ce..06db2c6a29d 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html
index b3455166afe..6202d12bed5 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_beh_lib.sv.html
index 0a193416161..33d3638a553 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_jtag_to_core_sync.v.html
index fe2bf0595fb..917c91a6766 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_mux.v.html
index b84b8b7ff2e..c68777f00ec 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_wrapper.v.html
index 97eafc04854..162c7d7cdae 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dbg.sv.html
index 661bb126040..a755b50f2ba 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec.sv.html
index bfa4a2b8a6a..a7d9eafc20a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -354,7 +354,7 @@
      250         2824 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            8 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253         1234 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253          619 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255           48 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256           48 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html
index 12a17198f81..7e8facd5ef1 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -107,11 +107,11 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           18 : logic csr_mstatus;
-       7            4 : logic csr_mtvec;
+       6            9 : logic csr_mstatus;
+       7            2 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
-      10            8 : logic csr_mcyclel;
+      10            4 : logic csr_mcyclel;
       11            0 : logic csr_mcycleh;
       12            0 : logic csr_minstretl;
       13            0 : logic csr_minstreth;
@@ -120,7 +120,7 @@
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            4 : logic csr_mrac;
+      19            2 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -185,7 +185,7 @@
       81            0 : logic csr_pmpaddr16;
       82            0 : logic csr_pmpaddr32;
       83            0 : logic csr_pmpaddr48;
-      84           18 : logic csr_cyclel;
+      84            9 : logic csr_cyclel;
       85            0 : logic csr_cycleh;
       86            0 : logic csr_instretl;
       87            0 : logic csr_instreth;
@@ -201,7 +201,7 @@
       97            0 : logic csr_mseccfgh;
       98            0 : logic valid_only;
       99            0 : logic presync;
-     100           10 : logic postsync;
+     100            5 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444           16 : logic legal;
+     444            8 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_decode_ctl.sv.html
index f04dca266f9..9939a424bef 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89       214698 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91         1234 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91          619 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_gpr_ctl.sv.html
index c6063e9422b..c8e6aa9a87f 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_ib_ctl.sv.html
index 919a86b1137..d205f3ad3fe 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_pmp_ctl.sv.html
index 7dc3d6a8bbb..78540340fb3 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_tlu_ctl.sv.html
index f94a8734bd2..a2c47e8bfa9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183         1234 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183          619 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186            8 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -379,7 +379,7 @@
      275            0 :    logic wr_mcounteren_r;
      276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277            0 :    logic wr_mseccfg_r;
-     278            4 :    logic [2:0] mseccfg_ns;
+     278            2 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -391,7 +391,7 @@
      287              : `ifdef RV_USER_MODE
      288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484           10 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485       134216 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484            5 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485        67108 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_trigger.sv.html
index 9d52d8fcfa9..6c23484c278 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dma_ctrl.sv.html
index 83db16dd028..bd862dd7a56 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu.sv.html
index 75bd2554201..1b202adc40c 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            8 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55         1234 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55          619 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57       226030 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_alu_ctl.sv.html
index 86977911b20..c05c1196b96 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30       253544 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            8 :    input  logic                  csr_ren_in,         // CSR select
-      33         1234 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33          619 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        30212 :    input  logic signed [31:0]    a_in,               // A operand
       35        73888 :    input  logic        [31:0]    b_in,               // B operand
       36            4 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_div_ctl.sv.html
index 8605af2f559..16a858883d2 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_mul_ctl.sv.html
index 3d4f06b100e..164825811ec 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu.sv.html
index 8e92fcc8c60..45d27649caf 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_aln_ctl.sv.html
index 668f4715d51..f83567fe0e9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_bp_ctl.sv.html
index 6535250da50..fe7af04d36a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_compress_ctl.sv.html
index 6546e86b8ae..fa073afb2d9 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ic_mem.sv.html
index ac4adc285a9..87fda948d1f 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_iccm_mem.sv.html
index e6549f57637..3443af17a61 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html
index 02d28c5f41d..431b0785d96 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_mem_ctl.sv.html
index beb6200e785..8878c7696d7 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lib.sv.html
index e8e4b856841..d91b33da92e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu.sv.html
index a5dc3fc0050..ac9c775d974 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_addrcheck.sv.html
index dc45a6a8746..7b8072691a6 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_buffer.sv.html
index 96e04ff26d7..2796d16d5da 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_intf.sv.html
index e63f39ddae3..a435bfea6d6 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_clkdomain.sv.html
index 498efe793f2..917ac9602da 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html
index c65a5a9c03b..29b8f57d476 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_mem.sv.html
index 33017a0e740..08865ef3474 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_ecc.sv.html
index d17ec739a2f..8fd7647c68a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html
index 35b74d359a1..a1192be7103 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_stbuf.sv.html
index 52f9ac3cae6..88c18a66b5c 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_trigger.sv.html
index 5a731f0ae45..06b69238615 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem.sv.html
index 20ef3f3ba57..92faf1e827a 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem_if.sv.html
index 8af39d45a9d..ae8b0934d2b 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pic_ctrl.sv.html
index 964226f6407..650480216d6 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pmp.sv.html
index 088e0915f8e..7c5e9ca649e 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        39.2%
+    
+        40.4%
     
     
-        20
+        21
     
     
-        51
+        52
     
 
             
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer.sv.html
index dad5fb93ffa..f334b1c111d 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -712,7 +712,7 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            8 :    logic        dec_csr_ren_d;
-     611         1234 :    logic [31:0] dec_csr_rddata_d;
+     611          619 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer_wrapper.sv.html
index 8ea3da71e79..6d2d786e593 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_mem_lib.sv.html
index 2fc6a6f71a2..e9e31afb529 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_rvjtag_tap.v.html
index 0a83228287e..0e2c4489b19 100644
--- a/html/main/coverage_dashboard/all_axi_cmark_iccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_cmark_iccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index.html b/html/main/coverage_dashboard/all_axi_csr_access/index.html
index 7609e42b3d3..9ac83898030 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design.html
index dcb8b186af5..7b6bd423f49 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dbg.html
index d92edabdac6..80dbab4bf5b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dec.html
index ccdc47b375a..62abd57c822 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dmi.html
index 774f45f6895..76e6cc59a1b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_exu.html
index 50e0bb60f8a..6ad646047ce 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_ifu.html
index 70675b81f6e..6819084b398 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_include.html
index 6a9c675295e..c2e83594cf3 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lib.html
index e842da14363..02cc8d95edb 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lsu.html
index 2984c029710..aa801cacff9 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_beh_lib.sv.html
index fc4f820d309..342ca1d892e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_jtag_to_core_sync.v.html
index c911ab7bb95..23a53227d09 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_mux.v.html
index 3956251f13d..629ae3f8f48 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_wrapper.v.html
index 0354f899c09..e702ae63dae 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dbg.sv.html
index 4110ecfbc11..c936e1ab78f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec.sv.html
index 07fd6cd3b6f..bb921eb2fa5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_csr_equ_mu.svh.html
index e3d14dbf919..df13090f533 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_decode_ctl.sv.html
index 231f903577d..ed38e562047 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_gpr_ctl.sv.html
index 3783ec33cbb..f47668309a2 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_ib_ctl.sv.html
index a82301f8a6a..4945eaf6962 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_pmp_ctl.sv.html
index 2a90ab22a01..a8ce1ea068f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_tlu_ctl.sv.html
index 147d478f1ac..bfa0affcbca 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_trigger.sv.html
index e1b357b704e..ca0afcd52ca 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dma_ctrl.sv.html
index 63d4de3556f..3f1adae4dd7 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu.sv.html
index 73a076e254e..0693570fbae 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_alu_ctl.sv.html
index 4df97db6477..1bc86ef01c8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_div_ctl.sv.html
index f665acea38d..24645f1e741 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_mul_ctl.sv.html
index b352f895ad5..212618607c6 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu.sv.html
index e92708fe171..21c99c1c5bb 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_aln_ctl.sv.html
index 327e8006441..47b11551471 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_bp_ctl.sv.html
index 1adabeed89e..6d266356ad9 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_compress_ctl.sv.html
index a1b39632b6d..651277f1aaf 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ic_mem.sv.html
index 3f8acae69d7..c5796ce9dbd 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_iccm_mem.sv.html
index 367876638a4..62a3d154f50 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ifc_ctl.sv.html
index df55e268bf5..36f9ea1ae4f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_mem_ctl.sv.html
index 08d12fd3e11..c5724f15f79 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lib.sv.html
index 5ec6ae58c60..94aa9eb128d 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu.sv.html
index bbb2fdacd76..92f74d56dd9 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_addrcheck.sv.html
index 209aeb82ac7..d48d241e591 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_buffer.sv.html
index 3d70452d815..8e33cdd77e8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_intf.sv.html
index 3d257198ebd..115ffe4f2dd 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_clkdomain.sv.html
index f93cc39a1ee..d15a7c42483 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_ctl.sv.html
index a952b03990f..cb5485bea34 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_mem.sv.html
index 1eeaaa59b81..ecafacab682 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_ecc.sv.html
index 5391e566e1a..c532c5e4772 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_lsc_ctl.sv.html
index 1253f347ed4..26ad9a7c6a3 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_stbuf.sv.html
index 4271705e495..af1635590b5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_trigger.sv.html
index 51eda06506b..2a6b97dfbe0 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem.sv.html
index 934cc1db083..cef8fd2a72f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem_if.sv.html
index 5e8ead1794b..179d9fe97d6 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pic_ctrl.sv.html
index 87483feda7c..fb4744b2239 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pmp.sv.html
index 78f12c8acea..8b0a6973c03 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer.sv.html
index b3af442a909..2a5d7bab9fe 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer_wrapper.sv.html
index 4d14a8a214e..0f3dc732763 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_access/index_mem_lib.sv.html
index 1d546c16934..5099779db42 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_access/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_csr_access/index_rvjtag_tap.v.html
index 7aa1564655d..63625b794cb 100644
--- a/html/main/coverage_dashboard/all_axi_csr_access/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_access/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index.html b/html/main/coverage_dashboard/all_axi_csr_misa/index.html
index 05c860aabb4..936f4dfe598 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        68.0%
+    
+        67.5%
     
     
-        623
+        618
     
     
-        916
+        915
     
 
       
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    52.1%
+                    51.4%
                 
             
 
             
-                37
+                36
                 /
-                71
+                70
             
         
     
@@ -507,19 +507,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    74.8%
+                    72.8%
                 
             
 
             
-                154
+                150
                 /
                 206
             
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design.html
index b63257a7750..dd03c614b87 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        52.1%
+    
+        51.4%
     
     
-        37
+        36
     
     
-        71
+        70
     
 
       
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.4%
+                    39.2%
                 
             
 
             
-                21
+                20
                 /
-                52
+                51
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dbg.html
index 62ada34ac92..d97697cc7f6 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dec.html
index 3d9ee8113c3..bca160500d3 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dmi.html
index 2783567dbbc..250b584b4fd 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_exu.html
index dd7913c33a9..f94b1e80761 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_ifu.html
index b8a575a99db..c8d7e3e4d54 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        74.8%
+    
+        72.8%
     
     
-        154
+        150
     
     
         206
@@ -643,19 +643,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    53.6%
+                    50.0%
                 
             
 
             
-                59
+                55
                 /
                 110
             
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_include.html
index bf8acaedd90..34b317bd1fd 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lib.html
index 2fff5e16e85..a574474ee13 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lsu.html
index 7e1deacf369..226a72c536a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_beh_lib.sv.html
index 6683268cab7..a22a21e885f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22        17932 :      input logic           clk,
+      22        14934 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38         8964 :    always_ff @(posedge clk or negedge rst_l) begin
+      38         5966 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42         8954 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42         5956 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52            0 :      input logic             en,
-      53        17932 :      input logic           clk,
+      53        14934 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -174,7 +174,7 @@
       70           68 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73        71728 :      input logic           clk,
+      73        59736 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -192,13 +192,13 @@
       88              : // _fpga versions
       89              : module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
       90              :    (
-      91         2656 :      input logic [WIDTH-1:0] din,
+      91         2080 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94        35864 :      input logic           rawclk,
+      94        29868 :      input logic           rawclk,
       95            4 :      input logic           rst_l,
       96              : 
-      97         2654 :      output logic [WIDTH-1:0] dout
+      97         2079 :      output logic [WIDTH-1:0] dout
       98              :      );
       99              : 
      100              : if (SHORT == 1) begin : genblock
@@ -220,7 +220,7 @@
      116            0 :      input logic             en,
      117            0 :      input logic           clk,
      118            4 :      input logic           clken,
-     119        35864 :      input logic           rawclk,
+     119        29868 :      input logic           rawclk,
      120            4 :      input logic           rst_l,
      121              : 
      122            0 :      output logic [WIDTH-1:0] dout
@@ -247,7 +247,7 @@
      143            0 :      input logic             clear,
      144            0 :      input logic             clk,
      145            6 :      input logic             clken,
-     146        53796 :      input logic             rawclk,
+     146        44802 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
      149            0 :      output logic [WIDTH-1:0] dout
@@ -271,7 +271,7 @@
      167              :    (
      168          432 :      input  logic [WIDTH-1:0] din,
      169            0 :      input  logic           en,
-     170        17932 :      input  logic           clk,
+     170        14934 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -309,12 +309,12 @@
      205              : 
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
-     208          264 :      input  logic [WIDTH-1:0] din,
-     209       215184 :      input  logic             clk,
+     208          149 :      input  logic [WIDTH-1:0] din,
+     209       179208 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
-     211        20644 :      input  logic             en,
+     211        17199 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
-     213          264 :      output logic [WIDTH-1:0] dout
+     213          149 :      output logic [WIDTH-1:0] dout
      214              :      );
      215              : 
      216              : 
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            0 :      input  logic [WIDTH-1:0] din,
-     242        17932 :      input  logic             clk,
+     242        14934 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -398,9 +398,9 @@
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
      296            0 :      input  logic [WIDTH-1:0] din,
-     297        17932 :      input  logic             clk,
+     297        14934 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
-     299         2764 :      input  logic             en,
+     299         2305 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
      301            0 :      output logic [WIDTH-1:0] dout
      302              :      );
@@ -442,14 +442,14 @@
      338              :    (
      339            0 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341        17932 :      input  logic           clk,
+     341        14934 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
      344            0 :      output logic [WIDTH-1:0] dout
      345              :      );
      346              : 
      347            0 :    logic                      l1clk;
-     348          204 :    logic                      en;
+     348          190 :    logic                      en;
      349              : 
      350              : 
      351              : 
@@ -519,7 +519,7 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418        17932 :      input  logic                 clk,
+     418        14934 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
      420            0 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434       555892 :      input  logic                 rawclk,
+     434       462954 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -560,7 +560,7 @@
      456           64 :    logic                cout;
      457           64 :    logic                sign;
      458              : 
-     459          368 :    logic [31:12]        rs1_inc;
+     459          252 :    logic [31:12]        rs1_inc;
      460          122 :    logic [31:12]        rs1_dec;
      461              : 
      462              :    assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480           16 :     input [31:1] pc,
-     481          740 :     input [12:1] offset,
+     481          667 :     input [12:1] offset,
      482              : 
-     483          264 :     output [31:1] dout
+     483          149 :     output [31:1] dout
      484              :     );
      485              : 
-     486         1018 :    logic          cout;
-     487         1286 :    logic          sign;
+     486          787 :    logic          cout;
+     487          940 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -805,7 +805,7 @@
      701              : 
      702              : module rvecc_encode_64  (
      703          436 :                       input [63:0] din,
-     704         1708 :                       output [6:0] ecc_out
+     704         1460 :                       output [6:0] ecc_out
      705              :                       );
      706              :   assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
      707              : 
@@ -896,10 +896,10 @@
      792              : 
      793              : module rvoclkhdr
      794              :   (
-     795        11178 :    input  logic en,
-     796       484164 :    input  logic clk,
+     795         9214 :    input  logic en,
+     796       403218 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798       484164 :    output logic l1clk
+     798       403218 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_jtag_to_core_sync.v.html
index 11d1058b869..17ed8ac0182 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32        17932 : input       clk,        // Core clock
+      32        14934 : input       clk,        // Core clock
       33              : 
       34            0 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35            0 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49         8964 : always @ ( posedge clk or negedge rst_n) begin
+      49         5966 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54         8960 :     else begin
-      55         8960 :         rden <= {rden[1:0], rd_en};
-      56         8960 :         wren <= {wren[1:0], wr_en};
+      54         5962 :     else begin
+      55         5962 :         rden <= {rden[1:0], rd_en};
+      56         5962 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_mux.v.html
index bb7f2b17af4..2f915b4b6fe 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_wrapper.v.html
index 384cb1283d5..c2220017cad 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36        17932 :   input              core_clk,            // Core clock                  
+      36        14934 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38            0 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39            0 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dbg.sv.html
index 25e8bfabb74..2876cf4073a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -140,7 +140,7 @@
       36            2 :    output logic                        dbg_core_rst_l,            // core reset from dm
       37              : 
       38              :    // inputs back from the core/dec
-      39            4 :    input logic [31:0]                  core_dbg_rddata,
+      39            8 :    input logic [31:0]                  core_dbg_rddata,
       40            0 :    input logic                         core_dbg_cmd_done,         // This will be treated like a valid signal
       41            0 :    input logic                         core_dbg_cmd_fail,         // Exception during command run
       42              : 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110        17932 :    input logic                         clk,
-     111        17932 :    input logic                         free_clk,
+     110        14934 :    input logic                         clk,
+     111        14934 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254            0 :    logic              dbg_free_clken;
-     255        17932 :    logic              dbg_free_clk;
+     255        14934 :    logic              dbg_free_clk;
      256              : 
      257            0 :    logic              sb_free_clken;
-     258        17932 :    logic              sb_free_clk;
+     258        14934 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474         8966 :             IDLE: begin
-     475         8966 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476         8966 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477         8966 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474         5968 :             IDLE: begin
+     475         5968 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476         5968 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477         5968 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604         8966 :             SBIDLE: begin
-     605         8966 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606         8966 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607         8966 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608         8966 :                      sbcs_sbbusy_din        = 1'b1;
-     609         8966 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610         8966 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604         5968 :             SBIDLE: begin
+     605         5968 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606         5968 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607         5968 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608         5968 :                      sbcs_sbbusy_din        = 1'b1;
+     609         5968 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610         5968 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec.sv.html
index 35dca13db62..dae2429a92e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,19 +136,19 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35        17932 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36        17932 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37        17932 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38        17932 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35        14934 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        14934 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37        14934 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38        14934 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
       42            0 :     output logic dec_extint_stall,  // Stall on external interrupt
       43              : 
-      44         2764 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
+      44         2306 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
       45            0 :     output logic dec_pause_state_cg, // to top for active state clock gating
       46              : 
-      47          496 :     output logic dec_tlu_core_empty,
+      47          494 :     output logic dec_tlu_core_empty,
       48              : 
       49            2 :     input logic        rst_l,   // reset, active low
       50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
@@ -174,8 +174,8 @@
       70            2 :     output logic mpc_debug_run_ack,   // Run ack
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
-      73          192 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74          494 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      73          178 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
+      74          377 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
       75          398 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
@@ -188,13 +188,13 @@
       84            8 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
       85            0 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
       86              : 
-      87          668 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
+      87          553 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
       88            0 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
       89            0 :     input logic lsu_pmu_bus_error,         // D side bus error
       90           12 :     input logic lsu_pmu_bus_busy,          // D side bus busy
       91            0 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
       92          224 :     input logic lsu_pmu_load_external_m,   // D side bus load
-      93          484 :     input logic lsu_pmu_store_external_m,  // D side bus store
+      93          368 :     input logic lsu_pmu_store_external_m,  // D side bus store
       94            0 :     input logic dma_pmu_dccm_read,         // DMA DCCM read
       95            0 :     input logic dma_pmu_dccm_write,        // DMA DCCM write
       96            0 :     input logic dma_pmu_any_read,          // DMA read
@@ -203,13 +203,13 @@
       99            0 :     input logic [31:1] lsu_fir_addr,  // Fast int address
      100            0 :     input logic [ 1:0] lsu_fir_error, // Fast int lookup error
      101              : 
-     102         2764 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
-     103          170 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
-     104         2780 :     input logic ifu_pmu_ic_miss,        // icache miss
+     102         2306 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
+     103          158 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
+     104         2318 :     input logic ifu_pmu_ic_miss,        // icache miss
      105            0 :     input logic ifu_pmu_ic_hit,         // icache hit
      106            0 :     input logic ifu_pmu_bus_error,      // Instruction side bus error
-     107         2776 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
-     108         5554 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
+     107         2316 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
+     108         4633 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
      109              : 
      110            0 :     input logic ifu_ic_error_start,         // IC single bit error
      111            0 :     input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
@@ -228,11 +228,11 @@
      124            0 :     input logic ifu_i0_icaf_second,  // i0 has access fault on second 2B of 4B inst
      125            0 :     input logic ifu_i0_dbecc,        // icache/iccm double-bit error
      126              : 
-     127          572 :     input logic lsu_idle_any,  // lsu idle for halting
+     127          456 :     input logic lsu_idle_any,  // lsu idle for halting
      128              : 
      129          144 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
      130           32 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
-     131          218 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
+     131          202 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
      132            0 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
      133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
      134              : 
@@ -258,17 +258,17 @@
      154              : 
      155            0 :     input logic iccm_dma_sb_error,  // ICCM DMA single bit error
      156              : 
-     157          204 :     input logic exu_flush_final,  // slot0 flush
+     157          190 :     input logic exu_flush_final,  // slot0 flush
      158              : 
      159            2 :     input logic [31:1] exu_npc_r,  // next PC
      160              : 
-     161           88 :     input logic [31:0] exu_i0_result_x,  // alu result x
+     161           94 :     input logic [31:0] exu_i0_result_x,  // alu result x
      162              : 
      163              : 
-     164         2764 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
+     164         2306 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
      165           36 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166           10 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167         1788 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167         1322 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            2 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
@@ -290,7 +290,7 @@
      186              :     // Debug start
      187            0 :     input logic dbg_halt_req,        // DM requests a halt
      188            0 :     input logic dbg_resume_req,      // DM requests a resume
-     189         2780 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
+     189         2318 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
      190              : 
      191            0 :     output logic        dec_tlu_dbg_halted,        // Core is halted and ready for debug command
      192            0 :     output logic        dec_tlu_debug_mode,        // Core is in debug mode
@@ -303,7 +303,7 @@
      199              : 
      200            0 :     output logic dec_debug_wdata_rs1_d,  // insert debug write data into rs1 at decode
      201              : 
-     202            4 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
+     202            8 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
      203              : 
      204            0 :     output logic dec_dbg_cmd_done,  // abstract command is done
      205            0 :     output logic dec_dbg_cmd_fail,  // abstract command failed (illegal reg address)
@@ -313,40 +313,40 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212          346 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212          243 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215          470 :     input  logic       exu_i0_br_valid_r,        // valid
-     216          192 :     input  logic       exu_i0_br_mp_r,           // mispredict
+     215          355 :     input  logic       exu_i0_br_valid_r,        // valid
+     216          178 :     input  logic       exu_i0_br_mp_r,           // mispredict
      217          514 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
      219              :     // branch info from pipe1 for errors or counter updates
      220              : 
      221           84 :     input logic exu_i0_br_way_r,  // way hit or repl
      222              : 
-     223         2068 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
-     224         1080 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
-     225            4 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
-     226          268 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
+     223         1838 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
+     224          964 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
+     225            6 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
+     226          136 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228          272 :     output logic [31:0] dec_i0_immed_d,    // immediate data
-     229          112 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
+     228          198 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     229          100 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
-     233         2116 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234          768 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     233         1774 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
+     234          652 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
-     236          276 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
+     236          162 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
      238           10 :     output logic [31:1] dec_i0_pc_d,             // pc's at decode
      239            0 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
      240            0 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
      241              : 
-     242            4 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
+     242            8 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
      243              : 
      244          100 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
-     245         2066 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
+     245         1724 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
      246            0 :     output el2_mul_pkt_t mul_p,           // mul packet
      247            0 :     output el2_div_pkt_t div_p,           // div packet
      248            0 :     output logic         dec_div_cancel,  // cancel divide operation
@@ -354,7 +354,7 @@
      250           64 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            4 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253           16 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253            8 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256            4 :     output logic dec_tlu_flush_lower_wb,
@@ -362,7 +362,7 @@
      258            0 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      259            0 :     output logic dec_tlu_fence_i_r,  // flush is a fence_i rfnpc, flush icache
      260              : 
-     261          264 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
+     261          149 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
      262              : 
      263           84 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
      264              : 
@@ -372,22 +372,22 @@
      268            0 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
      269              : 
      270          144 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
-     271          218 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
+     271          202 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
      272           32 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
      273            0 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
      274              : 
      275            0 :     output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index,  // Fully associt btb error index
      276              : 
-     277          708 :     output logic dec_lsu_valid_raw_d,
+     277          592 :     output logic dec_lsu_valid_raw_d,
      278              : 
      279            0 :     output logic [31:0] dec_tlu_mrac_ff,  // CSR for memory region control
      280              : 
-     281         2764 :     output logic [1:0] dec_data_en,  // clock-gate control logic
-     282         2764 :     output logic [1:0] dec_ctl_en,
+     281         2305 :     output logic [1:0] dec_data_en,  // clock-gate control logic
+     282         2305 :     output logic [1:0] dec_ctl_en,
      283              : 
      284          240 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
      285              : 
-     286         2764 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
+     286         2304 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
      287              : 
      288              :     // PMP signals
      289            0 :     output el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
@@ -423,7 +423,7 @@
      319            0 :     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
      320            0 :     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
      321              : 
-     322         2764 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+     322         2304 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
      323            0 :     input  logic scan_mode               // Flop scan mode control
      324              : 
      325              : );
@@ -432,16 +432,16 @@
      328            0 :   logic dec_tlu_dec_clk_override;  // to and from dec blocks
      329            0 :   logic clk_override;
      330              : 
-     331         2764 :   logic dec_ib0_valid_d;
+     331         2306 :   logic dec_ib0_valid_d;
      332              : 
-     333         2764 :   logic dec_pmu_instr_decoded;
+     333         2306 :   logic dec_pmu_instr_decoded;
      334            0 :   logic dec_pmu_decode_stall;
      335            0 :   logic dec_pmu_presync_stall;
      336            0 :   logic dec_pmu_postsync_stall;
      337              : 
      338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
-     340          788 :   logic [4:0] dec_i0_rs1_d;
+     340          704 :   logic [4:0] dec_i0_rs1_d;
      341          640 :   logic [4:0] dec_i0_rs2_d;
      342              : 
      343           36 :   logic [31:0] dec_i0_instr_d;
@@ -450,11 +450,11 @@
      346            0 :   logic dec_tlu_pipelining_disable;
      347              : 
      348              : 
-     349          916 :   logic [4:0] dec_i0_waddr_r;
-     350         1520 :   logic dec_i0_wen_r;
-     351            4 :   logic [31:0] dec_i0_wdata_r;
+     349          818 :   logic [4:0] dec_i0_waddr_r;
+     350         1292 :   logic dec_i0_wen_r;
+     351            8 :   logic [31:0] dec_i0_wdata_r;
      352            0 :   logic dec_csr_wen_r;  // csr write enable at wb
-     353          640 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
+     353          540 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
      354            0 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
      355            0 :   logic [31:0] dec_csr_wrdata_r;  // csr write data at wb
      356              : 
@@ -467,7 +467,7 @@
      363              : 
      364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366         1788 :   logic dec_i0_pc4_d;
+     366         1322 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
      368            0 :   logic dec_tlu_postsync_d;
      369            0 :   logic dec_tlu_debug_stall;
@@ -485,13 +485,13 @@
      381            0 :   logic dec_tlu_flush_pause_r;
      382          144 :   el2_br_pkt_t dec_i0_brp;
      383           32 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
-     384          218 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
+     384          202 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
      385            0 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
      386            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
      387              : 
      388            2 :   logic [31:1] dec_tlu_i0_pc_r;
      389            0 :   logic dec_tlu_i0_kill_writeb_wb;
-     390         2764 :   logic dec_tlu_i0_valid_r;
+     390         2304 :   logic dec_tlu_i0_valid_r;
      391              : 
      392            0 :   logic dec_pause_state;
      393              : 
@@ -501,7 +501,7 @@
      397              : 
      398          220 :   logic [31:0] dec_i0_inst_wb;
      399            2 :   logic [31:1] dec_i0_pc_wb;
-     400         2764 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
+     400         2304 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
      401            0 :   logic [ 4:0] dec_tlu_exc_cause_wb1;
      402            0 :   logic [31:0] dec_tlu_mtval_wb1;
      403            0 :   logic        dec_tlu_i0_exc_valid_wb1;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_csr_equ_mu.svh.html
index 045f72411c1..8216c3bd504 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -102,12 +102,12 @@
 
 
            Line data    Source code

 
-       1            4 : logic csr_misa;
+       1            2 : logic csr_misa;
        2            0 : logic csr_mvendorid;
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6            6 : logic csr_mstatus;
+       6            3 : logic csr_mstatus;
        7            0 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
@@ -185,7 +185,7 @@
       81            0 : logic csr_pmpaddr16;
       82            0 : logic csr_pmpaddr32;
       83            0 : logic csr_pmpaddr48;
-      84            6 : logic csr_cyclel;
+      84            3 : logic csr_cyclel;
       85            0 : logic csr_cycleh;
       86            0 : logic csr_instretl;
       87            0 : logic csr_instreth;
@@ -201,7 +201,7 @@
       97            0 : logic csr_mseccfgh;
       98            0 : logic valid_only;
       99            0 : logic presync;
-     100            6 : logic postsync;
+     100            3 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444            4 : logic legal;
+     444            2 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_decode_ctl.sv.html
index 5a53741efbe..0fc1a825d85 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -170,11 +170,11 @@
       66              : 
       67          144 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
       68           32 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69          218 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      69          202 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
-      73          572 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
+      73          456 :    input logic lsu_idle_any,                          // lsu idle: if fence instr & ~lsu_idle then stall decode
       74              : 
       75            8 :    input logic lsu_load_stall_any,                    // stall any load at decode
       76            8 :    input logic lsu_store_stall_any,                   // stall any store at decode
@@ -190,9 +190,9 @@
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
       87            0 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89         1788 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89         1322 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91           16 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91            8 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92            4 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
@@ -200,55 +200,55 @@
       96            0 :    input logic [31:0] lsu_result_m,                   // load result
       97            0 :    input logic [31:0] lsu_result_corr_r,              // load result - corrected data for writing gpr's, not for bypassing
       98              : 
-      99          204 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
+      99          190 :    input logic exu_flush_final,                       // lower flush or i0 flush at X or D
      100              : 
      101            2 :    input logic [31:1] exu_i0_pc_x,                    // pcs at e1
      102              : 
      103           36 :    input logic [31:0] dec_i0_instr_d,                 // inst at decode
      104              : 
-     105         2764 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
+     105         2306 :    input logic  dec_ib0_valid_d,                      // inst valid at decode
      106              : 
-     107           88 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
+     107           94 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109        17932 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110        17932 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111        17932 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109        14934 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110        14934 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111        14934 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
      115              : 
      116              : 
      117              : 
-     118         2068 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
-     119         1080 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
+     118         1838 :    output logic        dec_i0_rs1_en_d,               // rs1 enable at decode
+     119          964 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
-     121          788 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
+     121          704 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
      122          640 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124          272 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124          198 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
-     127          112 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
+     127          100 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
      128              : 
      129            0 :    output el2_alu_pkt_t i0_ap,                       // alu packets
      130              : 
-     131         2764 :    output logic        dec_i0_decode_d,               // i0 decode
+     131         2306 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
-     133         2116 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134          768 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     133         1774 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
+     134          652 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
-     136          916 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137         1520 :    output logic        dec_i0_wen_r,                  // i0 write enable
-     138            4 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
+     136          818 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
+     137         1292 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     138            8 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
-     140          276 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
+     140          162 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
      141              : 
      142            0 :    output logic [3:0]    dec_i0_rs1_bypass_en_d,      // i0 rs1 bypass enable
      143            0 :    output logic [3:0]    dec_i0_rs2_bypass_en_d,      // i0 rs2 bypass enable
-     144            4 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
+     144            8 :    output logic [31:0]   dec_i0_result_r,             // Result R-stage
      145              : 
      146          100 :    output el2_lsu_pkt_t    lsu_p,                    // load/store packet
-     147         2066 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
+     147         1724 :    output logic             dec_qual_lsu_d,           // LSU instruction at D.  Use to quiet LSU operands
      148              : 
      149            0 :    output el2_mul_pkt_t    mul_p,                    // multiply packet
      150              : 
@@ -256,7 +256,7 @@
      152            0 :    output logic [4:0]       div_waddr_wb,             // DIV write address to GPR
      153            0 :    output logic             dec_div_cancel,           // cancel the divide operation
      154              : 
-     155          708 :    output logic        dec_lsu_valid_raw_d,
+     155          592 :    output logic        dec_lsu_valid_raw_d,
      156           64 :    output logic [11:0] dec_lsu_offset_d,
      157              : 
      158            4 :    output logic        dec_csr_ren_d,                 // valid csr decode
@@ -264,31 +264,31 @@
      160            4 :    output logic        dec_csr_any_unq_d,             // valid csr - for csr legal
      161            4 :    output logic [11:0] dec_csr_rdaddr_d,              // read address for csr
      162            0 :    output logic        dec_csr_wen_r,                 // csr write enable at r
-     163          640 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
+     163          540 :    output logic [11:0] dec_csr_rdaddr_r,              // read address for csr
      164            0 :    output logic [11:0] dec_csr_wraddr_r,              // write address for csr
      165            0 :    output logic [31:0] dec_csr_wrdata_r,              // csr write data at r
      166            0 :    output logic        dec_csr_stall_int_ff,          // csr is mie/mstatus
      167              : 
-     168         2764 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
+     168         2304 :    output              dec_tlu_i0_valid_r,            // i0 valid inst at c
      169              : 
      170            0 :    output el2_trap_pkt_t   dec_tlu_packet_r,              // trap packet
      171              : 
      172            2 :    output logic [31:1] dec_tlu_i0_pc_r,               // i0 trap pc
      173              : 
      174            0 :    output logic [31:0] dec_illegal_inst,              // illegal inst
-     175          264 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
+     175          149 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
      177          144 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178          218 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     178          202 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
      179           32 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      183              : 
-     184         2764 :    output logic [1:0] dec_data_en,                    // clock-gating logic
-     185         2764 :    output logic [1:0] dec_ctl_en,
+     184         2305 :    output logic [1:0] dec_data_en,                    // clock-gating logic
+     185         2305 :    output logic [1:0] dec_ctl_en,
      186              : 
-     187         2764 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
+     187         2306 :    output logic       dec_pmu_instr_decoded,          // number of instructions decode this cycle encoded
      188            0 :    output logic       dec_pmu_decode_stall,           // decode is stalled
      189            0 :    output logic       dec_pmu_presync_stall,          // decode has presync stall
      190            0 :    output logic       dec_pmu_postsync_stall,         // decode has postsync stall
@@ -309,24 +309,24 @@
      205            0 :    el2_dec_pkt_t           i0_dp_raw, i0_dp;
      206              : 
      207           36 :    logic [31:0]        i0;
-     208         2764 :    logic               i0_valid_d;
+     208         2306 :    logic               i0_valid_d;
      209              : 
-     210            4 :    logic [31:0]        i0_result_r;
+     210            8 :    logic [31:0]        i0_result_r;
      211              : 
      212            8 :    logic [2:0]         i0_rs1bypass, i0_rs2bypass;
      213              : 
      214           36 :    logic               i0_jalimm20;
-     215          260 :    logic               i0_uiimm20;
+     215          146 :    logic               i0_uiimm20;
      216              : 
-     217          708 :    logic               lsu_decode_d;
-     218          272 :    logic [31:0]        i0_immed_d;
+     217          592 :    logic               lsu_decode_d;
+     218          198 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
      220           52 :    logic               i0_postsync;
      221              : 
      222            0 :    logic               postsync_stall;
      223            0 :    logic               ps_stall;
      224              : 
-     225         2764 :    logic               prior_inflight, prior_inflight_wb;
+     225         2304 :    logic               prior_inflight, prior_inflight_wb;
      226              : 
      227            0 :    logic               csr_clr_d, csr_set_d, csr_write_d;
      228              : 
@@ -351,14 +351,14 @@
      247            0 :    logic               i0_div_prior_div_stall;
      248            0 :    logic               nonblock_div_cancel;
      249              : 
-     250         2712 :    logic               i0_legal;
+     250         2254 :    logic               i0_legal;
      251            0 :    logic               shift_illegal;
      252            0 :    logic               illegal_inst_en;
      253            0 :    logic               illegal_lockout_in, illegal_lockout;
-     254         2764 :    logic               i0_legal_decode_d;
+     254         2306 :    logic               i0_legal_decode_d;
      255            0 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
-     257          720 :    logic [12:1]        last_br_immed_d;
+     257          502 :    logic [12:1]        last_br_immed_d;
      258            0 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
@@ -369,16 +369,16 @@
      265            8 :    logic               i0_load_stall_d;
      266            0 :    logic               i0_store_stall_d;
      267              : 
-     268          312 :    logic               i0_predict_nt, i0_predict_t;
+     268          208 :    logic               i0_predict_nt, i0_predict_t;
      269              : 
      270           44 :    logic               i0_notbr_error, i0_br_toffset_error;
      271            0 :    logic               i0_ret_error;
      272           52 :    logic               i0_br_error;
      273           52 :    logic               i0_br_error_all;
-     274          904 :    logic [11:0]        i0_br_offset;
+     274          674 :    logic [11:0]        i0_br_offset;
      275              : 
      276          232 :    logic [20:1]        i0_pcall_imm;                          // predicted jal's
-     277         2570 :    logic               i0_pcall_12b_offset;
+     277         2110 :    logic               i0_pcall_12b_offset;
      278           12 :    logic               i0_pcall_raw;
      279           12 :    logic               i0_pcall_case;
      280           12 :    logic               i0_pcall;
@@ -393,7 +393,7 @@
      289            8 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292          708 :    logic               i0_predict_br;
+     292          592 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301         1788 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301         1322 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303         1708 :    logic               i0_rd_en_d;
+     303         1482 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -414,14 +414,14 @@
      310              : 
      311            0 :    logic               i0_csr_write_only_d;
      312              : 
-     313         2764 :    logic               prior_inflight_x, prior_inflight_eff;
+     313         2305 :    logic               prior_inflight_x, prior_inflight_eff;
      314            4 :    logic               any_csr_d;
      315              : 
      316            0 :    logic               prior_csr_write;
      317              : 
-     318         2764 :    logic [3:0]        i0_pipe_en;
-     319         2764 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
-     320         2764 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
+     318         2304 :    logic [3:0]        i0_pipe_en;
+     319         2304 :    logic              i0_r_ctl_en,  i0_x_ctl_en,  i0_wb_ctl_en;
+     320         2304 :    logic              i0_x_data_en, i0_r_data_en, i0_wb_data_en;
      321              : 
      322            0 :    logic              debug_fence_i;
      323            0 :    logic              debug_fence;
@@ -436,16 +436,16 @@
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335          524 :    logic              i0_brp_valid;
+     335          408 :    logic              i0_brp_valid;
      336          132 :    logic              nonblock_load_cancel;
-     337          572 :    logic              lsu_idle;
+     337          456 :    logic              lsu_idle;
      338            0 :    logic              lsu_pmu_misaligned_r;
      339            4 :    logic              csr_ren_qual_d;
      340            4 :    logic              csr_read_x;
      341            8 :    logic              i0_block_d;
      342            0 :    logic              i0_block_raw_d;  // This is use to create the raw valid
      343            0 :    logic              ps_stall_in;
-     344          144 :    logic [31:0]       i0_result_x;
+     344          150 :    logic [31:0]       i0_result_x;
      345              : 
      346          224 :    el2_dest_pkt_t         d_d, x_d, r_d, wbd;
      347          224 :    el2_dest_pkt_t         x_d_in, r_d_in;
@@ -460,12 +460,12 @@
      356            8 :    logic i0_br_unpred;
      357              : 
      358          216 :    logic nonblock_load_valid_m_delay;
-     359         1708 :    logic i0_wen_r;
+     359         1480 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
      363              : 
-     364          204 :    logic flush_final_r;
+     364          190 :    logic flush_final_r;
      365              : 
      366            2 :    logic bitmanip_zbb_legal;
      367            2 :    logic bitmanip_zbs_legal;
@@ -514,10 +514,10 @@
      410              : 
      411            0 :    logic debug_fence_raw;
      412              : 
-     413            4 :    logic [31:0] i0_result_r_raw;
-     414            4 :    logic [31:0] i0_result_corr_r;
+     413            8 :    logic [31:0] i0_result_r_raw;
+     414            8 :    logic [31:0] i0_result_corr_r;
      415              : 
-     416          416 :    logic [12:1] last_br_immed_x;
+     416          345 :    logic [12:1] last_br_immed_x;
      417              : 
      418          240 :    logic [31:0]        i0_inst_d;
      419          220 :    logic [31:0]        i0_inst_x;
@@ -527,14 +527,14 @@
      423              : 
      424            2 :    logic [31:1]        i0_pc_wb;
      425              : 
-     426         2764 :    logic               i0_wb_en;
+     426         2304 :    logic               i0_wb_en;
      427              : 
      428            2 :    logic               trace_enable;
      429              : 
      430            0 :    logic               debug_valid_x;
      431              : 
-     432          716 :    el2_inst_pkt_t i0_itype;
-     433          640 :    el2_reg_pkt_t i0r;
+     432          600 :    el2_inst_pkt_t i0_itype;
+     433          630 :    el2_reg_pkt_t i0r;
      434              : 
      435              : 
      436              :    rvdffie  #(8) misc1ff (.*,
@@ -710,15 +710,15 @@
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
      608          554 :             if (~cam[i].valid) begin
-     609         8860 :                cam_wen[i] = cam_write;
-     610         8860 :                found = 1'b1;
+     609         5862 :                cam_wen[i] = cam_write;
+     610         5862 :                found = 1'b1;
      611              :             end
      612          554 :             else begin
      613          554 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617        28242 :             cam_wen[i] = 0;
+     617        19248 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -771,13 +771,13 @@
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
      668            4 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670        37310 :            cam_in[i] = cam[i];
+     670        25318 :            cam_in[i] = cam[i];
      671              : 
      672          342 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
      673          342 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676        35864 :          if (dec_tlu_force_halt)
+     676        23872 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,25 +847,25 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746         1608 :       if (i0_legal_decode_d) begin
-     747         1608 :          if (i0_dp.mul)                  i0_itype = MUL;
+     746         1150 :       if (i0_legal_decode_d) begin
+     747         1150 :          if (i0_dp.mul)                  i0_itype = MUL;
      748          130 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749          254 :          if (i0_dp.store)                i0_itype = STORE;
-     750          744 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751         1608 :          if (i0_dp.zbb | i0_dp.zbs |
+     749          138 :          if (i0_dp.store)                i0_itype = STORE;
+     750          512 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751         1150 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
      756            2 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757         1608 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758         1608 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759         1608 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760         1608 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761         1608 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762         1608 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763         1608 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764          330 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     757         1150 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758         1150 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759         1150 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760         1150 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761         1150 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762         1150 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763         1150 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764          214 :          if (i0_dp.condbr)               i0_itype = CONDBR;
      765           28 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862         8966 :       if (dec_extint_stall) begin
+     862         5968 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868         8966 :       else begin
-     869         8966 :          lsu_p.valid = lsu_decode_d;
+     868         5968 :       else begin
+     869         5968 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871         8966 :          lsu_p.load                         =  i0_dp.load ;
-     872         8966 :          lsu_p.store                        =  i0_dp.store;
-     873         8966 :          lsu_p.by                           =  i0_dp.by   ;
-     874         8966 :          lsu_p.half                         =  i0_dp.half ;
-     875         8966 :          lsu_p.word                         =  i0_dp.word ;
-     876         8966 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871         5968 :          lsu_p.load                         =  i0_dp.load ;
+     872         5968 :          lsu_p.store                        =  i0_dp.store;
+     873         5968 :          lsu_p.by                           =  i0_dp.by   ;
+     874         5968 :          lsu_p.half                         =  i0_dp.half ;
+     875         5968 :          lsu_p.word                         =  i0_dp.word ;
+     876         5968 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878         8966 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879         8966 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880         8966 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878         5968 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879         5968 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880         5968 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882         8966 :          lsu_p.unsign  =  i0_dp.unsign;
+     882         5968 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_gpr_ctl.sv.html
index c5709d1731c..e0ccd07cd4b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -122,12 +122,12 @@
       18              : #(
       19              :    `include "el2_param.vh"
       20              :  )  (
-      21          788 :     input logic [4:0]  raddr0,       // logical read addresses
+      21          704 :     input logic [4:0]  raddr0,       // logical read addresses
       22          640 :     input logic [4:0]  raddr1,
       23              : 
-      24         1520 :     input logic        wen0,         // write enable
-      25          916 :     input logic [4:0]  waddr0,       // write address
-      26            4 :     input logic [31:0] wd0,          // write data
+      24         1292 :     input logic        wen0,         // write enable
+      25          818 :     input logic [4:0]  waddr0,       // write address
+      26            8 :     input logic [31:0] wd0,          // write data
       27              : 
       28          228 :     input logic        wen1,         // write enable
       29           32 :     input logic [4:0]  waddr1,       // write address
@@ -137,11 +137,11 @@
       33            0 :     input logic [4:0]  waddr2,       // write address
       34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36        17932 :     input logic        clk,
+      36        14934 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
-      39            4 :     output logic [31:0] rd0,         // read data
-      40          268 :     output logic [31:0] rd1,
+      39            6 :     output logic [31:0] rd0,         // read data
+      40          136 :     output logic [31:0] rd1,
       41              : 
       42            0 :     input  logic        scan_mode
       43              : );
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_ib_ctl.sv.html
index cf6f11adb0e..7c791bfcd3b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,12 +131,12 @@
       27              : 
       28          144 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
       29           32 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30          218 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      30          202 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34         1788 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
-      35         2764 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
+      34         1322 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      35         2306 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
       38              : 
@@ -146,7 +146,7 @@
       42           10 :    input logic [31:1]  ifu_i0_pc,                                  // i0 pc from the aligner
       43              : 
       44              : 
-      45         2764 :    output logic dec_ib0_valid_d,                                   // ib0 valid
+      45         2306 :    output logic dec_ib0_valid_d,                                   // ib0 valid
       46            0 :    output logic dec_debug_valid_d,                                 // Debug read or write at D-stage
       47              : 
       48              : 
@@ -154,11 +154,11 @@
       50              : 
       51           10 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53         1788 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53         1322 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
       55          144 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
       56           32 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57          218 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      57          202 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_pmp_ctl.sv.html
index 96d79ed559d..54a98cc40a1 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32        17932 :    input logic clk,
-      33        17932 :    input logic free_l2clk,
-      34        17932 :    input logic csr_wr_clk,
+      32        14934 :    input logic clk,
+      33        14934 :    input logic free_l2clk,
+      34        14934 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
       37            0 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_tlu_ctl.sv.html
index 407dbef0ab7..3b2a8e93025 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32        17932 :    input logic clk,
-      33        17932 :    input logic free_clk,
-      34        17932 :    input logic free_l2clk,
+      32        14934 :    input logic clk,
+      33        14934 :    input logic free_clk,
+      34        14934 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
@@ -149,29 +149,29 @@
       45              : 
       46              : 
       47              :    // perf counter inputs
-      48         2764 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
-      49          170 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
-      50         2780 :    input logic       ifu_pmu_ic_miss, // icache miss
+      48         2306 :    input logic       ifu_pmu_instr_aligned,   // aligned instructions
+      49          158 :    input logic       ifu_pmu_fetch_stall, // fetch unit stalled
+      50         2318 :    input logic       ifu_pmu_ic_miss, // icache miss
       51            0 :    input logic       ifu_pmu_ic_hit, // icache hit
       52            0 :    input logic       ifu_pmu_bus_error, // Instruction side bus error
-      53         2776 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
-      54         5554 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
-      55         2764 :    input logic       dec_pmu_instr_decoded, // decoded instructions
+      53         2316 :    input logic       ifu_pmu_bus_busy, // Instruction side bus busy
+      54         4633 :    input logic       ifu_pmu_bus_trxn, // Instruction side bus transaction
+      55         2306 :    input logic       dec_pmu_instr_decoded, // decoded instructions
       56            0 :    input logic       dec_pmu_decode_stall, // decode stall
       57            0 :    input logic       dec_pmu_presync_stall, // decode stall due to presync'd inst
       58            0 :    input logic       dec_pmu_postsync_stall,// decode stall due to postsync'd inst
       59            8 :    input logic       lsu_store_stall_any,    // SB or WB is full, stall decode
       60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
-      62          192 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63          494 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      62          178 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
+      63          377 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
       64          398 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
-      65          668 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
+      65          553 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
       66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
       68           12 :    input logic       lsu_pmu_bus_busy,       // D side bus busy
       69          224 :    input logic       lsu_pmu_load_external_m, // D side bus load
-      70          484 :    input logic       lsu_pmu_store_external_m, // D side bus store
+      70          368 :    input logic       lsu_pmu_store_external_m, // D side bus store
       71            0 :    input logic       dma_pmu_dccm_read,          // DMA DCCM read
       72            0 :    input logic       dma_pmu_dccm_write,         // DMA DCCM write
       73            0 :    input logic       dma_pmu_any_read,           // DMA read
@@ -195,13 +195,13 @@
       91            4 :    input logic [11:0] dec_csr_rdaddr_d,      // read address for csr
       92              : 
       93            0 :    input logic        dec_csr_wen_r,      // csr write enable at wb
-      94          640 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
+      94          540 :    input logic [11:0] dec_csr_rdaddr_r,      // read address for csr
       95            0 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
       96            0 :    input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
       97              : 
       98            0 :    input logic        dec_csr_stall_int_ff, // csr is mie/mstatus
       99              : 
-     100         2764 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
+     100         2304 :    input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
      101              : 
      102            2 :    input logic [31:1] exu_npc_r, // for NPC tracking
      103              : 
@@ -210,21 +210,21 @@
      106            0 :    input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
      107              : 
      108            0 :    input logic [31:0] dec_illegal_inst, // For mtval
-     109         2764 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
+     109         2306 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112          346 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112          243 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115          470 :    input logic        exu_i0_br_valid_r, // valid
-     116          192 :    input logic        exu_i0_br_mp_r, // mispredict
+     115          355 :    input logic        exu_i0_br_valid_r, // valid
+     116          178 :    input logic        exu_i0_br_mp_r, // mispredict
      117          514 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
      119              :    // branch info from pipe1 for errors or counter updates
      120              : 
      121           84 :    input logic             exu_i0_br_way_r, // way hit or repl
      122              : 
-     123          496 :    output logic dec_tlu_core_empty,  // core is empty
+     123          494 :    output logic dec_tlu_core_empty,  // core is empty
      124              :    // Debug start
      125            0 :    output logic dec_dbg_cmd_done, // abstract command done
      126            0 :    output logic dec_dbg_cmd_fail, // abstract command failed
@@ -243,8 +243,8 @@
      139              : 
      140            0 :    input  logic dbg_halt_req, // DM requests a halt
      141            0 :    input  logic dbg_resume_req, // DM requests a resume
-     142         2780 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
-     143          572 :    input  logic lsu_idle_any, // lsu is idle
+     142         2318 :    input  logic ifu_miss_state_idle, // I-side miss buffer empty
+     143          456 :    input  logic lsu_idle_any, // lsu is idle
      144            0 :    input  logic dec_div_active, // oop div is active
      145            0 :    output el2_trigger_pkt_t  [3:0] trigger_pkt_any, // trigger info for trigger blocks
      146              : 
@@ -284,14 +284,14 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183           16 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183            8 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184            4 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186           84 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
      187              : 
      188            0 :    output logic dec_tlu_i0_kill_writeb_wb,    // I0 is flushed, don't writeback any results to arch state
      189            4 :    output logic dec_tlu_flush_lower_wb,       // commit has a flush (exception, int, mispredict at e4)
-     190         2764 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
+     190         2304 :    output logic dec_tlu_i0_commit_cmt,        // committed an instruction
      191              : 
      192            0 :    output logic dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
      193            4 :    output logic dec_tlu_flush_lower_r,       // commit has a flush (exception, int)
@@ -314,7 +314,7 @@
      210            0 :    output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
      211              : 
      212            0 :    output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
-     213         2764 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
+     213         2304 :    output logic dec_tlu_i0_valid_wb1,  // pipe 0 valid
      214            0 :    output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
      215            0 :    output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
      216            0 :    output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
@@ -391,7 +391,7 @@
      287              : `ifdef RV_USER_MODE
      288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -402,7 +402,7 @@
      298            0 :    logic [15:2] dcsr_ns, dcsr;
      299            0 :    logic [5:0] mip_ns, mip;
      300            0 :    logic [5:0] mie_ns, mie;
-     301           16 :    logic [31:0] mcyclel_ns, mcyclel;
+     301           13 :    logic [31:0] mcyclel_ns, mcyclel;
      302            0 :    logic [31:0] mcycleh_ns, mcycleh;
      303            2 :    logic [31:0] minstretl_ns, minstretl;
      304            0 :    logic [31:0] minstreth_ns, minstreth;
@@ -428,8 +428,8 @@
      324            0 :    logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
      325            4 :    logic        tlu_flush_lower_r, tlu_flush_lower_r_d1;
      326            0 :    logic [31:1] tlu_flush_path_r,  tlu_flush_path_r_d1;
-     327         2764 :    logic i0_valid_wb;
-     328         2764 :    logic tlu_i0_commit_cmt;
+     327         2304 :    logic i0_valid_wb;
+     328         2304 :    logic tlu_i0_commit_cmt;
      329            0 :    logic [31:1] vectored_path, interrupt_path;
      330            0 :    logic [16:0] dicawics_ns, dicawics;
      331            0 :    logic        wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
@@ -444,11 +444,11 @@
      340            0 :    logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
      341            0 :    logic synchronous_flush_r;
      342            0 :    logic [4:0]  exc_cause_r, exc_cause_wb;
-     343           68 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
-     344           16 :    logic [31:0] mcyclel_inc;
+     343           56 :    logic        mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
+     344           13 :    logic [31:0] mcyclel_inc;
      345            0 :    logic [31:0] mcycleh_inc;
      346              : 
-     347           12 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
+     347           10 :    logic        minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
      348              : 
      349            2 :    logic [31:0] minstretl_inc, minstretl_read;
      350            0 :    logic [31:0] minstreth_inc, minstreth_read;
@@ -456,10 +456,10 @@
      352            4 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355          356 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355          252 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
      357            0 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
-     358         2764 :    logic i0_trigger_eval_r;
+     358         2304 :    logic i0_trigger_eval_r;
      359              : 
      360            0 :    logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
      361            4 :    logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
@@ -506,17 +506,17 @@
      402            0 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405        17932 :    logic csr_wr_clk;
+     405        14934 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
      407          224 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
      409            0 :    logic lsu_single_ecc_error_r;
      410            0 :    logic [31:0] lsu_error_pkt_addr_r;
      411            2 :    logic mcyclel_cout_in;
-     412         2764 :    logic i0_valid_no_ebreak_ecall_r;
-     413         2764 :    logic minstret_enable_f;
+     412         2304 :    logic i0_valid_no_ebreak_ecall_r;
+     413         2304 :    logic minstret_enable_f;
      414            4 :    logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
-     415         2764 :    logic pc0_valid_r;
+     415         2304 :    logic pc0_valid_r;
      416            0 :    logic [15:0] mfdc_int, mfdc_ns;
      417            0 :    logic [31:0] mrac_in;
      418            0 :    logic [31:27] csr_sat;
@@ -539,7 +539,7 @@
      435            0 :    logic [3:0] perfcnt_during_sleep;
      436            0 :    logic [9:0] event_r;
      437              : 
-     438          716 :    el2_inst_pkt_t pmu_i0_itype_qual;
+     438          600 :    el2_inst_pkt_t pmu_i0_itype_qual;
      439              : 
      440            0 :    logic dec_csr_wen_r_mod;
      441              : 
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484            2 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         1158 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484            1 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485          579 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
@@ -2828,9 +2828,9 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727        17932 :    input logic clk,
-    2728        17932 :    input logic free_l2clk,
-    2729        17932 :    input logic csr_wr_clk,
+    2727        14934 :    input logic clk,
+    2728        14934 :    input logic free_l2clk,
+    2729        14934 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
     2731            0 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
     2732            0 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
@@ -2859,12 +2859,12 @@
     2755              :    localparam MITCTL_ENABLE_HALTED      = 1;
     2756              :    localparam MITCTL_ENABLE_PAUSED      = 2;
     2757              : 
-    2758           16 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
+    2758           13 :    logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
     2759            0 :    logic [2:0] mitctl0_ns, mitctl0;
     2760            0 :    logic [3:0] mitctl1_ns, mitctl1;
     2761            0 :    logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
     2762            2 :    logic mitcnt0_inc_ok, mitcnt1_inc_ok;
-    2763           68 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
+    2763           56 :    logic mitcnt0_inc_cout, mitcnt1_inc_cout;
     2764            0 :  logic mit0_match_ns;
     2765            0 :  logic mit1_match_ns;
     2766            0 :  logic mitctl0_0_b_ns;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_trigger.sv.html
index 0c93cee73b0..64a844dbbe3 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dma_ctrl.sv.html
index 18c141e3dec..645a7675f5b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29        17932 :    input logic         clk,
-      30        17932 :    input logic         free_clk,
+      29        14934 :    input logic         clk,
+      30        14934 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -173,8 +173,8 @@
       69            0 :    output logic        dma_active,         // DMA is busy
       70            0 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
       71            0 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
-      72          710 :    input logic         dccm_ready, // dccm ready to accept DMA request
-      73          202 :    input logic         iccm_ready, // iccm ready to accept DMA request
+      72          594 :    input logic         dccm_ready, // dccm ready to accept DMA request
+      73          188 :    input logic         iccm_ready, // iccm ready to accept DMA request
       74            2 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
       75              : 
       76              :    // PMU signals
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185        17932 :    logic                    dma_buffer_c1_clk;
-     186        17932 :    logic                    dma_free_clk;
+     185        14934 :    logic                    dma_buffer_c1_clk;
+     186        14934 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu.sv.html
index b1b15b54c7a..4c501eabbe7 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,46 +124,46 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        17932 :    input logic          clk,                                           // Top level clock
+      23        14934 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
-      27         2764 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
-      28         2764 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
+      27         2305 :    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
+      28         2305 :    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse
       29            0 :    input logic  [31:0]  dbg_cmd_wrdata,                                // Debug data   to primary I0 RS1
       30            0 :    input el2_alu_pkt_t i0_ap,                                         // DEC alu {valid,predecodes}
       31              : 
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
       34          144 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35          218 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      35          202 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
       36           32 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
       39            0 :    input logic  [31:0]  lsu_result_m,                                  // Load result M-stage
       40            0 :    input logic  [31:0]  lsu_nonblock_load_data,                        // nonblock load data
-      41         2068 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
-      42         1080 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
-      43            4 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
-      44          268 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45          272 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
-      46            4 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
-      47          112 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
-      48         2116 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49          768 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
-      50          276 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
+      41         1838 :    input logic          dec_i0_rs1_en_d,                               // Qualify GPR RS1 data
+      42          964 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
+      43            6 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
+      44          136 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
+      45          198 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      46            8 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
+      47          100 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
+      48         1774 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
+      49          652 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      50          162 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51           10 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            4 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55           16 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55            8 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
-      57         2066 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
+      57         1724 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
       59            0 :    input el2_div_pkt_t div_p,                                         // DEC {valid, unsigned, rem}
       60            0 :    input logic          dec_div_cancel,                                // Cancel the divide operation
       61              : 
-      62          264 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
+      62          149 :    input logic  [31:1]  pred_correct_npc_x,                            // DEC NPC for correctly predicted branch
       63              : 
       64            4 :    input logic          dec_tlu_flush_lower_r,                         // Flush divide and secondary ALUs
       65            0 :    input logic  [31:1]  dec_tlu_flush_path_r,                          // Redirect target
@@ -176,33 +176,33 @@
       72          104 :    output logic [31:0]  exu_lsu_rs1_d,                                 // LSU operand
       73            0 :    output logic [31:0]  exu_lsu_rs2_d,                                 // LSU operand
       74              : 
-      75          204 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
+      75          190 :    output logic         exu_flush_final,                               // Pipe is being flushed this cycle
       76            8 :    output logic [31:1]  exu_flush_path_final,                          // Target for the oldest flush source
       77              : 
-      78           88 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
+      78           94 :    output logic [31:0]  exu_i0_result_x,                               // Primary ALU result to DEC
       79            2 :    output logic [31:1]  exu_i0_pc_x,                                   // Primary PC  result to DEC
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            2 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83          346 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83          243 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
       86            8 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87          470 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
-      88          192 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
+      87          355 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      88          178 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
       89          514 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90           46 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      90           42 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
       91           84 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
       93            0 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
-      94          132 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95           46 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      94          120 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
+      95           42 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
       96            8 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
-     100          192 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101          494 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     100          178 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
+     101          377 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
      102          398 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
@@ -217,46 +217,46 @@
      113            8 :    logic [31:0]                i0_rs2_bypass_data_d;
      114          144 :    logic                       i0_rs1_bypass_en_d;
      115            8 :    logic                       i0_rs2_bypass_en_d;
-     116            4 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
-     117            4 :    logic [31:0]                muldiv_rs1_d;
-     118          264 :    logic [31:1]                pred_correct_npc_r;
-     119          504 :    logic                       i0_pred_correct_upper_r;
+     116            6 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
+     117            6 :    logic [31:0]                muldiv_rs1_d;
+     118          149 :    logic [31:1]                pred_correct_npc_r;
+     119          402 :    logic                       i0_pred_correct_upper_r;
      120            2 :    logic [31:1]                i0_flush_path_upper_r;
      121            4 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
-     122         2764 :    logic                       x_ctl_en,  r_ctl_en;
+     122         2305 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124           46 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125           46 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126          496 :    logic                       i0_taken_d;
-     127          496 :    logic                       i0_taken_x;
-     128          472 :    logic                       i0_valid_d;
-     129          472 :    logic                       i0_valid_x;
-     130           46 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124           42 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125           42 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126          378 :    logic                       i0_taken_d;
+     127          378 :    logic                       i0_taken_x;
+     128          356 :    logic                       i0_valid_d;
+     129          356 :    logic                       i0_valid_x;
+     130           42 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
      132            0 :    el2_predict_pkt_t          final_predict_mp;
      133          144 :    el2_predict_pkt_t          i0_predict_newp_d;
      134              : 
      135            0 :    logic                       flush_in_d;
-     136           88 :    logic [31:0]                alu_result_x;
+     136           94 :    logic [31:0]                alu_result_x;
      137              : 
      138            0 :    logic                       mul_valid_x;
      139            0 :    logic [31:0]                mul_result_x;
      140              : 
      141           84 :    el2_predict_pkt_t          i0_pp_r;
      142              : 
-     143          200 :    logic                       i0_flush_upper_d;
+     143          186 :    logic                       i0_flush_upper_d;
      144           10 :    logic [31:1]                i0_flush_path_d;
      145          144 :    el2_predict_pkt_t          i0_predict_p_d;
-     146          504 :    logic                       i0_pred_correct_upper_d;
+     146          402 :    logic                       i0_pred_correct_upper_d;
      147              : 
-     148          200 :    logic                       i0_flush_upper_x;
+     148          186 :    logic                       i0_flush_upper_x;
      149            2 :    logic [31:1]                i0_flush_path_x;
      150           84 :    el2_predict_pkt_t          i0_predict_p_x;
-     151          504 :    logic                       i0_pred_correct_upper_x;
-     152          768 :    logic                       i0_branch_x;
+     151          402 :    logic                       i0_pred_correct_upper_x;
+     152          652 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
-     155           64 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
+     155           62 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
      156              : 
      157              : 
      158              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_alu_ctl.sv.html
index fc26ce3f005..c4bd83d01c9 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,52 +124,52 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        17932 :    input  logic                  clk,                // Top level clock
+      23        14934 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
-      27          200 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
+      27          186 :    input  logic                  flush_upper_x,      // Branch flush from previous cycle
       28            4 :    input  logic                  flush_lower_r,      // Master flush of entire pipeline
-      29         2764 :    input  logic                  enable,             // Clock enable
-      30         2116 :    input  logic                  valid_in,           // Valid
+      29         2306 :    input  logic                  enable,             // Clock enable
+      30         1774 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            4 :    input  logic                  csr_ren_in,         // CSR select
-      33           16 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
-      34            4 :    input  logic signed [31:0]    a_in,               // A operand
-      35          352 :    input  logic        [31:0]    b_in,               // B operand
+      33            8 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      34            6 :    input  logic signed [31:0]    a_in,               // A operand
+      35          240 :    input  logic        [31:0]    b_in,               // B operand
       36           10 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
       37          144 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
-      38          112 :    input  logic        [12:1]    brimm_in,           // Branch offset
+      38          100 :    input  logic        [12:1]    brimm_in,           // Branch offset
       39              : 
       40              : 
-      41           88 :    output logic        [31:0]    result_ff,          // final result
-      42          200 :    output logic                  flush_upper_out,    // Branch flush
-      43          204 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
+      41           94 :    output logic        [31:0]    result_ff,          // final result
+      42          186 :    output logic                  flush_upper_out,    // Branch flush
+      43          190 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
       44           10 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            2 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46          504 :    output logic                  pred_correct_out,   // NPC control
+      46          402 :    output logic                  pred_correct_out,   // NPC control
       47          144 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
       50              : 
-      51            4 :    logic               [31:0]    zba_a_in;
-      52           92 :    logic               [31:0]    aout;
+      51            6 :    logic               [31:0]    zba_a_in;
+      52           98 :    logic               [31:0]    aout;
       53           12 :    logic                         cout,ov,neg;
       54            0 :    logic               [31:0]    lout;
-      55            4 :    logic               [31:0]    sout;
+      55            6 :    logic               [31:0]    sout;
       56           88 :    logic                         sel_shift;
-      57         1956 :    logic                         sel_adder;
-      58            0 :    logic                         slt_one;
-      59          496 :    logic                         actual_taken;
+      57         1614 :    logic                         sel_adder;
+      58            2 :    logic                         slt_one;
+      59          378 :    logic                         actual_taken;
       60           10 :    logic               [31:1]    pcout;
-      61          192 :    logic                         cond_mispredict;
+      61          178 :    logic                         cond_mispredict;
       62           12 :    logic                         target_mispredict;
-      63         1692 :    logic                         eq, ne, lt, ge;
+      63         1354 :    logic                         eq, ne, lt, ge;
       64           56 :    logic                         any_jal;
-      65          374 :    logic               [1:0]     newhist;
+      65          353 :    logic               [1:0]     newhist;
       66           56 :    logic                         sel_pc;
-      67            4 :    logic               [31:0]    csr_write_data;
-      68           88 :    logic               [31:0]    result;
+      67            6 :    logic               [31:0]    csr_write_data;
+      68           94 :    logic               [31:0]    result;
       69              : 
       70              : 
       71              : 
@@ -348,7 +348,7 @@
      244              :                                 ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |
      245              :                                 ( {32{~ap_zba   }} &  a_in[31:0]       );
      246              : 
-     247          996 :    logic        [31:0]    bm;
+     247          768 :    logic        [31:0]    bm;
      248              : 
      249              :    assign bm[31:0]            = ( ap.sub )  ?  ~b_in[31:0]  :  b_in[31:0];
      250              : 
@@ -383,8 +383,8 @@
      279              : 
      280            0 :    logic        [5:0]     shift_amount;
      281            2 :    logic        [31:0]    shift_mask;
-     282          288 :    logic        [62:0]    shift_extend;
-     283          288 :    logic        [62:0]    shift_long;
+     282          290 :    logic        [62:0]    shift_extend;
+     283          290 :    logic        [62:0]    shift_long;
      284              : 
      285              : 
      286              :    assign shift_amount[5:0]            = ( { 6{ap.sll}}   & (6'd32 - {1'b0,b_in[4:0]}) ) |   // [5] unused
@@ -416,7 +416,7 @@
      312              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CLZ,CTZ      * * * * * * * * * * * * * * * * * *
      313              : 
      314            0 :    logic                  bitmanip_clz_ctz_sel;
-     315            4 :    logic        [31:0]    bitmanip_a_reverse_ff;
+     315            6 :    logic        [31:0]    bitmanip_a_reverse_ff;
      316            0 :    logic        [31:0]    bitmanip_lzd_in;
      317            2 :    logic        [5:0]     bitmanip_dw_lzd_enc;
      318            0 :    logic        [5:0]     bitmanip_clz_ctz_result;
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342       301248 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343       301248 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342       205312 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343       205312 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
@@ -460,8 +460,8 @@
      356              : 
      357              :    // * * * * * * * * * * * * * * * * * *  BitManip  :  CPOP         * * * * * * * * * * * * * * * * * *
      358              : 
-     359            0 :    logic        [5:0]     bitmanip_cpop;
-     360            0 :    logic        [5:0]     bitmanip_cpop_result;
+     359            2 :    logic        [5:0]     bitmanip_cpop;
+     360            0 :    logic        [5:0]     bitmanip_cpop_result;
      361              : 
      362              : 
      363              :    integer                bitmanip_cpop_i;
@@ -499,7 +499,7 @@
      395              : 
      396              :    assign bitmanip_minmax_sel          =  ap_min | ap_max;
      397              : 
-     398         1694 :    logic                  bitmanip_minmax_sel_a;
+     398         1356 :    logic                  bitmanip_minmax_sel_a;
      399              : 
      400              :    assign bitmanip_minmax_sel_a        =  ge  ^ ap_min;
      401              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_div_ctl.sv.html
index b275f595f84..84fddcf069d 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,13 +124,13 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        17932 :    input logic           clk,                       // Top level clock
+      23        14934 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
       27            0 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
-      28            4 :    input logic  [31:0]   dividend,                  // Numerator
-      29          352 :    input logic  [31:0]   divisor,                   // Denominator
+      28            6 :    input logic  [31:0]   dividend,                  // Numerator
+      29          240 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
@@ -1414,7 +1414,7 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313        17932 :    input  logic            clk,                       // Top level clock
+    1313        14934 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
@@ -1422,8 +1422,8 @@
     1318            0 :    input  logic            valid_in,
     1319          206 :    input  logic            signed_in,
     1320            0 :    input  logic            rem_in,
-    1321            4 :    input  logic [31:0]     dividend_in,
-    1322          352 :    input  logic [31:0]     divisor_in,
+    1321            6 :    input  logic [31:0]     dividend_in,
+    1322          240 :    input  logic [31:0]     divisor_in,
     1323              : 
     1324            0 :    output logic            valid_out,
     1325            0 :    output logic [31:0]     data_out
@@ -1446,7 +1446,7 @@
     1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
     1344            0 :    logic                   b_enable, b_twos_comp;
-    1345          352 :    logic        [32:0]     b_in;
+    1345          240 :    logic        [32:0]     b_in;
     1346            0 :    logic        [37:0]     b_ff;
     1347              : 
     1348            0 :    logic        [31:0]     q_in, q_ff;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_mul_ctl.sv.html
index bcdce7f1908..f0f937437d0 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23        17932 :    input logic          clk,              // Top level clock
+      23        14934 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209       301248 :              if (bcompress_test_bit_d)
+     209       205312 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236       301248 :              if (bdecompress_test_bit_d)
+     236       205312 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu.sv.html
index 5767ee1a353..b1d02a8a83c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,15 +129,15 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28        17932 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29        17932 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30        17932 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28        14934 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        14934 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        14934 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
-      33         2764 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
+      33         2306 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
       34              : 
-      35          204 :    input logic exu_flush_final, // flush, includes upper and lower
-      36         2764 :    input logic dec_tlu_i0_commit_cmt , // committed i0
+      35          190 :    input logic exu_flush_final, // flush, includes upper and lower
+      36         2304 :    input logic dec_tlu_i0_commit_cmt , // committed i0
       37            0 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
       38            0 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
       39            8 :    input logic [31:1] exu_flush_path_final, // flush fetch address
@@ -172,9 +172,9 @@
       68            0 :    output logic                            ifu_axi_bready,
       69              : 
       70              :    // AXI Read Channels
-      71         2778 :    output logic                            ifu_axi_arvalid,
-      72         5556 :    input  logic                            ifu_axi_arready,
-      73         1724 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      71         2317 :    output logic                            ifu_axi_arvalid,
+      72         4635 :    input  logic                            ifu_axi_arready,
+      73         1378 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
       74           36 :    output logic [31:0]                     ifu_axi_araddr,
       75            2 :    output logic [3:0]                      ifu_axi_arregion,
       76            0 :    output logic [7:0]                      ifu_axi_arlen,
@@ -185,10 +185,10 @@
       81            2 :    output logic [2:0]                      ifu_axi_arprot,
       82            0 :    output logic [3:0]                      ifu_axi_arqos,
       83              : 
-      84         5554 :    input  logic                            ifu_axi_rvalid,
+      84         4633 :    input  logic                            ifu_axi_rvalid,
       85            2 :    output logic                            ifu_axi_rready,
-      86          960 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-      87          200 :    input  logic [63:0]                     ifu_axi_rdata,
+      86          729 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+      87          188 :    input  logic [63:0]                     ifu_axi_rdata,
       88            0 :    input  logic [1:0]                      ifu_axi_rresp,
       89              : 
       90            2 :    input  logic                      ifu_bus_clk_en,
@@ -206,10 +206,10 @@
      102            0 :    output logic                      iccm_dma_rvalid,
      103            0 :    output logic [63:0]               iccm_dma_rdata,
      104            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     105          202 :    output logic                      iccm_ready,
+     105          188 :    output logic                      iccm_ready,
      106              : 
-     107         2764 :    output logic       ifu_pmu_instr_aligned,
-     108          170 :    output logic       ifu_pmu_fetch_stall,
+     107         2306 :    output logic       ifu_pmu_instr_aligned,
+     108          158 :    output logic       ifu_pmu_fetch_stall,
      109            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
      110              : 
      111              : //   I$ & ITAG Ports
@@ -218,7 +218,7 @@
      114            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      115              : 
      116           96 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     117          496 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     117          474 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      118            0 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      119            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
      120            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
@@ -227,8 +227,8 @@
      123              : 
      124            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
      125            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     126          496 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     127         2514 :    output logic                      ic_sel_premux_data, // Select the premux data.
+     126          474 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     127         2049 :    output logic                      ic_sel_premux_data, // Select the premux data.
      128              : 
      129            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      130            0 :    output logic                      ic_debug_rd_en,     // Icache debug rd
@@ -259,40 +259,40 @@
      155            0 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
      156              : 
      157              : // Perf counter sigs
-     158         2780 :    output logic       ifu_pmu_ic_miss, // ic miss
+     158         2318 :    output logic       ifu_pmu_ic_miss, // ic miss
      159            0 :    output logic       ifu_pmu_ic_hit, // ic hit
      160            0 :    output logic       ifu_pmu_bus_error, // iside bus error
-     161         2776 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
-     162         5554 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
+     161         2316 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
+     162         4633 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
      163              : 
      164              : 
      165            0 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
      166            0 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
      167              : 
-     168         2764 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
+     168         2306 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
      169            0 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
      170            0 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
      172           36 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173           10 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174         1788 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174         1322 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
-     176         2780 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
+     176         2318 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
      178          144 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
      179           32 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180          218 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     180          202 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
      184            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
-     185          132 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186           46 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     185          120 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
+     186           42 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
      187            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
      190           84 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191           46 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     191           42 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
      192            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
@@ -320,7 +320,7 @@
      216            2 :    logic [31:1]            ifc_fetch_addr_bf;
      217              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
      218              : 
-     219         2712 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
+     219         2254 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
      220            2 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
      221              : 
      222            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
@@ -329,33 +329,33 @@
      225              :    assign ifu_ic_error_start = ic_error_start;
      226              : 
      227              : 
-     228         1224 :    logic        ic_write_stall;
+     228          992 :    logic        ic_write_stall;
      229            0 :    logic        ic_dma_active;
-     230          206 :    logic        ifc_dma_access_ok;
+     230          192 :    logic        ifc_dma_access_ok;
      231            0 :    logic [1:0]  ic_access_fault_f;
      232            0 :    logic [1:0]  ic_access_fault_type_f;
-     233         2784 :    logic        ifu_ic_mb_empty;
+     233         2320 :    logic        ifu_ic_mb_empty;
      234              : 
-     235         2772 :    logic ic_hit_f;
+     235         2314 :    logic ic_hit_f;
      236              : 
-     237          196 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238          368 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     237          174 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
+     238          264 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
      239            0 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
      240           46 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
      241          104 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
-     242           44 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243          136 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     242           38 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
+     243          108 :    logic [11:0] ifu_bp_poffset_f; // predicted target
      244            0 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
-     245          128 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
+     245           84 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
      246          132 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247           46 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     247           42 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
-     251         2712 :    logic [1:0]   ic_fetch_val_f;
-     252          496 :    logic [31:0] ic_data_f;
-     253          496 :    logic [31:0] ifu_fetch_data_f;
-     254         1290 :    logic ifc_fetch_req_f;
+     251         2254 :    logic [1:0]   ic_fetch_val_f;
+     252          500 :    logic [31:0] ic_data_f;
+     253          500 :    logic [31:0] ifu_fetch_data_f;
+     254         1058 :    logic ifc_fetch_req_f;
      255            0 :    logic ifc_fetch_req_f_raw;
      256            0 :    logic iccm_dma_rd_ecc_double_err;
      257            0 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
@@ -369,7 +369,7 @@
      265              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
      266              : 
      267            2 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
-     268         1290 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
+     268         1058 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
      269            2 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
      270            0 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
      271            0 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_aln_ctl.sv.html
index 64e53a0dd18..0abbb381adf 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30        17932 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31        17932 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        14934 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        14934 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -141,18 +141,18 @@
       37            0 :    input logic [1:0]                              ic_access_fault_f,        // Instruction access fault for the current fetch.
       38            0 :    input logic [1:0]                              ic_access_fault_type_f,   // Instruction access fault types
       39              : 
-      40          204 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
+      40          190 :    input logic                                    exu_flush_final,          // Flush from the pipeline.
       41              : 
-      42         2764 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
+      42         2306 :    input logic                                    dec_i0_decode_d,          // Valid instruction at D-stage and not blocked
       43              : 
-      44          496 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
+      44          500 :    input logic [31:0]                             ifu_fetch_data_f,         // fetch data in memory format - not right justified
       45              : 
-      46         2712 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
+      46         2254 :    input logic [1:0]                              ifu_fetch_val,            // valids on a 2B boundary, right justified
       47            2 :    input logic [31:1]                             ifu_fetch_pc,             // starting pc of fetch
       48              : 
       49              : 
       50              : 
-      51         2764 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
+      51         2306 :    output logic                                   ifu_i0_valid,             // Instruction 0 is valid
       52            0 :    output logic                                   ifu_i0_icaf,              // Instruction 0 has access fault
       53            0 :    output logic [1:0]                             ifu_i0_icaf_type,         // Instruction 0 access fault type
       54            0 :    output logic                                   ifu_i0_icaf_second,       // Instruction 0 has access fault on second 2B of 4B inst
@@ -160,95 +160,95 @@
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
       57           36 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58           10 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59         1788 :    output logic                                   ifu_i0_pc4,
+      59         1322 :    output logic                                   ifu_i0_pc4,
       60              : 
-      61         2284 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
+      61         1836 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
       62           40 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65           46 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      65           42 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
       66            0 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67          136 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      67          108 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
-      70           44 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
+      70           38 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
       71          104 :    input logic [1:0]                              ifu_bp_hist1_f,           // history counters for all 4 potential branches, bit 1, right justified
-      72          128 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
-      73          196 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
+      72           84 :    input logic [1:0]                              ifu_bp_pc4_f,             // pc4 indication, right justified
+      73          174 :    input logic [1:0]                              ifu_bp_way_f,             // way indication, right justified
       74          132 :    input logic [1:0]                              ifu_bp_valid_f,           // branch valid, right justified
       75            0 :    input logic [1:0]                              ifu_bp_ret_f,             // predicted ret indication, right justified
       76              : 
       77              : 
       78          144 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
       79           32 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80          218 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      80          202 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
       84              : 
-      85         2764 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
+      85         2306 :    output logic                                   ifu_pmu_instr_aligned,    // number of inst aligned this cycle
       86              : 
       87          240 :    output logic [15:0]                            ifu_i0_cinst              // 16b compress inst for i0
       88              :    );
       89              : 
       90              : 
       91              : 
-      92         2772 :    logic                                          ifvalid;
+      92         2314 :    logic                                          ifvalid;
       93            0 :    logic                                          shift_f1_f0, shift_f2_f0, shift_f2_f1;
       94            0 :    logic                                          fetch_to_f0, fetch_to_f1, fetch_to_f2;
       95              : 
       96            0 :    logic [1:0]                                    f2val_in, f2val;
-      97          660 :    logic [1:0]                                    f1val_in, f1val;
-      98         2052 :    logic [1:0]                                    f0val_in, f0val;
+      97          668 :    logic [1:0]                                    f1val_in, f1val;
+      98         1586 :    logic [1:0]                                    f0val_in, f0val;
       99            0 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
      101          240 :    logic [31:0]                                   aligndata;
-     102         1788 :    logic                                          first4B, first2B;
+     102         1322 :    logic                                          first4B, first2B;
      103              : 
      104           36 :    logic [31:0]                                   uncompress0;
-     105         2764 :    logic                                          i0_shift;
-     106          664 :    logic                                          shift_2B, shift_4B;
-     107          700 :    logic                                          f1_shift_2B;
-     108          660 :    logic                                          f2_valid, sf1_valid, sf0_valid;
+     105         2306 :    logic                                          i0_shift;
+     106          666 :    logic                                          shift_2B, shift_4B;
+     107          708 :    logic                                          f1_shift_2B;
+     108          668 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
      110          240 :    logic [31:0]                                   ifirst;
-     111         2072 :    logic [1:0]                                    alignval;
+     111         1606 :    logic [1:0]                                    alignval;
      112           36 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
      114           88 :    logic [11:0]                                   f1poffset;
-     115           88 :    logic [11:0]                                   f0poffset;
-     116           50 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117          194 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
-     118          168 :    logic [1:0]                                    f1hist1;
-     119          212 :    logic [1:0]                                    f0hist1;
-     120          100 :    logic [1:0]                                    f1hist0;
-     121          124 :    logic [1:0]                                    f0hist0;
+     115           82 :    logic [11:0]                                   f0poffset;
+     116           46 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117          174 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     118          114 :    logic [1:0]                                    f1hist1;
+     119          156 :    logic [1:0]                                    f0hist1;
+     120           76 :    logic [1:0]                                    f1hist0;
+     121          104 :    logic [1:0]                                    f0hist0;
      122              : 
      123            0 :    logic [1:0][$clog2(pt.BTB_SIZE)-1:0]           f0index, f1index, alignindex;
      124              : 
      125            0 :    logic [1:0]                                    f1ictype;
      126            0 :    logic [1:0]                                    f0ictype;
      127              : 
-     128          128 :    logic [1:0]                                    f1pc4;
-     129          524 :    logic [1:0]                                    f0pc4;
+     128           84 :    logic [1:0]                                    f1pc4;
+     129          300 :    logic [1:0]                                    f0pc4;
      130              : 
      131            0 :    logic [1:0]                                    f1ret;
      132            0 :    logic [1:0]                                    f0ret;
      133           68 :    logic [1:0]                                    f1way;
      134           72 :    logic [1:0]                                    f0way;
      135              : 
-     136          196 :    logic [1:0]                                    f1brend;
+     136          120 :    logic [1:0]                                    f1brend;
      137           88 :    logic [1:0]                                    f0brend;
      138              : 
      139           72 :    logic [1:0]                                    alignbrend;
-     140          400 :    logic [1:0]                                    alignpc4;
+     140          284 :    logic [1:0]                                    alignpc4;
      141              : 
      142            0 :    logic [1:0]                                    alignret;
      143          108 :    logic [1:0]                                    alignway;
-     144          176 :    logic [1:0]                                    alignhist1;
-     145          100 :    logic [1:0]                                    alignhist0;
-     146          508 :    logic [1:1]                                    alignfromf1;
-     147          256 :    logic                                          i0_ends_f1;
+     144          174 :    logic [1:0]                                    alignhist1;
+     145           96 :    logic [1:0]                                    alignhist0;
+     146          510 :    logic [1:1]                                    alignfromf1;
+     147          258 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
      150            0 :    logic [31:1]                                   f1prett;
@@ -260,47 +260,47 @@
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159          400 :    logic                                          i0_brp_pc4;
+     159          284 :    logic                                          i0_brp_pc4;
      160              : 
      161           28 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165          916 :    logic [1:0]                                    wrptr, wrptr_in;
-     166          836 :    logic [1:0]                                    rdptr, rdptr_in;
-     167          844 :    logic [2:0]                                    qwen;
+     165          763 :    logic [1:0]                                    wrptr, wrptr_in;
+     166          691 :    logic [1:0]                                    rdptr, rdptr_in;
+     167          698 :    logic [2:0]                                    qwen;
      168           36 :    logic [31:0]                                   q2,q1,q0;
-     169          420 :    logic                                          q2off_in, q2off;
-     170          380 :    logic                                          q1off_in, q1off;
-     171          440 :    logic                                          q0off_in, q0off;
-     172         1232 :    logic                                          f0_shift_2B;
+     169          423 :    logic                                          q2off_in, q2off;
+     170          382 :    logic                                          q1off_in, q1off;
+     171          444 :    logic                                          q0off_in, q0off;
+     172         1242 :    logic                                          f0_shift_2B;
      173              : 
-     174          260 :    logic [31:0]                                   q0eff;
+     174          266 :    logic [31:0]                                   q0eff;
      175          288 :    logic [31:0]                                   q0final;
-     176          892 :    logic                                          q0ptr;
-     177          892 :    logic [1:0]                                    q0sel;
+     176          893 :    logic                                          q0ptr;
+     177          893 :    logic [1:0]                                    q0sel;
      178              : 
-     179          280 :    logic [31:0]                                   q1eff;
-     180          336 :    logic [15:0]                                   q1final;
-     181          664 :    logic                                          q1ptr;
-     182          664 :    logic [1:0]                                    q1sel;
+     179          270 :    logic [31:0]                                   q1eff;
+     180          338 :    logic [15:0]                                   q1final;
+     181          672 :    logic                                          q1ptr;
+     182          672 :    logic [1:0]                                    q1sel;
      183              : 
-     184          836 :    logic [2:0]                                    qren;
+     184          691 :    logic [2:0]                                    qren;
      185              : 
      186           40 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
      190              :    localparam                                     BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
-     191           94 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
-     192          608 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
-     193          588 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
+     191           49 :    logic [BRDATA_SIZE-1:0]                        brdata_in, brdata2, brdata1, brdata0;
+     192          384 :    logic [BRDATA_SIZE-1:0]                        brdata1eff, brdata0eff;
+     193          364 :    logic [BRDATA_SIZE-1:0]                        brdata1final, brdata0final;
      194              : 
      195              :    localparam                                     MHI   = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
-     198           20 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199          152 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     198           18 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
+     199          150 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201            0 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_bp_ctl.sv.html
index 9d9b57e7f43..14dfa692774 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,16 +135,16 @@
       31              :  )
       32              :   (
       33              : 
-      34        17932 :    input logic clk,
+      34        14934 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
-      37         2772 :    input logic ic_hit_f,      // Icache hit, enables F address capture
+      37         2314 :    input logic ic_hit_f,      // Icache hit, enables F address capture
       38              : 
       39            2 :    input logic [31:1] ifc_fetch_addr_f, // look up btb address
-      40         1290 :    input logic ifc_fetch_req_f,  // F1 valid
+      40         1058 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
       42           84 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43           46 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      43           42 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
       44            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
@@ -156,26 +156,26 @@
       52              : 
       53            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
-      55          132 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56           46 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      55          120 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
+      56           42 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
       57            8 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
-      60          204 :    input logic exu_flush_final, // all flushes
+      60          190 :    input logic exu_flush_final, // all flushes
       61              : 
-      62          368 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      62          264 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
       63            0 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       64           46 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66           46 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66           42 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
-      68          196 :    output logic [1:0] ifu_bp_way_f, // way
+      68          174 :    output logic [1:0] ifu_bp_way_f, // way
       69            0 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
       70          104 :    output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified
-      71           44 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
-      72          128 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
+      71           38 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
+      72           84 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
       73          132 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74          136 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      74          108 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -205,32 +205,32 @@
      101              :    localparam BHT_NO_ADDR_MATCH  = ( pt.BHT_ARRAY_DEPTH <= 16 );
      102              : 
      103              : 
-     104           68 :    logic exu_mp_valid_write;
-     105          192 :    logic exu_mp_ataken;
-     106          192 :    logic exu_mp_valid; // conditional branch mispredict
+     104           66 :    logic exu_mp_valid_write;
+     105          178 :    logic exu_mp_ataken;
+     106          178 :    logic exu_mp_valid; // conditional branch mispredict
      107           88 :    logic exu_mp_boffset; // branch offsett
-     108          132 :    logic exu_mp_pc4; // branch is a 4B inst
+     108          120 :    logic exu_mp_pc4; // branch is a 4B inst
      109           12 :    logic exu_mp_call; // branch is a call inst
      110           12 :    logic exu_mp_ret; // branch is a ret inst
      111           12 :    logic exu_mp_ja; // branch is a jump always
-     112          192 :    logic [1:0] exu_mp_hist; // new history
-     113           84 :    logic [11:0] exu_mp_tgt; // target offset
+     112          178 :    logic [1:0] exu_mp_hist; // new history
+     113           76 :    logic [11:0] exu_mp_tgt; // target offset
      114            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115          356 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116          346 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     115          252 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116          243 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
      117            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120           46 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120           42 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122            0 :    logic use_mp_way, use_mp_way_p1;
      123            0 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
      124            0 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127          136 :    logic [11:0]       btb_rd_tgt_f;
+     127          108 :    logic [11:0]       btb_rd_tgt_f;
      128           16 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
-     129          314 :    logic [1:1]        bp_total_branch_offset_f;
+     129          198 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
      131            2 :    logic [31:1]       bp_btb_target_adder_f;
      132            2 :    logic [31:1]       bp_rs_call_target_f;
@@ -241,17 +241,17 @@
      137            0 :    logic               btb_wr_en_way0, btb_wr_en_way1;
      138              : 
      139              : 
-     140          192 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
+     140          178 :    logic               dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;
      141            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]        btb_error_addr_wb;
      142            0 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144            0 :    logic  branch_error_bank_conflict_f;
-     145           46 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145           42 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146            0 :    logic [1:0] num_valids;
      147            0 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
-     148          232 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
+     148          116 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
      149            0 :                         mp_wrindex_dec, mp_wrlru_b0;
-     150          468 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
+     150          353 :    logic                btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;
      151            0 :    logic  tag_match_way0_f, tag_match_way1_f;
      152           44 :    logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;
      153            4 :    logic [1:0] bht_valid_f, bht_force_taken_f;
@@ -270,12 +270,12 @@
      166              : 
      167           12 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169          368 :    logic                                         final_h;
+     169          264 :    logic                                         final_h;
      170           28 :    logic                                         btb_fg_crossing_f;
-     171          132 :    logic                                         middle_of_bank;
+     171          120 :    logic                                         middle_of_bank;
      172              : 
      173              : 
-     174           44 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
+     174           38 :    logic [1:0]                                   bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;
      175            0 :    logic                                         branch_error_bank_conflict_p1_f;
      176            0 :    logic                                         tag_match_way0_p1_f, tag_match_way1_p1_f;
      177              : 
@@ -291,9 +291,9 @@
      187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
-     190           44 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191          284 :     logic [1:0]                                  bht_bank1_rd_data_f;
-     192           56 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
+     190           38 :     logic [1:0]                                  bht_bank0_rd_data_f;
+     191          186 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     192           50 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
      195              :    assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict
@@ -348,7 +348,7 @@
      244              :    // set on leak one, hold until next flush without leak one
      245              :    assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
      246              : 
-     247          204 : logic exu_flush_final_d1;
+     247          190 : logic exu_flush_final_d1;
      248              : 
      249              :  if(!pt.BTB_FULLYA) begin : genblock1
      250              :    assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460           46 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460           42 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -719,8 +719,8 @@
      615              :                                                 exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
-     618          192 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619           48 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     618          166 :    logic [1:0] bht_wr_data0, bht_wr_data2;
+     619           46 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -732,9 +732,9 @@
      628              : 
      629              : 
      630              : 
-     631           54 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
+     631           50 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;
      632              : 
-     633           54 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
+     633           50 :    logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;
      634              :    el2_btb_ghr_hash #(.pt(pt)) mpghrhs  (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      635              :    el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
      636              :    el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676         8966 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676         5968 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678         8966 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679         8966 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678         5968 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679         5968 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684         8966 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684         5968 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686         8966 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687         8966 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686         5968 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687         5968 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -933,7 +933,7 @@
      829              : 
      830              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0]      bht_bank_wr_data ;
      831              :    logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0]                bht_bank_rd_data_out ;
-     832            4 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
+     832            8 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clken ;
      833            0 :    logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0]                 bht_bank_clk   ;
      834              : //   logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0]           bht_bank_sel   ;
      835              : 
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877         8966 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878         8966 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879         8966 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877         5968 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878         5968 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879         5968 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881         8966 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882         8966 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881         5968 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882         5968 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_compress_ctl.sv.html
index 6567e0cde07..6460d6f9b99 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              :    );
       29              : 
       30              : 
-      31          664 :    logic               legal;
+      31          666 :    logic               legal;
       32              : 
       33          116 :    logic [15:0]  i;
       34              : 
@@ -144,22 +144,22 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43          492 :    logic rdrd;
+      43          494 :    logic rdrd;
       44          292 :    logic rdrs1;
       45          372 :    logic rs2rs2;
       46           64 :    logic rdprd;
       47           92 :    logic rdprs1;
       48            0 :    logic rs2prs2;
-      49          658 :    logic rs2prd;
-      50          666 :    logic uimm9_2;
+      49          660 :    logic rs2prd;
+      50          668 :    logic uimm9_2;
       51           16 :    logic ulwimm6_2;
       52           32 :    logic ulwspimm7_2;
       53           16 :    logic rdeq2;
       54           12 :    logic rdeq1;
-      55          598 :    logic rs1eq2;
+      55          600 :    logic rs1eq2;
       56           76 :    logic sbroffset8_1;
       57           16 :    logic simm9_4;
-      58          200 :    logic simm5_0;
+      58          202 :    logic simm5_0;
       59           36 :    logic sjaloffset11_1;
       60            0 :    logic sluimm17_12;
       61           80 :    logic uimm5_0;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ic_mem.sv.html
index 2c271ca6bd2..546260a5489 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26        17932 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27        17932 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26        14934 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27        14934 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -141,11 +141,11 @@
       37            0 :       input logic                                   ic_debug_wr_en,     // Icache debug wr
       38            0 :       input logic                                   ic_debug_tag_array, // Debug tag array
       39            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_debug_way,       // Debug way. Rd or Wr.
-      40          496 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-      41         2514 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
+      40          474 :       input logic [63:0]                            ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+      41         2049 :       input logic                                   ic_sel_premux_data, // Select the pre_muxed data
       42              : 
       43           96 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data,         // Data to fill to the Icache. With ECC
-      44          496 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      44          474 :       output logic [63:0]                           ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       45            0 :       output logic [70:0]                           ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       46            0 :       output logic [25:0]                           ictag_debug_rd_data,// Debug icache tag.
       47            0 :       input logic  [70:0]                           ic_debug_wr_data,   // Debug wr cache.
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91        17932 :       input logic clk,
-      92        17932 :       input logic active_clk,
+      91        14934 :       input logic clk,
+      92        14934 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -202,7 +202,7 @@
       98            0 :       input logic                          ic_rd_en,           // Read enable
       99              : 
      100           96 :       input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]    ic_wr_data,         // Data to fill to the Icache. With ECC
-     101          496 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     101          474 :       output logic [63:0]                             ic_rd_data ,                                 // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      102            0 :       input  logic [70:0]                             ic_debug_wr_data,   // Debug wr cache.
      103            0 :       output logic [70:0]                             ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      104            0 :       output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
@@ -212,8 +212,8 @@
      108            0 :       input logic                            ic_debug_wr_en,      // Icache debug wr
      109            0 :       input logic                            ic_debug_tag_array,  // Debug tag array
      110            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way,        // Debug way. Rd or Wr.
-     111          496 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-     112         2514 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
+     111          474 :       input logic [63:0]                     ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+     112         2049 :       input logic                            ic_sel_premux_data,  // Select the pre_muxed data
      113              : 
      114            0 :       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
      115            0 :       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
@@ -233,7 +233,7 @@
      129              :    logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0]                  wb_dout ;       //  ways x bank
      130           96 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]                                          ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;
      131              :    logic [pt.ICACHE_NUM_WAYS-1:0] [141:0]                                         wb_dout_way_pre;
-     132          496 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
+     132          474 :    logic [pt.ICACHE_NUM_WAYS-1:0] [63:0]                                          wb_dout_way, wb_dout_way_with_premux;
      133            0 :    logic [141:0]                                                                  wb_dout_ecc;
      134              : 
      135            0 :    logic [pt.ICACHE_BANKS_WAY-1:0]                                                bank_check_en;
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803        17932 :       input logic                                                   clk,
-     804        17932 :       input logic                                                   active_clk,
+     803        14934 :       input logic                                                   clk,
+     804        14934 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_iccm_mem.sv.html
index 51237d3c83d..df0837599a1 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,8 +129,8 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28        17932 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29        17932 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28        14934 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29        14934 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
@@ -159,7 +159,7 @@
       55            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
       57            8 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58          696 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      58          583 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
       59           40 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
       60            0 :    logic             [63:0]              iccm_rd_data_pre;
       61            0 :    logic             [63:0]              iccm_data;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ifc_ctl.sv.html
index c9bbbe4066e..db90213ffc3 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,27 +130,27 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29        17932 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30        17932 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        14934 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        14934 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
       34              : 
-      35         2772 :    input logic ic_hit_f,      // Icache hit
-      36         2784 :    input logic ifu_ic_mb_empty, // Miss buffer empty
+      35         2314 :    input logic ic_hit_f,      // Icache hit
+      36         2320 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
-      38         2284 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
+      38         1836 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
       39           40 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
       41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
-      42          204 :    input logic exu_flush_final, // FLush
+      42          190 :    input logic exu_flush_final, // FLush
       43            8 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45          368 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      45          264 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
       46            0 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
       48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
-      49         1224 :    input logic ic_write_stall, // IC is writing, stop fetching
+      49          992 :    input logic ic_write_stall, // IC is writing, stop fetching
       50            0 :    input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
       51              : 
       52            0 :    input logic [31:0]  dec_tlu_mrac_ff ,   // side_effect and cacheable for each region
@@ -158,17 +158,17 @@
       54            2 :    output logic [31:1] ifc_fetch_addr_f, // fetch addr F
       55            2 :    output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
       56              : 
-      57         1290 :    output logic  ifc_fetch_req_f,  // fetch request valid F
+      57         1058 :    output logic  ifc_fetch_req_f,  // fetch request valid F
       58              : 
-      59          170 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
+      59          158 :    output logic  ifu_pmu_fetch_stall, // pmu event measuring fetch stall
       60              : 
       61            2 :    output logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. BF stage
-      62         1290 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
+      62         1058 :    output logic                      ifc_fetch_req_bf,              // Fetch request. Comes with the address.  BF stage
       63            2 :    output logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. BF stage
       64            0 :    output logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       65            0 :    output logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       66              : 
-      67          206 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
+      67          192 :    output logic  ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
       68              : 
       69              : 
       70              :    );
@@ -179,11 +179,11 @@
       75              : 
       76           64 :    logic     fb_full_f_ns, fb_full_f;
       77            4 :    logic     fb_right, fb_right2, fb_left, wfm, idle;
-      78         2460 :    logic     sel_last_addr_bf, sel_next_addr_bf;
-      79         4030 :    logic     miss_f, miss_a;
+      78         2106 :    logic     sel_last_addr_bf, sel_next_addr_bf;
+      79         3338 :    logic     miss_f, miss_a;
       80            0 :    logic     flush_fb, dma_iccm_stall_any_f;
       81            4 :    logic     mb_empty_mod, goto_idle, leave_idle;
-      82         1282 :    logic     fetch_bf_en;
+      82         1050 :    logic     fetch_bf_en;
       83           92 :    logic         line_wrap;
       84           40 :    logic         fetch_addr_next_1;
       85              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_mem_ctl.sv.html
index b31bfca0e6a..a1f454e1e8b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        53.6%
+    
+        50.0%
     
     
-        59
+        55
     
     
         110
@@ -131,40 +131,40 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30        17932 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31        17932 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32        17932 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30        14934 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        14934 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32        14934 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
-      35          204 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
+      35          190 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
       36            4 :    input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
       37            0 :    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
-      38         2764 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
+      38         2304 :    input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
       39            0 :    input logic                       dec_tlu_force_halt,            // force halt.
       40              : 
       41            2 :    input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
       42            2 :    input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
-      43         1290 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
+      43         1058 :    input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
       44            2 :    input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
       45            0 :    input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
-      47          206 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
+      47          192 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49          368 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49          264 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
       51           46 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
-      53         2780 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
-      54         2784 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
+      53         2318 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
+      54         2320 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
       55            0 :    output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
-      56         1224 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
+      56          992 :    output logic                      ic_write_stall,                // Stall fetch the cycle we are writing the cache.
       57              : 
       58              : /// PMU signals
-      59         2780 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
+      59         2318 :    output logic                      ifu_pmu_ic_miss,               // IC miss event
       60            0 :    output logic                      ifu_pmu_ic_hit,                // IC hit event
       61            0 :    output logic                      ifu_pmu_bus_error,             // Bus error event
-      62         2776 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
-      63         5554 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
+      62         2316 :    output logic                      ifu_pmu_bus_busy,              // Bus busy event
+      63         4633 :    output logic                      ifu_pmu_bus_trxn,              // Bus transaction
       64              : 
       65              :   //-------------------------- IFU AXI signals--------------------------
       66              :    // AXI Write Channels
@@ -188,9 +188,9 @@
       84            0 :    output logic                            ifu_axi_bready,
       85              : 
       86              :    // AXI Read Channels
-      87         2778 :    output logic                            ifu_axi_arvalid,
-      88         5556 :    input  logic                            ifu_axi_arready,
-      89         1724 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+      87         2317 :    output logic                            ifu_axi_arvalid,
+      88         4635 :    input  logic                            ifu_axi_arready,
+      89         1378 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
       90           36 :    output logic [31:0]                     ifu_axi_araddr,
       91            2 :    output logic [3:0]                      ifu_axi_arregion,
       92            0 :    output logic [7:0]                      ifu_axi_arlen,
@@ -201,10 +201,10 @@
       97            2 :    output logic [2:0]                      ifu_axi_arprot,
       98            0 :    output logic [3:0]                      ifu_axi_arqos,
       99              : 
-     100         5554 :    input  logic                            ifu_axi_rvalid,
+     100         4633 :    input  logic                            ifu_axi_rvalid,
      101            2 :    output logic                            ifu_axi_rready,
-     102          960 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     103          200 :    input  logic [63:0]                     ifu_axi_rdata,
+     102          729 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     103          188 :    input  logic [63:0]                     ifu_axi_rdata,
      104            0 :    input  logic [1:0]                      ifu_axi_rresp,
      105              : 
      106            2 :     input  logic                     ifu_bus_clk_en,
@@ -221,7 +221,7 @@
      117            0 :    output logic                      iccm_dma_rvalid,   //   Data read from iccm is valid
      118            0 :    output logic [63:0]               iccm_dma_rdata,    //   dma data read from iccm
      119            0 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
-     120          202 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
+     120          188 :    output logic                      iccm_ready,        //   iccm ready to accept new command.
      121              : 
      122              : 
      123              : //   I$ & ITAG Ports
@@ -230,7 +230,7 @@
      126            0 :    output logic                      ic_rd_en,           // Icache read  enable.
      127              : 
      128           96 :    output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0]               ic_wr_data,           // Data to fill to the Icache. With ECC
-     129          496 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     129          474 :    input  logic [63:0]               ic_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      130            0 :    input  logic [70:0]               ic_debug_rd_data ,          // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      131            0 :    input  logic [25:0]               ictag_debug_rd_data,  // Debug icache tag.
      132            0 :    output logic [70:0]               ic_debug_wr_data,     // Debug wr cache.
@@ -261,9 +261,9 @@
      157              : 
      158            0 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
      159            0 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
-     160         2712 :    input  logic [1:0]                ifu_fetch_val,
+     160         2254 :    input  logic [1:0]                ifu_fetch_val,
      161              :    // IFU control signals
-     162         2772 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
+     162         2314 :    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
      163            0 :    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
      164            0 :    output logic [1:0]                ic_access_fault_type_f, // Access fault types
      165            0 :    output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
@@ -274,10 +274,10 @@
      170              : 
      171            0 :    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
      172            0 :    output logic                      iccm_dma_sb_error,      // Single Bit ECC error from a DMA access
-     173         2712 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
-     174          496 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
-     175          496 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
-     176         2514 :    output logic                      ic_sel_premux_data,     // Select premux data.
+     173         2254 :    output logic [1:0]                ic_fetch_val_f,         // valid bytes for fetch. To the Aligner.
+     174          500 :    output logic [31:0]               ic_data_f,              // Data read from Icache or ICCM. To the Aligner.
+     175          474 :    output logic [63:0]               ic_premux_data,         // Premuxed data to be muxed with Icache data
+     176         2049 :    output logic                      ic_sel_premux_data,     // Select premux data.
      177              : 
      178              : /////  Debug
      179            0 :    input  el2_cache_debug_pkt_t     dec_tlu_ic_diag_pkt ,       // Icache/tag debug read/write packet
@@ -304,8 +304,8 @@
      200              : 
      201              : 
      202              : 
-     203         5554 :    logic           bus_ifu_wr_en     ;
-     204         5552 :    logic           bus_ifu_wr_en_ff  ;
+     203         4633 :    logic           bus_ifu_wr_en     ;
+     204         4631 :    logic           bus_ifu_wr_en_ff  ;
      205            0 :    logic           bus_ifu_wr_en_ff_q  ;
      206            0 :    logic           bus_ifu_wr_en_ff_wo_err  ;
      207            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     bus_ic_wr_en ;
@@ -333,36 +333,36 @@
      229            0 :    logic           scnd_miss_index_match ;
      230              : 
      231              : 
-     232          202 :    logic           ifc_dma_access_q_ok;
+     232          188 :    logic           ifc_dma_access_q_ok;
      233            0 :    logic           ifc_iccm_access_f ;
      234            0 :    logic           ifc_region_acc_fault_f;
      235            0 :    logic           ifc_region_acc_fault_final_f;
      236            0 :    logic  [1:0]    ifc_bus_acc_fault_f;
-     237         2780 :    logic           ic_act_miss_f;
+     237         2318 :    logic           ic_act_miss_f;
      238            0 :    logic           ic_miss_under_miss_f;
-     239          160 :    logic           ic_ignore_2nd_miss_f;
+     239          146 :    logic           ic_ignore_2nd_miss_f;
      240            0 :    logic           ic_act_hit_f;
-     241         2778 :    logic           miss_pending;
+     241         2316 :    logic           miss_pending;
      242            2 :    logic [31:1]    imb_in , imb_ff  ;
      243            2 :    logic [31:pt.ICACHE_BEAT_ADDR_HI+1]    miss_addr_in , miss_addr  ;
      244          172 :    logic           miss_wrap_f ;
-     245          204 :    logic           flush_final_f;
-     246         1474 :    logic           ifc_fetch_req_f;
-     247         1290 :    logic           ifc_fetch_req_f_raw;
-     248         2772 :    logic           fetch_req_f_qual   ;
-     249         1290 :    logic           ifc_fetch_req_qual_bf ;
+     245          190 :    logic           flush_final_f;
+     246         1228 :    logic           ifc_fetch_req_f;
+     247         1058 :    logic           ifc_fetch_req_f_raw;
+     248         2314 :    logic           fetch_req_f_qual   ;
+     249         1058 :    logic           ifc_fetch_req_qual_bf ;
      250            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]     replace_way_mb_any;
-     251         2776 :    logic           last_beat;
-     252         4012 :    logic           reset_beat_cnt  ;
-     253         1696 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
-     254         2468 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
+     251         2315 :    logic           last_beat;
+     252         3319 :    logic           reset_beat_cnt  ;
+     253         1351 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_req_addr_bits_hi_3 ;
+     254         2005 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]     ic_wr_addr_bits_hi_3 ;
      255            2 :    logic [31:1]    ifu_fetch_addr_int_f ;
      256            2 :    logic [31:1]    ifu_ic_rw_int_addr ;
-     257         2778 :    logic           crit_wd_byp_ok_ff ;
-     258         2772 :    logic           ic_crit_wd_rdy_new_ff;
+     257         2317 :    logic           crit_wd_byp_ok_ff ;
+     258         2314 :    logic           ic_crit_wd_rdy_new_ff;
      259          256 :    logic   [79:0]  ic_byp_data_only_pre_new;
-     260          212 :    logic   [79:0]  ic_byp_data_only_new;
-     261         2772 :    logic           ic_byp_hit_f ;
+     260          208 :    logic   [79:0]  ic_byp_data_only_new;
+     261         2314 :    logic           ic_byp_hit_f ;
      262            2 :    logic           ic_valid ;
      263            2 :    logic           ic_valid_ff;
      264            0 :    logic           reset_all_tags;
@@ -385,75 +385,75 @@
      281            0 :    logic           sel_mb_addr ;
      282            0 :    logic           sel_mb_addr_ff ;
      283            0 :    logic           sel_mb_status_addr ;
-     284          496 :    logic [63:0]    ic_final_data;
+     284          474 :    logic [63:0]    ic_final_data;
      285              : 
      286            0 :    logic [pt.ICACHE_STATUS_BITS-1:0]                              way_status_new_ff ;
      287            0 :    logic                                    way_status_wr_en_ff ;
      288            0 :    logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0]        way_status_out ;
      289            0 :    logic [1:0]                              ic_debug_way_enc;
      290              : 
-     291          958 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
+     291          728 :    logic [pt.IFU_BUS_TAG-1:0]             ifu_bus_rid_ff;
      292              : 
-     293         1474 :    logic         fetch_req_icache_f;
+     293         1228 :    logic         fetch_req_icache_f;
      294            0 :    logic         fetch_req_iccm_f;
      295            0 :    logic         ic_iccm_hit_f;
      296            2 :    logic         fetch_uncacheable_ff;
      297            0 :    logic         way_status_wr_en;
-     298         2514 :    logic         sel_byp_data;
-     299         2516 :    logic         sel_ic_data;
+     298         2049 :    logic         sel_byp_data;
+     299         2050 :    logic         sel_ic_data;
      300            0 :    logic         sel_iccm_data;
      301            0 :    logic         ic_rd_parity_final_err;
-     302         2780 :    logic         ic_act_miss_f_delayed;
+     302         2318 :    logic         ic_act_miss_f_delayed;
      303            0 :    logic         bus_ifu_wr_data_error;
      304            0 :    logic         bus_ifu_wr_data_error_ff;
      305            0 :    logic         way_status_wr_en_w_debug;
      306            0 :    logic         ic_debug_tag_val_rd_out;
-     307         2780 :    logic         ifu_pmu_ic_miss_in;
+     307         2318 :    logic         ifu_pmu_ic_miss_in;
      308            0 :    logic         ifu_pmu_ic_hit_in;
      309            0 :    logic         ifu_pmu_bus_error_in;
-     310         5556 :    logic         ifu_pmu_bus_trxn_in;
-     311         2776 :    logic         ifu_pmu_bus_busy_in;
+     310         4634 :    logic         ifu_pmu_bus_trxn_in;
+     311         2316 :    logic         ifu_pmu_bus_busy_in;
      312            0 :    logic         ic_debug_ict_array_sel_in;
      313            0 :    logic         ic_debug_ict_array_sel_ff;
      314            0 :    logic         debug_data_clken;
-     315         2776 :    logic         last_data_recieved_in ;
-     316         2776 :    logic         last_data_recieved_ff ;
+     315         2315 :    logic         last_data_recieved_in ;
+     316         2314 :    logic         last_data_recieved_ff ;
      317              : 
-     318         5554 :    logic                          ifu_bus_rvalid           ;
-     319         5552 :    logic                          ifu_bus_rvalid_ff        ;
-     320         5552 :    logic                          ifu_bus_rvalid_unq_ff    ;
-     321         5556 :    logic                          ifu_bus_arready_unq       ;
-     322         5554 :    logic                          ifu_bus_arready_unq_ff    ;
-     323         2778 :    logic                          ifu_bus_arvalid           ;
-     324         2778 :    logic                          ifu_bus_arvalid_ff        ;
-     325         5556 :    logic                          ifu_bus_arready           ;
-     326         5554 :    logic                          ifu_bus_arready_ff        ;
-     327          200 :    logic [63:0]                   ifu_bus_rdata_ff        ;
+     318         4633 :    logic                          ifu_bus_rvalid           ;
+     319         4631 :    logic                          ifu_bus_rvalid_ff        ;
+     320         4631 :    logic                          ifu_bus_rvalid_unq_ff    ;
+     321         4635 :    logic                          ifu_bus_arready_unq       ;
+     322         4633 :    logic                          ifu_bus_arready_unq_ff    ;
+     323         2317 :    logic                          ifu_bus_arvalid           ;
+     324         2317 :    logic                          ifu_bus_arvalid_ff        ;
+     325         4635 :    logic                          ifu_bus_arready           ;
+     326         4633 :    logic                          ifu_bus_arready_ff        ;
+     327          188 :    logic [63:0]                   ifu_bus_rdata_ff        ;
      328            0 :    logic [1:0]                    ifu_bus_rresp_ff          ;
-     329         5554 :    logic                          ifu_bus_rsp_valid ;
+     329         4633 :    logic                          ifu_bus_rsp_valid ;
      330            2 :    logic                          ifu_bus_rsp_ready ;
-     331          960 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
-     332          200 :    logic [63:0]                   ifu_bus_rsp_rdata;
+     331          729 :    logic [pt.IFU_BUS_TAG-1:0]     ifu_bus_rsp_tag;
+     332          188 :    logic [63:0]                   ifu_bus_rsp_rdata;
      333            0 :    logic [1:0]                    ifu_bus_rsp_opc;
      334              : 
-     335          364 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
+     335          348 :    logic [pt.ICACHE_NUM_BEATS-1:0]    write_fill_data;
      336            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    wr_data_c1_clk;
-     337          364 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
-     338          364 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
+     337          348 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid_in;
+     338          348 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_valid;
      339            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error_in;
      340            0 :    logic [pt.ICACHE_NUM_BEATS-1:0]    ic_miss_buff_data_error;
      341           40 :    logic [pt.ICACHE_BEAT_ADDR_HI:1]    byp_fetch_index;
-     342          452 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
+     342          336 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_0;
      343            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_1;
-     344          472 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
-     345          472 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
+     344          357 :    logic [pt.ICACHE_BEAT_ADDR_HI:3]    byp_fetch_index_inc;
+     345          357 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_0;
      346            2 :    logic [pt.ICACHE_BEAT_ADDR_HI:2]    byp_fetch_index_inc_1;
-     347         4024 :    logic          miss_buff_hit_unq_f ;
+     347         3333 :    logic          miss_buff_hit_unq_f ;
      348            0 :    logic          stream_hit_f ;
      349            0 :    logic          stream_miss_f ;
      350            0 :    logic          stream_eol_f ;
-     351         2772 :    logic          crit_byp_hit_f ;
-     352          958 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
+     351         2314 :    logic          crit_byp_hit_f ;
+     352          728 :    logic [pt.IFU_BUS_TAG-1:0] other_tag ;
      353              :    logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;
      354          196 :    logic [63:0] ic_miss_buff_half;
      355            0 :    logic        scnd_miss_req, scnd_miss_req_q;
@@ -467,7 +467,7 @@
      363            0 :    logic                                iccm_rd_ecc_single_err_ff   ;
      364            0 :    logic                                iccm_error_start;     // start the error fsm
      365            0 :    logic                                perr_state_en;
-     366         6356 :    logic                                miss_state_en;
+     366         5213 :    logic                                miss_state_en;
      367              : 
      368            0 :    logic        busclk;
      369            0 :    logic        busclk_force;
@@ -475,46 +475,46 @@
      371            2 :    logic        bus_ifu_bus_clk_en_ff;
      372            2 :    logic        bus_ifu_bus_clk_en ;
      373              : 
-     374         2778 :    logic        ifc_bus_ic_req_ff_in;
-     375         2778 :    logic        ifu_bus_cmd_valid ;
-     376         5556 :    logic        ifu_bus_cmd_ready ;
+     374         2317 :    logic        ifc_bus_ic_req_ff_in;
+     375         2317 :    logic        ifu_bus_cmd_valid ;
+     376         4635 :    logic        ifu_bus_cmd_ready ;
      377              : 
-     378         2776 :    logic        bus_inc_data_beat_cnt     ;
-     379         4012 :    logic        bus_reset_data_beat_cnt   ;
-     380         6790 :    logic        bus_hold_data_beat_cnt    ;
+     378         2316 :    logic        bus_inc_data_beat_cnt     ;
+     379         3319 :    logic        bus_reset_data_beat_cnt   ;
+     380         5637 :    logic        bus_hold_data_beat_cnt    ;
      381              : 
-     382         5556 :    logic        bus_inc_cmd_beat_cnt     ;
+     382         4634 :    logic        bus_inc_cmd_beat_cnt     ;
      383            0 :    logic        bus_reset_cmd_beat_cnt_0   ;
-     384         2780 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
-     385         5558 :    logic        bus_hold_cmd_beat_cnt    ;
+     384         2318 :    logic        bus_reset_cmd_beat_cnt_secondlast   ;
+     385         4636 :    logic        bus_hold_cmd_beat_cnt    ;
      386              : 
      387            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_data_beat_count  ;
      388            0 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_data_beat_count      ;
      389              : 
-     390         2778 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
-     391         2778 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
+     390         2317 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_cmd_beat_count  ;
+     391         2317 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_cmd_beat_count      ;
      392              : 
      393              : 
-     394         1696 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
-     395         1696 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
+     394         1351 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_new_rd_addr_count;
+     395         1351 :    logic [pt.ICACHE_BEAT_BITS-1:0]  bus_rd_addr_count;
      396              : 
      397              : 
-     398         5556 :    logic        bus_cmd_sent           ;
-     399         2776 :    logic        bus_last_data_beat     ;
+     398         4634 :    logic        bus_cmd_sent           ;
+     399         2315 :    logic        bus_last_data_beat     ;
      400              : 
      401              : 
      402            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren            ;
      403              : 
      404            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       bus_wren_last       ;
      405            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]       wren_reset_miss      ;
-     406          206 :    logic        ifc_dma_access_ok_d;
-     407          206 :    logic        ifc_dma_access_ok_prev;
+     406          192 :    logic        ifc_dma_access_ok_d;
+     407          192 :    logic        ifc_dma_access_ok_prev;
      408              : 
-     409         2780 :    logic   bus_cmd_req_in ;
-     410         2780 :    logic   bus_cmd_req_hold ;
+     409         2318 :    logic   bus_cmd_req_in ;
+     410         2318 :    logic   bus_cmd_req_hold ;
      411              : 
-     412         1320 :    logic   second_half_available ;
-     413         1320 :    logic   write_ic_16_bytes ;
+     412         1090 :    logic   second_half_available ;
+     413         1090 :    logic   write_ic_16_bytes ;
      414              : 
      415            0 :    logic   ifc_region_acc_fault_final_bf;
      416            0 :    logic   ifc_region_acc_fault_memory_bf;
@@ -523,21 +523,21 @@
      419              : 
      420            0 :    logic   iccm_correct_ecc;
      421            0 :    logic   dma_sb_err_state, dma_sb_err_state_ff;
-     422         2016 :    logic   two_byte_instr;
+     422         1547 :    logic   two_byte_instr;
      423              : 
      424              :    typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;
-     425            4 :    miss_state_t miss_state, miss_nxtstate;
+     425            2 :    miss_state_t miss_state, miss_nxtstate;
      426              : 
      427              :    typedef enum logic [1:0] {ERR_STOP_IDLE=2'b00, ERR_FETCH1=2'b01 , ERR_FETCH2=2'b10 , ERR_STOP_FETCH=2'b11} err_stop_state_t;
      428            0 :    err_stop_state_t err_stop_state, err_stop_nxtstate;
      429            0 :    logic   err_stop_state_en ;
      430            0 :    logic   err_stop_fetch ;
      431              : 
-     432         2774 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
+     432         2315 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434          312 :    logic   ifu_bp_hit_taken_q_f;
-     435         5554 :    logic   ifu_bus_rvalid_unq;
-     436         5556 :    logic   bus_cmd_beat_en;
+     434          208 :    logic   ifu_bp_hit_taken_q_f;
+     435         4633 :    logic   ifu_bus_rvalid_unq;
+     436         4634 :    logic   bus_cmd_beat_en;
      437              : 
      438              : 
      439              : // ---- Clock gating section -----
@@ -587,21 +587,21 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486         2022 :          IDLE: begin : idle
-     487         2022 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488         2022 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486         1328 :          IDLE: begin : idle
+     487         1328 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488         1328 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490         4436 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491         4436 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492         4436 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493         4436 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494         4436 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495         4436 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496         4436 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497         4436 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498         4436 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499         4436 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500         4436 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490         3064 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491         3064 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492         3064 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493         3064 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494         3064 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495         3064 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496         3064 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497         3064 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498         3064 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499         3064 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500         3064 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,26 +611,26 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510         2422 :          MISS_WAIT: begin : miss_wait
-     511         2422 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512         2422 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510         1510 :          MISS_WAIT: begin : miss_wait
+     511         1510 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512         1510 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514           80 :          HIT_U_MISS: begin : hit_u_miss
-     515           80 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516           80 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517           80 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514           66 :          HIT_U_MISS: begin : hit_u_miss
+     515           66 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516           66 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517           66 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
      521            0 :                                     exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;
      522            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      523              :          end
-     524            6 :          STALL_SCND_MISS: begin : stall_scnd_miss
-     525            6 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
-     526            6 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
-     527            6 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
+     524            0 :          STALL_SCND_MISS: begin : stall_scnd_miss
+     525            0 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
+     526            0 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
+     527            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      528              :          end
-     529            0 :          default: begin : def_case
+     529            0 :          default: begin : def_case
      530            0 :                   miss_nxtstate   = IDLE;
      531            0 :                   miss_state_en   = 1'b0;
      532              :          end
@@ -638,7 +638,7 @@
      534              :    end
      535              :    rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en),   .*);
      536              : 
-     537         2778 :   logic    sel_hold_imb     ;
+     537         2317 :   logic    sel_hold_imb     ;
      538              : 
      539              :    assign miss_pending       =  (miss_state != IDLE) ;
      540              :    assign crit_wd_byp_ok_ff  =  (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
@@ -902,7 +902,7 @@
      798              : /////////////////////////////////////////////////////////////////////////////////////
      799              : //  Create full buffer...                                                          //
      800              : /////////////////////////////////////////////////////////////////////////////////////
-     801          200 :      logic [63:0]       ic_miss_buff_data_in;
+     801          188 :      logic [63:0]       ic_miss_buff_data_in;
      802              :      assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
      803              : 
      804              :      for (genvar i=0; i<pt.ICACHE_NUM_BEATS; i++) begin :  wr_flop
@@ -940,9 +940,9 @@
      836              : // New bypass ready                                                                //
      837              : /////////////////////////////////////////////////////////////////////////////////////
      838           40 :    logic   [pt.ICACHE_BEAT_ADDR_HI:1]  bypass_index;
-     839          464 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
-     840         2778 :    logic   bypass_data_ready_in;
-     841         2774 :    logic   ic_crit_wd_rdy_new_in;
+     839          349 :    logic   [pt.ICACHE_BEAT_ADDR_HI:3]  bypass_index_5_3_inc;
+     840         2316 :    logic   bypass_data_ready_in;
+     841         2315 :    logic   ic_crit_wd_rdy_new_in;
      842              : 
      843              :    assign bypass_index[pt.ICACHE_BEAT_ADDR_HI:1] = imb_ff[pt.ICACHE_BEAT_ADDR_HI:1] ;
      844              :    assign bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3] = bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] + 1 ;
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945         8966 :       ERR_IDLE: begin : err_idle
-     946         8966 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947         8966 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948         8966 :         perr_sb_write_status = perr_state_en;
+     945         5968 :       ERR_IDLE: begin : err_idle
+     946         5968 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947         5968 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948         5968 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990         8966 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991         8966 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992         8966 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990         5968 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991         5968 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992         5968 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1469,7 +1469,7 @@
     1365              :                               ((miss_state == CRIT_BYP_OK) &  miss_state_en &  (miss_nxtstate == MISS_WAIT))  ))  |
     1366              :                              ( ifc_fetch_req_bf & exu_flush_final  & ~ifc_fetch_uncacheable_bf & ~ifc_iccm_access_bf )     ;
     1367              : 
-    1368         2896 : logic   ic_real_rd_wp_unused;
+    1368         2421 : logic   ic_real_rd_wp_unused;
     1369              : assign  ic_real_rd_wp_unused  =  (ifc_fetch_req_bf &  ~ifc_iccm_access_bf  &  ~ifc_region_acc_fault_final_bf & ~dec_tlu_fence_i_wb & ~stream_miss_f & ~ic_act_miss_f &
     1370              :                             ~(((miss_state == STREAM) & ~miss_state_en) |
     1371              :                               ((miss_state == CRIT_BYP_OK) & ~miss_state_en & ~(miss_nxtstate == MISS_WAIT)) |
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446         8966 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447         8966 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446         5968 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447         5968 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509         8966 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510         8966 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511        17932 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509         5968 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510         5968 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511        11936 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lib.sv.html
index 35045927d99..5e44892573a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -159,8 +159,8 @@
       55              : `include "el2_param.vh"
       56              :  )(
       57           32 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58          270 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59          258 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      58          246 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59          236 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu.sv.html
index 3b609170f67..a2be59b7277 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -152,7 +152,7 @@
       48           64 :    input logic [11:0]                      dec_lsu_offset_d,     // address offset operand
       49              : 
       50          100 :    input                                   el2_lsu_pkt_t lsu_p,  // lsu control packet
-      51          708 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
+      51          592 :    input logic                             dec_lsu_valid_raw_d,   // Raw valid for address computation
       52            0 :    input logic [31:0]                      dec_tlu_mrac_ff,       // CSR for memory region control
       53              : 
       54            0 :    output logic [31:0]                     lsu_result_m,          // lsu load data
@@ -160,8 +160,8 @@
       56            8 :    output logic                            lsu_load_stall_any,    // This is for blocking loads in the decode
       57            8 :    output logic                            lsu_store_stall_any,   // This is for blocking stores in the decode
       58            0 :    output logic                            lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
-      59          572 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
-      60          570 :    output logic                            lsu_active,            // Used to turn off top level clk
+      59          456 :    output logic                            lsu_idle_any,          // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
+      60          454 :    output logic                            lsu_active,            // Used to turn off top level clk
       61              : 
       62            0 :    output logic [31:1]                     lsu_fir_addr,        // fast interrupt address
       63            0 :    output logic [1:0]                      lsu_fir_error,       // Error during fast interrupt lookup
@@ -183,9 +183,9 @@
       79            0 :    output logic [31:0]                        lsu_nonblock_load_data,         // Data of the non block load
       80              : 
       81          224 :    output logic                            lsu_pmu_load_external_m,        // PMU : Bus loads
-      82          484 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
+      82          368 :    output logic                            lsu_pmu_store_external_m,       // PMU : Bus loads
       83            0 :    output logic                            lsu_pmu_misaligned_m,           // PMU : misaligned
-      84          668 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
+      84          553 :    output logic                            lsu_pmu_bus_trxn,               // PMU : bus transaction
       85            0 :    output logic                            lsu_pmu_bus_misaligned,         // PMU : misaligned access going to the bus
       86            0 :    output logic                            lsu_pmu_bus_error,              // PMU : bus sending error back
       87           12 :    output logic                            lsu_pmu_bus_busy,               // PMU : bus is not ready
@@ -217,8 +217,8 @@
      113            0 :    input logic [31:0]                      picm_rd_data, // PIC memory read/mask data
      114              : 
      115              :    // AXI Write Channels
-     116          504 :    output logic                            lsu_axi_awvalid,
-     117          506 :    input  logic                            lsu_axi_awready,
+     116          389 :    output logic                            lsu_axi_awvalid,
+     117          390 :    input  logic                            lsu_axi_awready,
      118            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      119            2 :    output logic [31:0]                     lsu_axi_awaddr,
      120            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -230,13 +230,13 @@
      126            0 :    output logic [2:0]                      lsu_axi_awprot,
      127            0 :    output logic [3:0]                      lsu_axi_awqos,
      128              : 
-     129          504 :    output logic                            lsu_axi_wvalid,
-     130          506 :    input  logic                            lsu_axi_wready,
+     129          389 :    output logic                            lsu_axi_wvalid,
+     130          390 :    input  logic                            lsu_axi_wready,
      131            0 :    output logic [63:0]                     lsu_axi_wdata,
      132           40 :    output logic [7:0]                      lsu_axi_wstrb,
      133            2 :    output logic                            lsu_axi_wlast,
      134              : 
-     135          504 :    input  logic                            lsu_axi_bvalid,
+     135          388 :    input  logic                            lsu_axi_bvalid,
      136            2 :    output logic                            lsu_axi_bready,
      137            0 :    input  logic [1:0]                      lsu_axi_bresp,
      138            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
@@ -276,22 +276,22 @@
      172            0 :    output logic                            dccm_dma_ecc_error,  // DMA load had ecc error
      173            0 :    output logic [2:0]                      dccm_dma_rtag,       // DMA request tag
      174            0 :    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
-     175          710 :    output logic                            dccm_ready,          // lsu ready for DMA access
+     175          594 :    output logic                            dccm_ready,          // lsu ready for DMA access
      176              : 
      177              :    // DCCM ECC status
      178            0 :    output logic                            lsu_dccm_rd_ecc_single_err,
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182        17932 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183        17932 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182        14934 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183        14934 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
      186           72 :     output logic [31:0] lsu_pmp_addr_start,
      187           72 :     output logic [31:0] lsu_pmp_addr_end,
      188            0 :     input  logic        lsu_pmp_error_start,
      189            0 :     input  logic        lsu_pmp_error_end,
-     190          484 :     output logic        lsu_pmp_we,
+     190          368 :     output logic        lsu_pmp_we,
      191          224 :     output logic        lsu_pmp_re
      192              : 
      193              :    );
@@ -338,7 +338,7 @@
      234            0 :    logic        store_stbuf_reqvld_r;
      235            0 :    logic        ldst_stbuf_reqvld_r;
      236              : 
-     237          708 :    logic        lsu_commit_r;
+     237          592 :    logic        lsu_commit_r;
      238            0 :    logic        lsu_exc_m;
      239              : 
      240            0 :    logic        addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
@@ -365,11 +365,11 @@
      261            0 :    logic        lsu_stbuf_full_any;
      262              : 
      263              :     // Bus signals
-     264          700 :    logic        lsu_busreq_r;
-     265          470 :    logic        lsu_bus_buffer_pend_any;
-     266          588 :    logic        lsu_bus_buffer_empty_any;
+     264          584 :    logic        lsu_busreq_r;
+     265          355 :    logic        lsu_bus_buffer_pend_any;
+     266          472 :    logic        lsu_bus_buffer_empty_any;
      267            8 :    logic        lsu_bus_buffer_full_any;
-     268          708 :    logic        lsu_busreq_m;
+     268          592 :    logic        lsu_busreq_m;
      269            0 :    logic [31:0] bus_read_data_m;
      270              : 
      271            0 :    logic        flush_m_up, flush_r;
@@ -381,16 +381,16 @@
      277            0 :    logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
      278              : 
      279              :    // Clocks
-     280          570 :    logic        lsu_busm_clken;
-     281         1066 :    logic        lsu_bus_obuf_c1_clken;
-     282        17932 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283        17932 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284        17932 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     280          454 :    logic        lsu_busm_clken;
+     281          835 :    logic        lsu_bus_obuf_c1_clken;
+     282        14934 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283        14934 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284        14934 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286        17932 :    logic        lsu_stbuf_c1_clk;
-     287        17932 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286        14934 :    logic        lsu_stbuf_c1_clk;
+     287        14934 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289        17932 :    logic        lsu_free_c2_clk;
+     289        14934 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_addrcheck.sv.html
index 88338ecc464..b867c6f29a5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,14 +131,14 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30        17932 :    input logic          lsu_c2_m_clk,              // clock
+      30        14934 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
       33           72 :    input logic [31:0]   start_addr_d,              // start address for lsu
       34           72 :    input logic [31:0]   end_addr_d,                // end address for lsu
       35          100 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
       36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
-      37          368 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
+      37          252 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
       38              : 
       39          104 :    input logic [31:0]   rs1_d,                     // address rs operand
       40              : 
@@ -167,7 +167,7 @@
       63            0 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
       64            0 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
       65            0 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
-      66          368 :    logic [4:0]  csr_idx;
+      66          252 :    logic [4:0]  csr_idx;
       67            0 :    logic        addr_in_iccm;
       68            0 :    logic        start_addr_dccm_or_pic;
       69            0 :    logic        base_reg_dccm_or_pic;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_buffer.sv.html
index 791ce4a80e4..eebb9f189e2 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31        17932 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        14934 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -142,17 +142,17 @@
       38            0 :    input logic                          dec_tlu_force_halt,
       39              : 
       40              :    // various clocks needed for the bus reads and writes
-      41         1066 :    input logic                          lsu_bus_obuf_c1_clken,
-      42          570 :    input logic                          lsu_busm_clken,
-      43        17932 :    input logic                          lsu_c2_r_clk,
-      44        17932 :    input logic                          lsu_bus_ibuf_c1_clk,
+      41          835 :    input logic                          lsu_bus_obuf_c1_clken,
+      42          454 :    input logic                          lsu_busm_clken,
+      43        14934 :    input logic                          lsu_c2_r_clk,
+      44        14934 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46        17932 :    input logic                          lsu_bus_buf_c1_clk,
-      47        17932 :    input logic                          lsu_free_c2_clk,
+      46        14934 :    input logic                          lsu_bus_buf_c1_clk,
+      47        14934 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
-      51          708 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
+      51          592 :    input logic                          dec_lsu_valid_raw_d,            // Raw valid for address computation
       52          100 :    input el2_lsu_pkt_t                 lsu_pkt_m,                      // lsu packet flowing down the pipe
       53          100 :    input el2_lsu_pkt_t                 lsu_pkt_r,                      // lsu packet flowing down the pipe
       54              : 
@@ -164,12 +164,12 @@
       60              : 
       61           36 :    input logic                          no_word_merge_r,                // r store doesn't need to wait in ibuf since it will not coalesce
       62           20 :    input logic                          no_dword_merge_r,               // r store doesn't need to wait in ibuf since it will not coalesce
-      63          708 :    input logic                          lsu_busreq_m,                   // bus request is in m
-      64          700 :    output logic                         lsu_busreq_r,                   // bus request is in r
+      63          592 :    input logic                          lsu_busreq_m,                   // bus request is in m
+      64          584 :    output logic                         lsu_busreq_r,                   // bus request is in r
       65            8 :    input logic                          ld_full_hit_m,                  // load can get all its byte from a write buffer entry
       66            4 :    input logic                          flush_m_up,                     // flush
       67            0 :    input logic                          flush_r,                        // flush
-      68          708 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
+      68          592 :    input logic                          lsu_commit_r,                   // lsu instruction in r commits
       69            0 :    input logic                          is_sideeffects_r,               // lsu attribute is side_effects
       70            0 :    input logic                          ldst_dual_d,                    // load/store is unaligned at 32 bit boundary
       71            0 :    input logic                          ldst_dual_m,                    // load/store is unaligned at 32 bit boundary
@@ -177,9 +177,9 @@
       73              : 
       74            0 :    input logic [7:0]                    ldst_byteen_ext_m,              // HI and LO signals
       75              : 
-      76          470 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
+      76          355 :    output logic                         lsu_bus_buffer_pend_any,          // bus buffer has a pending bus entry
       77            8 :    output logic                         lsu_bus_buffer_full_any,          // bus buffer is full
-      78          588 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
+      78          472 :    output logic                         lsu_bus_buffer_empty_any,         // bus buffer is empty
       79              : 
       80            0 :    output logic [3:0]                   ld_byte_hit_buf_lo, ld_byte_hit_buf_hi,    // Byte enables for forwarding data
       81            0 :    output logic [31:0]                  ld_fwddata_buf_lo, ld_fwddata_buf_hi,      // load forwarding data
@@ -199,14 +199,14 @@
       95            0 :    output logic [31:0]                        lsu_nonblock_load_data,        // Data of the non block load
       96              : 
       97              :    // PMU events
-      98          668 :    output logic                         lsu_pmu_bus_trxn,
+      98          553 :    output logic                         lsu_pmu_bus_trxn,
       99            0 :    output logic                         lsu_pmu_bus_misaligned,
      100            0 :    output logic                         lsu_pmu_bus_error,
      101           12 :    output logic                         lsu_pmu_bus_busy,
      102              : 
      103              :    // AXI Write Channels
-     104          504 :    output logic                            lsu_axi_awvalid,
-     105          506 :    input  logic                            lsu_axi_awready,
+     104          389 :    output logic                            lsu_axi_awvalid,
+     105          390 :    input  logic                            lsu_axi_awready,
      106            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      107            2 :    output logic [31:0]                     lsu_axi_awaddr,
      108            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -218,13 +218,13 @@
      114            0 :    output logic [2:0]                      lsu_axi_awprot,
      115            0 :    output logic [3:0]                      lsu_axi_awqos,
      116              : 
-     117          504 :    output logic                            lsu_axi_wvalid,
-     118          506 :    input  logic                            lsu_axi_wready,
+     117          389 :    output logic                            lsu_axi_wvalid,
+     118          390 :    input  logic                            lsu_axi_wready,
      119            0 :    output logic [63:0]                     lsu_axi_wdata,
      120           40 :    output logic [7:0]                      lsu_axi_wstrb,
      121            2 :    output logic                            lsu_axi_wlast,
      122              : 
-     123          504 :    input  logic                            lsu_axi_bvalid,
+     123          388 :    input  logic                            lsu_axi_bvalid,
      124            2 :    output logic                            lsu_axi_bready,
      125            0 :    input  logic [1:0]                      lsu_axi_bresp,
      126            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
@@ -298,8 +298,8 @@
      194            0 :    logic                                bus_coalescing_disable;
      195              : 
      196           20 :    logic                                bus_addr_match_pending;
-     197          668 :    logic                                bus_cmd_sent, bus_cmd_ready;
-     198          504 :    logic                                bus_wcmd_sent, bus_wdata_sent;
+     197          553 :    logic                                bus_cmd_sent, bus_cmd_ready;
+     198          389 :    logic                                bus_wcmd_sent, bus_wdata_sent;
      199          228 :    logic                                bus_rsp_read, bus_rsp_write;
      200            0 :    logic [pt.LSU_BUS_TAG-1:0]           bus_rsp_read_tag, bus_rsp_write_tag;
      201            0 :    logic                                bus_rsp_read_error, bus_rsp_write_error;
@@ -337,7 +337,7 @@
      233            0 :    logic   [DEPTH-1:0]                  buf_sideeffect_in;
      234          176 :    logic   [DEPTH-1:0]                  buf_unsign_in;
      235          100 :    logic   [DEPTH-1:0][1:0]             buf_sz_in;
-     236          484 :    logic   [DEPTH-1:0]                  buf_write_in;
+     236          368 :    logic   [DEPTH-1:0]                  buf_write_in;
      237            4 :    logic   [DEPTH-1:0]                  buf_wr_en;
      238            0 :    logic   [DEPTH-1:0]                  buf_dualhi_in;
      239          136 :    logic   [DEPTH-1:0][DEPTH_LOG2-1:0]  buf_dualtag_in;
@@ -356,7 +356,7 @@
      252            0 :    logic   [DEPTH-1:0][DEPTH-1:0]       buf_rspageQ;
      253              : 
      254              :    // Input buffer signals
-     255          484 :    logic                               ibuf_valid;
+     255          368 :    logic                               ibuf_valid;
      256            0 :    logic                               ibuf_dual;
      257            2 :    logic                               ibuf_samedw;
      258            0 :    logic                               ibuf_nomerge;
@@ -369,13 +369,13 @@
      265           18 :    logic [3:0]                         ibuf_byteen;
      266            2 :    logic [31:0]                        ibuf_addr;
      267            0 :    logic [31:0]                        ibuf_data;
-     268          486 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
+     268          370 :    logic [TIMER_LOG2-1:0]              ibuf_timer;
      269              : 
      270          240 :    logic                               ibuf_byp;
-     271          484 :    logic                               ibuf_wr_en;
-     272          484 :    logic                               ibuf_rst;
+     271          368 :    logic                               ibuf_wr_en;
+     272          368 :    logic                               ibuf_rst;
      273           40 :    logic                               ibuf_force_drain;
-     274          484 :    logic                               ibuf_drain_vld;
+     274          368 :    logic                               ibuf_drain_vld;
      275            4 :    logic [DEPTH-1:0]                   ibuf_drainvec_vld;
      276          116 :    logic [DEPTH_LOG2-1:0]              ibuf_tag_in;
      277          116 :    logic [DEPTH_LOG2-1:0]              ibuf_dualtag_in;
@@ -383,13 +383,13 @@
      279           72 :    logic [31:0]                        ibuf_addr_in;
      280          152 :    logic [3:0]                         ibuf_byteen_in;
      281            0 :    logic [31:0]                        ibuf_data_in;
-     282          486 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
+     282          370 :    logic [TIMER_LOG2-1:0]              ibuf_timer_in;
      283           18 :    logic [3:0]                         ibuf_byteen_out;
      284            0 :    logic [31:0]                        ibuf_data_out;
      285            2 :    logic                               ibuf_merge_en, ibuf_merge_in;
      286              : 
      287              :    // Output buffer signals
-     288          636 :    logic                               obuf_valid;
+     288          521 :    logic                               obuf_valid;
      289          142 :    logic                               obuf_write;
      290            0 :    logic                               obuf_nosend;
      291          228 :    logic                               obuf_rdrsp_pend;
@@ -406,9 +406,9 @@
      302              : 
      303          216 :    logic                               ibuf_buf_byp;
      304           64 :    logic                               obuf_force_wr_en;
-     305          458 :    logic                               obuf_wr_wait;
-     306          636 :    logic                               obuf_wr_en, obuf_wr_enQ;
-     307          636 :    logic                               obuf_rst;
+     305          343 :    logic                               obuf_wr_wait;
+     306          521 :    logic                               obuf_wr_en, obuf_wr_enQ;
+     307          521 :    logic                               obuf_rst;
      308          146 :    logic                               obuf_write_in;
      309          132 :    logic                               obuf_nosend_in;
      310            2 :    logic                               obuf_rdrsp_pend_en;
@@ -426,12 +426,12 @@
      322            0 :    logic [pt.LSU_BUS_TAG-1:0]          obuf_rdrsp_tag_in;
      323              : 
      324            0 :    logic                               obuf_merge_en;
-     325          396 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
+     325          282 :    logic [TIMER_LOG2-1:0]              obuf_wr_timer, obuf_wr_timer_in;
      326           60 :    logic [7:0]                         obuf_byteen0_in, obuf_byteen1_in;
      327            0 :    logic [63:0]                        obuf_data0_in, obuf_data1_in;
      328              : 
-     329          504 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
-     330          504 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
+     329          388 :    logic                               lsu_axi_awvalid_q, lsu_axi_awready_q;
+     330          388 :    logic                               lsu_axi_wvalid_q, lsu_axi_wready_q;
      331          216 :    logic                               lsu_axi_arvalid_q, lsu_axi_arready_q;
      332            2 :    logic                               lsu_axi_bvalid_q, lsu_axi_bready_q;
      333            2 :    logic                               lsu_axi_rvalid_q, lsu_axi_rready_q;
@@ -445,15 +445,15 @@
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344        26906 :    function automatic logic [2:0] f_Enc8to3;
+     344        17912 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348        26906 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349        26906 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350        26906 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348        17912 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349        17912 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350        17912 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352        26906 :       return Enc_value[2:0];
+     352        17912 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -758,51 +758,51 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657        33306 :             IDLE: begin
-     658        33306 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659        33306 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660        33306 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661        33306 :                      buf_wr_en[i]    = buf_state_en[i];
-     662        33306 :                      buf_data_en[i]  = buf_state_en[i];
-     663        33306 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664        33306 :                      buf_cmd_state_bus_en[i]  = '0;
+     657        22458 :             IDLE: begin
+     658        22458 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659        22458 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660        22458 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661        22458 :                      buf_wr_en[i]    = buf_state_en[i];
+     662        22458 :                      buf_data_en[i]  = buf_state_en[i];
+     663        22458 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664        22458 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         2062 :             CMD: begin
-     672         2062 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         2062 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         2062 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         2062 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         2062 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         2062 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         2062 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         2062 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         2062 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         2062 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671         1034 :             CMD: begin
+     672         1034 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673         1034 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674         1034 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675         1034 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676         1034 :                      buf_ldfwd_in[i]          = 1'b1;
+     677         1034 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678         1034 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679         1034 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680         1034 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681         1034 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683          382 :             RESP: begin
-     684          382 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685          382 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686          382 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687          382 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688          382 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689          382 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690          382 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691          382 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692          382 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693          382 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694          382 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695          382 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683          266 :             RESP: begin
+     684          266 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685          266 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686          266 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687          266 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688          266 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689          266 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690          266 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691          266 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692          266 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693          266 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694          266 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695          266 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697          382 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698          382 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699          382 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700          382 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701          382 :                      buf_cmd_state_bus_en[i]  = '0;
+     697          266 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698          266 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699          266 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700          266 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701          266 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
      703            0 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
      704            0 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_intf.sv.html
index 75eaeb46804..431ea4cb08e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30        17932 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        14934 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -140,20 +140,20 @@
       36            2 :    input logic                          dec_tlu_sideeffect_posted_disable,  // disable the posted sideeffect load store to the bus
       37              : 
       38              :    // various clocks needed for the bus reads and writes
-      39         1066 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
-      40          570 :    input logic                          lsu_busm_clken,                     // bus clock enable
+      39          835 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
+      40          454 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42        17932 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43        17932 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44        17932 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42        14934 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43        14934 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44        14934 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46        17932 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47        17932 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48        17932 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46        14934 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47        14934 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48        14934 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
-      51          708 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
-      52          708 :    input logic                          lsu_busreq_m,                      // bus request is in m
+      51          592 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
+      52          592 :    input logic                          lsu_busreq_m,                      // bus request is in m
       53              : 
       54          100 :    input                                el2_lsu_pkt_t lsu_pkt_m,          // lsu packet flowing down the pipe
       55          100 :    input                                el2_lsu_pkt_t lsu_pkt_r,          // lsu packet flowing down the pipe
@@ -167,16 +167,16 @@
       63            0 :    input logic [31:0]                   store_data_r,                      // store data flowing down the pipe
       64            0 :    input logic                          dec_tlu_force_halt,
       65              : 
-      66          708 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
+      66          592 :    input logic                          lsu_commit_r,                      // lsu instruction in r commits
       67            0 :    input logic                          is_sideeffects_m,                  // lsu attribute is side_effects
       68            4 :    input logic                          flush_m_up,                        // flush
       69            0 :    input logic                          flush_r,                           // flush
       70            0 :    input logic                          ldst_dual_d, ldst_dual_m, ldst_dual_r,
       71              : 
-      72          700 :    output logic                         lsu_busreq_r,                      // bus request is in r
-      73          470 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      72          584 :    output logic                         lsu_busreq_r,                      // bus request is in r
+      73          355 :    output logic                         lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
       74            8 :    output logic                         lsu_bus_buffer_full_any,           // write buffer is full
-      75          588 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
+      75          472 :    output logic                         lsu_bus_buffer_empty_any,          // write buffer is empty
       76            0 :    output logic [31:0]                  bus_read_data_m,                   // the bus return data
       77              : 
       78              : 
@@ -195,14 +195,14 @@
       91            0 :    output logic [31:0]                        lsu_nonblock_load_data,      // Data of the non block load
       92              : 
       93              :    // PMU events
-      94          668 :    output logic                         lsu_pmu_bus_trxn,
+      94          553 :    output logic                         lsu_pmu_bus_trxn,
       95            0 :    output logic                         lsu_pmu_bus_misaligned,
       96            0 :    output logic                         lsu_pmu_bus_error,
       97           12 :    output logic                         lsu_pmu_bus_busy,
       98              : 
       99              :    // AXI Write Channels
-     100          504 :    output logic                        lsu_axi_awvalid,
-     101          506 :    input  logic                        lsu_axi_awready,
+     100          389 :    output logic                        lsu_axi_awvalid,
+     101          390 :    input  logic                        lsu_axi_awready,
      102            0 :    output logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_awid,
      103            2 :    output logic [31:0]                 lsu_axi_awaddr,
      104            2 :    output logic [3:0]                  lsu_axi_awregion,
@@ -214,13 +214,13 @@
      110            0 :    output logic [2:0]                  lsu_axi_awprot,
      111            0 :    output logic [3:0]                  lsu_axi_awqos,
      112              : 
-     113          504 :    output logic                        lsu_axi_wvalid,
-     114          506 :    input  logic                        lsu_axi_wready,
+     113          389 :    output logic                        lsu_axi_wvalid,
+     114          390 :    input  logic                        lsu_axi_wready,
      115            0 :    output logic [63:0]                 lsu_axi_wdata,
      116           40 :    output logic [7:0]                  lsu_axi_wstrb,
      117            2 :    output logic                        lsu_axi_wlast,
      118              : 
-     119          504 :    input  logic                        lsu_axi_bvalid,
+     119          388 :    input  logic                        lsu_axi_bvalid,
      120            2 :    output logic                        lsu_axi_bready,
      121            0 :    input  logic [1:0]                  lsu_axi_bresp,
      122            0 :    input  logic [pt.LSU_BUS_TAG-1:0]   lsu_axi_bid,
@@ -263,8 +263,8 @@
      159            0 :    logic [31:0]       store_data_hi_r;
      160            0 :    logic [31:0]       store_data_lo_r;
      161              : 
-     162          726 :    logic              addr_match_dw_lo_r_m;
-     163          710 :    logic              addr_match_word_lo_r_m;
+     162          610 :    logic              addr_match_dw_lo_r_m;
+     163          594 :    logic              addr_match_word_lo_r_m;
      164           20 :    logic              no_word_merge_r, no_dword_merge_r;
      165              : 
      166            0 :    logic              ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_clkdomain.sv.html
index bc29a73c4e5..7838d035728 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31        17932 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32        17932 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31        14934 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32        14934 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -144,9 +144,9 @@
       40              : 
       41            0 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
       42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
-      43          700 :    input logic      lsu_busreq_r,                      // busreq in r
-      44          470 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
-      45          588 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
+      43          584 :    input logic      lsu_busreq_r,                      // busreq in r
+      44          355 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
+      45          472 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
       46            2 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
       47              : 
       48            2 :    input logic      lsu_bus_clk_en,                    // bus clock enable
@@ -157,39 +157,39 @@
       53          100 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
       54              : 
       55              :    // Outputs
-      56         1066 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
-      57          570 :    output logic     lsu_busm_clken,                    // bus clock enable
+      56          835 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
+      57          454 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59        17932 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60        17932 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59        14934 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60        14934 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62        17932 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63        17932 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62        14934 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63        14934 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65        17932 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66        17932 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65        14934 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66        14934 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68        17932 :    output logic     lsu_stbuf_c1_clk,
+      68        14934 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70        17932 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71        17932 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70        14934 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71        14934 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74        17932 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74        14934 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
       78              : 
-      79          708 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
-      80          708 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
-      81          708 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
-      82          484 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
+      79          592 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
+      80          592 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
+      81          592 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
+      82          368 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
       83              : 
       84              : 
       85            0 :    logic lsu_stbuf_c1_clken;
-      86          570 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
+      86          454 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
       87              : 
-      88          566 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
+      88          450 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
       89              : 
       90              :    //-------------------------------------------------------------------------------------------
       91              :    // Clock Enable logic
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_ctl.sv.html
index e6220f578e4..3b6a42b1d6e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,13 +136,13 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35        17932 :    input logic                             lsu_c2_m_clk,            // clocks
-      36        17932 :    input logic                             lsu_c2_r_clk,            // clocks
-      37        17932 :    input logic                             lsu_c1_r_clk,            // clocks
-      38        17932 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39        17932 :    input logic                             lsu_free_c2_clk,         // clocks
+      35        14934 :    input logic                             lsu_c2_m_clk,            // clocks
+      36        14934 :    input logic                             lsu_c2_r_clk,            // clocks
+      37        14934 :    input logic                             lsu_c1_r_clk,            // clocks
+      38        14934 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39        14934 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41        17932 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41        14934 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
@@ -155,7 +155,7 @@
       51            0 :    input logic                             addr_in_dccm_m, addr_in_dccm_r,   // address in dccm per pipe stage
       52            0 :    input logic                             addr_in_pic_r,                    // address in pic  per pipe stage
       53            0 :    input logic                             lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,
-      54          708 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
+      54          592 :    input logic                             lsu_commit_r,            // lsu instruction in r commits
       55            0 :    input logic                             ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage
       56              : 
       57              :    // lsu address down the pipe
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_mem.sv.html
index 227e09f75fe..74742b411f9 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35        17932 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36        17932 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35        14934 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        14934 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_ecc.sv.html
index f3a571d5d5a..e141705cca2 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,8 +135,8 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34        17932 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35        17932 :    input logic                           lsu_c2_r_clk,       // clock
+      34        14934 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        14934 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_lsc_ctl.sv.html
index cb2f7f29ae1..5e0902bf42e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35        17932 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        14934 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38        17932 :    input logic                lsu_c1_m_clk,
-      39        17932 :    input logic                lsu_c1_r_clk,
-      40        17932 :    input logic                lsu_c2_m_clk,
-      41        17932 :    input logic                lsu_c2_r_clk,
-      42        17932 :    input logic                lsu_store_c1_m_clk,
+      38        14934 :    input logic                lsu_c1_m_clk,
+      39        14934 :    input logic                lsu_c1_r_clk,
+      40        14934 :    input logic                lsu_c2_m_clk,
+      41        14934 :    input logic                lsu_c2_r_clk,
+      42        14934 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
@@ -164,7 +164,7 @@
       60            0 :    input logic [31:0]         exu_lsu_rs2_d,             // store data
       61              : 
       62          100 :    input el2_lsu_pkt_t       lsu_p,                     // lsu control packet
-      63          708 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
+      63          592 :    input logic                dec_lsu_valid_raw_d,       // Raw valid for address computation
       64           64 :    input logic [11:0]         dec_lsu_offset_d,          // 12b offset for load/store addresses
       65              : 
       66            0 :    input  logic [31:0]        picm_mask_data_m,          // PIC data M-stage
@@ -185,7 +185,7 @@
       81            0 :    input  logic [31:0]         dec_tlu_mrac_ff,          // CSR for memory region control
       82            0 :    output logic                lsu_exc_m,                // Access or misaligned fault
       83            0 :    output logic                is_sideeffects_m,         // is sideffects space
-      84          708 :    output logic                lsu_commit_r,             // lsu instruction in r commits
+      84          592 :    output logic                lsu_commit_r,             // lsu instruction in r commits
       85            0 :    output logic                lsu_single_ecc_error_incr,// LSU inc SB error counter
       86            0 :    output el2_lsu_error_pkt_t lsu_error_pkt_r,          // lsu exception packet
       87              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_stbuf.sv.html
index ce3da0b0077..dcddd762e42 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,16 +137,16 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36        17932 :    input logic                           clk,                         // core clock
+      36        14934 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39        17932 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40        17932 :    input logic                           lsu_free_c2_clk,             // free clk
+      39        14934 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40        14934 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
-      44          708 :    input logic                           lsu_commit_r,                // lsu commits
-      45          708 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
+      44          592 :    input logic                           lsu_commit_r,                // lsu commits
+      45          592 :    input logic                           dec_lsu_valid_raw_d,         // Speculative decode valid
       46            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_hi_r,             // merged data from the dccm for stores. This is used for fwding
       47            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_data_lo_r,             // merged data from the dccm for stores. This is used for fwding
       48            0 :    input logic [pt.DCCM_DATA_WIDTH-1:0]  store_datafn_hi_r,           // merged data from the dccm for stores
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_trigger.sv.html
index 70652f5f159..7c2236295c6 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem.sv.html
index d184cb39381..06f57c3e66f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25        17932 :    input logic         clk,
+      25        14934 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -164,8 +164,8 @@
       60            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
       61            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
       62            0 :    input  logic         ic_rd_en,
-      63          496 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
-      64         2514 :    input  logic         ic_sel_premux_data, // Premux data sel
+      63          474 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+      64         2049 :    input  logic         ic_sel_premux_data, // Premux data sel
       65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
       66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
       67              : 
@@ -178,7 +178,7 @@
       74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
       75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
       76              : 
-      77          496 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+      77          474 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
       78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
       79              : 
       80              : 
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92        17932 :    logic active_clk;
+      92        14934 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem_if.sv.html
index 2dd490b9fe3..3feb155dc90 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29        53796 :   logic                                                               clk;
+      29        44802 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pic_ctrl.sv.html
index 8d43b496d65..b62e9ea2adc 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              :  )
       28              :                   (
       29              : 
-      30        17932 :                      input  logic                   clk,                  // Core clock
-      31        17932 :                      input  logic                   free_clk,             // free clock
+      30        14934 :                      input  logic                   clk,                  // Core clock
+      31        14934 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
@@ -228,7 +228,7 @@
      124            0 : logic                                        intpriord;
      125            0 : logic                                        config_reg_we ;
      126            0 : logic                                        config_reg_re ;
-     127          284 : logic                                        config_reg_in ;
+     127          166 : logic                                        config_reg_in ;
      128            0 : logic                                        prithresh_reg_write , prithresh_reg_read;
      129            0 : logic                                        intpriority_reg_read ;
      130            0 : logic                                        intenable_reg_read   ;
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155        17932 :    logic                                     pic_raddr_c1_clk;
-     156        17932 :    logic                                     pic_data_c1_clk;
-     157        17932 :    logic                                     pic_pri_c1_clk;
-     158        17932 :    logic                                     pic_int_c1_clk;
-     159        17932 :    logic                                     gw_config_c1_clk;
+     155        14934 :    logic                                     pic_raddr_c1_clk;
+     156        14934 :    logic                                     pic_data_c1_clk;
+     157        14934 :    logic                                     pic_pri_c1_clk;
+     158        14934 :    logic                                     pic_int_c1_clk;
+     159        14934 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500       286912 :               if (intenable_reg_re[i]) begin
+     500       190976 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503       286912 :               if (intpriority_reg_re[i]) begin
+     503       190976 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506       286912 :               if (gw_config_reg_re[i]) begin
+     506       190976 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562       555892 :                              input logic rawclk,
+     562       462954 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pmp.sv.html
index 8faed70c596..8c0afff3cb2 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        40.4%
+    
+        39.2%
     
     
-        21
+        20
     
     
-        52
+        51
     
 
             
@@ -127,7 +127,7 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26        17932 :     input logic clk,       // Top level clock
+      26        14934 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133       451872 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133       307968 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139       451872 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139       307968 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            6 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -270,7 +270,7 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       460704 :       if (!matched && match_all[r]) begin
+     169       316800 :       if (!matched && match_all[r]) begin
      170            0 :         access_fail = ~final_perm_check[r];
      171            0 :         matched = 1'b1;
      172              :       end
@@ -348,7 +348,7 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247       430368 :           OFF:     region_match_all[c][r] = 1'b0;
+     247       286464 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
      250            0 :           TOR: begin
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer.sv.html
index a48f930f645..9d44bdf323b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29        17932 :    input logic                  clk,
+      29        14934 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
@@ -138,12 +138,12 @@
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37        17932 :    output logic                 active_l2clk,
-      38        17932 :    output logic                 free_l2clk,
+      37        14934 :    output logic                 active_l2clk,
+      38        14934 :    output logic                 free_l2clk,
       39              : 
       40          220 :    output logic [31:0] trace_rv_i_insn_ip,
       41            2 :    output logic [31:0] trace_rv_i_address_ip,
-      42         2764 :    output logic   trace_rv_i_valid_ip,
+      42         2304 :    output logic   trace_rv_i_valid_ip,
       43            0 :    output logic   trace_rv_i_exception_ip,
       44            0 :    output logic [4:0]  trace_rv_i_ecause_ip,
       45            0 :    output logic   trace_rv_i_interrupt_ip,
@@ -209,15 +209,15 @@
      105            0 :    output logic                  ic_rd_en,
      106              : 
      107           96 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
-     108          496 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+     108          474 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      109            0 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      112              : 
      113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
      114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
-     115          496 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
-     116         2514 :    output logic                      ic_sel_premux_data, // Select premux data
+     115          474 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
+     116         2049 :    output logic                      ic_sel_premux_data, // Select premux data
      117              : 
      118              : 
      119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
@@ -233,8 +233,8 @@
      129              : 
      130              :    //-------------------------- LSU AXI signals--------------------------
      131              :    // AXI Write Channels
-     132          504 :    output logic                            lsu_axi_awvalid,
-     133          506 :    input  logic                            lsu_axi_awready,
+     132          389 :    output logic                            lsu_axi_awvalid,
+     133          390 :    input  logic                            lsu_axi_awready,
      134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      135            2 :    output logic [31:0]                     lsu_axi_awaddr,
      136            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -246,13 +246,13 @@
      142            0 :    output logic [2:0]                      lsu_axi_awprot,
      143            0 :    output logic [3:0]                      lsu_axi_awqos,
      144              : 
-     145          504 :    output logic                            lsu_axi_wvalid,
-     146          506 :    input  logic                            lsu_axi_wready,
+     145          389 :    output logic                            lsu_axi_wvalid,
+     146          390 :    input  logic                            lsu_axi_wready,
      147            0 :    output logic [63:0]                     lsu_axi_wdata,
      148           40 :    output logic [7:0]                      lsu_axi_wstrb,
      149            2 :    output logic                            lsu_axi_wlast,
      150              : 
-     151          504 :    input  logic                            lsu_axi_bvalid,
+     151          388 :    input  logic                            lsu_axi_bvalid,
      152            2 :    output logic                            lsu_axi_bready,
      153            0 :    input  logic [1:0]                      lsu_axi_bresp,
      154            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
@@ -305,9 +305,9 @@
      201            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      202              : 
      203              :    // AXI Read Channels
-     204         2778 :    output logic                            ifu_axi_arvalid,
-     205         5556 :    input  logic                            ifu_axi_arready,
-     206         1724 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     204         2317 :    output logic                            ifu_axi_arvalid,
+     205         4635 :    input  logic                            ifu_axi_arready,
+     206         1378 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
      207           36 :    output logic [31:0]                     ifu_axi_araddr,
      208            2 :    output logic [3:0]                      ifu_axi_arregion,
      209            0 :    output logic [7:0]                      ifu_axi_arlen,
@@ -318,12 +318,12 @@
      214            2 :    output logic [2:0]                      ifu_axi_arprot,
      215            0 :    output logic [3:0]                      ifu_axi_arqos,
      216              : 
-     217         5554 :    input  logic                            ifu_axi_rvalid,
+     217         4633 :    input  logic                            ifu_axi_rvalid,
      218            2 :    output logic                            ifu_axi_rready,
-     219          960 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     220          200 :    input  logic [63:0]                     ifu_axi_rdata,
+     219          729 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     220          188 :    input  logic [63:0]                     ifu_axi_rdata,
      221            0 :    input  logic [1:0]                      ifu_axi_rresp,
-     222         5554 :    input  logic                            ifu_axi_rlast,
+     222         4633 :    input  logic                            ifu_axi_rlast,
      223              : 
      224              :    //-------------------------- SB AXI signals--------------------------
      225              :    // AXI Write Channels
@@ -501,7 +501,7 @@
      397              :    //
      398              :    //----------------------------------------------------------------------
      399              : 
-     400         2764 :    logic                         ifu_pmu_instr_aligned;
+     400         2306 :    logic                         ifu_pmu_instr_aligned;
      401            0 :    logic                         ifu_ic_error_start;
      402            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
      403            0 :    logic                         ifu_iccm_rd_ecc_single_err;
@@ -522,9 +522,9 @@
      418            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
      419            0 :    logic                         lsu_axi_rlast_ahb;
      420              : 
-     421          506 :    logic                         lsu_axi_awready_int;
-     422          506 :    logic                         lsu_axi_wready_int;
-     423          504 :    logic                         lsu_axi_bvalid_int;
+     421          390 :    logic                         lsu_axi_awready_int;
+     422          390 :    logic                         lsu_axi_wready_int;
+     423          388 :    logic                         lsu_axi_bvalid_int;
      424            2 :    logic                         lsu_axi_bready_int;
      425            0 :    logic [1:0]                   lsu_axi_bresp_int;
      426            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
@@ -554,12 +554,12 @@
      450            0 :    logic                         ifu_axi_bready_int;
      451            0 :    logic [1:0]                   ifu_axi_bresp_int;
      452            0 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
-     453         5556 :    logic                         ifu_axi_arready_int;
-     454         5554 :    logic                         ifu_axi_rvalid_int;
-     455          960 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
-     456          200 :    logic [63:0]                  ifu_axi_rdata_int;
+     453         4635 :    logic                         ifu_axi_arready_int;
+     454         4633 :    logic                         ifu_axi_rvalid_int;
+     455          729 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
+     456          188 :    logic [63:0]                  ifu_axi_rdata_int;
      457            0 :    logic [1:0]                   ifu_axi_rresp_int;
-     458         5554 :    logic                         ifu_axi_rlast_int;
+     458         4633 :    logic                         ifu_axi_rlast_int;
      459              : 
      460            0 :    logic                         sb_axi_awready_ahb;
      461            0 :    logic                         sb_axi_wready_ahb;
@@ -636,13 +636,13 @@
      532            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
      533              : 
      534              : 
-     535         2068 :    logic         dec_i0_rs1_en_d;
-     536         1080 :    logic         dec_i0_rs2_en_d;
-     537            4 :    logic  [31:0] gpr_i0_rs1_d;
-     538          268 :    logic  [31:0] gpr_i0_rs2_d;
+     535         1838 :    logic         dec_i0_rs1_en_d;
+     536          964 :    logic         dec_i0_rs2_en_d;
+     537            6 :    logic  [31:0] gpr_i0_rs1_d;
+     538          136 :    logic  [31:0] gpr_i0_rs2_d;
      539              : 
-     540            4 :    logic [31:0] dec_i0_result_r;
-     541           88 :    logic [31:0] exu_i0_result_x;
+     540            8 :    logic [31:0] dec_i0_result_r;
+     541           94 :    logic [31:0] exu_i0_result_x;
      542            2 :    logic [31:1] exu_i0_pc_x;
      543            2 :    logic [31:1] exu_npc_r;
      544              : 
@@ -653,26 +653,26 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552          272 :    logic [31:0] dec_i0_immed_d;
-     553          112 :    logic [12:1] dec_i0_br_immed_d;
-     554          276 :    logic         dec_i0_select_pc_d;
+     552          198 :    logic [31:0] dec_i0_immed_d;
+     553          100 :    logic [12:1] dec_i0_br_immed_d;
+     554          162 :    logic         dec_i0_select_pc_d;
      555              : 
      556           10 :    logic [31:1] dec_i0_pc_d;
      557            0 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
      558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
-     560         2116 :    logic         dec_i0_alu_decode_d;
-     561          768 :    logic         dec_i0_branch_d;
+     560         1774 :    logic         dec_i0_alu_decode_d;
+     561          652 :    logic         dec_i0_branch_d;
      562              : 
-     563         2780 :    logic         ifu_miss_state_idle;
+     563         2318 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
      565            0 :    logic         dec_tlu_flush_leak_one_r;
      566            0 :    logic         dec_tlu_flush_err_r;
-     567         2764 :    logic         ifu_i0_valid;
+     567         2306 :    logic         ifu_i0_valid;
      568           36 :    logic [31:0]  ifu_i0_instr;
      569           10 :    logic [31:1]  ifu_i0_pc;
      570              : 
-     571          204 :    logic        exu_flush_final;
+     571          190 :    logic        exu_flush_final;
      572              : 
      573            8 :    logic [31:1] exu_flush_path_final;
      574              : 
@@ -681,9 +681,9 @@
      577              : 
      578              : 
      579          100 :    el2_lsu_pkt_t    lsu_p;
-     580         2066 :    logic             dec_qual_lsu_d;
+     580         1724 :    logic             dec_qual_lsu_d;
      581              : 
-     582          708 :    logic        dec_lsu_valid_raw_d;
+     582          592 :    logic        dec_lsu_valid_raw_d;
      583           64 :    logic [11:0] dec_lsu_offset_d;
      584              : 
      585            0 :    logic [31:0]  lsu_result_m;
@@ -695,8 +695,8 @@
      591            2 :    logic [31:0]  lsu_imprecise_error_addr_any;
      592            8 :    logic         lsu_load_stall_any;       // This is for blocking loads
      593            8 :    logic         lsu_store_stall_any;      // This is for blocking stores
-     594          572 :    logic         lsu_idle_any;             // doesn't include DMA
-     595          570 :    logic         lsu_active;               // lsu is active. used for clock
+     594          456 :    logic         lsu_idle_any;             // doesn't include DMA
+     595          454 :    logic         lsu_active;               // lsu is active. used for clock
      596              : 
      597              : 
      598            0 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
@@ -712,11 +712,11 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            4 :    logic        dec_csr_ren_d;
-     611           16 :    logic [31:0] dec_csr_rddata_d;
+     611            8 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
-     615         2764 :    logic        dec_tlu_i0_commit_cmt;
+     615         2304 :    logic        dec_tlu_i0_commit_cmt;
      616            4 :    logic        dec_tlu_flush_lower_r;
      617            4 :    logic        dec_tlu_flush_lower_wb;
      618            0 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
@@ -725,7 +725,7 @@
      621            0 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624         1788 :    logic        ifu_i0_pc4;
+     624         1322 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
@@ -735,25 +735,25 @@
      631            0 :    logic [31:0] exu_div_result;
      632            0 :    logic exu_div_wren;
      633              : 
-     634         2764 :    logic dec_i0_decode_d;
+     634         2306 :    logic dec_i0_decode_d;
      635              : 
      636              : 
-     637          264 :    logic [31:1] pred_correct_npc_x;
+     637          149 :    logic [31:1] pred_correct_npc_x;
      638              : 
      639           84 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
      640              : 
      641            0 :    el2_predict_pkt_t  exu_mp_pkt;
-     642          132 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643           46 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     642          120 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
+     643           42 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
      644            8 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647           46 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648          346 :    logic [1:0]  exu_i0_br_hist_r;
+     647           42 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648          243 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651          470 :    logic        exu_i0_br_valid_r;
-     652          192 :    logic        exu_i0_br_mp_r;
+     651          355 :    logic        exu_i0_br_valid_r;
+     652          178 :    logic        exu_i0_br_mp_r;
      653          514 :    logic        exu_i0_br_middle_r;
      654              : 
      655           84 :    logic        exu_i0_br_way_r;
@@ -779,8 +779,8 @@
      675              : 
      676            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
      677            0 :    logic        dma_iccm_stall_any;       // Stall the fetch
-     678          710 :    logic        dccm_ready;
-     679          202 :    logic        iccm_ready;
+     678          594 :    logic        dccm_ready;
+     679          188 :    logic        iccm_ready;
      680              : 
      681            0 :    logic        dma_pmu_dccm_read;
      682            0 :    logic        dma_pmu_dccm_write;
@@ -797,7 +797,7 @@
      693              : 
      694          144 :    el2_br_pkt_t i0_brp;
      695           32 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696          218 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     696          202 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697            0 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
@@ -806,7 +806,7 @@
      702              : 
      703          144 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705          218 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     705          202 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
      706           32 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707            0 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
@@ -853,7 +853,7 @@
      749            0 :   logic        lsu_pmp_error_start;
      750           72 :   logic [31:0] lsu_pmp_addr_end;
      751            0 :   logic        lsu_pmp_error_end;
-     752          484 :   logic        lsu_pmp_we;
+     752          368 :   logic        lsu_pmp_we;
      753          224 :   logic        lsu_pmp_re;
      754              : 
      755              :    // -----------------------DEBUG  START -------------------------------
@@ -870,7 +870,7 @@
      766              : 
      767            0 :    logic                   core_dbg_cmd_done;         // Final muxed cmd done to debug
      768            0 :    logic                   core_dbg_cmd_fail;         // Final muxed cmd done to debug
-     769            4 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
+     769            8 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
      770              : 
      771            0 :    logic                   dma_dbg_cmd_done;          // Abstarct memory command sent to dma is done
      772            0 :    logic                   dma_dbg_cmd_fail;          // Abstarct memory command sent to dma failed
@@ -879,7 +879,7 @@
      775            0 :    logic                   dbg_dma_bubble;            // Debug needs a bubble to send a valid
      776            0 :    logic                   dma_dbg_ready;             // DMA is ready to accept debug request
      777              : 
-     778            4 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
+     778            8 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
      779            0 :    logic                   dec_dbg_cmd_done;          // This will be treated like a valid signal
      780            0 :    logic                   dec_dbg_cmd_fail;          // Abstract command failed
      781            0 :    logic                   dec_tlu_mpc_halted_only;   // Only halted due to MPC
@@ -889,32 +889,32 @@
      785            0 :    logic                   dec_debug_wdata_rs1_d;
      786            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
      787              : 
-     788         2764 :    logic [1:0]             dec_data_en;
-     789         2764 :    logic [1:0]             dec_ctl_en;
+     788         2305 :    logic [1:0]             dec_data_en;
+     789         2305 :    logic [1:0]             dec_ctl_en;
      790              : 
      791              :    // PMU Signals
-     792          192 :    logic                   exu_pmu_i0_br_misp;
-     793          494 :    logic                   exu_pmu_i0_br_ataken;
+     792          178 :    logic                   exu_pmu_i0_br_misp;
+     793          377 :    logic                   exu_pmu_i0_br_ataken;
      794          398 :    logic                   exu_pmu_i0_pc4;
      795              : 
      796          224 :    logic                   lsu_pmu_load_external_m;
-     797          484 :    logic                   lsu_pmu_store_external_m;
+     797          368 :    logic                   lsu_pmu_store_external_m;
      798            0 :    logic                   lsu_pmu_misaligned_m;
-     799          668 :    logic                   lsu_pmu_bus_trxn;
+     799          553 :    logic                   lsu_pmu_bus_trxn;
      800            0 :    logic                   lsu_pmu_bus_misaligned;
      801            0 :    logic                   lsu_pmu_bus_error;
      802           12 :    logic                   lsu_pmu_bus_busy;
      803              : 
-     804          170 :    logic                   ifu_pmu_fetch_stall;
-     805         2780 :    logic                   ifu_pmu_ic_miss;
+     804          158 :    logic                   ifu_pmu_fetch_stall;
+     805         2318 :    logic                   ifu_pmu_ic_miss;
      806            0 :    logic                   ifu_pmu_ic_hit;
      807            0 :    logic                   ifu_pmu_bus_error;
-     808         2776 :    logic                   ifu_pmu_bus_busy;
-     809         5554 :    logic                   ifu_pmu_bus_trxn;
+     808         2316 :    logic                   ifu_pmu_bus_busy;
+     809         4633 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812        17932 :    logic                   free_clk;
-     813        17932 :    logic                   active_clk;
+     812        14934 :    logic                   free_clk;
+     813        14934 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
@@ -925,7 +925,7 @@
      821            0 :    logic [31:2]            dec_tlu_meihap;
      822            0 :    logic                   dec_extint_stall;
      823              : 
-     824         2764 :    el2_trace_pkt_t  trace_rv_trace_pkt;
+     824         2304 :    el2_trace_pkt_t  trace_rv_trace_pkt;
      825              : 
      826              : 
      827            0 :    logic                   lsu_fastint_stall_any;
@@ -941,7 +941,7 @@
      837            0 :    logic        pause_state;
      838            0 :    logic        halt_state;
      839              : 
-     840          496 :    logic        dec_tlu_core_empty;
+     840          494 :    logic        dec_tlu_core_empty;
      841              : 
      842              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
      843              : 
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer_wrapper.sv.html
index 4f06034ce6c..d29840833d6 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30        17932 :    input logic                             clk,
+      30        14934 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
@@ -142,7 +142,7 @@
       38              : 
       39          220 :    output logic [31:0]                     trace_rv_i_insn_ip,
       40            2 :    output logic [31:0]                     trace_rv_i_address_ip,
-      41         2764 :    output logic                            trace_rv_i_valid_ip,
+      41         2304 :    output logic                            trace_rv_i_valid_ip,
       42            0 :    output logic                            trace_rv_i_exception_ip,
       43            0 :    output logic [4:0]                      trace_rv_i_ecause_ip,
       44            0 :    output logic                            trace_rv_i_interrupt_ip,
@@ -152,8 +152,8 @@
       48              : `ifdef RV_BUILD_AXI4
       49              :    //-------------------------- LSU AXI signals--------------------------
       50              :    // AXI Write Channels
-      51          504 :    output logic                            lsu_axi_awvalid,
-      52          506 :    input  logic                            lsu_axi_awready,
+      51          389 :    output logic                            lsu_axi_awvalid,
+      52          390 :    input  logic                            lsu_axi_awready,
       53            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
       54            2 :    output logic [31:0]                     lsu_axi_awaddr,
       55            2 :    output logic [3:0]                      lsu_axi_awregion,
@@ -165,13 +165,13 @@
       61            0 :    output logic [2:0]                      lsu_axi_awprot,
       62            0 :    output logic [3:0]                      lsu_axi_awqos,
       63              : 
-      64          504 :    output logic                            lsu_axi_wvalid,
-      65          506 :    input  logic                            lsu_axi_wready,
+      64          389 :    output logic                            lsu_axi_wvalid,
+      65          390 :    input  logic                            lsu_axi_wready,
       66            0 :    output logic [63:0]                     lsu_axi_wdata,
       67           40 :    output logic [7:0]                      lsu_axi_wstrb,
       68            2 :    output logic                            lsu_axi_wlast,
       69              : 
-      70          504 :    input  logic                            lsu_axi_bvalid,
+      70          388 :    input  logic                            lsu_axi_bvalid,
       71            2 :    output logic                            lsu_axi_bready,
       72            0 :    input  logic [1:0]                      lsu_axi_bresp,
       73            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
@@ -224,9 +224,9 @@
      120            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
      121              : 
      122              :    // AXI Read Channels
-     123         2778 :    output logic                            ifu_axi_arvalid,
-     124         5556 :    input  logic                            ifu_axi_arready,
-     125         1724 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
+     123         2317 :    output logic                            ifu_axi_arvalid,
+     124         4635 :    input  logic                            ifu_axi_arready,
+     125         1378 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
      126           36 :    output logic [31:0]                     ifu_axi_araddr,
      127            2 :    output logic [3:0]                      ifu_axi_arregion,
      128            0 :    output logic [7:0]                      ifu_axi_arlen,
@@ -237,12 +237,12 @@
      133            2 :    output logic [2:0]                      ifu_axi_arprot,
      134            0 :    output logic [3:0]                      ifu_axi_arqos,
      135              : 
-     136         5554 :    input  logic                            ifu_axi_rvalid,
+     136         4633 :    input  logic                            ifu_axi_rvalid,
      137            2 :    output logic                            ifu_axi_rready,
-     138          960 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
-     139          200 :    input  logic [63:0]                     ifu_axi_rdata,
+     138          729 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
+     139          188 :    input  logic [63:0]                     ifu_axi_rdata,
      140            0 :    input  logic [1:0]                      ifu_axi_rresp,
-     141         5554 :    input  logic                            ifu_axi_rlast,
+     141         4633 :    input  logic                            ifu_axi_rlast,
      142              : 
      143              :    //-------------------------- SB AXI signals--------------------------
      144              :    // AXI Write Channels
@@ -454,8 +454,8 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353        17932 :    logic                             active_l2clk;
-     354        17932 :    logic                             free_l2clk;
+     353        14934 :    logic                             active_l2clk;
+     354        14934 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
@@ -491,15 +491,15 @@
      387              : 
      388            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
      389           96 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
-     390          496 :    logic [63:0]  ic_rd_data;
+     390          474 :    logic [63:0]  ic_rd_data;
      391            0 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      392            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
      393              : 
      394            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
      395            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
      396              : 
-     397          496 :    logic [63:0]  ic_premux_data;
-     398         2514 :    logic         ic_sel_premux_data;
+     397          474 :    logic [63:0]  ic_premux_data;
+     398         2049 :    logic         ic_sel_premux_data;
      399              : 
      400              :    // ICCM ports
      401            8 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_mem_lib.sv.html
index 803428ff025..b9998072925 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111       143424 : `EL2_RAM(4096, 39)
+     111        95456 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175        35856 : `EL2_RAM_BE(512, 142)
+     175        23864 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208        17928 : `EL2_RAM_BE(128, 52)
+     208        11932 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_axi_csr_misa/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_csr_misa/index_rvjtag_tap.v.html
index 0344e6d9d64..61292e2e8ef 100644
--- a/html/main/coverage_dashboard/all_axi_csr_misa/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_misa/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index.html
index 5ebc19a27c6..0dc8686ae08 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design.html
index 743756d5a8c..207d43d486c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html
index fc53866136a..f44ba985679 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html
index 8648a08236c..6b3fd216477 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html
index 18b8f85784c..4af8efca7de 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html
index c9cae732438..fb9d13a8073 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html
index 5c4d9e7a747..46939052bd4 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html
index c152508d316..a9103cc9b7a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html
index d20c0a882a2..a7a84ec8e1c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html
index 34639a04610..be7aa919ef0 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_beh_lib.sv.html
index 4b8c6b547bd..6df0113dca8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html
index f364d42de4c..b02d1f0d1d8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_mux.v.html
index c6099a1dd64..b125a44fbea 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_wrapper.v.html
index 018b735cb93..8ba04a1a5a4 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dbg.sv.html
index cc5eb0f5c20..05f25bd59c1 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec.sv.html
index 67476b26ffb..601168c1222 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html
index d57b6763eb8..f55affb0951 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_decode_ctl.sv.html
index 9dca7ccd1e2..a4582f9f320 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html
index 677be4471e5..e42982489ae 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_ib_ctl.sv.html
index 9ed83f57a8c..18f6f9d2e8b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html
index 85c3c27f6e1..6329ba6bf5e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html
index 10878c131f5..5bd7a31545b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_trigger.sv.html
index c1f3d5d74ed..ba394d4b68a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dma_ctrl.sv.html
index 9918eaa04d3..3c6bda0c6c5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu.sv.html
index ca5618ddac9..742c4524b04 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_alu_ctl.sv.html
index 2a81d487179..bb20f020f11 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_div_ctl.sv.html
index d463b30b668..155284676db 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_mul_ctl.sv.html
index 72ffe42d935..43df54bca14 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu.sv.html
index 857ac1dc4b0..54398bd87bb 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html
index 03e838fd15d..9fa56144799 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html
index 6d230b336c9..adcd74614a5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html
index 51660aefe4a..6799ca88c10 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ic_mem.sv.html
index 62561a6c323..99eb18e0fa3 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html
index 49f4d724f50..7630b651781 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html
index 4848444cbf3..2d105a8e78b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html
index c54e6fc90bc..b06524f71d6 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lib.sv.html
index dad3d3e297b..78265692f44 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu.sv.html
index b5fc09ffcf0..7047414409e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_addrcheck.sv.html
index 9c3b90551e9..201c745ff0b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html
index 9c8db51059e..9f553df5947 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_intf.sv.html
index d2f0d92fc8b..aceb10fb9b0 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_clkdomain.sv.html
index 5cdf5c281a7..d445ca0446c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html
index a592a26c65a..fea843fd182 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html
index b08c76e5c3b..91753a83638 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_ecc.sv.html
index fcc7cc050af..d86d29d401f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html
index ea85ca11a73..04b4a046352 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_stbuf.sv.html
index c520be59f8c..992edc5633a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_trigger.sv.html
index 9192199277e..edbf9ff7562 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem.sv.html
index dc76dc849b9..ff57eca29f7 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem_if.sv.html
index f21b2193a93..f2260dc2bdc 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pic_ctrl.sv.html
index 97d764bc36c..95e6ddbc269 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pmp.sv.html
index 7ab6c5e9fc0..bf150f161aa 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer.sv.html
index c775dc44508..d97f23499ed 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer_wrapper.sv.html
index e0359483946..3dbd43e89bf 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_mem_lib.sv.html
index 4a60a3b14dc..862072c6be7 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_rvjtag_tap.v.html
index d601d3e6d63..6c42576b9aa 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mseccfg/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index.html
index 8ded5b5bfe2..1cb53fa86f0 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design.html
index f28aeabdb4e..2e2852a7b43 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html
index daad7416186..d798fb1863f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html
index 04b83d36450..bd1cf9684d2 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html
index 383df2efcf1..28a95fe4100 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html
index d8618983b78..c064ccd6900 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html
index f4841b44a2c..cad53d4f566 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_include.html
index 13d03627dda..f54aec3fc35 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html
index d6c283ac7f8..ce8299fb059 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html
index 7db9da85802..2d73685cf78 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_beh_lib.sv.html
index c7ec6c0576a..49bef463472 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_jtag_to_core_sync.v.html
index 99ff3f3ce7e..b4f21a6b5fc 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_mux.v.html
index f663822bff6..17b9311d388 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_wrapper.v.html
index 434fa4f2aa2..fd68940a4d7 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dbg.sv.html
index 347a22abd03..17b872be223 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec.sv.html
index 2362a18b175..e4be791237b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_csr_equ_mu.svh.html
index bf85bb59c2a..30cabebc4eb 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_decode_ctl.sv.html
index d9785ca0d4a..e2f7853eaf5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_gpr_ctl.sv.html
index d65dc275305..d267cfce8a5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_ib_ctl.sv.html
index 10649053913..1694df52e5c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_pmp_ctl.sv.html
index 0a8d16490c3..4863028412c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_tlu_ctl.sv.html
index a8f8b013db3..45003d877c8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_trigger.sv.html
index d2a557691c3..018dedda3bd 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dma_ctrl.sv.html
index f49b912829f..55b7ecee0b0 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu.sv.html
index eea90a73d21..fd6b69c0d2d 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_alu_ctl.sv.html
index ad3f78f6089..1afc74770a4 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_div_ctl.sv.html
index 6baf40c4652..38314d9cf1c 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_mul_ctl.sv.html
index a9134cd1f38..47007e14036 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu.sv.html
index a93a848b4bb..03d3a66c39a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_aln_ctl.sv.html
index 6b51f164657..8aecfa1769a 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_bp_ctl.sv.html
index e4b1f9808e4..acecd6d2e5b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_compress_ctl.sv.html
index f5a1ec4b108..dff1a126980 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ic_mem.sv.html
index f56a7dc5d96..369b3a727e5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_iccm_mem.sv.html
index b279b0683d3..2fc0c1cec98 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html
index b54b29cf215..5edeadcf796 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_mem_ctl.sv.html
index 9741384a926..f0cebe845da 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lib.sv.html
index d222d7882a4..0e5abb46ec8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu.sv.html
index 8baad68baa4..b1bb4d37c82 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_addrcheck.sv.html
index 7797991b9cf..8f264d4f2c2 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_buffer.sv.html
index 79e421d6264..74dd9138913 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_intf.sv.html
index a993821bc9b..94fc59b0dce 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_clkdomain.sv.html
index 8d479eb503a..27e9cf8b306 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html
index d40f3481b73..9adb7cbbc4e 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_mem.sv.html
index f892530a286..292ac634c68 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_ecc.sv.html
index a684b15b525..5d8c513983b 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html
index ebdeaee9d32..0b8305b8dff 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_stbuf.sv.html
index 859dcc910a5..c93d95a81f7 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_trigger.sv.html
index 4d91c2c6c6d..f5cedbb8e89 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem.sv.html
index 8e2d4f784ae..dec23c75bf9 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem_if.sv.html
index b05937cf228..0e4f104c7f5 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pic_ctrl.sv.html
index 5ce1b6aadb5..182c9ec31ad 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pmp.sv.html
index de7bfe14793..b39805cc584 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer.sv.html
index 727fe62a1cf..43acddea1ae 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer_wrapper.sv.html
index eafca16c643..00fc2e87e88 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_mem_lib.sv.html
index 2b84df51e38..b9bb99f99e8 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_rvjtag_tap.v.html
index 1317957df93..eaaaec3be8f 100644
--- a/html/main/coverage_dashboard/all_axi_csr_mstatus/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_csr_mstatus/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index.html b/html/main/coverage_dashboard/all_axi_dhry/index.html
index e862a8f0650..324221403db 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        42.3%
+    
+        42.1%
     
     
-        2172
+        2182
     
     
-        5131
+        5178
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    25.1%
+                    25.0%
                 
             
 
             
-                318
+                319
                 /
-                1265
+                1275
             
         
             
@@ -275,21 +275,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    40.5%
+                    40.3%
                 
             
 
             
-                400
+                406
                 /
-                987
+                1007
             
         
             
@@ -411,19 +411,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    59.7%
+                    60.3%
                 
             
 
             
-                206
+                208
                 /
                 345
             
@@ -547,21 +547,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    8.3%
+                    7.9%
                 
             
 
             
-                7
+                8
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design.html
index 1f216838d56..998a573f8a0 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        25.1%
+    
+        25.0%
     
     
-        318
+        319
     
     
-        1265
+        1275
     
 
       
@@ -343,21 +343,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.0%
+                    35.0%
                 
             
 
             
                 7
                 /
-                14
+                20
             
         
             
@@ -411,7 +411,7 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
@@ -423,9 +423,9 @@
             
 
             
-                179
+                180
                 /
-                627
+                631
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dbg.html
index 5f1aa96957f..806ecfdf2d9 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dec.html
index a0f12079927..336aef0b29d 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dec.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        40.5%
+    
+        40.3%
     
     
-        400
+        406
     
     
-        987
+        1007
     
 
       
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    42.7%
+                    42.4%
                 
             
 
             
-                108
+                109
                 /
-                253
+                257
             
         
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    60.4%
+                    60.7%
                 
             
 
             
-                166
+                167
                 /
                 275
             
@@ -411,21 +411,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    21.9%
+                    21.2%
                 
             
 
             
                 7
                 /
-                32
+                33
             
         
             
@@ -479,21 +479,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
             
                 
-                    24.7%
+                    24.8%
                 
             
 
             
-                89
+                93
                 /
-                360
+                375
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dmi.html
index b049ac69e77..3cc4bafc9b9 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_exu.html
index 4e380a37135..0112dfe6dc3 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_exu.html
@@ -51,18 +51,18 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        59.7%
+    
+        60.3%
     
     
-        206
+        208
     
     
         345
@@ -139,19 +139,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    81.0%
+                    82.0%
                 
             
 
             
-                81
+                82
                 /
                 100
             
@@ -207,19 +207,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    50.0%
+                    51.1%
                 
             
 
             
-                44
+                45
                 /
                 88
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_ifu.html
index 00e8eeb6211..6392d7b9e97 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_include.html
index 1c412b5daf9..4234c3c8872 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_include.html
@@ -51,21 +51,21 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
     
         Toggle
     
-    
-        8.3%
+    
+        7.9%
     
     
-        7
+        8
     
     
-        84
+        101
     
 
       
@@ -121,8 +121,8 @@
     
         
             
-            
-                el2_dec_csr_equ_m.svh
+            
+                el2_dec_csr_equ_mu.svh
             
             
         
@@ -139,21 +139,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    8.3%
+                    7.9%
                 
             
 
             
-                7
+                8
                 /
-                84
+                101
             
         
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lib.html
index 7ca8d8c31d1..f9fa09cc030 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lsu.html
index 4ecca661a26..b901fac801e 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_beh_lib.sv.html
index f4d5b6aa80a..03eebfa10d7 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_dhry/index_dmi_jtag_to_core_sync.v.html
index e190468e768..ec8d7c21f63 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_dhry/index_dmi_mux.v.html
index 6bf61edbf2e..479b96a22bc 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_dhry/index_dmi_wrapper.v.html
index ebc8ffc40db..32f2aae97a8 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dbg.sv.html
index 07de4cd91f1..cca51a6dce9 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec.sv.html
index b40cd6b717d..74a4b8935f5 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        42.7%
+    
+        42.4%
     
     
-        108
+        109
     
     
-        253
+        257
     
 
             
diff --git a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_csr_equ_mu.svh.html
similarity index 99%
rename from html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_csr_equ_mu.svh.html
rename to html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_csr_equ_mu.svh.html
index 157db8e6128..f69bc323cba 100644
--- a/html/main/coverage_dashboard/all_ahb_dhry/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -72,7 +72,7 @@
             
                 Test:
                 
-                    ahb_dhry
+                    axi_dhry
                 
                 
                 
@@ -107,7 +107,7 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           13 : logic csr_mstatus;
+       6           11 : logic csr_mstatus;
        7            2 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
@@ -185,7 +185,7 @@
       81            0 : logic csr_pmpaddr16;
       82            0 : logic csr_pmpaddr32;
       83            0 : logic csr_pmpaddr48;
-      84           13 : logic csr_cyclel;
+      84           11 : logic csr_cyclel;
       85            0 : logic csr_cycleh;
       86            0 : logic csr_instretl;
       87            0 : logic csr_instreth;
@@ -201,7 +201,7 @@
       97            0 : logic csr_mseccfgh;
       98            0 : logic valid_only;
       99            0 : logic presync;
-     100            9 : logic postsync;
+     100            7 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444           12 : logic legal;
+     444           10 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_decode_ctl.sv.html
index ed3bc72b47f..505f8d71677 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_decode_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        60.4%
+    
+        60.7%
     
     
-        166
+        167
     
     
         275
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_gpr_ctl.sv.html
index 4d48b41e35f..c1d3b9b3506 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_ib_ctl.sv.html
index f15f40d0f94..f13669f1261 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_pmp_ctl.sv.html
index 87134ef8732..3636d617c4c 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_pmp_ctl.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        21.9%
+    
+        21.2%
     
     
         7
     
     
-        32
+        33
     
 
             
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_tlu_ctl.sv.html
index 79351e2c895..8cfb793ec9f 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -59,13 +59,13 @@
         Toggle
     
     
-        24.7%
+        24.8%
     
     
-        89
+        93
     
     
-        360
+        375
     
 
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_trigger.sv.html
index 645834fddf5..838ceb68338 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dma_ctrl.sv.html
index 14539554714..b6d625e5833 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu.sv.html
index 8cc2544df08..a307786d69e 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        81.0%
+    
+        82.0%
     
     
-        81
+        82
     
     
         100
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_alu_ctl.sv.html
index 74463238a26..f9e4d6f6b32 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_alu_ctl.sv.html
@@ -51,18 +51,18 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.0%
+    
+        51.1%
     
     
-        44
+        45
     
     
         88
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_div_ctl.sv.html
index f972e2aa409..26fb225c7ea 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_mul_ctl.sv.html
index 3756f0633c6..486f6fdb591 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu.sv.html
index a6209418df8..e65e1249832 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_aln_ctl.sv.html
index 11204753add..4573e1cd792 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_bp_ctl.sv.html
index c4648d4b72d..3e6e9e4dd5a 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_compress_ctl.sv.html
index c38a05484d6..9001f550007 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ic_mem.sv.html
index 33e64ca8da6..3077540d0f3 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_iccm_mem.sv.html
index e9fff91a266..8b25038c76a 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ifc_ctl.sv.html
index 1c57831575d..5b5fdb1ad87 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_mem_ctl.sv.html
index 75d55d14a60..cde7fb7daa7 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lib.sv.html
index 1f3d89c6411..5e43e9fb2a7 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu.sv.html
index d1d80019cbd..3e949a3f511 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_addrcheck.sv.html
index 6346f510a8c..ac91ec591d5 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_buffer.sv.html
index a974530e0ab..7a3bcbaf9b3 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_intf.sv.html
index c6c87cf9114..2645936f86d 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_clkdomain.sv.html
index 4d1483399f6..0dd2ef186ca 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_ctl.sv.html
index 9ebd8d377d6..1b6dfce247d 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_mem.sv.html
index 48bf9e255d3..0f8dcdf369e 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_ecc.sv.html
index 8ee867acf47..8e80f27c383 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_lsc_ctl.sv.html
index 835f398da0c..098cc6f1c5a 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_stbuf.sv.html
index 4eb5f6f07b9..813eeb9f775 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_trigger.sv.html
index 865506974ec..0f7a4b9ae74 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem.sv.html
index e25b7d648b0..b5cd7289a79 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem_if.sv.html
index 1cc79225a13..db7287e9853 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_pic_ctrl.sv.html
index af9a2f82599..2f370483f00 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_pmp.sv.html
index 8f3f1babda7..2509e3bfb2c 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_pmp.sv.html
@@ -51,21 +51,21 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
     
         Toggle
     
-    
-        50.0%
+    
+        35.0%
     
     
         7
     
     
-        14
+        20
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161              :     logic access_fail = 1'b0;
+     161            3 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer.sv.html
index 120a05ca872..86866149cd6 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -62,10 +62,10 @@
         28.5%
     
     
-        179
+        180
     
     
-        627
+        631
     
 
             
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer_wrapper.sv.html
index 01ec3d82744..1b68ddce2d0 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_dhry/index_mem_lib.sv.html
index 307288e1b13..fdfb267ca9b 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_dhry/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_dhry/index_rvjtag_tap.v.html
index 0e935819cc1..946c18f492a 100644
--- a/html/main/coverage_dashboard/all_axi_dhry/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_dhry/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index.html b/html/main/coverage_dashboard/all_axi_ecc/index.html
index 4555576ce90..233572c9fc1 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design.html
index f6a3833532b..c306908c217 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dbg.html
index 74a73894e14..e31c361b8aa 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dec.html
index eed4990d830..aad85719103 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dmi.html
index 15bd392e098..5dde5854721 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_exu.html
index dfc3eb82629..4149d2471cf 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_ifu.html
index 0ccfcc05d7d..e4342ffc7ab 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_include.html
index 1f093223a25..81effeba3d1 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lib.html
index fe2f8704508..e9d0c86a801 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lsu.html
index 3895746ebbe..1f7c838fa77 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_beh_lib.sv.html
index 869934d92ea..6ed04999952 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_ecc/index_dmi_jtag_to_core_sync.v.html
index 356645bb374..14c235aaa2a 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_ecc/index_dmi_mux.v.html
index 9c170607700..b01afd1b77e 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_ecc/index_dmi_wrapper.v.html
index ad236857eea..3f572ed277c 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dbg.sv.html
index 3c06628dae5..172e38341e7 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec.sv.html
index f2d1137084f..d74f700f2b3 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_csr_equ_m.svh.html
index d6b705a7192..30abd1525f4 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_decode_ctl.sv.html
index 68e5a0fb081..a8249e9a780 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_gpr_ctl.sv.html
index 446fd346d24..2e6bc5c0942 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_ib_ctl.sv.html
index 699ee5f9ec7..c5f33b86088 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_pmp_ctl.sv.html
index 100c364d11f..2d679d41b95 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_tlu_ctl.sv.html
index c5f54e5b659..26b3edb1017 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_trigger.sv.html
index b97bca5a836..dd1b2625e15 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dma_ctrl.sv.html
index e4bd8a977ef..2ca548e2d27 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu.sv.html
index dc9009c1f23..4df76b2edf6 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_alu_ctl.sv.html
index e32cf7f3abc..922ca701082 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_div_ctl.sv.html
index eb731e2c948..b58cb391903 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_mul_ctl.sv.html
index 6828f4ee484..0af089a3a78 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu.sv.html
index 8a0b598b523..385c20c6cb5 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_aln_ctl.sv.html
index 96c5c4d4739..d666a75af25 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_bp_ctl.sv.html
index 82939fdd5a5..4164d27e64d 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_compress_ctl.sv.html
index 5fc51210716..b7e0eff3aa9 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ic_mem.sv.html
index d3861ecf052..45203f74c28 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_iccm_mem.sv.html
index 33ce0bbcba0..03b1839dbef 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ifc_ctl.sv.html
index 7864b3fc7db..8047445ca5c 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_mem_ctl.sv.html
index a0d73ba95b5..9c20b680aff 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lib.sv.html
index f04218d036a..19cfa6c3295 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu.sv.html
index 2eef55f43ac..31a7bb87b58 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_addrcheck.sv.html
index 8bc126cc5b8..1f92d1086bb 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_buffer.sv.html
index 930d8796c10..97d752b4bd7 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_intf.sv.html
index 63cfc70eabc..a04c593dac7 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_clkdomain.sv.html
index 868f1f8178e..51897f6b443 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_ctl.sv.html
index 4ab33f8432a..907c312e6cc 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_mem.sv.html
index 5cab6fea5cf..40aa9eef743 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_ecc.sv.html
index 2e0f7ac1321..2a61c238837 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_lsc_ctl.sv.html
index bee81f4f35d..8a18ac90f8b 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_stbuf.sv.html
index f7ae730b3b0..d80ea64dac2 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_trigger.sv.html
index b083abde0b0..6f0e10b130e 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem.sv.html
index a2ec05fbc33..5537876db5a 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem_if.sv.html
index 64d6561bfc3..15a35f2f4b7 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_pic_ctrl.sv.html
index 67492af4ca9..03d5c454c83 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_pmp.sv.html
index 436e6cec1bc..657392ab71c 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer.sv.html
index dac779e9bc1..7731db332e8 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer_wrapper.sv.html
index f55d4327f8c..009fd4949f6 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_ecc/index_mem_lib.sv.html
index 80dfb0251a9..8fd60754abe 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_ecc/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_ecc/index_rvjtag_tap.v.html
index bb2ec3e3fca..5ba4ced5ac2 100644
--- a/html/main/coverage_dashboard/all_axi_ecc/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_ecc/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index.html b/html/main/coverage_dashboard/all_axi_hello_world/index.html
index 9b4bed04a0b..e6a1a36c759 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design.html
index 3d8c796817b..b729d28bb06 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dbg.html
index d0bdf322ce9..b492d8135c6 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dec.html
index e91d0db707a..eac8ab8546d 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dmi.html
index bcec71edd38..5f8e81a0b5b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_exu.html
index 1231bbdd548..a66a14a1173 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_ifu.html
index ec03cad531d..93101c17066 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_include.html
index b0c00f2b784..aa4b00168cb 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lib.html
index 9b84b076b02..7754af04570 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lsu.html
index 86bcb78c481..64a126a2e9d 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_beh_lib.sv.html
index d974ccfae96..fe6ac140a8a 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_jtag_to_core_sync.v.html
index 3b393d0ae0d..8e2391cfdb4 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_mux.v.html
index c3360e68828..06f36d905cb 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_wrapper.v.html
index 8c5912e02da..49e63a11ea4 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dbg.sv.html
index 5c333894e19..0ef1f491b61 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec.sv.html
index 6ac65255409..d090688e866 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -354,7 +354,7 @@
      250            0 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            0 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253           10 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253            3 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255           16 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256           16 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_csr_equ_m.svh.html
index 11b224fcdd9..36dbdf8c53d 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -107,20 +107,20 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           23 : logic csr_mstatus;
-       7            6 : logic csr_mtvec;
+       6           41 : logic csr_mstatus;
+       7           10 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
       10            0 : logic csr_mcyclel;
       11            0 : logic csr_mcycleh;
-      12            2 : logic csr_minstretl;
-      13            2 : logic csr_minstreth;
+      12            6 : logic csr_minstretl;
+      13            6 : logic csr_minstreth;
       14            0 : logic csr_mscratch;
       15            0 : logic csr_mepc;
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            6 : logic csr_mrac;
+      19           10 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -183,8 +183,8 @@
       79            0 : logic csr_pmpaddr32;
       80            0 : logic csr_pmpaddr48;
       81            0 : logic valid_only;
-      82            8 : logic presync;
-      83            7 : logic postsync;
+      82           16 : logic presync;
+      83           17 : logic postsync;
       84              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
       85              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
       86              : 
@@ -471,7 +471,7 @@
      367              :     &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
      368              :     &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);
      369              : 
-     370           20 : logic legal;
+     370           36 : logic legal;
      371              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      372              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      373              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_decode_ctl.sv.html
index a20db9ad588..a965ed00903 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89         1458 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91           10 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91            3 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           44 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_gpr_ctl.sv.html
index 4e3a6819a59..a3a2d270bc2 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_ib_ctl.sv.html
index 2e3360cedbc..3ab827abda2 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_pmp_ctl.sv.html
index 972878dca40..15a10afbe80 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_tlu_ctl.sv.html
index d876687746c..897b29f3564 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183           10 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183            3 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           44 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186            0 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -379,7 +379,7 @@
      275            0 :    logic wr_mcounteren_r;
      276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277            0 :    logic wr_mseccfg_r;
-     278            6 :    logic [2:0] mseccfg_ns;
+     278            2 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484           27 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         4966 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484            9 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485         1656 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_trigger.sv.html
index ee706516fb1..590c2aa773c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dma_ctrl.sv.html
index e40d63314f9..0b6e4c87cee 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu.sv.html
index 40360873b3b..683c97c7726 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53          744 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            0 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55           10 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55            3 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57         9204 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_alu_ctl.sv.html
index 88c5b7b30a7..a980f165f2e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30         9198 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            0 :    input  logic                  csr_ren_in,         // CSR select
-      33           10 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33            3 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34            0 :    input  logic signed [31:0]    a_in,               // A operand
       35           12 :    input  logic        [31:0]    b_in,               // B operand
       36            0 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_div_ctl.sv.html
index 9a38a4db92f..38c20235cdd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_mul_ctl.sv.html
index 2c7ae351a98..b26686b7977 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu.sv.html
index 2430ad9033e..dda7fe7f941 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_aln_ctl.sv.html
index 6f0b2eae48d..f0b15f2b354 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_bp_ctl.sv.html
index 88b1c10238f..8b41da460bc 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_compress_ctl.sv.html
index 98c0e5e1b71..88bbf7b40dd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ic_mem.sv.html
index a482446eb61..236a6de927c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_iccm_mem.sv.html
index 870caa45ec2..bf97ca4007e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ifc_ctl.sv.html
index 39f80767b65..7d5edba2944 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_mem_ctl.sv.html
index 9470701c968..389bc89404e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lib.sv.html
index 0b096752102..0e4af5428cf 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu.sv.html
index 2f7f69cfc4c..c3b6fc2cd71 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_addrcheck.sv.html
index 588ce86c4ca..a7eb4fb8ff9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_buffer.sv.html
index 47d2f412f74..fe350764312 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_intf.sv.html
index 2925c2b60f4..8a487a74410 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_clkdomain.sv.html
index 2eea35bce10..df66abc6d02 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_ctl.sv.html
index 2c8e83be450..901c5718f90 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_mem.sv.html
index b84c0b1e8ab..96c3790d0c2 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_ecc.sv.html
index 3c2097fb7cd..0ce72f0b35e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_lsc_ctl.sv.html
index 0d38764bb3d..dd2fd2cf784 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_stbuf.sv.html
index e756a2eab91..aa8f6031bb2 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_trigger.sv.html
index ee45e1e3774..ba409c2771b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem.sv.html
index b8c06db5359..f26dec82662 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem_if.sv.html
index df0d9aab7e1..22beebc3a8d 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pic_ctrl.sv.html
index 24c3797ab92..9a3ca265d97 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pmp.sv.html
index b00ad354eee..1a70f6fd492 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer.sv.html
index 2295a4349aa..94b19c59d49 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -712,7 +712,7 @@
      608            4 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            0 :    logic        dec_csr_ren_d;
-     611           10 :    logic [31:0] dec_csr_rddata_d;
+     611            3 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer_wrapper.sv.html
index 58e503800d4..4e53a966622 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world/index_mem_lib.sv.html
index 817181e0562..4a1b673ed68 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_hello_world/index_rvjtag_tap.v.html
index 6b3dcd277db..f7f7c70cad7 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index.html
index f0053a303d0..4d364c5cfd1 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -83,10 +83,10 @@
         65.6%
     
     
-        600
+        601
     
     
-        915
+        916
     
 
       
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    51.4%
+                    52.1%
                 
             
 
             
-                36
+                37
                 /
-                70
+                71
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design.html
index ac97a6b2b50..87cdc86185b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        51.4%
+    
+        52.1%
     
     
-        36
+        37
     
     
-        70
+        71
     
 
       
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    39.2%
+                    40.4%
                 
             
 
             
-                20
+                21
                 /
-                51
+                52
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html
index bbed334614b..0b9854a8685 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html
index edc70a51197..532bee84f50 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html
index fd396604c6d..bac0f8aa4ee 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html
index c4235f3b516..1cb1b5fa599 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html
index ec2cd4d6171..45e11ba12be 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html
index 9b0a4c61724..2f77c485504 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html
index c53a9a0ea33..063afd551e3 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html
index f373a11d9af..9810c854036 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_beh_lib.sv.html
index 18273f19d2b..4282fde9cbd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html
index e37ec23965d..bd347c70733 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_mux.v.html
index c600c28cd38..bb25d2f8ff1 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_wrapper.v.html
index 40a68215725..9b4d8ff12ec 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dbg.sv.html
index ef6f97691ef..316075ea5d7 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec.sv.html
index bc1ac2daf9a..d646a132fa0 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -354,7 +354,7 @@
      250            0 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
      251              : 
      252            0 :     output logic        dec_csr_ren_d,    // CSR read enable
-     253            6 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
+     253            3 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
      254              : 
      255            4 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
      256            4 :     output logic dec_tlu_flush_lower_wb,
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html
index 2eb80c2944c..144ace6db53 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -107,20 +107,20 @@
        3            0 : logic csr_marchid;
        4            0 : logic csr_mimpid;
        5            0 : logic csr_mhartid;
-       6           18 : logic csr_mstatus;
-       7            4 : logic csr_mtvec;
+       6            9 : logic csr_mstatus;
+       7            2 : logic csr_mtvec;
        8            0 : logic csr_mip;
        9            0 : logic csr_mie;
       10            0 : logic csr_mcyclel;
       11            0 : logic csr_mcycleh;
-      12            4 : logic csr_minstretl;
-      13            4 : logic csr_minstreth;
+      12            2 : logic csr_minstretl;
+      13            2 : logic csr_minstreth;
       14            0 : logic csr_mscratch;
       15            0 : logic csr_mepc;
       16            0 : logic csr_mcause;
       17            0 : logic csr_mscause;
       18            0 : logic csr_mtval;
-      19            4 : logic csr_mrac;
+      19            2 : logic csr_mrac;
       20            0 : logic csr_dmst;
       21            0 : logic csr_mdseac;
       22            0 : logic csr_meihap;
@@ -185,7 +185,7 @@
       81            0 : logic csr_pmpaddr16;
       82            0 : logic csr_pmpaddr32;
       83            0 : logic csr_pmpaddr48;
-      84           18 : logic csr_cyclel;
+      84            9 : logic csr_cyclel;
       85            0 : logic csr_cycleh;
       86            0 : logic csr_instretl;
       87            0 : logic csr_instreth;
@@ -200,8 +200,8 @@
       96            0 : logic csr_mseccfgl;
       97            0 : logic csr_mseccfgh;
       98            0 : logic valid_only;
-      99            8 : logic presync;
-     100           10 : logic postsync;
+      99            4 : logic presync;
+     100            5 : logic postsync;
      101              : assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]
      102              :     &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
      103              : 
@@ -545,7 +545,7 @@
      441              :     !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]
      442              :     &dec_csr_rdaddr_d[0]);
      443              : 
-     444           16 : logic legal;
+     444            8 : logic legal;
      445              : assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
      446              :     &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]
      447              :     &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_decode_ctl.sv.html
index 39344f066c5..3b8459bb1b9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -192,7 +192,7 @@
       88              : 
       89          434 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
-      91            6 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
+      91            3 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92           16 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
       93              : 
       94            0 :    input logic [31:0] exu_csr_rs1_x,                  // rs1 for csr instr
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html
index 85cf8b989f7..621029daf88 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_ib_ctl.sv.html
index 9950132a136..67d9a34f03e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html
index c82aa0add85..8b8d3ad3c44 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html
index c22252c605b..9db84397ce9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -284,7 +284,7 @@
      180            0 :    output logic [3:0] dec_tlu_meipt, // to PIC
      181              : 
      182              : 
-     183            6 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
+     183            3 :    output logic [31:0] dec_csr_rddata_d,      // csr read data at wb
      184           16 :    output logic dec_csr_legal_d,              // csr indicates legal operation
      185              : 
      186            0 :    output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
@@ -379,7 +379,7 @@
      275            0 :    logic wr_mcounteren_r;
      276            0 :    logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
      277            0 :    logic wr_mseccfg_r;
-     278            4 :    logic [2:0] mseccfg_ns;
+     278            2 :    logic [2:0] mseccfg_ns;
      279              : `endif
      280            0 :    logic [6:0] mcountinhibit;
      281            0 :    logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
@@ -391,7 +391,7 @@
      287              : `ifdef RV_USER_MODE
      288            0 :    logic [3:0]  mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
      289              : `else
-     290              :    logic [1:0]  mstatus_ns, mstatus;
+     290            0 :    logic [1:0]  mstatus_ns, mstatus;
      291              : `endif
      292            0 :    logic [1:0] mfdhs_ns, mfdhs;
      293            0 :    logic [31:0] force_halt_ctr, force_halt_ctr_f;
@@ -585,8 +585,8 @@
      481              :    `include "el2_dec_csr_equ_mu.svh"
      482              : 
      483            0 :    logic  csr_acc_r;    // CSR access error
-     484           18 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
-     485         3312 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
+     484            9 :    logic  csr_wr_usr_r; // Write to an unprivileged/user-level CSR
+     485         1656 :    logic  csr_rd_usr_r; // REad from an unprivileged/user-level CSR
      486              : 
      487              : `else
      488              : 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_trigger.sv.html
index 4cf9c866508..3cf6c138360 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dma_ctrl.sv.html
index 4387b9133a6..6b75c93222b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu.sv.html
index 26dd546978c..9c051ccefb4 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -156,7 +156,7 @@
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       53            0 :    input logic  [3:0]   dec_i0_rs2_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
       54            0 :    input logic          dec_csr_ren_d,                                 // CSR read select
-      55            6 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
+      55            3 :    input logic  [31:0]  dec_csr_rddata_d,                              // CSR read data
       56              : 
       57         3340 :    input logic          dec_qual_lsu_d,                                // LSU instruction at D.  Use to quiet LSU operands
       58            0 :    input el2_mul_pkt_t mul_p,                                         // DEC {valid, operand signs, low, operand bypass}
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_alu_ctl.sv.html
index 5819bdede19..c4c86e838fb 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30         3338 :    input  logic                  valid_in,           // Valid
       31            0 :    input  el2_alu_pkt_t         ap,                 // predecodes
       32            0 :    input  logic                  csr_ren_in,         // CSR select
-      33            6 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
+      33            3 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34            0 :    input  logic signed [31:0]    a_in,               // A operand
       35            4 :    input  logic        [31:0]    b_in,               // B operand
       36            0 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_div_ctl.sv.html
index 309ba87b1ca..ad6f3729c71 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_mul_ctl.sv.html
index e349c1d18ef..663efe7d086 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu.sv.html
index b8c54416ce6..9dad258509c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html
index 75c892a270e..422c8c060d7 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html
index 9279120082c..710ce4638b8 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html
index 4222bc075ac..38220e77779 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ic_mem.sv.html
index 7b1db6ca255..639bbd1c911 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html
index c89a669e1b7..1e3d6bcd07f 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html
index e12d77d27f8..0cdbb16bc5b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html
index f59771f389e..054ae61665a 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lib.sv.html
index c3593d2e9d8..6de60b18aff 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu.sv.html
index 35b93487967..93e8fc5ecdd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_addrcheck.sv.html
index 82971cccc50..1dd369a5889 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html
index 37fd3030120..6ea7e0dc453 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_intf.sv.html
index 8c2f7086488..5d8c7d4981c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_clkdomain.sv.html
index e8cf41a6305..18e7e589a09 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html
index 1448b7fe7a4..fd3f53a9903 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html
index ecb9bdf6e41..b487a6cf878 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_ecc.sv.html
index e8f3b73ac10..6978c25ef82 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html
index 2a34f127dcf..83b9044a13f 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_stbuf.sv.html
index 41422c22399..f56c4ed43fe 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_trigger.sv.html
index 7fd1ae2d1bb..58b1762196d 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem.sv.html
index d00f2d6fdfc..4f0dc7e53e5 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem_if.sv.html
index b5d79a225b3..0362a7227f9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pic_ctrl.sv.html
index 257437fbb33..bb17eb374ed 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pmp.sv.html
index 31c8a88fc76..17be4639f67 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        39.2%
+    
+        40.4%
     
     
-        20
+        21
     
     
-        51
+        52
     
 
             
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer.sv.html
index 59910e98e1e..4cd4a25ac05 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -712,7 +712,7 @@
      608            0 :    logic [31:0]                          lsu_nonblock_load_data;
      609              : 
      610            0 :    logic        dec_csr_ren_d;
-     611            6 :    logic [31:0] dec_csr_rddata_d;
+     611            3 :    logic [31:0] dec_csr_rddata_d;
      612              : 
      613            0 :    logic [31:0] exu_csr_rs1_x;
      614              : 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer_wrapper.sv.html
index 8463de7a76f..27722cf784e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_mem_lib.sv.html
index 74fc17245c5..db7472ef3ff 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_rvjtag_tap.v.html
index 1a0fdbf0175..e60434225cf 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_dccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index.html
index 9e8fbfb9abb..78acb250a98 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        67.4%
+    
+        67.5%
     
     
-        617
+        618
     
     
-        915
+        916
     
 
       
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    51.4%
+                    52.1%
                 
             
 
             
-                36
+                37
                 /
-                70
+                71
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design.html
index fe2159539a1..35212126014 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        51.4%
+    
+        52.1%
     
     
-        36
+        37
     
     
-        70
+        71
     
 
       
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    39.2%
+                    40.4%
                 
             
 
             
-                20
+                21
                 /
-                51
+                52
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html
index 0ce3751dfcd..612ed435154 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html
index 1a37d279112..95b5716b95e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html
index dd5873df517..3f06ac27ba3 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html
index 728138681e7..fab78840190 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html
index d675b53a0ad..5ce87292170 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html
index 642fea00f58..bcf79700b78 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html
index d3a0db3ed99..04b40ee4478 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html
index b3f2c7b3cbc..01743796fd0 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_beh_lib.sv.html
index db2b04d3727..50df4d2cf25 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html
index 5bb456ba30f..7073916bd41 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_mux.v.html
index 604e7b01abc..97e8a18a24b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_wrapper.v.html
index 24926ad5ff8..82a3c0d09bb 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dbg.sv.html
index 85835c85aab..b915f981ef9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec.sv.html
index 62315535eee..b673b9859fc 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html
index 22d3652b198..975a57f78a9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_decode_ctl.sv.html
index c94f786a471..284a15711c7 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html
index 99cec5d2eae..1156454b38e 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_ib_ctl.sv.html
index 09f1537ecef..1b9732ee33c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html
index 3d809bc437d..91147bfdf80 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html
index 89910aae8ed..13727a0cbb8 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_trigger.sv.html
index 6d3115e611f..6933ec479e2 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dma_ctrl.sv.html
index 0effdeff325..dc61f4e6d30 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu.sv.html
index 902b72ed16d..a2e4dc84739 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_alu_ctl.sv.html
index 82c15d85bed..5e850e2d7dd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_div_ctl.sv.html
index 94b1c28a46c..815a2d61060 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_mul_ctl.sv.html
index 2d4f8a20a7d..331158c1f30 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu.sv.html
index 54907790ef5..a7f8b195a42 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html
index fed123c6bb0..5cc8ddb0b04 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html
index fe081560146..783fb3d8300 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html
index ee8ca599afb..31387a00b0f 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ic_mem.sv.html
index 9e4219457e5..ef6a117ab14 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html
index c708a15d140..3340b49a5f0 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html
index 6d2d4e10b53..18cc4a39413 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html
index 071a5c08ec4..62c0e6196f9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lib.sv.html
index 8d5e4ba66f8..b155cb41283 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu.sv.html
index 155581aed2d..a3613bff0cd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_addrcheck.sv.html
index f1d36da6552..c96ad71031c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html
index 20fa732bccc..aaa58278ab6 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_intf.sv.html
index d7307121635..ea42da400df 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_clkdomain.sv.html
index 4b74363f80b..b777e659dab 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html
index 20e56ae0ad0..e8dd9f3431a 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html
index f4625f6d366..5e9bad0d063 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_ecc.sv.html
index 9a2a988f5d1..63f1f254e36 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html
index 2110fb50a48..8bdb0b67cf9 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_stbuf.sv.html
index 99dbf440919..57344ce420b 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_trigger.sv.html
index 9c153bcfb38..e0aa0172773 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem.sv.html
index 9dc19b00834..cd125b0b425 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem_if.sv.html
index f9bc9b2218f..682b21e332d 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pic_ctrl.sv.html
index 3856fcdcd7c..1ddcfd65777 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pmp.sv.html
index a3bcaac98e3..d32f10ea910 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        39.2%
+    
+        40.4%
     
     
-        20
+        21
     
     
-        51
+        52
     
 
             
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154              :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155              :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            6 :     logic access_fail = 1'b0;
+     161            3 :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer.sv.html
index c09ac6a9355..bb03ad2ea81 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer_wrapper.sv.html
index c5b09f2efaf..7d81db6a32a 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_mem_lib.sv.html
index 8a76081ddfe..680b994b79c 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_rvjtag_tap.v.html
index b3c060f90ff..e3006c0d2fd 100644
--- a/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_hello_world_iccm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index.html b/html/main/coverage_dashboard/all_axi_insns/index.html
index 5690e4683e3..6de1b9c3b29 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        69.0%
+    
+        69.7%
     
     
-        631
+        638
     
     
-        915
+        916
     
 
       
@@ -167,21 +167,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    58.6%
+                    59.2%
                 
             
 
             
-                41
+                42
                 /
-                70
+                71
             
         
     
@@ -711,19 +711,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    89.8%
+                    92.6%
                 
             
 
             
-                193
+                199
                 /
                 215
             
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design.html
index 34d6bfcf2d7..963d2088f83 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        58.6%
+    
+        59.2%
     
     
-        41
+        42
     
     
-        70
+        71
     
 
       
@@ -371,21 +371,21 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    49.0%
+                    50.0%
                 
             
 
             
-                25
+                26
                 /
-                51
+                52
             
         
     
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dbg.html
index b7d9cd51ec1..5113aa33193 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dec.html
index 414e9f61d5a..045894ad4c8 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dmi.html
index d0180a5e6a9..4eed449c1a3 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_exu.html
index ffa02f3c18a..618d0d7a46d 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_ifu.html
index 5ba9c99cc3e..e4a55e3cbf2 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_include.html
index 97b3ed69c1b..88df3b65f4a 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lib.html
index 2ceb669b773..421ad7cc0c8 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lsu.html
index ae5bfebf277..d47eb1eb35c 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        89.8%
+    
+        92.6%
     
     
-        193
+        199
     
     
         215
@@ -303,19 +303,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    86.0%
+                    89.8%
                 
             
 
             
-                135
+                141
                 /
                 157
             
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_beh_lib.sv.html
index 69e3217c342..6f5fd8d4f2d 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38        43426 :    always_ff @(posedge clk or negedge rst_l) begin
+      38        83624 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42        43416 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42        83614 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_insns/index_dmi_jtag_to_core_sync.v.html
index f295f17f4ed..6245608e710 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49        43426 : always @ ( posedge clk or negedge rst_n) begin
+      49        83624 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54        43422 :     else begin
-      55        43422 :         rden <= {rden[1:0], rd_en};
-      56        43422 :         wren <= {wren[1:0], wr_en};
+      54        83620 :     else begin
+      55        83620 :         rden <= {rden[1:0], rd_en};
+      56        83620 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_insns/index_dmi_mux.v.html
index dd05b35da45..6f546c720d5 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_insns/index_dmi_wrapper.v.html
index 7b1780cab9b..2b8a5882171 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dbg.sv.html
index 9f13df54b3a..0e0824c7959 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474        43428 :             IDLE: begin
-     475        43428 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476        43428 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477        43428 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474        83626 :             IDLE: begin
+     475        83626 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476        83626 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477        83626 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604        43428 :             SBIDLE: begin
-     605        43428 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606        43428 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607        43428 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608        43428 :                      sbcs_sbbusy_din        = 1'b1;
-     609        43428 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610        43428 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604        83626 :             SBIDLE: begin
+     605        83626 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606        83626 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607        83626 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608        83626 :                      sbcs_sbbusy_din        = 1'b1;
+     609        83626 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610        83626 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec.sv.html
index 75f8548a79f..0a1a7021dc5 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_csr_equ_mu.svh.html
index 38d609de9d0..f7740ba49e1 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_decode_ctl.sv.html
index 3ebd5609529..b4401afd02d 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -631,14 +631,14 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530         1421 :       if (i0_br_error_all | i0_instr_error) begin
-     531         1421 :          i0_dp          =   '0;
-     532         1421 :          i0_dp.alu      = 1'b1;
-     533         1421 :          i0_dp.rs1      = 1'b1;
-     534         1421 :          i0_dp.rs2      = 1'b1;
-     535         1421 :          i0_dp.lor      = 1'b1;
-     536         1421 :          i0_dp.legal    = 1'b1;
-     537         1421 :          i0_dp.postsync = 1'b1;
+     530         2488 :       if (i0_br_error_all | i0_instr_error) begin
+     531         2488 :          i0_dp          =   '0;
+     532         2488 :          i0_dp.alu      = 1'b1;
+     533         2488 :          i0_dp.rs1      = 1'b1;
+     534         2488 :          i0_dp.rs2      = 1'b1;
+     535         2488 :          i0_dp.lor      = 1'b1;
+     536         2488 :          i0_dp.legal    = 1'b1;
+     537         2488 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -709,16 +709,16 @@
      605            2 :       found = 0;
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
-     608         5544 :             if (~cam[i].valid) begin
-     609        42146 :                cam_wen[i] = cam_write;
-     610        42146 :                found = 1'b1;
+     608        10288 :             if (~cam[i].valid) begin
+     609        81318 :                cam_wen[i] = cam_write;
+     610        81318 :                found = 1'b1;
      611              :             end
-     612         5544 :             else begin
-     613         5544 :                cam_wen[i] = 0;
+     612        10288 :             else begin
+     613        10288 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617       143070 :             cam_wen[i] = 0;
+     617       274818 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,28 +756,28 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655         1101 :          if (cam_data_reset_val[i])
-     656         1101 :            cam[i].valid = 1'b0;
+     655         2066 :          if (cam_data_reset_val[i])
+     656         2066 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
      659              : 
-     660         3303 :          if (cam_wen[i]) begin
-     661         3303 :             cam_in[i].valid    = 1'b1;
-     662         3303 :             cam_in[i].wb       = 1'b0;
-     663         3303 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
-     664         3303 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
+     660         6198 :          if (cam_wen[i]) begin
+     661         6198 :             cam_in[i].valid    = 1'b1;
+     662         6198 :             cam_in[i].wb       = 1'b0;
+     663         6198 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
+     664         6198 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666           59 :          else if ( (cam_inv_reset_val[i]) |
+     666          114 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
-     668           59 :            cam_in[i].valid = 1'b0;
+     668          114 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670       187398 :            cam_in[i] = cam[i];
+     670       360112 :            cam_in[i] = cam[i];
      671              : 
-     672         3303 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
-     673         3303 :            cam_in[i].wb = 1'b1;
+     672         6198 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     673         6198 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676       173712 :          if (dec_tlu_force_halt)
+     676       334504 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746         8462 :       if (i0_legal_decode_d) begin
-     747         8462 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748         1287 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749         1163 :          if (i0_dp.store)                i0_itype = STORE;
-     750         3995 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751         8462 :          if (i0_dp.zbb | i0_dp.zbs |
+     746        16302 :       if (i0_legal_decode_d) begin
+     747        16302 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748         2434 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749         2188 :          if (i0_dp.store)                i0_itype = STORE;
+     750         7804 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751        16302 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756           38 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757           15 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758         8462 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759          313 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760          313 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761         8462 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762         8462 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763          320 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764         1677 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765          274 :          if (i0_dp.jal)                  i0_itype = JAL;
+     756           74 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757           24 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758        16302 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759            4 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760            4 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761        16302 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762        16302 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763           18 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764         3218 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765          534 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862        43428 :       if (dec_extint_stall) begin
+     862        83626 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868        43428 :       else begin
-     869        43428 :          lsu_p.valid = lsu_decode_d;
+     868        83626 :       else begin
+     869        83626 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871        43428 :          lsu_p.load                         =  i0_dp.load ;
-     872        43428 :          lsu_p.store                        =  i0_dp.store;
-     873        43428 :          lsu_p.by                           =  i0_dp.by   ;
-     874        43428 :          lsu_p.half                         =  i0_dp.half ;
-     875        43428 :          lsu_p.word                         =  i0_dp.word ;
-     876        43428 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871        83626 :          lsu_p.load                         =  i0_dp.load ;
+     872        83626 :          lsu_p.store                        =  i0_dp.store;
+     873        83626 :          lsu_p.by                           =  i0_dp.by   ;
+     874        83626 :          lsu_p.half                         =  i0_dp.half ;
+     875        83626 :          lsu_p.word                         =  i0_dp.word ;
+     876        83626 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878        43428 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879        43428 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880        43428 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878        83626 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879        83626 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880        83626 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882        43428 :          lsu_p.unsign  =  i0_dp.unsign;
+     882        83626 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1380,7 +1380,7 @@
     1276            2 :       r_t_in.i0trigger[3:0]              = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
     1277            2 :       r_t_in.pmu_lsu_misaligned          = lsu_pmu_misaligned_r;   // only valid if a load/store is valid in DC3 stage
     1278              : 
-    1279           17 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
+    1279           32 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
     1280              : 
     1281              :    end
     1282              : 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_gpr_ctl.sv.html
index fdc0e6745b8..a11cbdb2b38 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_ib_ctl.sv.html
index 3f37bf18889..f99932b65e3 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_pmp_ctl.sv.html
index e787aee3d90..39e36d14fd6 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_tlu_ctl.sv.html
index 320995c63f2..f7985703ff8 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_trigger.sv.html
index 2ea272d3576..41ad1a6c4c6 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_dma_ctrl.sv.html
index 39466143160..320e60d48b9 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu.sv.html
index c196cfebf10..d23ee211ca2 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_alu_ctl.sv.html
index 04bc5222b9b..f0bbe01273b 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342      1526080 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343      1526080 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342      2931392 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343      2931392 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_div_ctl.sv.html
index 2c2eac9e0ce..7040fe54146 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_mul_ctl.sv.html
index 8965844c083..6ab413233b1 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209      1526080 :              if (bcompress_test_bit_d)
+     209      2931392 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236      1526080 :              if (bdecompress_test_bit_d)
+     236      2931392 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu.sv.html
index 823567305a6..027cd0f2b96 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_aln_ctl.sv.html
index bcad96e5db0..0c961be9197 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_bp_ctl.sv.html
index 13238f967fa..67448adae92 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676        43428 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676        83626 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678        43428 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679        43428 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678        83626 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679        83626 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684        43428 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684        83626 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686        43428 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687        43428 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686        83626 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687        83626 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877        43428 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878        43428 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879        43428 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877        83626 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878        83626 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879        83626 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881        43428 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882        43428 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881        83626 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882        83626 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_compress_ctl.sv.html
index 04f06e084e1..749619ca34a 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ic_mem.sv.html
index 75e85f5b65c..909327046ad 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_iccm_mem.sv.html
index 37f689c3911..adf8b065f12 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ifc_ctl.sv.html
index 5084c53a740..888501719a1 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_mem_ctl.sv.html
index 59a96e62226..cb138fb9b51 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -587,21 +587,21 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486         9468 :          IDLE: begin : idle
-     487         9468 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488         9468 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486        18216 :          IDLE: begin : idle
+     487        18216 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488        18216 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490        23299 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491        23299 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492        23299 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493        23299 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494        23299 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495        23299 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496        23299 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497        23299 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498        23299 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499        23299 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500        23299 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490        44816 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491        44816 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492        44816 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493        44816 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494        44816 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495        44816 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496        44816 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497        44816 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498        44816 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499        44816 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500        44816 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,24 +611,24 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510        10352 :          MISS_WAIT: begin : miss_wait
-     511        10352 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512        10352 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510        20052 :          MISS_WAIT: begin : miss_wait
+     511        20052 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512        20052 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514          252 :          HIT_U_MISS: begin : hit_u_miss
-     515          252 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516          252 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517          252 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514          460 :          HIT_U_MISS: begin : hit_u_miss
+     515          460 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516          460 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517          460 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
      521            0 :                                     exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;
      522            0 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      523              :          end
-     524           57 :          STALL_SCND_MISS: begin : stall_scnd_miss
-     525           57 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
-     526           57 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
-     527           57 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
+     524           82 :          STALL_SCND_MISS: begin : stall_scnd_miss
+     525           82 :                   miss_nxtstate   =  dec_tlu_force_halt ? IDLE  :
+     526           82 :                                      exu_flush_final ?  ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;
+     527           82 :                   miss_state_en   = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;
      528              :          end
      529            0 :          default: begin : def_case
      530            0 :                   miss_nxtstate   = IDLE;
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945        43428 :       ERR_IDLE: begin : err_idle
-     946        43428 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947        43428 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948        43428 :         perr_sb_write_status = perr_state_en;
+     945        83626 :       ERR_IDLE: begin : err_idle
+     946        83626 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947        83626 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948        83626 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990        43428 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991        43428 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992        43428 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990        83626 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991        83626 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992        83626 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446        43428 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447        43428 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446        83626 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447        83626 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509        43428 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510        43428 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511        86856 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509        83626 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510        83626 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511       167252 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lib.sv.html
index 88b015fa4e6..59c9ce290cf 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu.sv.html
index 9962166de17..ac10b6bf840 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_addrcheck.sv.html
index 36064fa04f8..a05e0793ca4 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_buffer.sv.html
index d4d2e5a2027..4f23062626f 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        86.0%
+    
+        89.8%
     
     
-        135
+        141
     
     
         157
@@ -445,15 +445,15 @@
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344       130316 :    function automatic logic [2:0] f_Enc8to3;
+     344       250934 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348       130316 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349       130316 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350       130316 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348       250934 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349       250934 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350       250934 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352       130316 :       return Enc_value[2:0];
+     352       250934 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -663,20 +663,20 @@
      559              : 
      560              :       // Find first write pointer
      561            2 :       for (int i=0; i<DEPTH; i++) begin
-     562          296 :          if (~found_wrptr0) begin
-     563          296 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     564          296 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     565          296 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     562          590 :          if (~found_wrptr0) begin
+     563          590 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     564          590 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     565          590 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      566              :          end
      567              :       end
      568              : 
      569              :       // Find second write pointer
      570            2 :       for (int i=0; i<DEPTH; i++) begin
-     571          443 :          if (~found_wrptr1) begin
-     572          443 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     573          443 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     574          443 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
-     575          443 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     571          884 :          if (~found_wrptr1) begin
+     572          884 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     573          884 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     574          884 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
+     575          884 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      576              :          end
      577              :       end
      578              :    end
@@ -758,71 +758,71 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657       161924 :             IDLE: begin
-     658       161924 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659       161924 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660       161924 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661       161924 :                      buf_wr_en[i]    = buf_state_en[i];
-     662       161924 :                      buf_data_en[i]  = buf_state_en[i];
-     663       161924 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664       161924 :                      buf_cmd_state_bus_en[i]  = '0;
+     657       311922 :             IDLE: begin
+     658       311922 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659       311922 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660       311922 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661       311922 :                      buf_wr_en[i]    = buf_state_en[i];
+     662       311922 :                      buf_data_en[i]  = buf_state_en[i];
+     663       311922 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664       311922 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         8291 :             CMD: begin
-     672         8291 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         8291 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         8291 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         8291 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         8291 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         8291 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         8291 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         8291 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         8291 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         8291 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671        15998 :             CMD: begin
+     672        15998 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673        15998 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674        15998 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675        15998 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676        15998 :                      buf_ldfwd_in[i]          = 1'b1;
+     677        15998 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678        15998 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679        15998 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680        15998 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681        15998 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683         2337 :             RESP: begin
-     684         2337 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685         2337 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686         2337 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687         2337 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688         2337 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689         2337 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690         2337 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691         2337 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692         2337 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693         2337 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694         2337 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695         2337 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683         4402 :             RESP: begin
+     684         4402 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685         4402 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686         4402 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687         4402 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688         4402 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689         4402 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690         4402 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691         4402 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692         4402 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693         4402 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694         4402 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695         4402 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697         2337 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698         2337 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699         2337 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700         2337 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701         2337 :                      buf_cmd_state_bus_en[i]  = '0;
+     697         4402 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698         4402 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699         4402 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700         4402 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701         4402 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
-     703            2 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
-     704            2 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
-     705            2 :                      buf_state_bus_en[i]       = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
-     706            2 :                                                                  (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
-     707            2 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     708            2 :                      buf_cmd_state_bus_en[i]  = '0;
+     703            4 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
+     704            4 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
+     705            4 :                      buf_state_bus_en[i]       = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
+     706            4 :                                                                  (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
+     707            4 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     708            4 :                      buf_cmd_state_bus_en[i]  = '0;
      709              :             end
-     710           54 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
-     711           54 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
-     712           54 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
-     713           54 :                       buf_cmd_state_bus_en[i]  = '0;
+     710          106 :             DONE_WAIT: begin  // START_WAIT state if there are multiple outstanding nb returns
+     711          106 :                       buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : DONE;
+     712          106 :                       buf_state_en[i]           = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
+     713          106 :                       buf_cmd_state_bus_en[i]  = '0;
      714              :             end
-     715         1104 :             DONE: begin
-     716         1104 :                      buf_nxtstate[i]           = IDLE;
-     717         1104 :                      buf_rst[i]                = 1'b1;
-     718         1104 :                      buf_state_en[i]           = 1'b1;
-     719         1104 :                      buf_ldfwd_in[i]           = 1'b0;
-     720         1104 :                      buf_ldfwd_en[i]           = buf_state_en[i];
-     721         1104 :                      buf_cmd_state_bus_en[i]  = '0;
+     715         2072 :             DONE: begin
+     716         2072 :                      buf_nxtstate[i]           = IDLE;
+     717         2072 :                      buf_rst[i]                = 1'b1;
+     718         2072 :                      buf_state_en[i]           = 1'b1;
+     719         2072 :                      buf_ldfwd_in[i]           = 1'b0;
+     720         2072 :                      buf_ldfwd_en[i]           = buf_state_en[i];
+     721         2072 :                      buf_cmd_state_bus_en[i]  = '0;
      722              :             end
      723            0 :             default : begin
      724            0 :                      buf_nxtstate[i]          = IDLE;
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_intf.sv.html
index 2f46b243b48..1c56a190da2 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_clkdomain.sv.html
index 5ff0c6192b2..fcda7bbe146 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_ctl.sv.html
index 0b3a747cd80..d695d4db859 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_mem.sv.html
index 7be5f59d221..8b982e84c22 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_ecc.sv.html
index 078c03e3e50..42cbc220a80 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_lsc_ctl.sv.html
index d758ca4ff63..96a52748317 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_stbuf.sv.html
index 686f6ae3e6b..47fd7ef013c 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_trigger.sv.html
index 57cba524af4..f847dd6dc5e 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_mem.sv.html
index 2cd56c0316f..ff0be7f2f12 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_mem_if.sv.html
index 7d6ebad3a4b..b0e78985c01 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_pic_ctrl.sv.html
index c7a721b7ca6..6c0e0d33baf 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500      1389696 :               if (intenable_reg_re[i]) begin
+     500      2676032 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503      1389696 :               if (intpriority_reg_re[i]) begin
+     503      2676032 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506      1389696 :               if (gw_config_reg_re[i]) begin
+     506      2676032 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_pmp.sv.html
index 53bfedb34ef..66b5e5c5cb1 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,14 +79,14 @@
     
         Branch
     
-    
-        49.0%
+    
+        50.0%
     
     
-        25
+        26
     
     
-        51
+        52
     
 
             
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133      2289408 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133      4397664 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139      2289408 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139      4397664 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -255,14 +255,14 @@
      151              :   `ifdef RV_SMEPMP
      152              :     // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
      153              :     // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
-     154            3 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
-     155            3 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
+     154            6 :     logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+     155            6 :                        (csr_pmp_mseccfg.MML && (req_type == EXEC));
      156              :   `else
      157              :     // When in user mode and at least one PMP region is enabled deny access by default.
      158              :     logic access_fail = any_region_enabled & priv_mode;
      159              :   `endif
      160              : `else
-     161            3 :     logic access_fail = 1'b0;
+     161              :     logic access_fail = 1'b0;
      162              : `endif
      163              : 
      164            6 :     logic matched = 1'b0;
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       145602 :       if (!matched && match_all[r]) begin
-     170       145602 :         access_fail = ~final_perm_check[r];
-     171       145602 :         matched = 1'b1;
+     169       280200 :       if (!matched && match_all[r]) begin
+     170       280200 :         access_fail = ~final_perm_check[r];
+     171       280200 :         matched = 1'b1;
      172              :       end
      173              :     end
      174            6 :     return access_fail;
@@ -348,12 +348,12 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247      1954662 :           OFF:     region_match_all[c][r] = 1'b0;
+     247      3763572 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250       129882 :           TOR: begin
-     251       129882 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252       129882 :                                      region_match_lt[c][r];
+     250       250476 :           TOR: begin
+     251       250476 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252       250476 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_veer.sv.html
index 68573eeba89..3c9f1ac632a 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_el2_veer_wrapper.sv.html
index 368c09d4256..a0ca2ac6841 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_insns/index_mem_lib.sv.html
index d86ae48d6df..f847450e1a3 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111       694816 : `EL2_RAM(4096, 39)
+     111      1337984 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175       173704 : `EL2_RAM_BE(512, 142)
+     175       334496 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208        86852 : `EL2_RAM_BE(128, 52)
+     208       167248 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_axi_insns/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_insns/index_rvjtag_tap.v.html
index 0fa6660830a..93c803ec175 100644
--- a/html/main/coverage_dashboard/all_axi_insns/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_insns/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index.html b/html/main/coverage_dashboard/all_axi_irq/index.html
index 1f63b67e4a1..9c466b0ed82 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design.html
index 8a0531fbcb4..388840edc50 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dbg.html
index 49626794eaf..2deb49d0ca1 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dec.html
index 50db9dffc9e..834896c5fc4 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dmi.html
index 5622aac29e1..31c755b0f1c 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_exu.html
index 64100c104d6..a4568a32bb4 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_ifu.html
index 9d04d010d1e..36f87eb4acd 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_include.html
index 8b42ad5fe60..750f9c1ec13 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lib.html
index 32edfa64838..4150f9e5fb0 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lsu.html
index 3ba772bf58c..33d4a39be18 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_beh_lib.sv.html
index 3cc11103425..bd5cfd52b4a 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_irq/index_dmi_jtag_to_core_sync.v.html
index 3d356ec17d8..3e347d7e263 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_irq/index_dmi_mux.v.html
index 50143422188..048b6006076 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_irq/index_dmi_wrapper.v.html
index 45aba19598a..379a9df3764 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dbg.sv.html
index f0c7082c7d7..cc7e482f788 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec.sv.html
index 9463b6ce6d8..3b18bf5f456 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_csr_equ_mu.svh.html
index 7bff74c5172..c32741decbe 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_decode_ctl.sv.html
index d39e16db921..04b1f647d93 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_gpr_ctl.sv.html
index 471d706810d..d125aa0cae7 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_ib_ctl.sv.html
index 9ea4c8ef218..89cf1375bd0 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_pmp_ctl.sv.html
index 54cd9abe5f5..2698f15bbcd 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_tlu_ctl.sv.html
index 34490c08c54..4b087bdc518 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_trigger.sv.html
index 7ee30715ece..757b7f53224 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_dma_ctrl.sv.html
index 95dbe7f8a03..7b1ffa033f5 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu.sv.html
index acb187d8f56..3c9fc54cdc2 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_alu_ctl.sv.html
index d07c0bc8fe9..f6103bf2863 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_div_ctl.sv.html
index 4934e93fa60..8ade01aa81c 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_mul_ctl.sv.html
index e672b95ea66..c89de4b7bd7 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu.sv.html
index 3deeb395d84..56684bc9696 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_aln_ctl.sv.html
index 9362bb4430c..62ee8b2ee81 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_bp_ctl.sv.html
index 74f62f29a79..f861a30112f 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_compress_ctl.sv.html
index 0cc9e245451..81db14fb88c 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ic_mem.sv.html
index 77a5559c1ac..0a1614e406d 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_iccm_mem.sv.html
index 06e0947c1b1..d055895ef0b 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ifc_ctl.sv.html
index ef1d6f0247e..064b87d6987 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_mem_ctl.sv.html
index 38e9f3a187a..6f1ab8d03a9 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lib.sv.html
index cfffc887bb0..d9ee9a872fb 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu.sv.html
index 7d8a4462830..7bd55e47229 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_addrcheck.sv.html
index 7291e029c56..b8f2f9111ba 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_buffer.sv.html
index 4bc8e1043e9..acc04ece6e7 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_intf.sv.html
index 015cead21a8..cd830a10553 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_clkdomain.sv.html
index 064ac0f2497..00281e871ed 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_ctl.sv.html
index 1c256f94e4f..bbe76d17399 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_mem.sv.html
index a026e11bd8a..81d8ac48745 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_ecc.sv.html
index d0aa6e09b1f..bc3f347aa70 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_lsc_ctl.sv.html
index 870b7815f96..1317521a0d3 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_stbuf.sv.html
index 77f345e39a6..9a11658c0f8 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_trigger.sv.html
index 37cd3766781..fb3638703c5 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_mem.sv.html
index 6769ac43dfa..3af1a07e8cc 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_mem_if.sv.html
index c2cbbc8feaa..001a5927c30 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_pic_ctrl.sv.html
index 858c1fad533..4b9d1dd1f4a 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_pmp.sv.html
index b4595e02594..18c92dcaf92 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_veer.sv.html
index 40ba2f20efd..fe4d09790bd 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_el2_veer_wrapper.sv.html
index 8ea8f3d20af..3e05b5fe686 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_irq/index_mem_lib.sv.html
index e509907f91c..bb46f8b5ee9 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_irq/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_irq/index_rvjtag_tap.v.html
index 580e1685f82..7f4e810ffd0 100644
--- a/html/main/coverage_dashboard/all_axi_irq/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_irq/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index.html b/html/main/coverage_dashboard/all_axi_modesw/index.html
index 3f3d8a6ffce..f061267ec4c 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design.html
index 238682b4cad..0f395afcd18 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dbg.html
index b3f7a264d09..ab278dec316 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dec.html
index cda2b63ed88..49430eb9654 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dmi.html
index 9800f06f9b0..6b5bffc8499 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_exu.html
index f6f8aaa4a8a..ab88c2d758b 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_ifu.html
index 8f31378373e..5007063d922 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_include.html
index fabfdebfba0..e55b131655f 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lib.html
index 7d1a151843a..57aa08c6b6a 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lsu.html
index b4cf2d1cf15..fbb25383e75 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_beh_lib.sv.html
index 02f7d1396bc..1fd64fa1570 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_modesw/index_dmi_jtag_to_core_sync.v.html
index 00f896c1fba..e5488b73ced 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_modesw/index_dmi_mux.v.html
index 36f87471579..9ef01452ecd 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_modesw/index_dmi_wrapper.v.html
index d0e55b9dcf4..fdf7ec1e15a 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dbg.sv.html
index 26a6d15761e..53eb4a36817 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec.sv.html
index 44fab7431bc..fb25e96f34d 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_csr_equ_mu.svh.html
index 4d6697c8c06..00db3de04ed 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_decode_ctl.sv.html
index 04a7e1a58a7..194b497af84 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_gpr_ctl.sv.html
index 5f4c675c368..b04543e2fd7 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_ib_ctl.sv.html
index 0c0a166bbf2..dbce0d88b53 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_pmp_ctl.sv.html
index 2970b0cca47..41d167eeafe 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_tlu_ctl.sv.html
index 2d3b4129141..d32591eac9c 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_trigger.sv.html
index b5451e37f21..be3ad757e2a 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dma_ctrl.sv.html
index 388ae548aac..9080b47f81b 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu.sv.html
index 2aa76ced754..2c4232436f8 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_alu_ctl.sv.html
index 643ac6e7651..28325058dba 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_div_ctl.sv.html
index 3afdb33c0c4..7c382bbed78 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_mul_ctl.sv.html
index 35d630a3d83..3fb3ab210c6 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu.sv.html
index c5f39730a87..711909917cd 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_aln_ctl.sv.html
index b3ce4c8f981..77a87b8b919 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_bp_ctl.sv.html
index e532ed9213e..9bea2870d8e 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_compress_ctl.sv.html
index d74421123f1..f45e9485c42 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ic_mem.sv.html
index fafebcda4f4..303ba50aae2 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_iccm_mem.sv.html
index a874819991f..bc0141beed7 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ifc_ctl.sv.html
index 08cca1e0f0a..0fdb6e589c5 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_mem_ctl.sv.html
index a4ab5a79493..c36234210b0 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lib.sv.html
index 0bfe9517f60..b4e2ca51713 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu.sv.html
index f0a13ea38b2..472ae6e9777 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_addrcheck.sv.html
index 8419396a0e2..fd39d47e540 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_buffer.sv.html
index 8dd2f073f7d..a389958ea6d 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_intf.sv.html
index ccf527c4ea4..1109e10b8ec 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_clkdomain.sv.html
index 8e79424bfd2..31e918d50d0 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_ctl.sv.html
index d78464a96f6..42301e2e883 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_mem.sv.html
index 5fc70699c52..304b2a5c81d 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_ecc.sv.html
index 105f4fa784e..67aaed1b937 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_lsc_ctl.sv.html
index dec104f6ad9..d99f6191046 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_stbuf.sv.html
index 297de014dac..d5af6a065bc 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_trigger.sv.html
index a22287fd140..81abb9a1ed4 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem.sv.html
index cfec906ebbc..b6851faa488 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem_if.sv.html
index 1c2a8ed14e6..078300ae4d3 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_pic_ctrl.sv.html
index 90c9d254c3d..6909e408031 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_pmp.sv.html
index d777ab5d34b..3f929a313d8 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer.sv.html
index ca268e00099..84403025aee 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer_wrapper.sv.html
index c05be6c1d5c..4968f9f433a 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_modesw/index_mem_lib.sv.html
index 59807a8dc8a..425e484084d 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_modesw/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_modesw/index_rvjtag_tap.v.html
index a9d98394789..017683ca1ce 100644
--- a/html/main/coverage_dashboard/all_axi_modesw/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_modesw/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index.html b/html/main/coverage_dashboard/all_axi_perf_counters/index.html
index 426583816a8..65f868ada59 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design.html
index 258fe460466..7705a0deb4a 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dbg.html
index 9c167e4ff14..441cabb9ff5 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dec.html
index 862e99684ba..5f03769dcc9 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dmi.html
index 42e2d7a04db..03d10c7ab3b 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_exu.html
index 0bbae40148b..7dce835c36f 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_ifu.html
index d6b8bd9fe55..8249c2972b7 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_include.html
index c965472d1cb..61643aed7ee 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lib.html
index 396a070205e..516d685f44a 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lsu.html
index 42aa51a8139..d938a8a0bee 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_beh_lib.sv.html
index 56e4ba2f15d..1895153aad8 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_jtag_to_core_sync.v.html
index 202bf20abbd..ed386fa1058 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_mux.v.html
index 00ab11da72f..5923780bd90 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_wrapper.v.html
index 34575ec5f6e..9f8736e18e4 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dbg.sv.html
index 2c1d7bde2d3..969dc676232 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec.sv.html
index e9cd2b32f52..3be301b330f 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_csr_equ_mu.svh.html
index e2e4567b8e1..67122f47730 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_decode_ctl.sv.html
index aef9cd8a433..cb1d49da0a2 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_gpr_ctl.sv.html
index 910b67ec92f..aff18d33736 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_ib_ctl.sv.html
index bb0ae9c243f..791e2c2f786 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_pmp_ctl.sv.html
index a3b189d3b09..488cea17156 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_tlu_ctl.sv.html
index ff82d2e3070..0515fa48e5f 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_trigger.sv.html
index 89ec8f953d5..98c59e56688 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dma_ctrl.sv.html
index 1f56c46b9cd..be036ba388d 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu.sv.html
index dbd76daf5a7..f141b825c32 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_alu_ctl.sv.html
index 0f11168e48d..ff808c6f584 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_div_ctl.sv.html
index 2fa5062e97f..ea8bcc69eb7 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_mul_ctl.sv.html
index 1af8e9bda85..161c4006d25 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu.sv.html
index eb70cc46cea..2049e170b16 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_aln_ctl.sv.html
index 10e826a61b0..13f9195cca1 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_bp_ctl.sv.html
index 593785f2ce5..1530e5f241a 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_compress_ctl.sv.html
index 518dacc7e80..de930c11d87 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ic_mem.sv.html
index 5bba7f4bd66..68dce49ed33 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_iccm_mem.sv.html
index 70f480e84db..0ba31ebbf3a 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ifc_ctl.sv.html
index cb44b6c1ae3..2d1dc7ff3d4 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_mem_ctl.sv.html
index 05ee93336bd..54e4dbd7fef 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lib.sv.html
index c4cf9eeb726..01e7951b330 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu.sv.html
index 735e3084cd5..a54f63d71fb 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_addrcheck.sv.html
index c4a9e2a7125..e568f62925a 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_buffer.sv.html
index c21286361d9..6ab2090f508 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_intf.sv.html
index f1544ad4fb8..54be6e50919 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_clkdomain.sv.html
index cac29be07ab..3fbfd62f5d3 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_ctl.sv.html
index bdabce71b16..e46db4f139c 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_mem.sv.html
index 1857200bfa4..b6137914085 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_ecc.sv.html
index e474d979366..a667ea17d17 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_lsc_ctl.sv.html
index 341466d1280..c49bcf7f25b 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_stbuf.sv.html
index f7a2938ca57..9e148a68faa 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_trigger.sv.html
index 973c5d99f63..dd42ba960fa 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem.sv.html
index b070071fa8d..9514b8cc5f6 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem_if.sv.html
index 77515132649..d0d567167e4 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pic_ctrl.sv.html
index 1604de59b33..af964631386 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pmp.sv.html
index 3efe2d9dd10..acad6b811cd 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer.sv.html
index 538dabf90a0..688d8dd3b96 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer_wrapper.sv.html
index 269e9eb4bef..355077f5370 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_mem_lib.sv.html
index ede055142bc..057cf016230 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_perf_counters/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_perf_counters/index_rvjtag_tap.v.html
index 043f9898314..3c853e0e819 100644
--- a/html/main/coverage_dashboard/all_axi_perf_counters/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_perf_counters/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index.html b/html/main/coverage_dashboard/all_axi_pmp/index.html
index 8a9e5a0d536..584d0d3798c 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design.html
index 27d6b225c4f..ebe1fd082f0 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dbg.html
index da37714c3e6..d74b629649a 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dec.html
index 530708e7965..8a4f5f61315 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dmi.html
index 45c8aedf03c..cc5dd30882e 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_exu.html
index 80bcfef5bba..4ad948bfdc3 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_ifu.html
index ed8cfc9b2e5..02478ded938 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_include.html
index 73b66c214dc..7701d53254b 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lib.html
index 9d3f328438b..4a698f5a7f7 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lsu.html
index dbbf9d2d426..a7640c8de01 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_beh_lib.sv.html
index 3655c707b98..2d92d43c1e3 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_axi_pmp/index_dmi_jtag_to_core_sync.v.html
index b6c3717528a..4b1bae9dbda 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_axi_pmp/index_dmi_mux.v.html
index 694bfd5b010..8325a151871 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_axi_pmp/index_dmi_wrapper.v.html
index 0f31a57ff23..1b1c0759775 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dbg.sv.html
index 7cb7f6a416b..a049e2deb38 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec.sv.html
index 59187613967..1d92fc1792c 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_csr_equ_mu.svh.html
index 04440fd7786..a18a2f15c19 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_decode_ctl.sv.html
index eed2062e038..3618fab8338 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_gpr_ctl.sv.html
index d4c815cc126..0ec72b29fd4 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_ib_ctl.sv.html
index 2f26c64b909..6a10648f362 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_pmp_ctl.sv.html
index e11c27da03e..7f92ab7a3b6 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_tlu_ctl.sv.html
index d37a88c4572..1d5066e7b38 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_trigger.sv.html
index c663d2dc86c..f174a66545f 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dma_ctrl.sv.html
index 60e64b89402..9ea9e10bd54 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu.sv.html
index e7fb7f2560d..ae8ae9a9ab4 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_alu_ctl.sv.html
index 4bd57f52eb7..eca9a52f6a1 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_div_ctl.sv.html
index de919444ddc..83c86b72161 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_mul_ctl.sv.html
index 148775cc008..34ec1ee617f 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu.sv.html
index 59ad07c2d0d..43096f611ed 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_aln_ctl.sv.html
index 2b636def7cd..889935a8b37 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_bp_ctl.sv.html
index c835fcbb2b5..93099137aa6 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_compress_ctl.sv.html
index b1e694ebedd..a4f1309d6cf 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ic_mem.sv.html
index 60194577e66..46054c627dc 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_iccm_mem.sv.html
index 20a5d603d97..423901ddb08 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ifc_ctl.sv.html
index d79d25c126e..e60d0f08d3d 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_mem_ctl.sv.html
index d388ce229bf..97582b56684 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lib.sv.html
index b2fc72b8d7c..2f5891b3389 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu.sv.html
index b41b426868e..7d473ad712a 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_addrcheck.sv.html
index fd3bd12f54b..a7871cbf5b3 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_buffer.sv.html
index e886f1aa64d..13ecaa7b078 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_intf.sv.html
index 7c6cd6750f4..5ea89dc2973 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_clkdomain.sv.html
index aafe63efa0c..0d6706a2324 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_ctl.sv.html
index 5579eaa3c7f..37bfb8e0aee 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_mem.sv.html
index e93390a1600..cfb8b168433 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_ecc.sv.html
index ae9ef013397..57ee6a1e0df 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_lsc_ctl.sv.html
index abe5bdb0241..3a6472ebaa4 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_stbuf.sv.html
index fc478aab2ac..d60635ee80f 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_trigger.sv.html
index 381955e0696..9ef1509e2d3 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem.sv.html
index b51499ee3aa..e3300d1ca82 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem_if.sv.html
index 7ca6e0374dc..ea17bbc9c3e 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_pic_ctrl.sv.html
index cf1ea22515c..55366cb09df 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_pmp.sv.html
index bd03ce1e38c..456e77ded3f 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer.sv.html
index a75c544a57d..500cff93dad 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer_wrapper.sv.html
index 2e984260d0a..c35d10a17d0 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_axi_pmp/index_mem_lib.sv.html
index af7f5a7cbaf..2e90420591c 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_axi_pmp/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_axi_pmp/index_rvjtag_tap.v.html
index 4ba6d37e435..6b06890d130 100644
--- a/html/main/coverage_dashboard/all_axi_pmp/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_axi_pmp/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index.html
index 8f9e1ebf346..6002d42a3b2 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html
index cece8b97316..77c0afcc123 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lsu.html
index 8a76ed06b50..a01bfc278fd 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_beh_lib.sv.html
index 53407ab6f56..13a5b530dfe 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_lsu_dccm_mem.sv.html
index 3004393e988..4f3f632d493 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_mem_if.sv.html
index 704fc621a8a..0c4b809ff30 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_mem_lib.sv.html
index b0cdd05d13e..0654b6cd899 100644
--- a/html/main/coverage_dashboard/all_dccm_test_readwrite/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dccm_test_readwrite/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index.html b/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index.html
index 689b01433ad..6271084b82b 100644
--- a/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index.html
+++ b/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_Cores-VeeR-EL2_design_dec.html
index 70913930e51..fe01c4e8f40 100644
--- a/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_el2_dec_ib_ctl.sv.html
index 974b62e7c64..1880c3f7c80 100644
--- a/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_dec_ib_test_dec_ib/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index.html b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index.html
index 8d608d765a8..da20115980c 100644
--- a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index.html
+++ b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_dec.html
index c38cc42175b..c1fa8e6ce5c 100644
--- a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_lib.html
index c24f7132058..e6e673a6225 100644
--- a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_beh_lib.sv.html
index f5f1d154464..41110f41512 100644
--- a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_el2_dec_trigger.sv.html
index f0bca618afa..ad42591edf6 100644
--- a/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_dec_tl_test_dec_tl/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_address/index.html b/html/main/coverage_dashboard/all_dma_test_address/index.html
index 66be8d4a227..d27265d8756 100644
--- a/html/main/coverage_dashboard/all_dma_test_address/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_address/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design.html
index c4a56752806..964b4201582 100644
--- a/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design_lib.html
index a7a56ff6781..1b2fdfb9a5d 100644
--- a/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_address/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_address/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_address/index_beh_lib.sv.html
index 3b0490607f8..eef08415c03 100644
--- a/html/main/coverage_dashboard/all_dma_test_address/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_address/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_address/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_address/index_el2_dma_ctrl.sv.html
index a91a9584ddc..80a7559c9bd 100644
--- a/html/main/coverage_dashboard/all_dma_test_address/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_address/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_address/index.html b/html/main/coverage_dashboard/all_dma_test_debug_address/index.html
index 7fe6de855ed..4cd5a3c7e2e 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_address/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_address/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design.html
index 5f8fb545120..4c82d1950ad 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design_lib.html
index 5b2a07266b3..7ae1c5ebc2f 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_address/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_address/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_debug_address/index_beh_lib.sv.html
index ada5aa80999..27fa248a654 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_address/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_address/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_address/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_debug_address/index_el2_dma_ctrl.sv.html
index d0cf262e53b..31759a43f48 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_address/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_address/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_read/index.html b/html/main/coverage_dashboard/all_dma_test_debug_read/index.html
index 93c5194e621..1a2fb0ee110 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_read/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_read/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design.html
index 34bfb8bb7d4..1e2643bbb9c 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design_lib.html
index e9a34b244e7..0f7df052c70 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_read/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_read/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_debug_read/index_beh_lib.sv.html
index 1a3482b00c7..05aa5815fe3 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_read/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_read/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_read/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_debug_read/index_el2_dma_ctrl.sv.html
index 836e611522c..1a6de83f587 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_read/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_read/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_write/index.html b/html/main/coverage_dashboard/all_dma_test_debug_write/index.html
index 0dcdc2146be..d30134497f3 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_write/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_write/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design.html
index e190b328b60..e369078a714 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design_lib.html
index 3c187559c8f..82cb2d090a0 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_write/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_write/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_debug_write/index_beh_lib.sv.html
index 9f9d05522c9..ca3ff256dd6 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_write/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_write/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_debug_write/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_debug_write/index_el2_dma_ctrl.sv.html
index 543062422fe..3fc9fc3c1a7 100644
--- a/html/main/coverage_dashboard/all_dma_test_debug_write/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_debug_write/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_ecc/index.html b/html/main/coverage_dashboard/all_dma_test_ecc/index.html
index f0e401ede69..e2ab18c3a23 100644
--- a/html/main/coverage_dashboard/all_dma_test_ecc/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_ecc/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design.html
index f40dc5cee58..1b184795d8c 100644
--- a/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design_lib.html
index 0dfe3e96943..3116d6b83ec 100644
--- a/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_ecc/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_ecc/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_ecc/index_beh_lib.sv.html
index 3b63a4b0041..369fa017e4e 100644
--- a/html/main/coverage_dashboard/all_dma_test_ecc/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_ecc/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_ecc/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_ecc/index_el2_dma_ctrl.sv.html
index 46a041baced..3d1f7f4ffcd 100644
--- a/html/main/coverage_dashboard/all_dma_test_ecc/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_ecc/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_read/index.html b/html/main/coverage_dashboard/all_dma_test_read/index.html
index 3f254d4194c..e5d04c58e79 100644
--- a/html/main/coverage_dashboard/all_dma_test_read/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_read/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design.html
index 9b36ea2b964..5f596e59e9a 100644
--- a/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design_lib.html
index b458f03f8b1..b3ae460e547 100644
--- a/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_read/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_read/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_read/index_beh_lib.sv.html
index 0c4e47a95bc..bb70c1e01ba 100644
--- a/html/main/coverage_dashboard/all_dma_test_read/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_read/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_read/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_read/index_el2_dma_ctrl.sv.html
index 0302893226e..6f063674dab 100644
--- a/html/main/coverage_dashboard/all_dma_test_read/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_read/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_reset/index.html b/html/main/coverage_dashboard/all_dma_test_reset/index.html
index 4d8ecb8fcc7..4a91cb2d4b5 100644
--- a/html/main/coverage_dashboard/all_dma_test_reset/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_reset/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design.html
index dea4cf89d82..a77c92eb6f5 100644
--- a/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design_lib.html
index 24fa9e82d6c..c87d513a117 100644
--- a/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_reset/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_reset/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_reset/index_beh_lib.sv.html
index c24ed6af9b6..8d4c8769420 100644
--- a/html/main/coverage_dashboard/all_dma_test_reset/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_reset/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_reset/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_reset/index_el2_dma_ctrl.sv.html
index 40431888ee3..d6f73d422f4 100644
--- a/html/main/coverage_dashboard/all_dma_test_reset/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_reset/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_write/index.html b/html/main/coverage_dashboard/all_dma_test_write/index.html
index bfe0ddc3813..1f6061d7c39 100644
--- a/html/main/coverage_dashboard/all_dma_test_write/index.html
+++ b/html/main/coverage_dashboard/all_dma_test_write/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design.html
index 4a26e7bfc76..1bd624f5d28 100644
--- a/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design_lib.html
index 2a07f1ac462..c70bf3c53d3 100644
--- a/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_dma_test_write/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dma_test_write/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_dma_test_write/index_beh_lib.sv.html
index 46c97b7e009..bdb4e3e3f5b 100644
--- a/html/main/coverage_dashboard/all_dma_test_write/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_write/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dma_test_write/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_dma_test_write/index_el2_dma_ctrl.sv.html
index 050d119d44f..8a97abbfffd 100644
--- a/html/main/coverage_dashboard/all_dma_test_write/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_dma_test_write/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index.html b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index.html
index 7b0e8fdae87..3f5d6244a0d 100644
--- a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index.html
+++ b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_Cores-VeeR-EL2_design_dmi.html
index 70cd5aecc52..ff071ead865 100644
--- a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_jtag_to_core_sync.v.html
index c7b2d8593c1..c795144c928 100644
--- a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_mux.v.html
index 40b7a2b68d7..3200d273618 100644
--- a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_wrapper.v.html
index 1377b86ac66..9fad049aa7c 100644
--- a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_rvjtag_tap.v.html
index 5e618a256f7..624501eb5d3 100644
--- a/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_dmi_read_write/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index.html b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index.html
index 900f79c2d50..fd9b524fc36 100644
--- a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index.html
+++ b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_Cores-VeeR-EL2_design_dmi.html
index 948a7c250d8..dc2009aeb29 100644
--- a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_jtag_to_core_sync.v.html
index 2c6fd7b5edd..31f2b639156 100644
--- a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_mux.v.html
index 2767bcc2673..a3c577ce40d 100644
--- a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_wrapper.v.html
index b52eb17512a..665cb98fc2a 100644
--- a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_rvjtag_tap.v.html
index 2b67e3879c6..d478355c05b 100644
--- a/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_dmi_test_jtag_ir/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_arith/index.html b/html/main/coverage_dashboard/all_exu_alu_test_arith/index.html
index c0890d88d7a..2c15c279f03 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_arith/index.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_arith/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_exu.html
index 2d40a997836..43e90e43997 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_lib.html
index 83e587229a2..4d7d2f5b34f 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_beh_lib.sv.html
index e4efde16521..1c2dfdb2d12 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_el2_exu_alu_ctl.sv.html
index 4bd2e1a7b8e..64a89d9c96a 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_arith/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_arith/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_logic/index.html b/html/main/coverage_dashboard/all_exu_alu_test_logic/index.html
index 0c88c2d183d..53741084486 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_logic/index.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_logic/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_exu.html
index a1dc220e7b7..81470c322d2 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_lib.html
index 0934133f7dc..92b736b0562 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_beh_lib.sv.html
index 7bf2f576b8f..85d89af5df7 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_el2_exu_alu_ctl.sv.html
index e6bfe144019..bf33af8fb37 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_logic/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_logic/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zba/index.html b/html/main/coverage_dashboard/all_exu_alu_test_zba/index.html
index 25841b7d875..d917e9663f2 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zba/index.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zba/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_exu.html
index 57243f19639..bef1d436455 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_lib.html
index c4feed30deb..5710bccb174 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_beh_lib.sv.html
index c03bd459a6a..e3232cb431a 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_el2_exu_alu_ctl.sv.html
index 58d92242750..919f0a98061 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zba/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zba/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index.html b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index.html
index 33acd180587..8082680c047 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_exu.html
index 93292af542b..5df7e991c07 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_lib.html
index b5ce2048fe1..0bd9e665c70 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_beh_lib.sv.html
index a051a695b29..3760ee41f11 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_el2_exu_alu_ctl.sv.html
index be40e48b1be..4e8b9fb2f47 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbb/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index.html b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index.html
index 576734af215..6b065ca2c1d 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_exu.html
index 18312441ff5..dd9b2247f3f 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_lib.html
index dd5b50ab697..7596f85abd7 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_beh_lib.sv.html
index 9320d281e16..a6c43e71452 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_el2_exu_alu_ctl.sv.html
index 425cdccad62..145f688f639 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbp/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index.html b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index.html
index b51898ac254..c240ce03e28 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_exu.html
index 3a2370fbbbc..d0acdb5a0e8 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_lib.html
index d09f699daa3..718296e0d3c 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_beh_lib.sv.html
index 420d0716dd5..690c39222ef 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_el2_exu_alu_ctl.sv.html
index 42ec51cbe22..aa5bb13a96a 100644
--- a/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_alu_test_zbs/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_div_test_div/index.html b/html/main/coverage_dashboard/all_exu_div_test_div/index.html
index b8c6a89ccb3..8a5e39e5f08 100644
--- a/html/main/coverage_dashboard/all_exu_div_test_div/index.html
+++ b/html/main/coverage_dashboard/all_exu_div_test_div/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_exu.html
index dc0a403c74a..68be65d7652 100644
--- a/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_lib.html
index a5511b32d51..43e95c22860 100644
--- a/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_div_test_div/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_div_test_div/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_div_test_div/index_beh_lib.sv.html
index 38ab3111853..9b193138bb3 100644
--- a/html/main/coverage_dashboard/all_exu_div_test_div/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_div_test_div/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_div_test_div/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_exu_div_test_div/index_el2_exu_div_ctl.sv.html
index 5fcd24da35d..8b5a764c914 100644
--- a/html/main/coverage_dashboard/all_exu_div_test_div/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_div_test_div/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_mul_test_mul/index.html b/html/main/coverage_dashboard/all_exu_mul_test_mul/index.html
index 164a8040936..2108a061056 100644
--- a/html/main/coverage_dashboard/all_exu_mul_test_mul/index.html
+++ b/html/main/coverage_dashboard/all_exu_mul_test_mul/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_exu.html
index 003eeae4081..0e377f69a57 100644
--- a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_lib.html
index 1ac3253874c..fa23ebcbf2f 100644
--- a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_beh_lib.sv.html
index aecf368b8da..b247e4c9ef8 100644
--- a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_el2_exu_mul_ctl.sv.html
index 8e676c6474c..56765571c32 100644
--- a/html/main/coverage_dashboard/all_exu_mul_test_mul/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_exu_mul_test_mul/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index.html
index dfc3a9523dd..8b80db314da 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_ifu.html
index 81918af9477..1073d87c261 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html
index 1cc221a19af..650b74c7095 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_beh_lib.sv.html
index e1bac4eb3b0..05cd879110f 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_ifu_iccm_mem.sv.html
index 0bb20c00fad..d663f04295e 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_mem_if.sv.html
index 08d493b35bd..4f853ceadfc 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_mem_lib.sv.html
index 944928abdc8..f9e2c9cd67b 100644
--- a/html/main/coverage_dashboard/all_iccm_test_readwrite/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_iccm_test_readwrite/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_ifu_compress_test_compress/index.html b/html/main/coverage_dashboard/all_ifu_compress_test_compress/index.html
index 3acf8647117..bfba0a82111 100644
--- a/html/main/coverage_dashboard/all_ifu_compress_test_compress/index.html
+++ b/html/main/coverage_dashboard/all_ifu_compress_test_compress/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_Cores-VeeR-EL2_design_ifu.html
index 171e5f524d2..dc21912a079 100644
--- a/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_el2_ifu_compress_ctl.sv.html
index 5a351b55265..3dee3506569 100644
--- a/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_ifu_compress_test_compress/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index.html
index bde133de66c..53ec884cc3d 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_Cores-VeeR-EL2_design_lib.html
index 3b29232f291..f94704a8201 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_ahb_to_axi4.sv.html
index 7f866346b06..47b9bb24603 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_beh_lib.sv.html
index 5bbc4129bb2..7187710bad2 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_read/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index.html
index b24b23fc6e5..188b44304e6 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_Cores-VeeR-EL2_design_lib.html
index 10001865e3c..0e067926955 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_ahb_to_axi4.sv.html
index 9a8ea77a91e..620a1626108 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_beh_lib.sv.html
index ef92bf75f27..e770562c0f3 100644
--- a/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_lib_ahb_to_axi4_test_write/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index.html
index cd9e51afa89..2264c5933cb 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_Cores-VeeR-EL2_design_lib.html
index e3a3ed87b6f..4883c1e7dac 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_axi4_to_ahb.sv.html
index bdc6e9cde23..1c16b3b601c 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_beh_lib.sv.html
index 7966d048ce3..f2d9e3b0bd6 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index.html
index 58078b551c8..a7cdedc67cb 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_Cores-VeeR-EL2_design_lib.html
index 4961f4ab84a..12b9e338b01 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_axi4_to_ahb.sv.html
index f37673869a6..0a76d893ef1 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_beh_lib.sv.html
index dafdcc2ed49..df0ea01dfd0 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_read_channel/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index.html
index be5f89e1060..16aee210641 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_Cores-VeeR-EL2_design_lib.html
index bf52e5bc6ad..2a615f9f131 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_axi4_to_ahb.sv.html
index 78a89543d83..bdc18a660cb 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_beh_lib.sv.html
index 613576680f8..33b03103dd0 100644
--- a/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_lib_axi4_to_ahb_test_axi_write_channel/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index.html b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index.html
index 2d9af48012b..884b2c9398a 100644
--- a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index.html
+++ b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lib.html
index c3f77dd2b94..8e48f860a6e 100644
--- a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lsu.html
index e381f28c9bf..dfa7dbc95a2 100644
--- a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_beh_lib.sv.html
index 834ee474e61..8055d0da7c7 100644
--- a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_el2_lsu_trigger.sv.html
index 19a44f5f306..b341a1c5c5e 100644
--- a/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_lsu_tl_test_lsu_tl/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index.html
index 091d94738f1..386f88bc93e 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design.html
index f2a1ff4b484..896754a59b1 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dbg.html
index 8502e0ec52f..912af131d72 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dec.html
index 321b864872b..b82fe81d99f 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dmi.html
index 606077b5983..a1cb4bd7eae 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_exu.html
index 24b688bb918..43c9192d6db 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_ifu.html
index 17c71a282cc..4dde21090e5 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_include.html
index 611dacf40d0..87c392cfbce 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lib.html
index 349203aaf73..5499e02c3e3 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lsu.html
index 0bdad31cdf7..48e6e0bdb68 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_ahb_to_axi4.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_ahb_to_axi4.sv.html
index 8fb8a43f68c..6e332012e83 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_ahb_to_axi4.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_ahb_to_axi4.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : )
       29              : //   ,TAG  = 1)
       30              : (
-      31        90604 :    input                   clk,
+      31        90580 :    input                   clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -242,9 +242,9 @@
      138            2 :       buf_read_error_in = 1'b0;              // signal indicating that an error came back with the read from the core
      139            2 :       cmdbuf_wr_en      = 1'b0;              // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
      140            2 :       case (buf_state)
-     141       128361 :          IDLE: begin  // No commands recieved
-     142       128361 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
-     143       128361 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
+     141       124149 :          IDLE: begin  // No commands recieved
+     142       124149 :                   buf_nxtstate      = ahb_hwrite ? WR : RD;
+     143       124149 :                   buf_state_en      = ahb_hready & ahb_htrans[1] & ahb_hsel;                 // only transition on a valid hrtans
      144              :           end
      145            0 :          WR: begin // Write command recieved last cycle
      146            0 :                   buf_nxtstate      = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite  ? WR : RD;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_axi4_to_ahb.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_axi4_to_ahb.sv.html
index de7d92c5b97..5b4f5799eff 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_axi4_to_ahb.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_axi4_to_ahb.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : `include "el2_param.vh"
       28              : ,parameter TAG  = 1) (
       29              : 
-      30        90604 :    input                   clk,
-      31        90604 :    input                   free_clk,
+      30        90580 :    input                   clk,
+      31        90580 :    input                   free_clk,
       32            2 :    input                   rst_l,
       33            0 :    input                   scan_mode,
       34            2 :    input                   bus_clk_en,
@@ -389,18 +389,18 @@
      285            2 :       rd_bypass_idle   = 1'b0;
      286              : 
      287            2 :       case (buf_state)
-     288       128317 :          IDLE: begin
-     289       128317 :                   master_ready   = 1'b1;
-     290       128317 :                   buf_write_in = (master_opc[2:1] == 2'b01);
-     291       128317 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
-     292       128317 :                   buf_state_en = master_valid & master_ready;
-     293       128317 :                   buf_wr_en    = buf_state_en;
-     294       128317 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
-     295       128317 :                   buf_cmd_byte_ptr_en   = buf_state_en;
-     296       128317 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
-     297       128317 :                   bypass_en       = buf_state_en;
-     298       128317 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
-     299       128317 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
+     288       124105 :          IDLE: begin
+     289       124105 :                   master_ready   = 1'b1;
+     290       124105 :                   buf_write_in = (master_opc[2:1] == 2'b01);
+     291       124105 :                   buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
+     292       124105 :                   buf_state_en = master_valid & master_ready;
+     293       124105 :                   buf_wr_en    = buf_state_en;
+     294       124105 :                   buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
+     295       124105 :                   buf_cmd_byte_ptr_en   = buf_state_en;
+     296       124105 :                   buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
+     297       124105 :                   bypass_en       = buf_state_en;
+     298       124105 :                   rd_bypass_idle  = bypass_en & (buf_nxtstate == CMD_RD);
+     299       124105 :                   ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
      300              :           end
      301            8 :          CMD_RD: begin
      302            8 :                   buf_nxtstate    = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_beh_lib.sv.html
index fcbaddbb1d0..7d1a6344c1d 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22        90604 :      input logic           clk,
+      22        90580 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38       128359 :    always_ff @(posedge clk or negedge rst_l) begin
+      38       124147 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42       128349 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42       124137 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52            0 :      input logic             en,
-      53        90604 :      input logic           clk,
+      53        90580 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -174,7 +174,7 @@
       70            0 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73       362416 :      input logic           clk,
+      73       362320 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -195,7 +195,7 @@
       91            4 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94        90604 :      input logic           rawclk,
+      94        90580 :      input logic           rawclk,
       95            2 :      input logic           rst_l,
       96              : 
       97            4 :      output logic [WIDTH-1:0] dout
@@ -220,7 +220,7 @@
      116           20 :      input logic             en,
      117            0 :      input logic           clk,
      118            6 :      input logic           clken,
-     119       271580 :      input logic           rawclk,
+     119       271508 :      input logic           rawclk,
      120            6 :      input logic           rst_l,
      121              : 
      122            0 :      output logic [WIDTH-1:0] dout
@@ -247,7 +247,7 @@
      143            0 :      input logic             clear,
      144            4 :      input logic             clk,
      145            6 :      input logic             clken,
-     146       271580 :      input logic             rawclk,
+     146       271508 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
      149           20 :      output logic [WIDTH-1:0] dout
@@ -271,7 +271,7 @@
      167              :    (
      168            0 :      input  logic [WIDTH-1:0] din,
      169            0 :      input  logic           en,
-     170        90604 :      input  logic           clk,
+     170        90580 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -310,7 +310,7 @@
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
      208            8 :      input  logic [WIDTH-1:0] din,
-     209      1085856 :      input  logic             clk,
+     209      1085568 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
      211         3578 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            0 :      input  logic [WIDTH-1:0] din,
-     242        90604 :      input  logic             clk,
+     242        90580 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -398,7 +398,7 @@
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
      296            0 :      input  logic [WIDTH-1:0] din,
-     297        90604 :      input  logic             clk,
+     297        90580 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
      299           30 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
@@ -442,7 +442,7 @@
      338              :    (
      339            0 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341        90604 :      input  logic           clk,
+     341        90580 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
      344            0 :      output logic [WIDTH-1:0] dout
@@ -519,7 +519,7 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418        90604 :      input  logic                 clk,
+     418        90580 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
      420            0 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434      2805128 :      input  logic                 rawclk,
+     434      2804384 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480            0 :     input [31:1] pc,
-     481        44804 :     input [12:1] offset,
+     481        44792 :     input [12:1] offset,
      482              : 
      483            8 :     output [31:1] dout
      484              :     );
      485              : 
-     486        45184 :    logic          cout;
-     487        45184 :    logic          sign;
+     486        45172 :    logic          cout;
+     487        45172 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -825,7 +825,7 @@
      721              : 
      722              : 
      723              : module rvecc_decode_64  (
-     724        44368 :                       input         en,
+     724        44356 :                       input         en,
      725         1198 :                       input [63:0]  din,
      726         1198 :                       input [6:0]   ecc_in,
      727            0 :                       output        ecc_error
@@ -897,9 +897,9 @@
      793              : module rvoclkhdr
      794              :   (
      795          562 :    input  logic en,
-     796      2446308 :    input  logic clk,
+     796      2445660 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798      2446308 :    output logic l1clk
+     798      2445660 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_jtag_to_core_sync.v.html
index 42b4f6fdeff..b63d0d45e4e 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32        90604 : input       clk,        // Core clock
+      32        90580 : input       clk,        // Core clock
       33              : 
       34          240 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35          112 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49       128359 : always @ ( posedge clk or negedge rst_n) begin
+      49       124147 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54       128355 :     else begin
-      55       128355 :         rden <= {rden[1:0], rd_en};
-      56       128355 :         wren <= {wren[1:0], wr_en};
+      54       124143 :     else begin
+      55       124143 :         rden <= {rden[1:0], rd_en};
+      56       124143 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_mux.v.html
index 7423ffdd992..c346effb355 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_wrapper.v.html
index 7f484854f95..f7cdade7a23 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36        90604 :   input              core_clk,            // Core clock                  
+      36        90580 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38           12 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39           20 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dbg.sv.html
index 2889abd9f64..5079932a002 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110        90604 :    input logic                         clk,
-     111        90604 :    input logic                         free_clk,
+     110        90580 :    input logic                         clk,
+     111        90580 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254          240 :    logic              dbg_free_clken;
-     255        90604 :    logic              dbg_free_clk;
+     255        90580 :    logic              dbg_free_clk;
      256              : 
      257          240 :    logic              sb_free_clken;
-     258        90604 :    logic              sb_free_clk;
+     258        90580 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474       128361 :             IDLE: begin
-     475       128361 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476       128361 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477       128361 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474       124149 :             IDLE: begin
+     475       124149 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476       124149 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477       124149 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604       128253 :             SBIDLE: begin
-     605       128253 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606       128253 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607       128253 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608       128253 :                      sbcs_sbbusy_din        = 1'b1;
-     609       128253 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610       128253 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604       124041 :             SBIDLE: begin
+     605       124041 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606       124041 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607       124041 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608       124041 :                      sbcs_sbbusy_din        = 1'b1;
+     609       124041 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610       124041 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            8 :             WAIT_RD: begin
      613            8 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec.sv.html
index 294cea57041..330465a164b 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,10 +136,10 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35        90604 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36        90604 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37        90604 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38        90604 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35        90580 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        90580 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37        90580 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38        90580 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
@@ -175,8 +175,8 @@
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
       73          424 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74        44368 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
-      75        44740 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
+      74        44356 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      75        44728 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
       78            0 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
@@ -232,7 +232,7 @@
      128              : 
      129            0 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
      130            0 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
-     131          362 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
+     131          360 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
      132            0 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
      133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
      134              : 
@@ -268,7 +268,7 @@
      164          450 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
      165          360 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166            0 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167        45112 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167        45100 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            0 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
@@ -313,10 +313,10 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212        44300 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212        44288 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215        44364 :     input  logic       exu_i0_br_valid_r,        // valid
+     215        44352 :     input  logic       exu_i0_br_valid_r,        // valid
      216          424 :     input  logic       exu_i0_br_mp_r,           // mispredict
      217          370 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
@@ -329,13 +329,13 @@
      225            0 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
      226            0 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228        44374 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     228        44362 :     output logic [31:0] dec_i0_immed_d,    // immediate data
      229           64 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
      233          450 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234        44732 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     234        44720 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
      236          360 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
@@ -372,7 +372,7 @@
      268            0 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
      269              : 
      270            0 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
-     271          362 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
+     271          360 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
      272            0 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
      273            0 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
      274              : 
@@ -442,7 +442,7 @@
      338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
      340          368 :   logic [4:0] dec_i0_rs1_d;
-     341        44374 :   logic [4:0] dec_i0_rs2_d;
+     341        44362 :   logic [4:0] dec_i0_rs2_d;
      342              : 
      343          360 :   logic [31:0] dec_i0_instr_d;
      344              : 
@@ -451,7 +451,7 @@
      347              : 
      348              : 
      349          426 :   logic [4:0] dec_i0_waddr_r;
-     350        44382 :   logic dec_i0_wen_r;
+     350        44370 :   logic dec_i0_wen_r;
      351            0 :   logic [31:0] dec_i0_wdata_r;
      352            8 :   logic dec_csr_wen_r;  // csr write enable at wb
      353          786 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
@@ -467,7 +467,7 @@
      363              : 
      364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366        45112 :   logic dec_i0_pc4_d;
+     366        45100 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
      368            8 :   logic dec_tlu_postsync_d;
      369            0 :   logic dec_tlu_debug_stall;
@@ -485,7 +485,7 @@
      381            0 :   logic dec_tlu_flush_pause_r;
      382            0 :   el2_br_pkt_t dec_i0_brp;
      383            0 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
-     384          362 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
+     384          360 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
      385            0 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
      386            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
      387              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_csr_equ_m.svh.html
index 59558456608..8dd4d433195 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_decode_ctl.sv.html
index 8f2cfcb7027..4ae34877a24 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -170,7 +170,7 @@
       66              : 
       67            0 :    input el2_br_pkt_t dec_i0_brp,                    // branch packet
       68            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      69          362 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
+      69          360 :    input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,  // BP FGHR
       70            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
       71            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       72              : 
@@ -190,7 +190,7 @@
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
       87            8 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89        45112 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89        45100 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
       91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92            8 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
@@ -210,9 +210,9 @@
      106              : 
      107            0 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109        90604 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110        90604 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111        90604 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109        90580 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110        90580 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111        90580 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
@@ -223,9 +223,9 @@
      119            0 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
      121          368 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122        44374 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     122        44362 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124        44374 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124        44362 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
      127           64 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
@@ -235,10 +235,10 @@
      131          454 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
      133          450 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134        44732 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     134        44720 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
      136          426 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137        44382 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     137        44370 :    output logic        dec_i0_wen_r,                  // i0 write enable
      138            0 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
      140          360 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
@@ -279,7 +279,7 @@
      175            4 :    output logic [31:1] pred_correct_npc_x,            // npc e2 if the prediction is correct
      176              : 
      177            0 :    output el2_predict_pkt_t dec_i0_predict_p_d,      // i0 predict packet decode
-     178          362 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
+     178          360 :    output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
      179            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
      180            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
      181              : 
@@ -319,7 +319,7 @@
      215            4 :    logic               i0_uiimm20;
      216              : 
      217            0 :    logic               lsu_decode_d;
-     218        44374 :    logic [31:0]        i0_immed_d;
+     218        44362 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
      220            8 :    logic               i0_postsync;
      221              : 
@@ -359,7 +359,7 @@
      255           12 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
      257          426 :    logic [12:1]        last_br_immed_d;
-     258        43954 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
+     258        43942 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
      261            0 :    logic               i0_div_decode_d;
@@ -393,7 +393,7 @@
      289            0 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292        44732 :    logic               i0_predict_br;
+     292        44720 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301        45112 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301        45100 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303        44386 :    logic               i0_rd_en_d;
+     303        44374 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -436,7 +436,7 @@
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335        44724 :    logic              i0_brp_valid;
+     335        44712 :    logic              i0_brp_valid;
      336            0 :    logic              nonblock_load_cancel;
      337            2 :    logic              lsu_idle;
      338            0 :    logic              lsu_pmu_misaligned_r;
@@ -460,7 +460,7 @@
      356            0 :    logic i0_br_unpred;
      357              : 
      358            0 :    logic nonblock_load_valid_m_delay;
-     359        44382 :    logic i0_wen_r;
+     359        44370 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
@@ -631,7 +631,7 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530       128361 :       if (i0_br_error_all | i0_instr_error) begin
+     530       124149 :       if (i0_br_error_all | i0_instr_error) begin
      531            0 :          i0_dp          =   '0;
      532            0 :          i0_dp.alu      = 1'b1;
      533            0 :          i0_dp.rs1      = 1'b1;
@@ -710,15 +710,15 @@
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
      608            0 :             if (~cam[i].valid) begin
-     609       128365 :                cam_wen[i] = cam_write;
-     610       128365 :                found = 1'b1;
+     609       124153 :                cam_wen[i] = cam_write;
+     610       124153 :                found = 1'b1;
      611              :             end
      612            0 :             else begin
      613            0 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617       385095 :             cam_wen[i] = 0;
+     617       372459 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,7 +756,7 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655       513444 :          if (cam_data_reset_val[i])
+     655       496596 :          if (cam_data_reset_val[i])
      656            0 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
@@ -767,17 +767,17 @@
      663            0 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
      664            0 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666       513460 :          else if ( (cam_inv_reset_val[i]) |
+     666       496612 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
      668            0 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670       513460 :            cam_in[i] = cam[i];
+     670       496612 :            cam_in[i] = cam[i];
      671              : 
-     672       513460 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     672       496612 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
      673            0 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676       513444 :          if (dec_tlu_force_halt)
+     676       496596 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746          650 :       if (i0_legal_decode_d) begin
-     747       127715 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748       127715 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749       127715 :          if (i0_dp.store)                i0_itype = STORE;
-     750        63597 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751       127715 :          if (i0_dp.zbb | i0_dp.zbs |
+     746          633 :       if (i0_legal_decode_d) begin
+     747       123520 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748       123520 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749       123520 :          if (i0_dp.store)                i0_itype = STORE;
+     750        61508 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751       123520 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756       127715 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     756       123520 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
      757            4 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758       127715 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759       127715 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760       127715 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761       127715 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762       127715 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763       127715 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764        63081 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765          512 :          if (i0_dp.jal)                  i0_itype = JAL;
+     758       123520 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759       123520 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760       123520 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761       123520 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762       123520 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763       123520 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764        61009 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765          495 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862       128361 :       if (dec_extint_stall) begin
+     862       124149 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868       128361 :       else begin
-     869       128361 :          lsu_p.valid = lsu_decode_d;
+     868       124149 :       else begin
+     869       124149 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871       128361 :          lsu_p.load                         =  i0_dp.load ;
-     872       128361 :          lsu_p.store                        =  i0_dp.store;
-     873       128361 :          lsu_p.by                           =  i0_dp.by   ;
-     874       128361 :          lsu_p.half                         =  i0_dp.half ;
-     875       128361 :          lsu_p.word                         =  i0_dp.word ;
-     876       128361 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871       124149 :          lsu_p.load                         =  i0_dp.load ;
+     872       124149 :          lsu_p.store                        =  i0_dp.store;
+     873       124149 :          lsu_p.by                           =  i0_dp.by   ;
+     874       124149 :          lsu_p.half                         =  i0_dp.half ;
+     875       124149 :          lsu_p.word                         =  i0_dp.word ;
+     876       124149 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878       128361 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879       128361 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880       128361 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878       124149 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879       124149 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880       124149 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882       128361 :          lsu_p.unsign  =  i0_dp.unsign;
+     882       124149 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_gpr_ctl.sv.html
index 5fe75ef7eeb..94ccc11a04d 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,9 +123,9 @@
       19              :    `include "el2_param.vh"
       20              :  )  (
       21          368 :     input logic [4:0]  raddr0,       // logical read addresses
-      22        44374 :     input logic [4:0]  raddr1,
+      22        44362 :     input logic [4:0]  raddr1,
       23              : 
-      24        44382 :     input logic        wen0,         // write enable
+      24        44370 :     input logic        wen0,         // write enable
       25          426 :     input logic [4:0]  waddr0,       // write address
       26            0 :     input logic [31:0] wd0,          // write data
       27              : 
@@ -137,7 +137,7 @@
       33            0 :     input logic [4:0]  waddr2,       // write address
       34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36        90604 :     input logic        clk,
+      36        90580 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
       39            0 :     output logic [31:0] rd0,         // read data
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_ib_ctl.sv.html
index b07a8ae4722..2fa36688da0 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,11 +131,11 @@
       27              : 
       28            0 :    input el2_br_pkt_t i0_brp,                                     // i0 branch packet from aligner
       29            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,    // BP index
-      30          362 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
+      30          360 :    input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,               // BP FGHR
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34        45112 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      34        45100 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
       35          450 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
@@ -154,11 +154,11 @@
       50              : 
       51            0 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53        45112 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53        45100 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
       55            0 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
       56            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
-      57          362 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
+      57          360 :    output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr,              // BP FGHR
       58            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag,             // BP tag
       59            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index,          // Fully associt btb index
       60              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_pmp_ctl.sv.html
index 0c27f6d82d2..417cf404d29 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32        90604 :    input logic clk,
-      33        90604 :    input logic free_l2clk,
-      34        90604 :    input logic csr_wr_clk,
+      32        90580 :    input logic clk,
+      33        90580 :    input logic free_l2clk,
+      34        90580 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
       36            8 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
       37            4 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_tlu_ctl.sv.html
index 310e701c63b..6b18f69a4f7 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32        90604 :    input logic clk,
-      33        90604 :    input logic free_clk,
-      34        90604 :    input logic free_l2clk,
+      32        90580 :    input logic clk,
+      33        90580 :    input logic free_clk,
+      34        90580 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
@@ -164,8 +164,8 @@
       60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
       62          424 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63        44368 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64        44740 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      63        44356 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64        44728 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
       65            0 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
       66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
@@ -213,10 +213,10 @@
      109          454 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112        44300 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112        44288 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115        44364 :    input logic        exu_i0_br_valid_r, // valid
+     115        44352 :    input logic        exu_i0_br_valid_r, // valid
      116          424 :    input logic        exu_i0_br_mp_r, // mispredict
      117          370 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
@@ -456,7 +456,7 @@
      352            8 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355        44660 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355        44648 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
      357            4 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
      358          454 :    logic i0_trigger_eval_r;
@@ -506,7 +506,7 @@
      402            0 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405        90604 :    logic csr_wr_clk;
+     405        90580 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
      407            0 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
@@ -2828,9 +2828,9 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727        90604 :    input logic clk,
-    2728        90604 :    input logic free_l2clk,
-    2729        90604 :    input logic csr_wr_clk,
+    2727        90580 :    input logic clk,
+    2728        90580 :    input logic free_l2clk,
+    2729        90580 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
     2731            8 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
     2732            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_trigger.sv.html
index 97657d9610d..1af1db633e7 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dma_ctrl.sv.html
index 68aa56ba59e..bf0c959fd53 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29        90604 :    input logic         clk,
-      30        90604 :    input logic         free_clk,
+      29        90580 :    input logic         clk,
+      30        90580 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185        90604 :    logic                    dma_buffer_c1_clk;
-     186        90604 :    logic                    dma_free_clk;
+     185        90580 :    logic                    dma_buffer_c1_clk;
+     186        90580 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu.sv.html
index 15620372bec..87ecfe0a0bc 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        90604 :    input logic          clk,                                           // Top level clock
+      23        90580 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
@@ -136,7 +136,7 @@
       32            0 :    input logic          dec_debug_wdata_rs1_d,                         // Debug select to primary I0 RS1
       33              : 
       34            0 :    input el2_predict_pkt_t dec_i0_predict_p_d,                        // DEC branch predict packet
-      35          362 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
+      35          360 :    input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,                // DEC predict fghr
       36            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,     // DEC predict index
       37            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,               // DEC predict branch tag
       38              : 
@@ -146,11 +146,11 @@
       42            0 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
       43            0 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
       44            0 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45        44374 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      45        44362 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
       46            0 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
       47           64 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
       48          450 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49        44732 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      49        44720 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
       50          360 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51            0 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
@@ -184,26 +184,26 @@
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            0 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83        44300 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83        44288 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
       86            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87        44364 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      87        44352 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
       88          424 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
       89          370 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
-      90          362 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
+      90          360 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
       91            0 :    output logic         exu_i0_br_way_r,                               // to DEC  I0 branch way
       92              : 
       93            0 :    output el2_predict_pkt_t exu_mp_pkt,                               // Mispredict branch packet
       94          396 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr,                    // Mispredict global history
-      95          362 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      95          360 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
       96            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       97            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       98              : 
       99              : 
      100          424 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101        44368 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102        44740 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     101        44356 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102        44728 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105            0 :    output logic [31:0]  exu_div_result,                                // Divide result
@@ -217,21 +217,21 @@
      113            0 :    logic [31:0]                i0_rs2_bypass_data_d;
      114          430 :    logic                       i0_rs1_bypass_en_d;
      115            0 :    logic                       i0_rs2_bypass_en_d;
-     116        44374 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
+     116        44362 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
      117            0 :    logic [31:0]                muldiv_rs1_d;
      118            4 :    logic [31:1]                pred_correct_npc_r;
-     119        43944 :    logic                       i0_pred_correct_upper_r;
+     119        43932 :    logic                       i0_pred_correct_upper_r;
      120            0 :    logic [31:1]                i0_flush_path_upper_r;
      121          454 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
      122           30 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
-     124          362 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
-     125          362 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126        44372 :    logic                       i0_taken_d;
-     127        44370 :    logic                       i0_taken_x;
-     128        44724 :    logic                       i0_valid_d;
-     129        44722 :    logic                       i0_valid_x;
-     130          362 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
+     124          360 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
+     125          360 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
+     126        44360 :    logic                       i0_taken_d;
+     127        44358 :    logic                       i0_taken_x;
+     128        44712 :    logic                       i0_valid_d;
+     129        44710 :    logic                       i0_valid_x;
+     130          360 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
      132            0 :    el2_predict_pkt_t          final_predict_mp;
      133            0 :    el2_predict_pkt_t          i0_predict_newp_d;
@@ -247,13 +247,13 @@
      143          428 :    logic                       i0_flush_upper_d;
      144            0 :    logic [31:1]                i0_flush_path_d;
      145            0 :    el2_predict_pkt_t          i0_predict_p_d;
-     146        43948 :    logic                       i0_pred_correct_upper_d;
+     146        43936 :    logic                       i0_pred_correct_upper_d;
      147              : 
      148          428 :    logic                       i0_flush_upper_x;
      149            0 :    logic [31:1]                i0_flush_path_x;
      150            0 :    el2_predict_pkt_t          i0_predict_p_x;
-     151        43946 :    logic                       i0_pred_correct_upper_x;
-     152        44730 :    logic                       i0_branch_x;
+     151        43934 :    logic                       i0_pred_correct_upper_x;
+     152        44718 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
      155            0 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_alu_ctl.sv.html
index 8e63bc51cf0..9938991a9e2 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        90604 :    input  logic                  clk,                // Top level clock
+      23        90580 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
@@ -136,7 +136,7 @@
       32            0 :    input  logic                  csr_ren_in,         // CSR select
       33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34            0 :    input  logic signed [31:0]    a_in,               // A operand
-      35        44374 :    input  logic        [31:0]    b_in,               // B operand
+      35        44362 :    input  logic        [31:0]    b_in,               // B operand
       36            0 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
       37            0 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
       38           64 :    input  logic        [12:1]    brimm_in,           // Branch offset
@@ -147,7 +147,7 @@
       43          436 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
       44            0 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            0 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46        43948 :    output logic                  pred_correct_out,   // NPC control
+      46        43936 :    output logic                  pred_correct_out,   // NPC control
       47            0 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
@@ -160,13 +160,13 @@
       56            0 :    logic                         sel_shift;
       57          434 :    logic                         sel_adder;
       58            0 :    logic                         slt_one;
-      59        44372 :    logic                         actual_taken;
+      59        44360 :    logic                         actual_taken;
       60            0 :    logic               [31:1]    pcout;
       61          428 :    logic                         cond_mispredict;
       62            0 :    logic                         target_mispredict;
       63            2 :    logic                         eq, ne, lt, ge;
       64          360 :    logic                         any_jal;
-      65         4190 :    logic               [1:0]     newhist;
+      65         4186 :    logic               [1:0]     newhist;
       66          360 :    logic                         sel_pc;
       67            0 :    logic               [31:0]    csr_write_data;
       68            0 :    logic               [31:0]    result;
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342      4107680 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343      4107680 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342      3972896 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343      3972896 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_div_ctl.sv.html
index 6fa6ab90f4f..a34489ea4e8 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,13 +124,13 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23        90604 :    input logic           clk,                       // Top level clock
+      23        90580 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
       27            0 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
       28            0 :    input logic  [31:0]   dividend,                  // Numerator
-      29        44374 :    input logic  [31:0]   divisor,                   // Denominator
+      29        44362 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
@@ -1414,7 +1414,7 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313        90604 :    input  logic            clk,                       // Top level clock
+    1313        90580 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
@@ -1423,7 +1423,7 @@
     1319            2 :    input  logic            signed_in,
     1320            0 :    input  logic            rem_in,
     1321            0 :    input  logic [31:0]     dividend_in,
-    1322        44374 :    input  logic [31:0]     divisor_in,
+    1322        44362 :    input  logic [31:0]     divisor_in,
     1323              : 
     1324            0 :    output logic            valid_out,
     1325            0 :    output logic [31:0]     data_out
@@ -1446,7 +1446,7 @@
     1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
     1344            0 :    logic                   b_enable, b_twos_comp;
-    1345        44374 :    logic        [32:0]     b_in;
+    1345        44362 :    logic        [32:0]     b_in;
     1346            0 :    logic        [37:0]     b_ff;
     1347              : 
     1348            0 :    logic        [31:0]     q_in, q_ff;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_mul_ctl.sv.html
index 560a8e61119..b952f3f73dc 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23        90604 :    input logic          clk,              // Top level clock
+      23        90580 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209      4107680 :              if (bcompress_test_bit_d)
+     209      3972896 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236      4107680 :              if (bdecompress_test_bit_d)
+     236      3972896 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu.sv.html
index 3c33906c962..27feb15bac7 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,9 +129,9 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28        90604 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29        90604 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30        90604 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28        90580 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        90580 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        90580 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
       33          454 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
@@ -275,24 +275,24 @@
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
      172          360 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173            0 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174        45112 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174        45100 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
      176           26 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
      178            0 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
      179            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
-     180          362 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
+     180          360 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
      181            0 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
      182            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
      183              : 
      184            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
      185          396 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
-     186          362 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+     186          360 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
      187            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
      188            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
      189              : 
      190            0 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
-     191          362 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+     191          360 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
      192            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
      193            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
      194              : 
@@ -339,16 +339,16 @@
      235          814 :    logic ic_hit_f;
      236              : 
      237          842 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238        44694 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     238        44682 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
      239            0 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240        43980 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     240        43968 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
      241          720 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
      242          704 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243        44314 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     243        44302 :    logic [11:0] ifu_bp_poffset_f; // predicted target
      244            0 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
      245          716 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
      246          716 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
-     247          362 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
+     247          360 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
      248            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
      249              : 
      250              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_aln_ctl.sv.html
index 15fc1cbe369..49dadcabedf 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30        90604 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31        90604 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30        90580 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        90580 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -160,15 +160,15 @@
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
       57          360 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58            0 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59        45112 :    output logic                                   ifu_i0_pc4,
+      59        45100 :    output logic                                   ifu_i0_pc4,
       60              : 
       61          740 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62        43592 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      62        43580 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
-      65          362 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
+      65          360 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
       66            0 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67        44314 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      67        44302 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
       70          704 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
@@ -181,7 +181,7 @@
       77              : 
       78            0 :    output el2_br_pkt_t                           i0_brp,                   // Branch packet for I0.
       79            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]   ifu_i0_bp_index,          // BP index
-      80          362 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
+      80          360 :    output logic [pt.BHT_GHR_SIZE-1:0]             ifu_i0_bp_fghr,           // BP FGHR
       81            0 :    output logic [pt.BTB_BTAG_SIZE-1:0]            ifu_i0_bp_btag,           // BP tag
       82              : 
       83            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
@@ -203,22 +203,22 @@
       99            0 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
      101          360 :    logic [31:0]                                   aligndata;
-     102        45112 :    logic                                          first4B, first2B;
+     102        45100 :    logic                                          first4B, first2B;
      103              : 
      104            4 :    logic [31:0]                                   uncompress0;
      105          454 :    logic                                          i0_shift;
-     106        44746 :    logic                                          shift_2B, shift_4B;
-     107        44376 :    logic                                          f1_shift_2B;
+     106        44734 :    logic                                          shift_2B, shift_4B;
+     107        44364 :    logic                                          f1_shift_2B;
      108          364 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
      110          360 :    logic [31:0]                                   ifirst;
      111          446 :    logic [1:0]                                    alignval;
      112            0 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114        44316 :    logic [11:0]                                   f1poffset;
+     114        44304 :    logic [11:0]                                   f1poffset;
      115          368 :    logic [11:0]                                   f0poffset;
-     116          362 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
-     117          362 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
+     116          360 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
+     117          360 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
      118          364 :    logic [1:0]                                    f1hist1;
      119          716 :    logic [1:0]                                    f0hist1;
      120          352 :    logic [1:0]                                    f1hist0;
@@ -234,21 +234,21 @@
      130              : 
      131            0 :    logic [1:0]                                    f1ret;
      132            0 :    logic [1:0]                                    f0ret;
-     133        43520 :    logic [1:0]                                    f1way;
-     134        43950 :    logic [1:0]                                    f0way;
+     133        43508 :    logic [1:0]                                    f1way;
+     134        43938 :    logic [1:0]                                    f0way;
      135              : 
      136          360 :    logic [1:0]                                    f1brend;
      137          716 :    logic [1:0]                                    f0brend;
      138              : 
-     139        44724 :    logic [1:0]                                    alignbrend;
-     140        44724 :    logic [1:0]                                    alignpc4;
+     139        44712 :    logic [1:0]                                    alignbrend;
+     140        44712 :    logic [1:0]                                    alignpc4;
      141              : 
      142            0 :    logic [1:0]                                    alignret;
-     143        44310 :    logic [1:0]                                    alignway;
-     144        41370 :    logic [1:0]                                    alignhist1;
-     145        40542 :    logic [1:0]                                    alignhist0;
-     146        44380 :    logic [1:1]                                    alignfromf1;
-     147        44376 :    logic                                          i0_ends_f1;
+     143        44298 :    logic [1:0]                                    alignway;
+     144        41362 :    logic [1:0]                                    alignhist1;
+     145        40534 :    logic [1:0]                                    alignhist0;
+     146        44368 :    logic [1:1]                                    alignfromf1;
+     147        44364 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
      150            0 :    logic [31:1]                                   f1prett;
@@ -260,34 +260,34 @@
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159        44724 :    logic                                          i0_brp_pc4;
+     159        44712 :    logic                                          i0_brp_pc4;
      160              : 
      161            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165        29961 :    logic [1:0]                                    wrptr, wrptr_in;
-     166        14788 :    logic [1:0]                                    rdptr, rdptr_in;
-     167        29557 :    logic [2:0]                                    qwen;
+     165        29953 :    logic [1:0]                                    wrptr, wrptr_in;
+     166        14784 :    logic [1:0]                                    rdptr, rdptr_in;
+     167        29549 :    logic [2:0]                                    qwen;
      168            2 :    logic [31:0]                                   q2,q1,q0;
-     169        29541 :    logic                                          q2off_in, q2off;
-     170        29951 :    logic                                          q1off_in, q1off;
-     171        29260 :    logic                                          q0off_in, q0off;
+     169        29533 :    logic                                          q2off_in, q2off;
+     170        29943 :    logic                                          q1off_in, q1off;
+     171        29252 :    logic                                          q0off_in, q0off;
      172          794 :    logic                                          f0_shift_2B;
      173              : 
      174           22 :    logic [31:0]                                   q0eff;
      175           10 :    logic [31:0]                                   q0final;
-     176        44384 :    logic                                          q0ptr;
-     177        44384 :    logic [1:0]                                    q0sel;
+     176        44372 :    logic                                          q0ptr;
+     177        44372 :    logic [1:0]                                    q0sel;
      178              : 
      179            6 :    logic [31:0]                                   q1eff;
      180          370 :    logic [15:0]                                   q1final;
-     181        44010 :    logic                                          q1ptr;
-     182        44010 :    logic [1:0]                                    q1sel;
+     181        43998 :    logic                                          q1ptr;
+     182        43998 :    logic [1:0]                                    q1sel;
      183              : 
-     184        14788 :    logic [2:0]                                    qren;
+     184        14784 :    logic [2:0]                                    qren;
      185              : 
-     186        43952 :    logic                                          consume_fb1, consume_fb0;
+     186        43940 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
@@ -300,7 +300,7 @@
      196              :    localparam                                     MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));
      197              : 
      198            6 :    logic [MHI:0]                                  misc_data_in, misc2, misc1, misc0;
-     199          362 :    logic [MHI:0]                                  misc1eff, misc0eff;
+     199          360 :    logic [MHI:0]                                  misc1eff, misc0eff;
      200              : 
      201            0 :    logic [pt.BTB_BTAG_SIZE-1:0]                  firstbrtag_hash, secondbrtag_hash;
      202              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_bp_ctl.sv.html
index ac2d093f574..7d038ed4fda 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,7 +135,7 @@
       31              :  )
       32              :   (
       33              : 
-      34        90604 :    input logic clk,
+      34        90580 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
       37          814 :    input logic ic_hit_f,      // Icache hit, enables F address capture
@@ -144,7 +144,7 @@
       40          382 :    input logic ifc_fetch_req_f,  // F1 valid
       41              : 
       42            0 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors
-      43          362 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
+      43          360 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
       44            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
       45              : 
       46            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index
@@ -157,17 +157,17 @@
       53            0 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
       54              : 
       55          396 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)
-      56          362 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
+      56          360 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
       57            0 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
       58            0 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
       59              : 
       60          436 :    input logic exu_flush_final, // all flushes
       61              : 
-      62        44694 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      62        44682 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
       63            0 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64        43980 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      64        43968 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
-      66          362 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
+      66          360 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
       68          842 :    output logic [1:0] ifu_bp_way_f, // way
       69            0 :    output logic [1:0] ifu_bp_ret_f, // predicted ret
@@ -175,7 +175,7 @@
       71          704 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
       72          716 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
       73          716 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74        44314 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      74        44302 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -216,19 +216,19 @@
      112          428 :    logic [1:0] exu_mp_hist; // new history
      113          424 :    logic [11:0] exu_mp_tgt; // target offset
      114            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115        44660 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116        44300 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     115        44648 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116        44288 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
      117            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
-     120          362 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
+     120          360 :    logic [pt.BHT_GHR_SIZE-1:0]             exu_i0_br_fghr_wb;
      121              : 
      122           60 :    logic use_mp_way, use_mp_way_p1;
      123            0 :    logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;
      124            0 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127        44314 :    logic [11:0]       btb_rd_tgt_f;
+     127        44302 :    logic [11:0]       btb_rd_tgt_f;
      128          384 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
      129          368 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
@@ -246,7 +246,7 @@
      142           60 :    logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;
      143              : 
      144            0 :    logic  branch_error_bank_conflict_f;
-     145          362 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
+     145          360 :    logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;
      146            0 :    logic [1:0] num_valids;
      147            0 :    logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,
      148          384 :                         fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,
@@ -262,7 +262,7 @@
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161        44370 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     161        44358 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
      162            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
      164          878 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
@@ -270,7 +270,7 @@
      166              : 
      167          360 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169        44694 :    logic                                         final_h;
+     169        44682 :    logic                                         final_h;
      170            0 :    logic                                         btb_fg_crossing_f;
      171          428 :    logic                                         middle_of_bank;
      172              : 
@@ -286,13 +286,13 @@
      182            0 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
      183            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185        44370 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185        44358 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
      187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
      189              : 
      190            0 :     logic [1:0]                                  bht_bank0_rd_data_f;
-     191         3314 :     logic [1:0]                                  bht_bank1_rd_data_f;
+     191         3311 :     logic [1:0]                                  bht_bank1_rd_data_f;
      192            0 :     logic [1:0]                                  bht_bank0_rd_data_p1_f;
      193              :    genvar                                        j, i;
      194              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372        44314 :    logic [16:1] btb_sel_data_f;
+     372        44302 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -561,7 +561,7 @@
      457              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH
      458              :                                             ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP
      459              : 
-     460          362 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
+     460          360 :    logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;
      461              :    assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];
      462              : 
      463              :    assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500        44340 : logic [1:0] bloc_f;
-     501        44340 : logic use_fa_plus;
+     500        44328 : logic [1:0] bloc_f;
+     501        44328 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -720,7 +720,7 @@
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
      618          428 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619        44660 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     619        44648 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676       128361 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676       124149 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678       128361 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679       128361 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678       124149 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679       124149 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684       128361 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684       124149 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686       128361 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687       128361 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686       124149 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687       124149 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877       128361 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878       128361 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879       128361 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877       124149 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878       124149 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879       124149 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881       128361 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882       128361 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881       124149 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882       124149 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_compress_ctl.sv.html
index 325db136137..f216a93f21c 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              :    );
       29              : 
       30              : 
-      31        44742 :    logic               legal;
+      31        44730 :    logic               legal;
       32              : 
       33            4 :    logic [15:0]  i;
       34              : 
@@ -144,22 +144,22 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43        44742 :    logic rdrd;
-      44        44738 :    logic rdrs1;
+      43        44730 :    logic rdrd;
+      44        44726 :    logic rdrs1;
       45            0 :    logic rs2rs2;
       46            0 :    logic rdprd;
       47            0 :    logic rdprs1;
       48            0 :    logic rs2prs2;
-      49        44744 :    logic rs2prd;
-      50        44744 :    logic uimm9_2;
+      49        44732 :    logic rs2prd;
+      50        44732 :    logic uimm9_2;
       51            0 :    logic ulwimm6_2;
       52            0 :    logic ulwspimm7_2;
       53            0 :    logic rdeq2;
       54            0 :    logic rdeq1;
-      55        44744 :    logic rs1eq2;
+      55        44732 :    logic rs1eq2;
       56            0 :    logic sbroffset8_1;
       57            0 :    logic simm9_4;
-      58        44742 :    logic simm5_0;
+      58        44730 :    logic simm5_0;
       59            0 :    logic sjaloffset11_1;
       60            0 :    logic sluimm17_12;
       61            0 :    logic uimm5_0;
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115        44374 :    logic [5:0] simm5d;
+     115        44362 :    logic [5:0] simm5d;
      116            4 :    logic [9:2] uimm9d;
      117              : 
-     118        44374 :    logic [9:4] simm9d;
-     119        44374 :    logic [6:2] ulwimm6d;
-     120        44374 :    logic [7:2] ulwspimm7d;
-     121        44374 :    logic [5:0] uimm5d;
+     118        44362 :    logic [9:4] simm9d;
+     119        44362 :    logic [6:2] ulwimm6d;
+     120        44362 :    logic [7:2] ulwspimm7d;
+     121        44362 :    logic [5:0] uimm5d;
      122            4 :    logic [20:1] sjald;
      123              : 
-     124        44374 :    logic [31:12] sluimmd;
+     124        44362 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,8 +272,8 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171        44374 :    logic [8:1]   sbr8d;
-     172        44374 :    logic [6:2]   uswimm6d;
+     171        44362 :    logic [8:1]   sbr8d;
+     172        44362 :    logic [6:2]   uswimm6d;
      173            4 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ic_mem.sv.html
index b7c0084f1d7..87935d2258a 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26        90604 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27        90604 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26        90580 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27        90580 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91        90604 :       input logic clk,
-      92        90604 :       input logic active_clk,
+      91        90580 :       input logic clk,
+      92        90580 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803        90604 :       input logic                                                   clk,
-     804        90604 :       input logic                                                   active_clk,
+     803        90580 :       input logic                                                   clk,
+     804        90580 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_iccm_mem.sv.html
index 209f318bf4f..7bf71f3e0b6 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,8 +129,8 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28        90604 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29        90604 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28        90580 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29        90580 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
@@ -159,7 +159,7 @@
       55            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
       57            0 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58        44384 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      58        44372 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
       59          362 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
       60            0 :    logic             [63:0]              iccm_rd_data_pre;
       61            0 :    logic             [63:0]              iccm_data;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ifc_ctl.sv.html
index aaae519969d..2829f808bc6 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29        90604 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30        90604 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29        90580 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        90580 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
@@ -140,13 +140,13 @@
       36           30 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
       38          740 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39        43592 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      39        43580 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
       41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
       42          436 :    input logic exu_flush_final, // FLush
       43            0 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45        44694 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      45        44682 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
       46            0 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
       48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_mem_ctl.sv.html
index 2679a3b2a2c..1ef0a52a53d 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,9 +131,9 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30        90604 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31        90604 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32        90604 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30        90580 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        90580 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32        90580 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
       35          436 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
@@ -150,9 +150,9 @@
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       47          438 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49        44694 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49        44682 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51        43980 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51        43968 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
       53           26 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
       54           30 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
@@ -535,7 +535,7 @@
      431              : 
      432           24 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434        44670 :    logic   ifu_bp_hit_taken_q_f;
+     434        44658 :    logic   ifu_bp_hit_taken_q_f;
      435           48 :    logic   ifu_bus_rvalid_unq;
      436           24 :    logic   bus_cmd_beat_en;
      437              : 
@@ -587,9 +587,9 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486       128277 :          IDLE: begin : idle
-     487       128277 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488       128277 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486       124065 :          IDLE: begin : idle
+     487       124065 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488       124065 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
      490           48 :          CRIT_BYP_OK: begin : crit_byp_ok
      491           48 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945       128361 :       ERR_IDLE: begin : err_idle
-     946       128361 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947       128361 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948       128361 :         perr_sb_write_status = perr_state_en;
+     945       124149 :       ERR_IDLE: begin : err_idle
+     946       124149 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947       124149 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948       124149 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990       128361 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991       128361 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992       128361 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990       124149 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991       124149 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992       124149 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446       128361 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447       128361 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446       124149 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447       124149 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509       128361 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510       128361 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511       256722 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509       124149 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510       124149 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511       248298 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lib.sv.html
index 9bcaeb7b922..e96c4ffb63c 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -159,8 +159,8 @@
       55              : `include "el2_param.vh"
       56              :  )(
       57            0 :                        input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,
-      58         1482 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
-      59         1482 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
+      58         1476 :                        input logic [pt.BHT_GHR_SIZE-1:0] ghr,
+      59         1476 :                        output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash
       60              :                        );
       61              : 
       62              :    // The hash function is too complex to write in verilog for all cases.
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu.sv.html
index 9522baf6603..8343fc5643a 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -283,8 +283,8 @@
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182        90604 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183        90604 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182        90580 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183        90580 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
      186            0 :     output logic [31:0] lsu_pmp_addr_start,
@@ -383,14 +383,14 @@
      279              :    // Clocks
      280            0 :    logic        lsu_busm_clken;
      281            0 :    logic        lsu_bus_obuf_c1_clken;
-     282        90604 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283        90604 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284        90604 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     282        90580 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283        90580 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284        90580 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286        90604 :    logic        lsu_stbuf_c1_clk;
-     287        90604 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286        90580 :    logic        lsu_stbuf_c1_clk;
+     287        90580 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289        90604 :    logic        lsu_free_c2_clk;
+     289        90580 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_addrcheck.sv.html
index 2d8bb3afa60..3cb0e0761b1 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30        90604 :    input logic          lsu_c2_m_clk,              // clock
+      30        90580 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
       33            0 :    input logic [31:0]   start_addr_d,              // start address for lsu
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_buffer.sv.html
index 5afc6f7a8de..39d2285ac44 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31        90604 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31        90580 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -144,11 +144,11 @@
       40              :    // various clocks needed for the bus reads and writes
       41            0 :    input logic                          lsu_bus_obuf_c1_clken,
       42            0 :    input logic                          lsu_busm_clken,
-      43        90604 :    input logic                          lsu_c2_r_clk,
-      44        90604 :    input logic                          lsu_bus_ibuf_c1_clk,
+      43        90580 :    input logic                          lsu_c2_r_clk,
+      44        90580 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46        90604 :    input logic                          lsu_bus_buf_c1_clk,
-      47        90604 :    input logic                          lsu_free_c2_clk,
+      46        90580 :    input logic                          lsu_bus_buf_c1_clk,
+      47        90580 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
@@ -445,15 +445,15 @@
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344       385091 :    function automatic logic [2:0] f_Enc8to3;
+     344       372455 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348       385091 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349       385091 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350       385091 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348       372455 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349       372455 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350       372455 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352       385091 :       return Enc_value[2:0];
+     352       372455 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -758,14 +758,14 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657       513444 :             IDLE: begin
-     658       513444 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659       513444 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660       513444 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661       513444 :                      buf_wr_en[i]    = buf_state_en[i];
-     662       513444 :                      buf_data_en[i]  = buf_state_en[i];
-     663       513444 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664       513444 :                      buf_cmd_state_bus_en[i]  = '0;
+     657       496596 :             IDLE: begin
+     658       496596 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659       496596 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660       496596 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661       496596 :                      buf_wr_en[i]    = buf_state_en[i];
+     662       496596 :                      buf_data_en[i]  = buf_state_en[i];
+     663       496596 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664       496596 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_intf.sv.html
index 8c075ae7712..0e13577c253 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30        90604 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30        90580 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -143,13 +143,13 @@
       39            0 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
       40            0 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42        90604 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43        90604 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44        90604 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42        90580 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43        90580 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44        90580 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46        90604 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47        90604 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48        90604 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46        90580 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47        90580 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48        90580 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
       51            4 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_clkdomain.sv.html
index 002754e34ee..61d3ecfcaa2 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31        90604 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32        90604 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31        90580 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32        90580 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -160,22 +160,22 @@
       56            0 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
       57            0 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59        90604 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60        90604 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59        90580 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60        90580 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62        90604 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63        90604 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62        90580 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63        90580 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65        90604 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66        90604 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65        90580 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66        90580 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68        90604 :    output logic     lsu_stbuf_c1_clk,
+      68        90580 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70        90604 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71        90604 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70        90580 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71        90580 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74        90604 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74        90580 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_ctl.sv.html
index 6c2ef537442..f60d6887a82 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,13 +136,13 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35        90604 :    input logic                             lsu_c2_m_clk,            // clocks
-      36        90604 :    input logic                             lsu_c2_r_clk,            // clocks
-      37        90604 :    input logic                             lsu_c1_r_clk,            // clocks
-      38        90604 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39        90604 :    input logic                             lsu_free_c2_clk,         // clocks
+      35        90580 :    input logic                             lsu_c2_m_clk,            // clocks
+      36        90580 :    input logic                             lsu_c2_r_clk,            // clocks
+      37        90580 :    input logic                             lsu_c1_r_clk,            // clocks
+      38        90580 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39        90580 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41        90604 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41        90580 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_mem.sv.html
index ae02e370c57..5fc007e5aa8 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35        90604 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36        90604 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35        90580 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36        90580 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_ecc.sv.html
index 64d93aa6429..819bd8a14fc 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,8 +135,8 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34        90604 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35        90604 :    input logic                           lsu_c2_r_clk,       // clock
+      34        90580 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        90580 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_lsc_ctl.sv.html
index 8e64d5c9ede..4a10cfe0f0e 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35        90604 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35        90580 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38        90604 :    input logic                lsu_c1_m_clk,
-      39        90604 :    input logic                lsu_c1_r_clk,
-      40        90604 :    input logic                lsu_c2_m_clk,
-      41        90604 :    input logic                lsu_c2_r_clk,
-      42        90604 :    input logic                lsu_store_c1_m_clk,
+      38        90580 :    input logic                lsu_c1_m_clk,
+      39        90580 :    input logic                lsu_c1_r_clk,
+      40        90580 :    input logic                lsu_c2_m_clk,
+      41        90580 :    input logic                lsu_c2_r_clk,
+      42        90580 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_stbuf.sv.html
index b32c28b80b9..8fe614699d6 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,11 +137,11 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36        90604 :    input logic                           clk,                         // core clock
+      36        90580 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39        90604 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40        90604 :    input logic                           lsu_free_c2_clk,             // free clk
+      39        90580 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40        90580 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_trigger.sv.html
index fd2ac80ee57..d83772bb946 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem.sv.html
index 3ef673997c2..d1415f75f35 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25        90604 :    input logic         clk,
+      25        90580 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92        90604 :    logic active_clk;
+      92        90580 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem_if.sv.html
index 8a3cadee921..1f73f83168a 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29       271464 :   logic                                                               clk;
+      29       271392 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pic_ctrl.sv.html
index 2ec27a01526..2c74bc4741a 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              :  )
       28              :                   (
       29              : 
-      30        90604 :                      input  logic                   clk,                  // Core clock
-      31        90604 :                      input  logic                   free_clk,             // free clock
+      30        90580 :                      input  logic                   clk,                  // Core clock
+      31        90580 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155        90604 :    logic                                     pic_raddr_c1_clk;
-     156        90604 :    logic                                     pic_data_c1_clk;
-     157        90604 :    logic                                     pic_pri_c1_clk;
-     158        90604 :    logic                                     pic_int_c1_clk;
-     159        90604 :    logic                                     gw_config_c1_clk;
+     155        90580 :    logic                                     pic_raddr_c1_clk;
+     156        90580 :    logic                                     pic_data_c1_clk;
+     157        90580 :    logic                                     pic_pri_c1_clk;
+     158        90580 :    logic                                     pic_int_c1_clk;
+     159        90580 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500      4107552 :               if (intenable_reg_re[i]) begin
+     500      3972768 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503      4107552 :               if (intpriority_reg_re[i]) begin
+     503      3972768 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506      4107552 :               if (gw_config_reg_re[i]) begin
+     506      3972768 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562      2805128 :                              input logic rawclk,
+     562      2804384 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pmp.sv.html
index 3c896d93302..f5d0c9dae24 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,7 +127,7 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26        90604 :     input logic clk,       // Top level clock
+      26        90580 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133      6161520 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133      5959344 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139      6161520 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139      5959344 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -270,7 +270,7 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169      6161520 :       if (!matched && match_all[r]) begin
+     169      5959344 :       if (!matched && match_all[r]) begin
      170            0 :         access_fail = ~final_perm_check[r];
      171            0 :         matched = 1'b1;
      172              :       end
@@ -348,7 +348,7 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247      6161328 :           OFF:     region_match_all[c][r] = 1'b0;
+     247      5959152 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
      250            0 :           TOR: begin
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer.sv.html
index 4087484e374..a91dfb99239 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29        90604 :    input logic                  clk,
+      29        90580 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
@@ -138,8 +138,8 @@
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37        90604 :    output logic                 active_l2clk,
-      38        90604 :    output logic                 free_l2clk,
+      37        90580 :    output logic                 active_l2clk,
+      38        90580 :    output logic                 free_l2clk,
       39              : 
       40            2 :    output logic [31:0] trace_rv_i_insn_ip,
       41            0 :    output logic [31:0] trace_rv_i_address_ip,
@@ -653,7 +653,7 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552        44374 :    logic [31:0] dec_i0_immed_d;
+     552        44362 :    logic [31:0] dec_i0_immed_d;
      553           64 :    logic [12:1] dec_i0_br_immed_d;
      554          360 :    logic         dec_i0_select_pc_d;
      555              : 
@@ -662,7 +662,7 @@
      558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
      560          450 :    logic         dec_i0_alu_decode_d;
-     561        44732 :    logic         dec_i0_branch_d;
+     561        44720 :    logic         dec_i0_branch_d;
      562              : 
      563           26 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
@@ -725,7 +725,7 @@
      621            0 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624        45112 :    logic        ifu_i0_pc4;
+     624        45100 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
@@ -744,15 +744,15 @@
      640              : 
      641            0 :    el2_predict_pkt_t  exu_mp_pkt;
      642          396 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
-     643          362 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
+     643          360 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
      644            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
-     647          362 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648        44300 :    logic [1:0]  exu_i0_br_hist_r;
+     647          360 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
+     648        44288 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651        44364 :    logic        exu_i0_br_valid_r;
+     651        44352 :    logic        exu_i0_br_valid_r;
      652          424 :    logic        exu_i0_br_mp_r;
      653          370 :    logic        exu_i0_br_middle_r;
      654              : 
@@ -797,7 +797,7 @@
      693              : 
      694            0 :    el2_br_pkt_t i0_brp;
      695            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
-     696          362 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
+     696          360 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
      697            0 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
      698              : 
      699            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
@@ -806,7 +806,7 @@
      702              : 
      703            0 :    el2_predict_pkt_t dec_i0_predict_p_d;
      704              : 
-     705          362 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
+     705          360 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
      706            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
      707            0 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
      708              : 
@@ -894,8 +894,8 @@
      790              : 
      791              :    // PMU Signals
      792          424 :    logic                   exu_pmu_i0_br_misp;
-     793        44368 :    logic                   exu_pmu_i0_br_ataken;
-     794        44740 :    logic                   exu_pmu_i0_pc4;
+     793        44356 :    logic                   exu_pmu_i0_br_ataken;
+     794        44728 :    logic                   exu_pmu_i0_pc4;
      795              : 
      796            0 :    logic                   lsu_pmu_load_external_m;
      797            0 :    logic                   lsu_pmu_store_external_m;
@@ -913,8 +913,8 @@
      809           24 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812        90604 :    logic                   free_clk;
-     813        90604 :    logic                   active_clk;
+     812        90580 :    logic                   free_clk;
+     813        90580 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer_wrapper.sv.html
index ca61d672dd9..05d579d0547 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30        90604 :    input logic                             clk,
+      30        90580 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
@@ -454,8 +454,8 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353        90604 :    logic                             active_l2clk;
-     354        90604 :    logic                             free_l2clk;
+     353        90580 :    logic                             active_l2clk;
+     354        90580 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_mem_lib.sv.html
index f1652775114..93195b0f6e0 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111      2053744 : `EL2_RAM(4096, 39)
+     111      1986352 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
diff --git a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_rvjtag_tap.v.html
index 1a1771114d9..2e2473d0a62 100644
--- a/html/main/coverage_dashboard/all_openocd_ahb_lite/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_openocd_ahb_lite/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -217,9 +217,9 @@
      113              :     endcase
      114              : end
      115              : 
-     116        13288 : always @ (posedge tck or negedge trst) begin
-     117        13288 :     if(!trst) state <= TEST_LOGIC_RESET_STATE;
-     118        13288 :     else state <= nstate;
+     116        13185 : always @ (posedge tck or negedge trst) begin
+     117        13185 :     if(!trst) state <= TEST_LOGIC_RESET_STATE;
+     118        13185 :     else state <= nstate;
      119              : end
      120              : 
      121              : assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
@@ -238,11 +238,11 @@
      134              : //                      IR register
      135              : ///////////////////////////////////////////////////////
      136              : 
-     137        13288 : always @ (negedge tck or negedge trst) begin
-     138        13288 :    if (!trst) ir <= 5'b1;
-     139        13288 :    else begin
+     137        13185 : always @ (negedge tck or negedge trst) begin
+     138        13185 :    if (!trst) ir <= 5'b1;
+     139        13185 :    else begin
      140           30 :       if (jtag_reset) ir <= 5'b1;
-     141          114 :       else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
+     141          113 :       else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
      142              :    end
      143              : end
      144              : 
@@ -254,12 +254,12 @@
      150              : ///////////////////////////////////////////////////////
      151              : //                      Shift register
      152              : ///////////////////////////////////////////////////////
-     153        13288 : always @ (posedge tck or negedge trst) begin
-     154        13288 :     if(!trst)begin
+     153        13185 : always @ (posedge tck or negedge trst) begin
+     154        13185 :     if(!trst)begin
      155            0 :         sr <= '0;
      156              :     end
-     157        13288 :     else begin
-     158        13288 :         sr <= nsr;
+     157        13185 :     else begin
+     158        13185 :         sr <= nsr;
      159              :     end
      160              : end
      161              : 
@@ -267,33 +267,33 @@
      163            2 : always_comb begin
      164            2 :     nsr = sr;
      165            2 :     case(1)
-     166        10820 :     shift_dr:   begin
-     167        10820 :                     case(1)
-     168        18696 :                     dr_en[1]:   nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
+     166        10738 :     shift_dr:   begin
+     167        10738 :                     case(1)
+     168        18532 :                     dr_en[1]:   nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
      169              : 
      170              :                     dr_en[0],
      171         2944 :                     devid_sel:  nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
      172            0 :                     default:    nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
      173              :                     endcase
      174              :                 end
-     175          234 :     capture_dr: begin
-     176          234 :                     nsr[0] = 1'b0;
-     177          234 :                     case(1)
+     175          232 :     capture_dr: begin
+     176          232 :                     nsr[0] = 1'b0;
+     177          232 :                     case(1)
      178            8 :                     dr_en[0]:   nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
-     179          456 :                     dr_en[1]:   nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
+     179          452 :                     dr_en[1]:   nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
      180            4 :                     devid_sel:  nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
      181              :                     endcase
      182              :                 end
-     183          574 :     shift_ir:   nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
-     184          114 :     capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
+     183          569 :     shift_ir:   nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
+     184          113 :     capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
      185              :     endcase
      186              : end
      187              : 
      188              : // TDO retiming
-     189        13288 : always @ (negedge tck ) tdo <= sr[0];
+     189        13185 : always @ (negedge tck ) tdo <= sr[0];
      190              : 
      191              : // DMI CS register
-     192        13288 : always @ (posedge tck or negedge trst) begin
+     192        13185 : always @ (posedge tck or negedge trst) begin
      193            0 :     if(!trst) begin
      194            0 :         dmi_hard_reset <= 1'b0;
      195            0 :         dmi_reset      <= 1'b0;
@@ -302,21 +302,21 @@
      198            4 :         dmi_hard_reset <= sr[17];
      199            4 :         dmi_reset      <= sr[16];
      200              :     end
-     201        13284 :     else begin
-     202        13284 :         dmi_hard_reset <= 1'b0;
-     203        13284 :         dmi_reset      <= 1'b0;
+     201        13181 :     else begin
+     202        13181 :         dmi_hard_reset <= 1'b0;
+     203        13181 :         dmi_reset      <= 1'b0;
      204              :     end
      205              : end
      206              : 
      207              : // DR register
-     208        13288 : always @ (posedge tck or negedge trst) begin
-     209        13288 :     if(!trst)
+     208        13185 : always @ (posedge tck or negedge trst) begin
+     209        13185 :     if(!trst)
      210            0 :         dr <=  '0;
-     211        13288 :     else begin
-     212          228 :         if (update_dr & dr_en[1])
-     213          228 :             dr <= sr;
+     211        13185 :     else begin
+     212          226 :         if (update_dr & dr_en[1])
+     213          226 :             dr <= sr;
      214              :         else
-     215        13060 :             dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
+     215        12959 :             dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
      216              :     end
      217              : end
      218              : 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index.html b/html/main/coverage_dashboard/all_openocd_axi4/index.html
index 972713547e7..c4c946cda99 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design.html
index db4d490f68b..fe644a581a6 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dbg.html
index 42ccb2abb8b..08d684664d1 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dec.html
index aa04809a4ed..3d8711820bd 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dmi.html
index 4c497954a63..e949ae08f66 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_exu.html
index e7f9d5eab47..16a57a59c14 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_ifu.html
index 806deedccef..9fb1407ed21 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_include.html
index c3233342ae9..09778db0b36 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lib.html
index 6cd50c7619e..b5c0c6dbb90 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lsu.html
index aa242e332b2..ffbff3142e1 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_beh_lib.sv.html
index 2ae241aa718..489c93a403f 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,7 +123,7 @@
       19              : module rvdff #( parameter WIDTH=1, SHORT=0 )
       20              :    (
       21            0 :      input logic [WIDTH-1:0] din,
-      22      6085356 :      input logic           clk,
+      22      6085362 :      input logic           clk,
       23            2 :      input logic                   rst_l,
       24              : 
       25            0 :      output logic [WIDTH-1:0] dout
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38      3106817 :    always_ff @(posedge clk or negedge rst_l) begin
+      38      3121783 :    always_ff @(posedge clk or negedge rst_l) begin
       39           10 :       if (rst_l == 0)
       40           10 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42      3106807 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42      3121773 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
@@ -154,7 +154,7 @@
       50              :    (
       51            0 :      input logic [WIDTH-1:0] din,
       52           24 :      input logic             en,
-      53      6085356 :      input logic           clk,
+      53      6085362 :      input logic           clk,
       54            2 :      input logic                   rst_l,
       55            0 :      output logic [WIDTH-1:0] dout
       56              :      );
@@ -174,7 +174,7 @@
       70            0 :      input logic [WIDTH-1:0] din,
       71            0 :      input logic             en,
       72            0 :      input logic             clear,
-      73     24341424 :      input logic           clk,
+      73     24341448 :      input logic           clk,
       74            8 :      input logic                   rst_l,
       75            0 :      output logic [WIDTH-1:0] dout
       76              :      );
@@ -195,7 +195,7 @@
       91            4 :      input logic [WIDTH-1:0] din,
       92            0 :      input logic           clk,
       93            4 :      input logic           clken,
-      94     12170712 :      input logic           rawclk,
+      94     12170724 :      input logic           rawclk,
       95            4 :      input logic           rst_l,
       96              : 
       97            4 :      output logic [WIDTH-1:0] dout
@@ -220,7 +220,7 @@
      116           72 :      input logic             en,
      117            0 :      input logic           clk,
      118            2 :      input logic           clken,
-     119     12170712 :      input logic           rawclk,
+     119     12170724 :      input logic           rawclk,
      120            4 :      input logic           rst_l,
      121              : 
      122            2 :      output logic [WIDTH-1:0] dout
@@ -247,7 +247,7 @@
      143            0 :      input logic             clear,
      144            0 :      input logic             clk,
      145            6 :      input logic             clken,
-     146     18256068 :      input logic             rawclk,
+     146     18256086 :      input logic             rawclk,
      147            6 :      input logic             rst_l,
      148              : 
      149            0 :      output logic [WIDTH-1:0] dout
@@ -271,7 +271,7 @@
      167              :    (
      168            0 :      input  logic [WIDTH-1:0] din,
      169            0 :      input  logic           en,
-     170      6085356 :      input  logic           clk,
+     170      6085362 :      input  logic           clk,
      171            2 :      input  logic           rst_l,
      172            0 :      input  logic             scan_mode,
      173            0 :      output logic [WIDTH-1:0] dout
@@ -310,7 +310,7 @@
      206              : module rvdffpcie #( parameter WIDTH=31 )
      207              :    (
      208            8 :      input  logic [WIDTH-1:0] din,
-     209     73024272 :      input  logic             clk,
+     209     73024344 :      input  logic             clk,
      210           24 :      input  logic             rst_l,
      211       195406 :      input  logic             en,
      212            0 :      input  logic             scan_mode,
@@ -343,7 +343,7 @@
      239              : module rvdfflie #( parameter WIDTH=16, LEFT=8 )
      240              :    (
      241            0 :      input  logic [WIDTH-1:0] din,
-     242      6085356 :      input  logic             clk,
+     242      6085362 :      input  logic             clk,
      243            2 :      input  logic             rst_l,
      244            2 :      input  logic             en,
      245            0 :      input  logic             scan_mode,
@@ -398,7 +398,7 @@
      294              : module rvdffppe #( parameter integer WIDTH = 39 )
      295              :    (
      296            0 :      input  logic [WIDTH-1:0] din,
-     297      6085356 :      input  logic             clk,
+     297      6085362 :      input  logic             clk,
      298            2 :      input  logic             rst_l,
      299           30 :      input  logic             en,
      300            0 :      input  logic             scan_mode,
@@ -442,7 +442,7 @@
      338              :    (
      339            0 :      input  logic [WIDTH-1:0] din,
      340              : 
-     341      6085356 :      input  logic           clk,
+     341      6085362 :      input  logic           clk,
      342            2 :      input  logic           rst_l,
      343            0 :      input  logic             scan_mode,
      344            0 :      output logic [WIDTH-1:0] dout
@@ -519,7 +519,7 @@
      415              : 
      416              : module rvsyncss #(parameter WIDTH = 251)
      417              :    (
-     418      6085356 :      input  logic                 clk,
+     418      6085362 :      input  logic                 clk,
      419            2 :      input  logic                 rst_l,
      420            0 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
@@ -535,7 +535,7 @@
      431              : module rvsyncss_fpga #(parameter WIDTH = 251)
      432              :    (
      433            0 :      input  logic                 gw_clk,
-     434    188646036 :      input  logic                 rawclk,
+     434    188646222 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436           62 :      input  logic                 rst_l,
      437            0 :      input  logic [WIDTH-1:0]     din,
@@ -582,13 +582,13 @@
      478              : module rvbradder
      479              :   (
      480            0 :     input [31:1] pc,
-     481      3018260 :     input [12:1] offset,
+     481      3018263 :     input [12:1] offset,
      482              : 
      483            8 :     output [31:1] dout
      484              :     );
      485              : 
-     486      3042618 :    logic          cout;
-     487      3042618 :    logic          sign;
+     486      3042621 :    logic          cout;
+     487      3042621 :    logic          sign;
      488              : 
      489           16 :    logic [31:13]  pc_inc;
      490            8 :    logic [31:13]  pc_dec;
@@ -825,7 +825,7 @@
      721              : 
      722              : 
      723              : module rvecc_decode_64  (
-     724      2993846 :                       input         en,
+     724      2993849 :                       input         en,
      725        48734 :                       input [63:0]  din,
      726        48734 :                       input [6:0]   ecc_in,
      727            0 :                       output        ecc_error
@@ -897,9 +897,9 @@
      793              : module rvoclkhdr
      794              :   (
      795          562 :    input  logic en,
-     796    164304612 :    input  logic clk,
+     796    164304774 :    input  logic clk,
      797            0 :    input  logic scan_mode,
-     798    164304612 :    output logic l1clk
+     798    164304774 :    output logic l1clk
      799              :    );
      800              : 
      801            0 :    logic   SE;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_jtag_to_core_sync.v.html
index 30f6d09042d..df1bc81fefe 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,7 +133,7 @@
       29              : 
       30              : // Processor Signals
       31            2 : input       rst_n,      // Core reset
-      32      6085356 : input       clk,        // Core clock
+      32      6085362 : input       clk,        // Core clock
       33              : 
       34          240 : output      reg_en,     // 1 bit  Write interface bit to Processor
       35          112 : output      reg_wr_en   // 1 bit  Write enable to Processor
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49      3106817 : always @ ( posedge clk or negedge rst_n) begin
+      49      3121783 : always @ ( posedge clk or negedge rst_n) begin
       50            4 :     if(!rst_n) begin
       51            4 :         rden <= '0;
       52            4 :         wren <= '0;
       53              :     end
-      54      3106813 :     else begin
-      55      3106813 :         rden <= {rden[1:0], rd_en};
-      56      3106813 :         wren <= {wren[1:0], wr_en};
+      54      3121779 :     else begin
+      55      3121779 :         rden <= {rden[1:0], rd_en};
+      56      3121779 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_mux.v.html
index d3c9f9f456f..7e14b759a77 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_wrapper.v.html
index b07294eebec..9dc690434a0 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,7 +137,7 @@
       33              : 
       34              :   // Processor Signals
       35            2 :   input              core_rst_n,          // Core reset                  
-      36      6085356 :   input              core_clk,            // Core clock                  
+      36      6085362 :   input              core_clk,            // Core clock                  
       37            0 :   input [31:1]       jtag_id,             // JTAG ID
       38           12 :   input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
       39           20 :   output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dbg.sv.html
index 87b694a5670..4aa20214d7c 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -211,8 +211,8 @@
      107            2 :    input logic                         dbg_bus_clk_en,
      108              : 
      109              :    // general inputs
-     110      6085356 :    input logic                         clk,
-     111      6085356 :    input logic                         free_clk,
+     110      6085362 :    input logic                         clk,
+     111      6085362 :    input logic                         free_clk,
      112            2 :    input logic                         rst_l,        // This includes both top rst and debug rst
      113            2 :    input logic                         dbg_rst_l,
      114            0 :    input logic                         clk_override,
@@ -356,10 +356,10 @@
      252              : 
      253              :    //clken
      254          240 :    logic              dbg_free_clken;
-     255      6085356 :    logic              dbg_free_clk;
+     255      6085362 :    logic              dbg_free_clk;
      256              : 
      257          240 :    logic              sb_free_clken;
-     258      6085356 :    logic              sb_free_clk;
+     258      6085362 :    logic              sb_free_clk;
      259              : 
      260              :    // clocking
      261              :    // used for the abstract commands.
@@ -575,10 +575,10 @@
      471            2 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            2 :        case (dbg_state)
-     474      3106819 :             IDLE: begin
-     475      3106819 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476      3106819 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477      3106819 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474      3121785 :             IDLE: begin
+     475      3121785 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476      3121785 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477      3121785 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            2 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            2 :       sbaddress0_reg_wren1   = 1'b0;
      603            2 :       case (sb_state)
-     604      3106647 :             SBIDLE: begin
-     605      3106647 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606      3106647 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607      3106647 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608      3106647 :                      sbcs_sbbusy_din        = 1'b1;
-     609      3106647 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610      3106647 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604      3121613 :             SBIDLE: begin
+     605      3121613 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606      3121613 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607      3121613 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608      3121613 :                      sbcs_sbbusy_din        = 1'b1;
+     609      3121613 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610      3121613 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            8 :             WAIT_RD: begin
      613            8 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec.sv.html
index 7f0589a1d29..84f390d7383 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,10 +136,10 @@
       32              : #(
       33              :     `include "el2_param.vh"
       34              : ) (
-      35      6085356 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36      6085356 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      37      6085356 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
-      38      6085356 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      35      6085362 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36      6085362 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      37      6085362 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+      38      6085362 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
       39              : 
       40            0 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
       41              : 
@@ -175,8 +175,8 @@
       71            0 :     output logic debug_brkpt_status,  // debug breakpoint
       72              : 
       73        24402 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
-      74      2993846 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
-      75      3018196 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
+      74      2993849 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
+      75      3018199 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
       76              : 
       77              : 
       78            0 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
@@ -268,7 +268,7 @@
      164        24428 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
      165        24338 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
      166            0 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
-     167      3042546 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
+     167      3042549 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
      168            0 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
@@ -313,10 +313,10 @@
      209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
      210              :     // Debug end
      211              :     // branch info from pipe0 for errors or counter updates
-     212      2993778 :     input  logic [1:0] exu_i0_br_hist_r,         // history
+     212      2993781 :     input  logic [1:0] exu_i0_br_hist_r,         // history
      213            0 :     input  logic       exu_i0_br_error_r,        // error
      214            0 :     input  logic       exu_i0_br_start_error_r,  // start error
-     215      2993842 :     input  logic       exu_i0_br_valid_r,        // valid
+     215      2993845 :     input  logic       exu_i0_br_valid_r,        // valid
      216        24402 :     input  logic       exu_i0_br_mp_r,           // mispredict
      217        24348 :     input  logic       exu_i0_br_middle_r,       // middle of bank
      218              : 
@@ -329,13 +329,13 @@
      225        12054 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
      226            0 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
      227              : 
-     228      2993852 :     output logic [31:0] dec_i0_immed_d,    // immediate data
+     228      2993855 :     output logic [31:0] dec_i0_immed_d,    // immediate data
      229           64 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
      230              : 
      231            0 :     output el2_alu_pkt_t i0_ap,  // alu packet
      232              : 
      233        24428 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
-     234      3018188 :     output logic dec_i0_branch_d,      // Branch in D-stage
+     234      3018191 :     output logic dec_i0_branch_d,      // Branch in D-stage
      235              : 
      236        24338 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
      237              : 
@@ -442,7 +442,7 @@
      338            0 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
      339              : 
      340        24346 :   logic [4:0] dec_i0_rs1_d;
-     341      2993852 :   logic [4:0] dec_i0_rs2_d;
+     341      2993855 :   logic [4:0] dec_i0_rs2_d;
      342              : 
      343        24338 :   logic [31:0] dec_i0_instr_d;
      344              : 
@@ -451,7 +451,7 @@
      347              : 
      348              : 
      349        24404 :   logic [4:0] dec_i0_waddr_r;
-     350      2993860 :   logic dec_i0_wen_r;
+     350      2993863 :   logic dec_i0_wen_r;
      351        12058 :   logic [31:0] dec_i0_wdata_r;
      352            8 :   logic dec_csr_wen_r;  // csr write enable at wb
      353        48742 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
@@ -467,7 +467,7 @@
      363              : 
      364            0 :   el2_trap_pkt_t dec_tlu_packet_r;
      365              : 
-     366      3042546 :   logic dec_i0_pc4_d;
+     366      3042549 :   logic dec_i0_pc4_d;
      367            0 :   logic dec_tlu_presync_d;
      368            8 :   logic dec_tlu_postsync_d;
      369            0 :   logic dec_tlu_debug_stall;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_csr_equ_m.svh.html
index c21be350a6a..9e3a699dede 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_decode_ctl.sv.html
index a8f4a3854da..92e3a41de4f 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -190,7 +190,7 @@
       86            0 :    input logic dec_tlu_presync_d,                     // CSR read needs to be presync'd
       87            8 :    input logic dec_tlu_postsync_d,                    // CSR ops that need to be postsync'd
       88              : 
-      89      3042546 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
+      89      3042549 :    input logic dec_i0_pc4_d,                          // inst is 4B inst else 2B
       90              : 
       91            0 :    input logic [31:0] dec_csr_rddata_d,               // csr read data at wb
       92            8 :    input logic dec_csr_legal_d,                       // csr indicates legal operation
@@ -210,9 +210,9 @@
      106              : 
      107        12058 :    input logic [31:0] exu_i0_result_x,                // from primary alu's
      108              : 
-     109      6085356 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     110      6085356 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-     111      6085356 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
+     109      6085362 :    input logic  clk,                                  // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     110      6085362 :    input logic  active_clk,                           // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     111      6085362 :    input logic  free_l2clk,                           // Clock always.                  Through one clock header.  For flops with    second header built in.
      112              : 
      113            0 :    input logic  clk_override,                         // Override non-functional clock gating
      114            2 :    input logic  rst_l,                                // Flop reset
@@ -223,9 +223,9 @@
      119            0 :    output logic        dec_i0_rs2_en_d,               // rs2 enable at decode
      120              : 
      121        24346 :    output logic [4:0]  dec_i0_rs1_d,                  // rs1 logical source
-     122      2993852 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
+     122      2993855 :    output logic [4:0]  dec_i0_rs2_d,                  // rs2 logical source
      123              : 
-     124      2993852 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
+     124      2993855 :    output logic [31:0] dec_i0_immed_d,                // 32b immediate data decode
      125              : 
      126              : 
      127           64 :    output logic [12:1] dec_i0_br_immed_d,             // 12b branch immediate
@@ -235,10 +235,10 @@
      131        24432 :    output logic        dec_i0_decode_d,               // i0 decode
      132              : 
      133        24428 :    output logic        dec_i0_alu_decode_d,           // decode to D-stage alu
-     134      3018188 :    output logic        dec_i0_branch_d,               // Branch in D-stage
+     134      3018191 :    output logic        dec_i0_branch_d,               // Branch in D-stage
      135              : 
      136        24404 :    output logic [4:0]  dec_i0_waddr_r,                // i0 logical source to write to gpr's
-     137      2993860 :    output logic        dec_i0_wen_r,                  // i0 write enable
+     137      2993863 :    output logic        dec_i0_wen_r,                  // i0 write enable
      138        12058 :    output logic [31:0] dec_i0_wdata_r,                // i0 write data
      139              : 
      140        24338 :    output logic        dec_i0_select_pc_d,            // i0 select pc for rs1 - branches
@@ -319,7 +319,7 @@
      215            4 :    logic               i0_uiimm20;
      216              : 
      217            0 :    logic               lsu_decode_d;
-     218      2993852 :    logic [31:0]        i0_immed_d;
+     218      2993855 :    logic [31:0]        i0_immed_d;
      219            0 :    logic               i0_presync;
      220            8 :    logic               i0_postsync;
      221              : 
@@ -359,7 +359,7 @@
      255           12 :    logic               i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
      256              : 
      257        24404 :    logic [12:1]        last_br_immed_d;
-     258      2969454 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
+     258      2969457 :    logic               i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
      259            0 :    logic               i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
      260              : 
      261            0 :    logic               i0_div_decode_d;
@@ -393,7 +393,7 @@
      289            0 :    logic               i0_jal;                                // jal's that are not predicted
      290              : 
      291              : 
-     292      3018188 :    logic               i0_predict_br;
+     292      3018191 :    logic               i0_predict_br;
      293              : 
      294            0 :    logic               store_data_bypass_d, store_data_bypass_m;
      295              : 
@@ -402,9 +402,9 @@
      298            0 :    el2_class_pkt_t         i0_d_c, i0_x_c, i0_r_c;
      299              : 
      300              : 
-     301      3042546 :    logic               i0_ap_pc2, i0_ap_pc4;
+     301      3042549 :    logic               i0_ap_pc2, i0_ap_pc4;
      302              : 
-     303      2993864 :    logic               i0_rd_en_d;
+     303      2993867 :    logic               i0_rd_en_d;
      304              : 
      305            0 :    logic               load_ldst_bypass_d;
      306              : 
@@ -436,7 +436,7 @@
      332            0 :    logic              pause_state_in, pause_state;
      333            0 :    logic              pause_stall;
      334              : 
-     335      3018180 :    logic              i0_brp_valid;
+     335      3018183 :    logic              i0_brp_valid;
      336            0 :    logic              nonblock_load_cancel;
      337            2 :    logic              lsu_idle;
      338            0 :    logic              lsu_pmu_misaligned_r;
@@ -460,7 +460,7 @@
      356            0 :    logic i0_br_unpred;
      357              : 
      358            0 :    logic nonblock_load_valid_m_delay;
-     359      2993860 :    logic i0_wen_r;
+     359      2993863 :    logic i0_wen_r;
      360              : 
      361            0 :    logic tlu_wr_pause_r1;
      362            0 :    logic tlu_wr_pause_r2;
@@ -631,7 +631,7 @@
      527              : 
      528            2 :    always_comb begin
      529            2 :       i0_dp = i0_dp_raw;
-     530      3106819 :       if (i0_br_error_all | i0_instr_error) begin
+     530      3121785 :       if (i0_br_error_all | i0_instr_error) begin
      531            0 :          i0_dp          =   '0;
      532            0 :          i0_dp.alu      = 1'b1;
      533            0 :          i0_dp.rs1      = 1'b1;
@@ -710,15 +710,15 @@
      606            2 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            2 :          if (~found) begin
      608            0 :             if (~cam[i].valid) begin
-     609      3106823 :                cam_wen[i] = cam_write;
-     610      3106823 :                found = 1'b1;
+     609      3121789 :                cam_wen[i] = cam_write;
+     610      3121789 :                found = 1'b1;
      611              :             end
      612            0 :             else begin
      613            0 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617      9320469 :             cam_wen[i] = 0;
+     617      9365367 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,7 +756,7 @@
      652              : 
      653            8 :          cam[i] = cam_raw[i];
      654              : 
-     655     12427276 :          if (cam_data_reset_val[i])
+     655     12487140 :          if (cam_data_reset_val[i])
      656            0 :            cam[i].valid = 1'b0;
      657              : 
      658            8 :          cam_in[i] = '0;
@@ -767,17 +767,17 @@
      663            0 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
      664            0 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666     12427292 :          else if ( (cam_inv_reset_val[i]) |
+     666     12487156 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
      668            0 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670     12427292 :            cam_in[i] = cam[i];
+     670     12487156 :            cam_in[i] = cam[i];
      671              : 
-     672     12427292 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     672     12487156 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
      673            0 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676     12427276 :          if (dec_tlu_force_halt)
+     676     12487140 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            2 :    always_comb begin
      744            2 :       i0_itype = NULL_OP;
      745              : 
-     746        12563 :       if (i0_legal_decode_d) begin
-     747      3094260 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748      3094260 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749      3094260 :          if (i0_dp.store)                i0_itype = STORE;
-     750      1540913 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751      3094260 :          if (i0_dp.zbb | i0_dp.zbs |
+     746        12623 :       if (i0_legal_decode_d) begin
+     747      3109166 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748      3109166 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749      3109166 :          if (i0_dp.store)                i0_itype = STORE;
+     750      1548336 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751      3109166 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756      3094260 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     756      3109166 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
      757            4 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758      3094260 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759      3094260 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
-     760      3094260 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761      3094260 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762      3094260 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
-     763      3094260 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764      1528484 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765        12425 :          if (i0_dp.jal)                  i0_itype = JAL;
+     758      3109166 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759      3109166 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     760      3109166 :          if (i0_dp.ecall)                i0_itype = ECALL;
+     761      3109166 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762      3109166 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     763      3109166 :          if (i0_dp.mret)                 i0_itype = MRET;
+     764      1535847 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765        12485 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            2 :    always_comb  begin
      860            2 :       lsu_p = '0;
      861              : 
-     862      3106819 :       if (dec_extint_stall) begin
+     862      3121785 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868      3106819 :       else begin
-     869      3106819 :          lsu_p.valid = lsu_decode_d;
+     868      3121785 :       else begin
+     869      3121785 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871      3106819 :          lsu_p.load                         =  i0_dp.load ;
-     872      3106819 :          lsu_p.store                        =  i0_dp.store;
-     873      3106819 :          lsu_p.by                           =  i0_dp.by   ;
-     874      3106819 :          lsu_p.half                         =  i0_dp.half ;
-     875      3106819 :          lsu_p.word                         =  i0_dp.word ;
-     876      3106819 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871      3121785 :          lsu_p.load                         =  i0_dp.load ;
+     872      3121785 :          lsu_p.store                        =  i0_dp.store;
+     873      3121785 :          lsu_p.by                           =  i0_dp.by   ;
+     874      3121785 :          lsu_p.half                         =  i0_dp.half ;
+     875      3121785 :          lsu_p.word                         =  i0_dp.word ;
+     876      3121785 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878      3106819 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879      3106819 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880      3106819 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878      3121785 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879      3121785 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880      3121785 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882      3106819 :          lsu_p.unsign  =  i0_dp.unsign;
+     882      3121785 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_gpr_ctl.sv.html
index a75dc0634e0..345ff9b752a 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -123,9 +123,9 @@
       19              :    `include "el2_param.vh"
       20              :  )  (
       21        24346 :     input logic [4:0]  raddr0,       // logical read addresses
-      22      2993852 :     input logic [4:0]  raddr1,
+      22      2993855 :     input logic [4:0]  raddr1,
       23              : 
-      24      2993860 :     input logic        wen0,         // write enable
+      24      2993863 :     input logic        wen0,         // write enable
       25        24404 :     input logic [4:0]  waddr0,       // write address
       26        12058 :     input logic [31:0] wd0,          // write data
       27              : 
@@ -137,7 +137,7 @@
       33            0 :     input logic [4:0]  waddr2,       // write address
       34            0 :     input logic [31:0] wd2,          // write data
       35              : 
-      36      6085356 :     input logic        clk,
+      36      6085362 :     input logic        clk,
       37            2 :     input logic        rst_l,
       38              : 
       39        12054 :     output logic [31:0] rd0,         // read data
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_ib_ctl.sv.html
index 7cce2d4d368..c2a147137f4 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,7 +135,7 @@
       31            0 :    input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,              // BP tag
       32            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,          // Fully associt btb index
       33              : 
-      34      3042546 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
+      34      3042549 :    input logic       ifu_i0_pc4,                                   // i0 is 4B inst else 2B
       35        24428 :    input logic       ifu_i0_valid,                                 // i0 valid from ifu
       36            0 :    input logic       ifu_i0_icaf,                                  // i0 instruction access fault
       37            0 :    input logic [1:0] ifu_i0_icaf_type,                             // i0 instruction access fault type
@@ -154,7 +154,7 @@
       50              : 
       51            0 :    output logic [31:1] dec_i0_pc_d,                                // i0 pc at decode
       52              : 
-      53      3042546 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
+      53      3042549 :    output logic dec_i0_pc4_d,                                      // i0 is 4B inst else 2B
       54              : 
       55            0 :    output el2_br_pkt_t dec_i0_brp,                                // i0 branch packet at decode
       56            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index,   // i0 branch index
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_pmp_ctl.sv.html
index 039b3572a85..2635fcb1511 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32      6085356 :    input logic clk,
-      33      6085356 :    input logic free_l2clk,
-      34      6085356 :    input logic csr_wr_clk,
+      32      6085362 :    input logic clk,
+      33      6085362 :    input logic free_l2clk,
+      34      6085362 :    input logic csr_wr_clk,
       35            2 :    input logic rst_l,
       36            8 :    input logic        dec_csr_wen_r_mod,  // csr write enable at wb
       37            4 :    input logic [11:0] dec_csr_wraddr_r,   // write address for csr
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_tlu_ctl.sv.html
index 3205a4476d1..c2022f62db5 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -133,9 +133,9 @@
       29              : `include "el2_param.vh"
       30              :  )
       31              :   (
-      32      6085356 :    input logic clk,
-      33      6085356 :    input logic free_clk,
-      34      6085356 :    input logic free_l2clk,
+      32      6085362 :    input logic clk,
+      33      6085362 :    input logic free_clk,
+      34      6085362 :    input logic free_l2clk,
       35            2 :    input logic rst_l,
       36            0 :    input logic scan_mode,
       37              : 
@@ -164,8 +164,8 @@
       60            0 :    input logic       dma_dccm_stall_any,     // DMA stall of lsu
       61            0 :    input logic       dma_iccm_stall_any,     // DMA stall of ifu
       62        24402 :    input logic       exu_pmu_i0_br_misp,     // pipe 0 branch misp
-      63      2993846 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
-      64      3018196 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
+      63      2993849 :    input logic       exu_pmu_i0_br_ataken,   // pipe 0 branch actual taken
+      64      3018199 :    input logic       exu_pmu_i0_pc4,         // pipe 0 4 byte branch
       65            0 :    input logic       lsu_pmu_bus_trxn,       // D side bus transaction
       66            0 :    input logic       lsu_pmu_bus_misaligned, // D side bus misaligned
       67            0 :    input logic       lsu_pmu_bus_error,      // D side bus error
@@ -213,10 +213,10 @@
      109        24432 :    input logic        dec_i0_decode_d,  // decode valid, used for clean icache diagnostics
      110              : 
      111              :    // branch info from pipe0 for errors or counter updates
-     112      2993778 :    input logic [1:0]  exu_i0_br_hist_r, // history
+     112      2993781 :    input logic [1:0]  exu_i0_br_hist_r, // history
      113            0 :    input logic        exu_i0_br_error_r, // error
      114            0 :    input logic        exu_i0_br_start_error_r, // start error
-     115      2993842 :    input logic        exu_i0_br_valid_r, // valid
+     115      2993845 :    input logic        exu_i0_br_valid_r, // valid
      116        24402 :    input logic        exu_i0_br_mp_r, // mispredict
      117        24348 :    input logic        exu_i0_br_middle_r, // middle of bank
      118              : 
@@ -456,7 +456,7 @@
      352            8 :    logic valid_csr;
      353            0 :    logic rfpc_i0_r;
      354            0 :    logic lsu_i0_rfnpc_r;
-     355      3018116 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
+     355      3018119 :    logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
      356            0 :    logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
      357            4 :          lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
      358        24432 :    logic i0_trigger_eval_r;
@@ -506,7 +506,7 @@
      402            0 :    logic dec_pmp_read_d;
      403              : 
      404            0 :    logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
-     405      6085356 :    logic csr_wr_clk;
+     405      6085362 :    logic csr_wr_clk;
      406            0 :    logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
      407            0 :    logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
      408            0 :    logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
@@ -2828,9 +2828,9 @@
     2724              : `include "el2_param.vh"
     2725              :  )
     2726              :   (
-    2727      6085356 :    input logic clk,
-    2728      6085356 :    input logic free_l2clk,
-    2729      6085356 :    input logic csr_wr_clk,
+    2727      6085362 :    input logic clk,
+    2728      6085362 :    input logic free_l2clk,
+    2729      6085362 :    input logic csr_wr_clk,
     2730            2 :    input logic rst_l,
     2731            8 :    input logic        dec_csr_wen_r_mod,      // csr write enable at wb
     2732            4 :    input logic [11:0] dec_csr_wraddr_r,      // write address for csr
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_trigger.sv.html
index b18269113fe..4eada0c8a1c 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dma_ctrl.sv.html
index b9d9d5dbe8a..2115f6a88d4 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : #(
       27              : `include "el2_param.vh"
       28              :  )(
-      29      6085356 :    input logic         clk,
-      30      6085356 :    input logic         free_clk,
+      29      6085362 :    input logic         clk,
+      30      6085362 :    input logic         free_clk,
       31            2 :    input logic         rst_l,
       32            2 :    input logic         dma_bus_clk_en, // slave bus clock enable
       33            0 :    input logic         clk_override,
@@ -286,8 +286,8 @@
      182              : 
      183            0 :    logic                    dma_buffer_c1_clken;
      184            0 :    logic                    dma_free_clken;
-     185      6085356 :    logic                    dma_buffer_c1_clk;
-     186      6085356 :    logic                    dma_free_clk;
+     185      6085362 :    logic                    dma_buffer_c1_clk;
+     186      6085362 :    logic                    dma_free_clk;
      187            0 :    logic                    dma_bus_clk;
      188              : 
      189            0 :    logic                    bus_rsp_valid, bus_rsp_sent;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu.sv.html
index 77547a097e6..c6b04623592 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23      6085356 :    input logic          clk,                                           // Top level clock
+      23      6085362 :    input logic          clk,                                           // Top level clock
       24            2 :    input logic          rst_l,                                         // Reset
       25            0 :    input logic          scan_mode,                                     // Scan control
       26              : 
@@ -146,11 +146,11 @@
       42            0 :    input logic          dec_i0_rs2_en_d,                               // Qualify GPR RS2 data
       43        12054 :    input logic  [31:0]  gpr_i0_rs1_d,                                  // DEC data gpr
       44            0 :    input logic  [31:0]  gpr_i0_rs2_d,                                  // DEC data gpr
-      45      2993852 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
+      45      2993855 :    input logic  [31:0]  dec_i0_immed_d,                                // DEC data immediate
       46        12058 :    input logic  [31:0]  dec_i0_result_r,                               // DEC result in R-stage
       47           64 :    input logic  [12:1]  dec_i0_br_immed_d,                             // Branch immediate
       48        24428 :    input logic          dec_i0_alu_decode_d,                           // Valid to X-stage ALU
-      49      3018188 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
+      49      3018191 :    input logic          dec_i0_branch_d,                               // Branch in D-stage
       50        24338 :    input logic          dec_i0_select_pc_d,                            // PC select to RS1
       51            0 :    input logic  [31:1]  dec_i0_pc_d,                                   // Instruction PC
       52            0 :    input logic  [3:0]   dec_i0_rs1_bypass_en_d,                        // DEC bypass select  1 - X-stage, 0 - dec bypass data
@@ -184,11 +184,11 @@
       80            0 :    output logic [31:0]  exu_csr_rs1_x,                                 // RS1 source for a CSR instruction
       81              : 
       82            0 :    output logic [31:1]  exu_npc_r,                                     // Divide NPC
-      83      2993778 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
+      83      2993781 :    output logic [1:0]   exu_i0_br_hist_r,                              // to DEC  I0 branch history
       84            0 :    output logic         exu_i0_br_error_r,                             // to DEC  I0 branch error
       85            0 :    output logic         exu_i0_br_start_error_r,                       // to DEC  I0 branch start error
       86            0 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r,     // to DEC  I0 branch index
-      87      2993842 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
+      87      2993845 :    output logic         exu_i0_br_valid_r,                             // to DEC  I0 branch valid
       88        24402 :    output logic         exu_i0_br_mp_r,                                // to DEC  I0 branch mispredict
       89        24348 :    output logic         exu_i0_br_middle_r,                            // to DEC  I0 branch middle
       90        24340 :    output logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r,               // to DEC  I0 branch fghr
@@ -202,8 +202,8 @@
       98              : 
       99              : 
      100        24402 :    output logic         exu_pmu_i0_br_misp,                            // to PMU - I0 E4 branch mispredict
-     101      2993846 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
-     102      3018196 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
+     101      2993849 :    output logic         exu_pmu_i0_br_ataken,                          // to PMU - I0 E4 taken
+     102      3018199 :    output logic         exu_pmu_i0_pc4,                                // to PMU - I0 E4 PC
      103              : 
      104              : 
      105            0 :    output logic [31:0]  exu_div_result,                                // Divide result
@@ -220,17 +220,17 @@
      116        12054 :    logic [31:0]                i0_rs1_d,  i0_rs2_d;
      117        12054 :    logic [31:0]                muldiv_rs1_d;
      118            4 :    logic [31:1]                pred_correct_npc_r;
-     119      2969444 :    logic                       i0_pred_correct_upper_r;
+     119      2969447 :    logic                       i0_pred_correct_upper_r;
      120            0 :    logic [31:1]                i0_flush_path_upper_r;
      121        24432 :    logic                       x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
      122           30 :    logic                       x_ctl_en,  r_ctl_en;
      123              : 
      124        24340 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
      125        24340 :    logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
-     126      2993850 :    logic                       i0_taken_d;
-     127      2993848 :    logic                       i0_taken_x;
-     128      3018180 :    logic                       i0_valid_d;
-     129      3018178 :    logic                       i0_valid_x;
+     126      2993853 :    logic                       i0_taken_d;
+     127      2993851 :    logic                       i0_taken_x;
+     128      3018183 :    logic                       i0_valid_d;
+     129      3018181 :    logic                       i0_valid_x;
      130        24340 :    logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
      131              : 
      132            0 :    el2_predict_pkt_t          final_predict_mp;
@@ -247,13 +247,13 @@
      143        24406 :    logic                       i0_flush_upper_d;
      144            0 :    logic [31:1]                i0_flush_path_d;
      145            0 :    el2_predict_pkt_t          i0_predict_p_d;
-     146      2969448 :    logic                       i0_pred_correct_upper_d;
+     146      2969451 :    logic                       i0_pred_correct_upper_d;
      147              : 
      148        24406 :    logic                       i0_flush_upper_x;
      149            0 :    logic [31:1]                i0_flush_path_x;
      150            0 :    el2_predict_pkt_t          i0_predict_p_x;
-     151      2969446 :    logic                       i0_pred_correct_upper_x;
-     152      3018186 :    logic                       i0_branch_x;
+     151      2969449 :    logic                       i0_pred_correct_upper_x;
+     152      3018189 :    logic                       i0_branch_x;
      153              : 
      154              :    localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
      155            0 :    logic [PREDPIPESIZE-1:0]    predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_alu_ctl.sv.html
index f7805fc67a6..ffd1ed95fb3 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23      6085356 :    input  logic                  clk,                // Top level clock
+      23      6085362 :    input  logic                  clk,                // Top level clock
       24            2 :    input  logic                  rst_l,              // Reset
       25            0 :    input  logic                  scan_mode,          // Scan control
       26              : 
@@ -136,7 +136,7 @@
       32            0 :    input  logic                  csr_ren_in,         // CSR select
       33            0 :    input  logic        [31:0]    csr_rddata_in,      // CSR data
       34        12054 :    input  logic signed [31:0]    a_in,               // A operand
-      35      2993852 :    input  logic        [31:0]    b_in,               // B operand
+      35      2993855 :    input  logic        [31:0]    b_in,               // B operand
       36            0 :    input  logic        [31:1]    pc_in,              // for pc=pc+2,4 calculations
       37            0 :    input  el2_predict_pkt_t     pp_in,              // Predicted branch structure
       38           64 :    input  logic        [12:1]    brimm_in,           // Branch offset
@@ -147,7 +147,7 @@
       43        24414 :    output logic                  flush_final_out,    // Branch flush or flush entire pipeline
       44            0 :    output logic        [31:1]    flush_path_out,     // Branch flush PC
       45            0 :    output logic        [31:1]    pc_ff,              // flopped PC
-      46      2969448 :    output logic                  pred_correct_out,   // NPC control
+      46      2969451 :    output logic                  pred_correct_out,   // NPC control
       47            0 :    output el2_predict_pkt_t     predict_p_out       // Predicted branch structure
       48              :   );
       49              : 
@@ -160,7 +160,7 @@
       56            0 :    logic                         sel_shift;
       57        24412 :    logic                         sel_adder;
       58            0 :    logic                         slt_one;
-      59      2993850 :    logic                         actual_taken;
+      59      2993853 :    logic                         actual_taken;
       60            0 :    logic               [31:1]    pcout;
       61        24406 :    logic                         cond_mispredict;
       62            0 :    logic                         target_mispredict;
@@ -443,8 +443,8 @@
      339              : 
      340            2 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342     99418336 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343     99418336 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342     99897248 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343     99897248 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_div_ctl.sv.html
index c0ca443320b..1b1eb9ca1c3 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,13 +124,13 @@
       20              : `include "el2_param.vh"
       21              : )
       22              :   (
-      23      6085356 :    input logic           clk,                       // Top level clock
+      23      6085362 :    input logic           clk,                       // Top level clock
       24            2 :    input logic           rst_l,                     // Reset
       25            0 :    input logic           scan_mode,                 // Scan mode
       26              : 
       27            0 :    input el2_div_pkt_t  dp,                        // valid, sign, rem
       28        12054 :    input logic  [31:0]   dividend,                  // Numerator
-      29      2993852 :    input logic  [31:0]   divisor,                   // Denominator
+      29      2993855 :    input logic  [31:0]   divisor,                   // Denominator
       30              : 
       31            0 :    input logic           cancel,                    // Cancel divide
       32              : 
@@ -1414,7 +1414,7 @@
     1310              : // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
     1311              : module el2_exu_div_new_4bit_fullshortq
     1312              :   (
-    1313      6085356 :    input  logic            clk,                       // Top level clock
+    1313      6085362 :    input  logic            clk,                       // Top level clock
     1314            2 :    input  logic            rst_l,                     // Reset
     1315            0 :    input  logic            scan_mode,                 // Scan mode
     1316              : 
@@ -1423,7 +1423,7 @@
     1319            2 :    input  logic            signed_in,
     1320            0 :    input  logic            rem_in,
     1321        12054 :    input  logic [31:0]     dividend_in,
-    1322      2993852 :    input  logic [31:0]     divisor_in,
+    1322      2993855 :    input  logic [31:0]     divisor_in,
     1323              : 
     1324            0 :    output logic            valid_out,
     1325            0 :    output logic [31:0]     data_out
@@ -1446,7 +1446,7 @@
     1342            0 :    logic        [31:0]     a_in, a_ff;
     1343              : 
     1344            0 :    logic                   b_enable, b_twos_comp;
-    1345      2993852 :    logic        [32:0]     b_in;
+    1345      2993855 :    logic        [32:0]     b_in;
     1346            0 :    logic        [37:0]     b_ff;
     1347              : 
     1348            0 :    logic        [31:0]     q_in, q_ff;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_mul_ctl.sv.html
index 859f457c81e..9744266ee63 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -124,7 +124,7 @@
       20              : `include "el2_param.vh"
       21              :  )
       22              :   (
-      23      6085356 :    input logic          clk,              // Top level clock
+      23      6085362 :    input logic          clk,              // Top level clock
       24            2 :    input logic          rst_l,            // Reset
       25            0 :    input logic          scan_mode,        // Scan mode
       26              : 
@@ -310,7 +310,7 @@
      206            2 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207           64 :          begin
      208           64 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209     99418336 :              if (bcompress_test_bit_d)
+     209     99897248 :              if (bcompress_test_bit_d)
      210            0 :                begin
      211            0 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
      212            0 :                   bcompress_j                  =  bcompress_j + 1;
@@ -337,7 +337,7 @@
      233            2 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234           64 :          begin
      235           64 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236     99418336 :              if (bdecompress_test_bit_d)
+     236     99897248 :              if (bdecompress_test_bit_d)
      237            0 :                begin
      238            0 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
      239            0 :                   bdecompress_j                =  bdecompress_j + 1;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu.sv.html
index f806db7948e..d080b9a5965 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,9 +129,9 @@
       25              : `include "el2_param.vh"
       26              :  )
       27              :   (
-      28      6085356 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
-      29      6085356 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      30      6085356 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      28      6085362 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29      6085362 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30      6085362 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            2 :    input logic rst_l,                        // reset, active low
       32              : 
       33        24432 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
@@ -275,7 +275,7 @@
      171            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
      172        24338 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
      173            0 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
-     174      3042546 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
+     174      3042549 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
      175              : 
      176           26 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
      177              : 
@@ -339,12 +339,12 @@
      235        48770 :    logic ic_hit_f;
      236              : 
      237        24820 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
-     238      3018150 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
+     238      3018153 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
      239            0 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
-     240      2969480 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
+     240      2969483 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
      241        48676 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
      242        48660 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
-     243      2993792 :    logic [11:0] ifu_bp_poffset_f; // predicted target
+     243      2993795 :    logic [11:0] ifu_bp_poffset_f; // predicted target
      244            0 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
      245        48672 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
      246        48672 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_aln_ctl.sv.html
index eef7264bf0b..e070a2dd418 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              : 
       28            0 :    input logic                                    scan_mode,                // Flop scan mode control
       29            2 :    input logic                                    rst_l,                    // reset, active low
-      30      6085356 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31      6085356 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      30      6085362 :    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31      6085362 :    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       32              : 
       33            0 :    input logic                                    ifu_async_error_start,    // ecc/parity related errors with current fetch - not sent down the pipe
       34              : 
@@ -160,15 +160,15 @@
       56            0 :    output logic                                   ifu_i0_dbecc,             // Instruction 0 has double bit ecc error
       57        24338 :    output logic [31:0]                            ifu_i0_instr,             // Instruction 0
       58            0 :    output logic [31:1]                            ifu_i0_pc,                // Instruction 0 PC
-      59      3042546 :    output logic                                   ifu_i0_pc4,
+      59      3042549 :    output logic                                   ifu_i0_pc4,
       60              : 
       61        48696 :    output logic                                   ifu_fb_consume1,          // Consumed one buffer. To fetch control fetch for buffer mass balance
-      62      2945114 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
+      62      2945117 :    output logic                                   ifu_fb_consume2,          // Consumed two buffers.To fetch control fetch for buffer mass balance
       63              : 
       64              : 
       65        24340 :    input logic [pt.BHT_GHR_SIZE-1:0]              ifu_bp_fghr_f,            // fetch GHR
       66            0 :    input logic [31:1]                             ifu_bp_btb_target_f,      // predicted RET target
-      67      2993792 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
+      67      2993795 :    input logic [11:0]                             ifu_bp_poffset_f,         // predicted target offset
       68            0 :    input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f,        // predicted branch index (fully associative option)
       69              : 
       70        48660 :    input logic [1:0]                              ifu_bp_hist0_f,           // history counters for all 4 potential branches, bit 1, right justified
@@ -203,19 +203,19 @@
       99            0 :    logic [1:0]                                    sf1val, sf0val;
      100              : 
      101        24338 :    logic [31:0]                                   aligndata;
-     102      3042546 :    logic                                          first4B, first2B;
+     102      3042549 :    logic                                          first4B, first2B;
      103              : 
      104            4 :    logic [31:0]                                   uncompress0;
      105        24432 :    logic                                          i0_shift;
-     106      3018202 :    logic                                          shift_2B, shift_4B;
-     107      2993854 :    logic                                          f1_shift_2B;
+     106      3018205 :    logic                                          shift_2B, shift_4B;
+     107      2993857 :    logic                                          f1_shift_2B;
      108        24342 :    logic                                          f2_valid, sf1_valid, sf0_valid;
      109              : 
      110        24338 :    logic [31:0]                                   ifirst;
      111        24424 :    logic [1:0]                                    alignval;
      112            0 :    logic [31:1]                                   firstpc, secondpc;
      113              : 
-     114      2993794 :    logic [11:0]                                   f1poffset;
+     114      2993797 :    logic [11:0]                                   f1poffset;
      115        24346 :    logic [11:0]                                   f0poffset;
      116        24340 :    logic [pt.BHT_GHR_SIZE-1:0]                    f1fghr;
      117        24340 :    logic [pt.BHT_GHR_SIZE-1:0]                    f0fghr;
@@ -234,21 +234,21 @@
      130              : 
      131            0 :    logic [1:0]                                    f1ret;
      132            0 :    logic [1:0]                                    f0ret;
-     133      2969020 :    logic [1:0]                                    f1way;
-     134      2969450 :    logic [1:0]                                    f0way;
+     133      2969023 :    logic [1:0]                                    f1way;
+     134      2969453 :    logic [1:0]                                    f0way;
      135              : 
      136        24338 :    logic [1:0]                                    f1brend;
      137        48672 :    logic [1:0]                                    f0brend;
      138              : 
-     139      3018180 :    logic [1:0]                                    alignbrend;
-     140      3018180 :    logic [1:0]                                    alignpc4;
+     139      3018183 :    logic [1:0]                                    alignbrend;
+     140      3018183 :    logic [1:0]                                    alignpc4;
      141              : 
      142            0 :    logic [1:0]                                    alignret;
-     143      2993788 :    logic [1:0]                                    alignway;
-     144      2823002 :    logic [1:0]                                    alignhist1;
-     145      2798196 :    logic [1:0]                                    alignhist0;
-     146      2993858 :    logic [1:1]                                    alignfromf1;
-     147      2993854 :    logic                                          i0_ends_f1;
+     143      2993791 :    logic [1:0]                                    alignway;
+     144      2823005 :    logic [1:0]                                    alignhist1;
+     145      2798199 :    logic [1:0]                                    alignhist0;
+     146      2993861 :    logic [1:1]                                    alignfromf1;
+     147      2993857 :    logic                                          i0_ends_f1;
      148            0 :    logic                                          i0_br_start_error;
      149              : 
      150            0 :    logic [31:1]                                   f1prett;
@@ -260,34 +260,34 @@
      156              : 
      157            0 :    logic [1:0]                                    aligndbecc;
      158            0 :    logic [1:0]                                    alignicaf;
-     159      3018180 :    logic                                          i0_brp_pc4;
+     159      3018183 :    logic                                          i0_brp_pc4;
      160              : 
      161            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]          firstpc_hash, secondpc_hash;
      162              : 
      163            0 :    logic                                          first_legal;
      164              : 
-     165      2020257 :    logic [1:0]                                    wrptr, wrptr_in;
-     166       997947 :    logic [1:0]                                    rdptr, rdptr_in;
-     167      1995875 :    logic [2:0]                                    qwen;
+     165      2020259 :    logic [1:0]                                    wrptr, wrptr_in;
+     166       997949 :    logic [1:0]                                    rdptr, rdptr_in;
+     167      1995877 :    logic [2:0]                                    qwen;
      168            2 :    logic [31:0]                                   q2,q1,q0;
-     169      1995860 :    logic                                          q2off_in, q2off;
-     170      2020247 :    logic                                          q1off_in, q1off;
-     171      1971601 :    logic                                          q0off_in, q0off;
+     169      1995862 :    logic                                          q2off_in, q2off;
+     170      2020249 :    logic                                          q1off_in, q1off;
+     171      1971603 :    logic                                          q0off_in, q0off;
      172        48750 :    logic                                          f0_shift_2B;
      173              : 
      174           22 :    logic [31:0]                                   q0eff;
      175           10 :    logic [31:0]                                   q0final;
-     176      2993862 :    logic                                          q0ptr;
-     177      2993862 :    logic [1:0]                                    q0sel;
+     176      2993865 :    logic                                          q0ptr;
+     177      2993865 :    logic [1:0]                                    q0sel;
      178              : 
      179            6 :    logic [31:0]                                   q1eff;
      180        24348 :    logic [15:0]                                   q1final;
-     181      2969510 :    logic                                          q1ptr;
-     182      2969510 :    logic [1:0]                                    q1sel;
+     181      2969513 :    logic                                          q1ptr;
+     182      2969513 :    logic [1:0]                                    q1sel;
      183              : 
-     184       997947 :    logic [2:0]                                    qren;
+     184       997949 :    logic [2:0]                                    qren;
      185              : 
-     186      2969452 :    logic                                          consume_fb1, consume_fb0;
+     186      2969455 :    logic                                          consume_fb1, consume_fb0;
      187            0 :    logic [1:0]                                    icaf_eff;
      188              : 
      189              :    localparam                                     BRDATA_SIZE  = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_bp_ctl.sv.html
index d68f4c3808a..4d4bbea22ed 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,7 +135,7 @@
       31              :  )
       32              :   (
       33              : 
-      34      6085356 :    input logic clk,
+      34      6085362 :    input logic clk,
       35            2 :    input logic rst_l,
       36              : 
       37        48770 :    input logic ic_hit_f,      // Icache hit, enables F address capture
@@ -163,9 +163,9 @@
       59              : 
       60        24414 :    input logic exu_flush_final, // all flushes
       61              : 
-      62      3018150 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
+      62      3018153 :    output logic ifu_bp_hit_taken_f, // btb hit, select target
       63            0 :    output logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
-      64      2969480 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
+      64      2969483 :    output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified
       65              : 
       66        24340 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr
       67              : 
@@ -175,7 +175,7 @@
       71        48660 :    output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified
       72        48672 :    output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified
       73        48672 :    output logic [1:0] ifu_bp_valid_f, // branch valid, right justified
-      74      2993792 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
+      74      2993795 :    output logic [11:0] ifu_bp_poffset_f, // predicted target
       75              : 
       76            0 :    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
       77              : 
@@ -216,8 +216,8 @@
      112        24406 :    logic [1:0] exu_mp_hist; // new history
      113        24402 :    logic [11:0] exu_mp_tgt; // target offset
      114            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
-     115      3018116 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
-     116      2993778 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
+     115      3018119 :    logic                                   dec_tlu_br0_v_wb; // WB stage history update
+     116      2993781 :    logic [1:0]                             dec_tlu_br0_hist_wb; // new history
      117            0 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr
      118            0 :    logic                                   dec_tlu_br0_error_wb; // error; invalidate bank
      119            0 :    logic                                   dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg
@@ -228,7 +228,7 @@
      124            0 :    logic [pt.RET_STACK_SIZE-1:0]        rsenable;
      125              : 
      126              : 
-     127      2993792 :    logic [11:0]       btb_rd_tgt_f;
+     127      2993795 :    logic [11:0]       btb_rd_tgt_f;
      128        24362 :    logic              btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;
      129        24346 :    logic [1:1]        bp_total_branch_offset_f;
      130              : 
@@ -262,7 +262,7 @@
      158              : 
      159              :    logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0]  btb_bank0_rd_data_way1_out ;
      160              : 
-     161      2993848 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
+     161      2993851 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;
      162            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;
      163              : 
      164        24856 :    logic                [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;
@@ -270,7 +270,7 @@
      166              : 
      167        24338 :    logic                [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;
      168              : 
-     169      3018150 :    logic                                         final_h;
+     169      3018153 :    logic                                         final_h;
      170            0 :    logic                                         btb_fg_crossing_f;
      171        24406 :    logic                                         middle_of_bank;
      172              : 
@@ -286,7 +286,7 @@
      182            0 :    logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;
      183            0 :    logic                [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;
      184              : 
-     185      2993848 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
+     185      2993851 :    logic                [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;
      186              : 
      187            0 :    logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;
      188              : 
@@ -473,7 +473,7 @@
      369              : 
      370              :    // mux out critical hit bank for pc computation
      371              :    // This is only useful for the first taken branch in the fetch group
-     372      2993792 :    logic [16:1] btb_sel_data_f;
+     372      2993795 :    logic [16:1] btb_sel_data_f;
      373              : 
      374              :    assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
      375              :    assign btb_rd_pc4_f       = btb_sel_data_f[4];
@@ -601,8 +601,8 @@
      497              : //    -1            10 -  10  0
      498              : //    10            10 0  01  1
      499              : //    10            10 1  01  0
-     500      2993818 : logic [1:0] bloc_f;
-     501      2993818 : logic use_fa_plus;
+     500      2993821 : logic [1:0] bloc_f;
+     501      2993821 : logic use_fa_plus;
      502              : assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]
      503              :      & fetch_start_f[0]);
      504              : assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]
@@ -720,7 +720,7 @@
      616              : 
      617              :    assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;
      618        24406 :    logic [1:0] bht_wr_data0, bht_wr_data2;
-     619      3018116 :    logic [1:0] bht_wr_en0, bht_wr_en2;
+     619      3018119 :    logic [1:0] bht_wr_en0, bht_wr_en2;
      620              : 
      621              :    assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
      622              :    assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
@@ -777,18 +777,18 @@
      673            2 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676      3106819 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676      3121785 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678      3106819 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679      3106819 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678      3121785 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679      3121785 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            2 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684      3106819 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684      3121785 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686      3106819 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687      3106819 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686      3121785 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687      3121785 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -978,12 +978,12 @@
      874            2 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            2 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            2 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877      3106819 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878      3106819 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879      3106819 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877      3121785 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878      3121785 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879      3121785 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881      3106819 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882      3106819 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881      3121785 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882      3121785 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_compress_ctl.sv.html
index ff77b847a78..292efcfbd65 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              :    );
       29              : 
       30              : 
-      31      3018198 :    logic               legal;
+      31      3018201 :    logic               legal;
       32              : 
       33            4 :    logic [15:0]  i;
       34              : 
@@ -144,22 +144,22 @@
       40              : 
       41            0 :    logic [4:0]   rs2d,rdd,rdpd,rs2pd;
       42              : 
-      43      3018198 :    logic rdrd;
-      44      3018194 :    logic rdrs1;
+      43      3018201 :    logic rdrd;
+      44      3018197 :    logic rdrs1;
       45            0 :    logic rs2rs2;
       46            0 :    logic rdprd;
       47            0 :    logic rdprs1;
       48            0 :    logic rs2prs2;
-      49      3018200 :    logic rs2prd;
-      50      3018200 :    logic uimm9_2;
+      49      3018203 :    logic rs2prd;
+      50      3018203 :    logic uimm9_2;
       51            0 :    logic ulwimm6_2;
       52            0 :    logic ulwspimm7_2;
       53            0 :    logic rdeq2;
       54            0 :    logic rdeq1;
-      55      3018200 :    logic rs1eq2;
+      55      3018203 :    logic rs1eq2;
       56            0 :    logic sbroffset8_1;
       57            0 :    logic simm9_4;
-      58      3018198 :    logic simm5_0;
+      58      3018201 :    logic simm5_0;
       59            0 :    logic sjaloffset11_1;
       60            0 :    logic sluimm17_12;
       61            0 :    logic uimm5_0;
@@ -216,16 +216,16 @@
      112              : 
      113              :    assign l1[31:25] = o[31:25];
      114              : 
-     115      2993852 :    logic [5:0] simm5d;
+     115      2993855 :    logic [5:0] simm5d;
      116            4 :    logic [9:2] uimm9d;
      117              : 
-     118      2993852 :    logic [9:4] simm9d;
-     119      2993852 :    logic [6:2] ulwimm6d;
-     120      2993852 :    logic [7:2] ulwspimm7d;
-     121      2993852 :    logic [5:0] uimm5d;
+     118      2993855 :    logic [9:4] simm9d;
+     119      2993855 :    logic [6:2] ulwimm6d;
+     120      2993855 :    logic [7:2] ulwspimm7d;
+     121      2993855 :    logic [5:0] uimm5d;
      122            4 :    logic [20:1] sjald;
      123              : 
-     124      2993852 :    logic [31:12] sluimmd;
+     124      2993855 :    logic [31:12] sluimmd;
      125              : 
      126              :    // merge in immediates + jal offset
      127              : 
@@ -272,8 +272,8 @@
      168              : 
      169              :    // merge in branch offset and store immediates
      170              : 
-     171      2993852 :    logic [8:1]   sbr8d;
-     172      2993852 :    logic [6:2]   uswimm6d;
+     171      2993855 :    logic [8:1]   sbr8d;
+     172      2993855 :    logic [6:2]   uswimm6d;
      173            4 :    logic [7:2]   uswspimm7d;
      174              : 
      175              : 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ic_mem.sv.html
index 9e3e6933587..81229e9ec0e 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,8 +127,8 @@
       23              : `include "el2_param.vh"
       24              :  )
       25              :   (
-      26      6085356 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      27      6085356 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      26      6085362 :       input logic                                   clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      27      6085362 :       input logic                                   active_clk,         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       28            2 :       input logic                                   rst_l,              // reset, active low
       29            0 :       input logic                                   clk_override,       // Override non-functional clock gating
       30            0 :       input logic                                   dec_tlu_core_ecc_disable,  // Disable ECC checking
@@ -192,8 +192,8 @@
       88              : `include "el2_param.vh"
       89              :  )
       90              :      (
-      91      6085356 :       input logic clk,
-      92      6085356 :       input logic active_clk,
+      91      6085362 :       input logic clk,
+      92      6085362 :       input logic active_clk,
       93            2 :       input logic rst_l,
       94            0 :       input logic clk_override,
       95              : 
@@ -904,8 +904,8 @@
      800              : `include "el2_param.vh"
      801              :  )
      802              :      (
-     803      6085356 :       input logic                                                   clk,
-     804      6085356 :       input logic                                                   active_clk,
+     803      6085362 :       input logic                                                   clk,
+     804      6085362 :       input logic                                                   active_clk,
      805            2 :       input logic                                                   rst_l,
      806            0 :       input logic                                                   clk_override,
      807            0 :       input logic                                                   dec_tlu_core_ecc_disable,
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_iccm_mem.sv.html
index b59a8cf4ec3..d7c6fe265f1 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -129,8 +129,8 @@
       25              : #(
       26              : `include "el2_param.vh"
       27              :  )(
-      28      6085356 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      29      6085356 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      28      6085362 :    input logic                                        clk,                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      29      6085362 :    input logic                                        active_clk,                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       30            2 :    input logic                                        rst_l,                               // reset, active low
       31            0 :    input logic                                        clk_override,                        // Override non-functional clock gating
       32              : 
@@ -159,7 +159,7 @@
       55            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_dout, iccm_bank_dout_fn;
       56            0 :    logic [pt.ICCM_NUM_BANKS-1:0] [38:0]  iccm_bank_wr_data;
       57            0 :    logic [pt.ICCM_BITS-1:1]              addr_bank_inc;
-      58      2993862 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
+      58      2993865 :    logic [pt.ICCM_BANK_HI : 2]           iccm_rd_addr_hi_q;
       59        24340 :    logic [pt.ICCM_BANK_HI : 1]           iccm_rd_addr_lo_q;
       60            0 :    logic             [63:0]              iccm_rd_data_pre;
       61            0 :    logic             [63:0]              iccm_data;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ifc_ctl.sv.html
index 7ff51f1fdcc..58d7b37efb3 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,8 +130,8 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29      6085356 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      30      6085356 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
+      29      6085362 :    input logic clk,                         // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30      6085362 :    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
       31              : 
       32            2 :    input logic rst_l, // reset enable, from core pin
       33            0 :    input logic scan_mode, // scan
@@ -140,13 +140,13 @@
       36           30 :    input logic ifu_ic_mb_empty, // Miss buffer empty
       37              : 
       38        48696 :    input logic ifu_fb_consume1,  // Aligner consumed 1 fetch buffer
-      39      2945114 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
+      39      2945117 :    input logic ifu_fb_consume2,  // Aligner consumed 2 fetch buffers
       40              : 
       41            0 :    input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
       42        24414 :    input logic exu_flush_final, // FLush
       43            0 :    input logic [31:1] exu_flush_path_final, // Flush path
       44              : 
-      45      3018150 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
+      45      3018153 :    input logic ifu_bp_hit_taken_f, // btb hit, select the target path
       46            0 :    input logic [31:1] ifu_bp_btb_target_f, //  predicted target PC
       47              : 
       48            0 :    input logic ic_dma_active, // IC DMA active, stop fetching
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_mem_ctl.sv.html
index cad200bce2c..2ac05fd3f5e 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,9 +131,9 @@
       27              : `include "el2_param.vh"
       28              :  )
       29              :   (
-      30      6085356 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      31      6085356 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
-      32      6085356 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
+      30      6085362 :    input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31      6085362 :    input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      32      6085362 :    input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
       33            2 :    input logic rst_l,                                               // reset, active low
       34              : 
       35        24414 :    input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
@@ -150,9 +150,9 @@
       46            0 :    input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
       47        24416 :    input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
       48            0 :    input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
-      49      3018150 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
+      49      3018153 :    input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
       50              : 
-      51      2969480 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
+      51      2969483 :    input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
       52              : 
       53           26 :    output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
       54           30 :    output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
@@ -535,7 +535,7 @@
      431              : 
      432           24 :    logic   ic_crit_wd_rdy;         // Critical fetch is ready to be bypassed.
      433              : 
-     434      3018126 :    logic   ifu_bp_hit_taken_q_f;
+     434      3018129 :    logic   ifu_bp_hit_taken_q_f;
      435           72 :    logic   ifu_bus_rvalid_unq;
      436           72 :    logic   bus_cmd_beat_en;
      437              : 
@@ -587,9 +587,9 @@
      483            2 :       miss_nxtstate   = IDLE;
      484            2 :       miss_state_en   = 1'b0;
      485            2 :       case (miss_state)
-     486      3106735 :          IDLE: begin : idle
-     487      3106735 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488      3106735 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486      3121701 :          IDLE: begin : idle
+     487      3121701 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488      3121701 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
      490           36 :          CRIT_BYP_OK: begin : crit_byp_ok
      491           36 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
@@ -1046,10 +1046,10 @@
      942            2 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            2 :     case (perr_state)
-     945      3106819 :       ERR_IDLE: begin : err_idle
-     946      3106819 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947      3106819 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948      3106819 :         perr_sb_write_status = perr_state_en;
+     945      3121785 :       ERR_IDLE: begin : err_idle
+     946      3121785 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947      3121785 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948      3121785 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            2 :       iccm_correction_state        = 1'b0;
      988              : 
      989            2 :       case (err_stop_state)
-     990      3106819 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991      3106819 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992      3106819 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990      3121785 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991      3121785 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992      3121785 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1547,8 +1547,8 @@
     1443            2 :   always_comb begin : way_status_out_mux
     1444            2 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446      3106819 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447      3106819 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446      3121785 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447      3121785 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            2 :   always_comb begin : tag_valid_out_mux
     1507            2 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            2 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509      3106819 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510      3106819 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511      6213638 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509      3121785 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510      3121785 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511      6243570 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lib.sv.html
index 1b743d37b7c..042b52ff346 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu.sv.html
index 326fc51969e..b9af338cc11 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -283,8 +283,8 @@
      179            0 :    output logic                            lsu_dccm_rd_ecc_double_err,
      180              : 
      181            0 :    input logic                             scan_mode,           // scan mode
-     182      6085356 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-     183      6085356 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+     182      6085362 :    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+     183      6085362 :    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      184            2 :     input logic                             rst_l,               // reset, active low
      185              : 
      186            0 :     output logic [31:0] lsu_pmp_addr_start,
@@ -383,14 +383,14 @@
      279              :    // Clocks
      280            0 :    logic        lsu_busm_clken;
      281            0 :    logic        lsu_bus_obuf_c1_clken;
-     282      6085356 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
-     283      6085356 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
-     284      6085356 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
+     282      6085362 :    logic        lsu_c1_m_clk, lsu_c1_r_clk;
+     283      6085362 :    logic        lsu_c2_m_clk, lsu_c2_r_clk;
+     284      6085362 :    logic        lsu_store_c1_m_clk, lsu_store_c1_r_clk;
      285              : 
-     286      6085356 :    logic        lsu_stbuf_c1_clk;
-     287      6085356 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
+     286      6085362 :    logic        lsu_stbuf_c1_clk;
+     287      6085362 :    logic        lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
      288            0 :    logic        lsu_busm_clk;
-     289      6085356 :    logic        lsu_free_c2_clk;
+     289      6085362 :    logic        lsu_free_c2_clk;
      290              : 
      291            0 :    logic        lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
      292            0 :    logic        lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_addrcheck.sv.html
index a27cc468cf4..a97de49f955 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30      6085356 :    input logic          lsu_c2_m_clk,              // clock
+      30      6085362 :    input logic          lsu_c2_m_clk,              // clock
       31            2 :    input logic          rst_l,                     // reset
       32              : 
       33            0 :    input logic [31:0]   start_addr_d,              // start address for lsu
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_buffer.sv.html
index 3c812cfbe5c..b11b6d71a45 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,7 +132,7 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              :  )(
-      31      6085356 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      31      6085362 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       32            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       33            2 :    input logic                          rst_l,                              // reset, active low
       34            0 :    input logic                          scan_mode,                          // scan mode
@@ -144,11 +144,11 @@
       40              :    // various clocks needed for the bus reads and writes
       41            0 :    input logic                          lsu_bus_obuf_c1_clken,
       42            0 :    input logic                          lsu_busm_clken,
-      43      6085356 :    input logic                          lsu_c2_r_clk,
-      44      6085356 :    input logic                          lsu_bus_ibuf_c1_clk,
+      43      6085362 :    input logic                          lsu_c2_r_clk,
+      44      6085362 :    input logic                          lsu_bus_ibuf_c1_clk,
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,
-      46      6085356 :    input logic                          lsu_bus_buf_c1_clk,
-      47      6085356 :    input logic                          lsu_free_c2_clk,
+      46      6085362 :    input logic                          lsu_bus_buf_c1_clk,
+      47      6085362 :    input logic                          lsu_free_c2_clk,
       48            0 :    input logic                          lsu_busm_clk,
       49              : 
       50              : 
@@ -445,15 +445,15 @@
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344      9320465 :    function automatic logic [2:0] f_Enc8to3;
+     344      9365363 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348      9320465 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349      9320465 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350      9320465 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348      9365363 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349      9365363 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350      9365363 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352      9320465 :       return Enc_value[2:0];
+     352      9365363 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -758,14 +758,14 @@
      654            8 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656            8 :          case (buf_state[i])
-     657     12427276 :             IDLE: begin
-     658     12427276 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659     12427276 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660     12427276 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661     12427276 :                      buf_wr_en[i]    = buf_state_en[i];
-     662     12427276 :                      buf_data_en[i]  = buf_state_en[i];
-     663     12427276 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664     12427276 :                      buf_cmd_state_bus_en[i]  = '0;
+     657     12487140 :             IDLE: begin
+     658     12487140 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659     12487140 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660     12487140 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661     12487140 :                      buf_wr_en[i]    = buf_state_en[i];
+     662     12487140 :                      buf_data_en[i]  = buf_state_en[i];
+     663     12487140 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664     12487140 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_intf.sv.html
index 56dd2b0da8d..3c2f04b2154 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : #(
       28              : `include "el2_param.vh"
       29              :  )(
-      30      6085356 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      30      6085362 :    input logic                          clk,                                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       31            0 :    input logic                          clk_override,                       // Override non-functional clock gating
       32            2 :    input logic                          rst_l,                              // reset, active low
       33            0 :    input logic                          scan_mode,                          // scan mode
@@ -143,13 +143,13 @@
       39            0 :    input logic                          lsu_bus_obuf_c1_clken,              // obuf clock enable
       40            0 :    input logic                          lsu_busm_clken,                     // bus clock enable
       41              : 
-      42      6085356 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
-      43      6085356 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
-      44      6085356 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
+      42      6085362 :    input logic                          lsu_c1_r_clk,                       // r pipe single pulse clock
+      43      6085362 :    input logic                          lsu_c2_r_clk,                       // r pipe double pulse clock
+      44      6085362 :    input logic                          lsu_bus_ibuf_c1_clk,                // ibuf single pulse clock
       45            0 :    input logic                          lsu_bus_obuf_c1_clk,                // obuf single pulse clock
-      46      6085356 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
-      47      6085356 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
-      48      6085356 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      46      6085362 :    input logic                          lsu_bus_buf_c1_clk,                 // buf  single pulse clock
+      47      6085362 :    input logic                          lsu_free_c2_clk,                    // free clock double pulse clock
+      48      6085362 :    input logic                          active_clk,                         // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       49            0 :    input logic                          lsu_busm_clk,                       // bus clock
       50              : 
       51            4 :    input logic                          dec_lsu_valid_raw_d,               // Raw valid for address computation
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_clkdomain.sv.html
index 216c12a92d4..01a88d86b81 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -132,8 +132,8 @@
       28              : #(
       29              : `include "el2_param.vh"
       30              : )(
-      31      6085356 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      32      6085356 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      31      6085362 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      32      6085362 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       33            2 :    input logic      rst_l,                             // reset, active low
       34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
       35              : 
@@ -160,22 +160,22 @@
       56            0 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
       57            0 :    output logic     lsu_busm_clken,                    // bus clock enable
       58              : 
-      59      6085356 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
-      60      6085356 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
+      59      6085362 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
+      60      6085362 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
       61              : 
-      62      6085356 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
-      63      6085356 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
+      62      6085362 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
+      63      6085362 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
       64              : 
-      65      6085356 :    output logic     lsu_store_c1_m_clk,                // store in m
-      66      6085356 :    output logic     lsu_store_c1_r_clk,                // store in r
+      65      6085362 :    output logic     lsu_store_c1_m_clk,                // store in m
+      66      6085362 :    output logic     lsu_store_c1_r_clk,                // store in r
       67              : 
-      68      6085356 :    output logic     lsu_stbuf_c1_clk,
+      68      6085362 :    output logic     lsu_stbuf_c1_clk,
       69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
-      70      6085356 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
-      71      6085356 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
+      70      6085362 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
+      71      6085362 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
       72            0 :    output logic     lsu_busm_clk,                      // bus clock
       73              : 
-      74      6085356 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
+      74      6085362 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
       75              : 
       76            0 :    input  logic     scan_mode                          // Scan mode
       77              : );
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_ctl.sv.html
index 3093dad0205..83880d396ba 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,13 +136,13 @@
       32              : `include "el2_param.vh"
       33              :  )
       34              :   (
-      35      6085356 :    input logic                             lsu_c2_m_clk,            // clocks
-      36      6085356 :    input logic                             lsu_c2_r_clk,            // clocks
-      37      6085356 :    input logic                             lsu_c1_r_clk,            // clocks
-      38      6085356 :    input logic                             lsu_store_c1_r_clk,      // clocks
-      39      6085356 :    input logic                             lsu_free_c2_clk,         // clocks
+      35      6085362 :    input logic                             lsu_c2_m_clk,            // clocks
+      36      6085362 :    input logic                             lsu_c2_r_clk,            // clocks
+      37      6085362 :    input logic                             lsu_c1_r_clk,            // clocks
+      38      6085362 :    input logic                             lsu_store_c1_r_clk,      // clocks
+      39      6085362 :    input logic                             lsu_free_c2_clk,         // clocks
       40            0 :    input logic                             clk_override,            // Override non-functional clock gating
-      41      6085356 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      41      6085362 :    input logic                             clk,                     // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       42              : 
       43            2 :    input logic                             rst_l,                   // reset, active low
       44              : 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_mem.sv.html
index f22a0562068..d6837555a26 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,8 +136,8 @@
       32              : #(
       33              : `include "el2_param.vh"
       34              :  )(
-      35      6085356 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      36      6085356 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+      35      6085362 :    input logic         clk,                                             // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      36      6085362 :    input logic         active_clk,                                      // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
       37            2 :    input logic         rst_l,                                           // reset, active low
       38            0 :    input logic         clk_override,                                    // Override non-functional clock gating
       39              : 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_ecc.sv.html
index c366594d07e..613282a99cf 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,8 +135,8 @@
       31              : `include "el2_param.vh"
       32              :  )
       33              : (
-      34      6085356 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
-      35      6085356 :    input logic                           lsu_c2_r_clk,       // clock
+      34      6085362 :    input logic                           clk,                // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35      6085362 :    input logic                           lsu_c2_r_clk,       // clock
       36            0 :    input logic                           clk_override,       // Override non-functional clock gating
       37            2 :    input logic                           rst_l,              // reset, active low
       38            0 :    input logic                           scan_mode,          // scan mode
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_lsc_ctl.sv.html
index b81121ad9f1..c175d6ae63c 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -136,14 +136,14 @@
       32              :  )(
       33            2 :    input logic                rst_l,                     // reset, active low
       34            0 :    input logic                clk_override,              // Override non-functional clock gating
-      35      6085356 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+      35      6085362 :    input logic                clk,                       // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
       36              : 
       37              :    // clocks per pipe
-      38      6085356 :    input logic                lsu_c1_m_clk,
-      39      6085356 :    input logic                lsu_c1_r_clk,
-      40      6085356 :    input logic                lsu_c2_m_clk,
-      41      6085356 :    input logic                lsu_c2_r_clk,
-      42      6085356 :    input logic                lsu_store_c1_m_clk,
+      38      6085362 :    input logic                lsu_c1_m_clk,
+      39      6085362 :    input logic                lsu_c1_r_clk,
+      40      6085362 :    input logic                lsu_c2_m_clk,
+      41      6085362 :    input logic                lsu_c2_r_clk,
+      42      6085362 :    input logic                lsu_store_c1_m_clk,
       43              : 
       44            0 :    input logic [31:0]         lsu_ld_data_r,             // Load data R-stage
       45            0 :    input logic [31:0]         lsu_ld_data_corr_r,        // ECC corrected data R-stage
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_stbuf.sv.html
index 18ccabf8e80..2cc6b042bab 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -137,11 +137,11 @@
       33              : `include "el2_param.vh"
       34              :  )
       35              : (
-      36      6085356 :    input logic                           clk,                         // core clock
+      36      6085362 :    input logic                           clk,                         // core clock
       37            2 :    input logic                           rst_l,                       // reset
       38              : 
-      39      6085356 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
-      40      6085356 :    input logic                           lsu_free_c2_clk,             // free clk
+      39      6085362 :    input logic                           lsu_stbuf_c1_clk,            // stbuf clock
+      40      6085362 :    input logic                           lsu_free_c2_clk,             // free clk
       41              : 
       42              :    // Store Buffer input
       43            0 :    input logic                           store_stbuf_reqvld_r,        // core instruction goes to stbuf
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_trigger.sv.html
index 5d4853f0300..e90582da368 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem.sv.html
index 0f36279a8f7..04b0b901bdd 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -126,7 +126,7 @@
       22              : `include "el2_param.vh"
       23              :  )
       24              : (
-      25      6085356 :    input logic         clk,
+      25      6085362 :    input logic         clk,
       26            2 :    input logic         rst_l,
       27            0 :    input logic         dccm_clk_override,
       28            0 :    input logic         icm_clk_override,
@@ -193,7 +193,7 @@
       89              : 
       90              : );
       91              : 
-      92      6085356 :    logic active_clk;
+      92      6085362 :    logic active_clk;
       93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
       94              : 
       95              :    el2_mem_if mem_export_local ();
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem_if.sv.html
index 578e10c41e9..154521d44b7 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : 
       27              :   //////////////////////////////////////////
       28              :   // Clock
-      29     18256068 :   logic                                                               clk;
+      29     18256086 :   logic                                                               clk;
       30              : 
       31              : 
       32              :   //////////////////////////////////////////
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pic_ctrl.sv.html
index e7bbf8f0bb6..8c18c830582 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,8 +131,8 @@
       27              :  )
       28              :                   (
       29              : 
-      30      6085356 :                      input  logic                   clk,                  // Core clock
-      31      6085356 :                      input  logic                   free_clk,             // free clock
+      30      6085362 :                      input  logic                   clk,                  // Core clock
+      31      6085362 :                      input  logic                   free_clk,             // free clock
       32            2 :                      input  logic                   rst_l,                // Reset for all flops
       33            0 :                      input  logic                   clk_override,         // Clock over-ride for gating
       34            2 :                      input  logic                   io_clk_override,      // PIC IO  Clock over-ride for gating
@@ -256,11 +256,11 @@
      152            0 :    logic                                     gw_config_c1_clken;
      153              : 
      154              : // clocks
-     155      6085356 :    logic                                     pic_raddr_c1_clk;
-     156      6085356 :    logic                                     pic_data_c1_clk;
-     157      6085356 :    logic                                     pic_pri_c1_clk;
-     158      6085356 :    logic                                     pic_int_c1_clk;
-     159      6085356 :    logic                                     gw_config_c1_clk;
+     155      6085362 :    logic                                     pic_raddr_c1_clk;
+     156      6085362 :    logic                                     pic_data_c1_clk;
+     157      6085362 :    logic                                     pic_pri_c1_clk;
+     158      6085362 :    logic                                     pic_int_c1_clk;
+     159      6085362 :    logic                                     gw_config_c1_clk;
      160              : 
      161              : // ---- Clock gating section ------
      162              : // c1 clock enables
@@ -601,13 +601,13 @@
      497            2 :          intpriority_rd_out =  '0 ;
      498            2 :          gw_config_rd_out =  '0 ;
      499            2 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500     99418208 :               if (intenable_reg_re[i]) begin
+     500     99897120 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503     99418208 :               if (intpriority_reg_re[i]) begin
+     503     99897120 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506     99418208 :               if (gw_config_reg_re[i]) begin
+     506     99897120 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
@@ -663,7 +663,7 @@
      559              : 
      560              : module el2_configurable_gw (
      561            0 :                              input logic gw_clk,
-     562    188646036 :                              input logic rawclk,
+     562    188646222 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564           62 :                              input logic rst_l,
      565            0 :                              input logic extintsrc_req ,
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pmp.sv.html
index fb6a158c8bf..e9317c1dda8 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -127,7 +127,7 @@
       23              :     parameter PMP_GRANULARITY = 0,  // TODO: Move to veer.config
       24              :     `include "el2_param.vh"
       25              : ) (
-      26      6085356 :     input logic clk,       // Top level clock
+      26      6085362 :     input logic clk,       // Top level clock
       27            2 :     input logic rst_l,     // Reset
       28            0 :     input logic scan_mode, // Scan mode
       29              : 
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133    149127504 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133    149845872 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139    149127504 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139    149845872 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -270,7 +270,7 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168            6 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169    149127504 :       if (!matched && match_all[r]) begin
+     169    149845872 :       if (!matched && match_all[r]) begin
      170            0 :         access_fail = ~final_perm_check[r];
      171            0 :         matched = 1'b1;
      172              :       end
@@ -348,7 +348,7 @@
      244           96 :       always_comb begin
      245           96 :         region_match_all[c][r] = 1'b0;
      246           96 :         unique case (pmp_pmpcfg[r].mode)
-     247    149127312 :           OFF:     region_match_all[c][r] = 1'b0;
+     247    149845680 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
      250            0 :           TOR: begin
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer.sv.html
index 50addb42280..b0efb3f5d64 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -130,7 +130,7 @@
       26              : `include "el2_param.vh"
       27              :  )
       28              :   (
-      29      6085356 :    input logic                  clk,
+      29      6085362 :    input logic                  clk,
       30            2 :    input logic                  rst_l,
       31            2 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
@@ -138,8 +138,8 @@
       34            0 :    input logic [31:1]           nmi_vec,
       35            2 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
-      37      6085356 :    output logic                 active_l2clk,
-      38      6085356 :    output logic                 free_l2clk,
+      37      6085362 :    output logic                 active_l2clk,
+      38      6085362 :    output logic                 free_l2clk,
       39              : 
       40            2 :    output logic [31:0] trace_rv_i_insn_ip,
       41            0 :    output logic [31:0] trace_rv_i_address_ip,
@@ -653,7 +653,7 @@
      549            0 :    logic [3:0]             lsu_trigger_match_m;
      550              : 
      551              : 
-     552      2993852 :    logic [31:0] dec_i0_immed_d;
+     552      2993855 :    logic [31:0] dec_i0_immed_d;
      553           64 :    logic [12:1] dec_i0_br_immed_d;
      554        24338 :    logic         dec_i0_select_pc_d;
      555              : 
@@ -662,7 +662,7 @@
      558            0 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
      559              : 
      560        24428 :    logic         dec_i0_alu_decode_d;
-     561      3018188 :    logic         dec_i0_branch_d;
+     561      3018191 :    logic         dec_i0_branch_d;
      562              : 
      563           26 :    logic         ifu_miss_state_idle;
      564            0 :    logic         dec_tlu_flush_noredir_r;
@@ -725,7 +725,7 @@
      621            0 :    logic [31:1] dec_tlu_flush_path_r;
      622            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
      623              : 
-     624      3042546 :    logic        ifu_i0_pc4;
+     624      3042549 :    logic        ifu_i0_pc4;
      625              : 
      626            0 :    el2_mul_pkt_t  mul_p;
      627              : 
@@ -749,10 +749,10 @@
      645            0 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
      646              : 
      647        24340 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
-     648      2993778 :    logic [1:0]  exu_i0_br_hist_r;
+     648      2993781 :    logic [1:0]  exu_i0_br_hist_r;
      649            0 :    logic        exu_i0_br_error_r;
      650            0 :    logic        exu_i0_br_start_error_r;
-     651      2993842 :    logic        exu_i0_br_valid_r;
+     651      2993845 :    logic        exu_i0_br_valid_r;
      652        24402 :    logic        exu_i0_br_mp_r;
      653        24348 :    logic        exu_i0_br_middle_r;
      654              : 
@@ -894,8 +894,8 @@
      790              : 
      791              :    // PMU Signals
      792        24402 :    logic                   exu_pmu_i0_br_misp;
-     793      2993846 :    logic                   exu_pmu_i0_br_ataken;
-     794      3018196 :    logic                   exu_pmu_i0_pc4;
+     793      2993849 :    logic                   exu_pmu_i0_br_ataken;
+     794      3018199 :    logic                   exu_pmu_i0_pc4;
      795              : 
      796            0 :    logic                   lsu_pmu_load_external_m;
      797            0 :    logic                   lsu_pmu_store_external_m;
@@ -913,8 +913,8 @@
      809           72 :    logic                   ifu_pmu_bus_trxn;
      810              : 
      811            2 :    logic                   active_state;
-     812      6085356 :    logic                   free_clk;
-     813      6085356 :    logic                   active_clk;
+     812      6085362 :    logic                   free_clk;
+     813      6085362 :    logic                   active_clk;
      814            0 :    logic                   dec_pause_state_cg;
      815              : 
      816            0 :    logic                   lsu_nonblock_load_data_error;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer_wrapper.sv.html
index 3b930c506c9..203a2374393 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -131,7 +131,7 @@
       27              : `include "el2_param.vh"
       28              : )
       29              : (
-      30      6085356 :    input logic                             clk,
+      30      6085362 :    input logic                             clk,
       31            2 :    input logic                             rst_l,
       32            2 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
@@ -454,8 +454,8 @@
      350            0 :    input logic                      [31:0] dmi_uncore_rdata
      351              : );
      352              : 
-     353      6085356 :    logic                             active_l2clk;
-     354      6085356 :    logic                             free_l2clk;
+     353      6085362 :    logic                             active_l2clk;
+     354      6085362 :    logic                             free_l2clk;
      355              : 
      356              :    // DCCM ports
      357            0 :    logic         dccm_wren;
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_openocd_axi4/index_mem_lib.sv.html
index 9dd926dc497..2c4c29cd98c 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111     49709072 : `EL2_RAM(4096, 39)
+     111     49948528 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
diff --git a/html/main/coverage_dashboard/all_openocd_axi4/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_openocd_axi4/index_rvjtag_tap.v.html
index d5853dbe0f9..3aefc0fe160 100644
--- a/html/main/coverage_dashboard/all_openocd_axi4/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_openocd_axi4/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index.html b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index.html
index 91e7cdb05ae..947d459adb5 100644
--- a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index.html
+++ b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design.html
index bc2205ca168..6e9cddfa1a6 100644
--- a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design_lib.html
index 666830d5c5f..8db381fff54 100644
--- a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_beh_lib.sv.html
index 18f07ba48bb..89b47efcaa9 100644
--- a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_el2_pic_ctrl.sv.html
index f23d0f9aa71..3d84cedc41d 100644
--- a/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_pic_gw_test_gateway/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_clken/index.html b/html/main/coverage_dashboard/all_pic_test_clken/index.html
index 035657a95e4..f7533deb923 100644
--- a/html/main/coverage_dashboard/all_pic_test_clken/index.html
+++ b/html/main/coverage_dashboard/all_pic_test_clken/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design.html
index 39db38bdc90..376ef690164 100644
--- a/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design_lib.html
index d76d4a9bd5d..7845668c1e2 100644
--- a/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_pic_test_clken/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_clken/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_pic_test_clken/index_beh_lib.sv.html
index 63c3801ee66..a83b4c20b94 100644
--- a/html/main/coverage_dashboard/all_pic_test_clken/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_clken/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_clken/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_pic_test_clken/index_el2_pic_ctrl.sv.html
index 8a2938a6696..e8e114eb12a 100644
--- a/html/main/coverage_dashboard/all_pic_test_clken/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_clken/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_config/index.html b/html/main/coverage_dashboard/all_pic_test_config/index.html
index 65fe8f2f08b..5d5c5689e29 100644
--- a/html/main/coverage_dashboard/all_pic_test_config/index.html
+++ b/html/main/coverage_dashboard/all_pic_test_config/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design.html
index 6b8c7e8438c..d4a1c0319b8 100644
--- a/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design_lib.html
index 6d67b745c4b..a31163777f0 100644
--- a/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_pic_test_config/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_config/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_pic_test_config/index_beh_lib.sv.html
index 83bfa3fe3e0..91de96ad203 100644
--- a/html/main/coverage_dashboard/all_pic_test_config/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_config/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_config/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_pic_test_config/index_el2_pic_ctrl.sv.html
index cf2a4e98d9d..4d4abcb2c04 100644
--- a/html/main/coverage_dashboard/all_pic_test_config/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_config/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_prioritization/index.html b/html/main/coverage_dashboard/all_pic_test_prioritization/index.html
index 1092c11e08b..855778d5437 100644
--- a/html/main/coverage_dashboard/all_pic_test_prioritization/index.html
+++ b/html/main/coverage_dashboard/all_pic_test_prioritization/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design.html
index d69c053bd4f..f78bde0702e 100644
--- a/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design_lib.html
index 33dd9126306..1abbfcbd562 100644
--- a/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_pic_test_prioritization/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_prioritization/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_pic_test_prioritization/index_beh_lib.sv.html
index d62f2896c06..d78a83cc150 100644
--- a/html/main/coverage_dashboard/all_pic_test_prioritization/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_prioritization/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_prioritization/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_pic_test_prioritization/index_el2_pic_ctrl.sv.html
index 56484106b81..d3df6bb6a7c 100644
--- a/html/main/coverage_dashboard/all_pic_test_prioritization/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_prioritization/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_reset/index.html b/html/main/coverage_dashboard/all_pic_test_reset/index.html
index 2897050b2cc..9803ccc10b4 100644
--- a/html/main/coverage_dashboard/all_pic_test_reset/index.html
+++ b/html/main/coverage_dashboard/all_pic_test_reset/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design.html
index 8740cf1d201..777c33d2375 100644
--- a/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design_lib.html
index 2f290a85453..f5cc567940b 100644
--- a/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_pic_test_reset/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_reset/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_pic_test_reset/index_beh_lib.sv.html
index c6088cc0e40..474d63b7724 100644
--- a/html/main/coverage_dashboard/all_pic_test_reset/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_reset/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_reset/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_pic_test_reset/index_el2_pic_ctrl.sv.html
index c7681587504..a947463bd05 100644
--- a/html/main/coverage_dashboard/all_pic_test_reset/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_reset/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_servicing/index.html b/html/main/coverage_dashboard/all_pic_test_servicing/index.html
index ce1ab0e1840..132fa916d46 100644
--- a/html/main/coverage_dashboard/all_pic_test_servicing/index.html
+++ b/html/main/coverage_dashboard/all_pic_test_servicing/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design.html
index fecd1b3f4c8..47d72cdfede 100644
--- a/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design_lib.html
index 80094a0f83c..6a707108414 100644
--- a/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_pic_test_servicing/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pic_test_servicing/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_pic_test_servicing/index_beh_lib.sv.html
index 9f0d35284cf..45d91b3eb5d 100644
--- a/html/main/coverage_dashboard/all_pic_test_servicing/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_servicing/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pic_test_servicing/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_pic_test_servicing/index_el2_pic_ctrl.sv.html
index dd1b9ffdb99..3c2edcd225c 100644
--- a/html/main/coverage_dashboard/all_pic_test_servicing/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_pic_test_servicing/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pmp_test_address_matching/index.html b/html/main/coverage_dashboard/all_pmp_test_address_matching/index.html
index 4450aa84ae3..a8d41924b53 100644
--- a/html/main/coverage_dashboard/all_pmp_test_address_matching/index.html
+++ b/html/main/coverage_dashboard/all_pmp_test_address_matching/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pmp_test_address_matching/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pmp_test_address_matching/index_Cores-VeeR-EL2_design.html
index 3c9b7fa65c7..50db005a999 100644
--- a/html/main/coverage_dashboard/all_pmp_test_address_matching/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pmp_test_address_matching/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pmp_test_address_matching/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_pmp_test_address_matching/index_el2_pmp.sv.html
index ef67bf545dc..896cf89cfec 100644
--- a/html/main/coverage_dashboard/all_pmp_test_address_matching/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_pmp_test_address_matching/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index.html b/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index.html
index b7909c36272..44b9301a281 100644
--- a/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index.html
+++ b/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_Cores-VeeR-EL2_design.html
index d1000ee8a15..e6f8461890e 100644
--- a/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_el2_pmp.sv.html
index af1d3fb83b7..6f2d29c9aea 100644
--- a/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_pmp_test_multiple_configs/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_pmp_test_xwr_access/index.html b/html/main/coverage_dashboard/all_pmp_test_xwr_access/index.html
index 5d80ed7836f..2881f634420 100644
--- a/html/main/coverage_dashboard/all_pmp_test_xwr_access/index.html
+++ b/html/main/coverage_dashboard/all_pmp_test_xwr_access/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_Cores-VeeR-EL2_design.html
index b1ac715bd94..9a6ce1a0e71 100644
--- a/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_el2_pmp.sv.html
index db5babe52f3..3443e143c6c 100644
--- a/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_pmp_test_xwr_access/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index.html b/html/main/coverage_dashboard/all_riscof_/index.html
index 145bc1f870a..fae659442b5 100644
--- a/html/main/coverage_dashboard/all_riscof_/index.html
+++ b/html/main/coverage_dashboard/all_riscof_/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design.html
index b455df93fd1..fdd40047d95 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dbg.html
index 2b527e46f47..c5213269dd2 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dec.html
index 947e99fcec9..5425c8b38f0 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dmi.html
index 4962bc4765d..f8bffe08396 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_exu.html
index 30e7904edc9..af738fb0035 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_ifu.html
index 3d1628b5b7b..76a7aa8d001 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_include.html
index 61461125866..7c41376f9d9 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lib.html
index 69bfaafbbf3..c66d879baae 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lsu.html
index de147238a5b..fac8b2de5ed 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscof_/index_beh_lib.sv.html
index e1a1bd7ee05..48542b016ad 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscof_/index_dmi_jtag_to_core_sync.v.html
index 049845b36d0..e9bacc2727b 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscof_/index_dmi_mux.v.html
index c475b61566f..63a1a1ae27c 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscof_/index_dmi_wrapper.v.html
index 9ab766e4435..39c31b21302 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dbg.sv.html
index 6c5ece5cebb..7a831995196 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec.sv.html
index f3026acf148..7941ce0aaf4 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_csr_equ_m.svh.html
index 868aaa9b3e1..701d914c11b 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_decode_ctl.sv.html
index bff43f3424f..36e6e5e1a4f 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_gpr_ctl.sv.html
index 646d6b39c7d..98353f89df3 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_ib_ctl.sv.html
index b0c8addc12b..f99258b07c4 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_pmp_ctl.sv.html
index b9f50824474..c138f4fb887 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_tlu_ctl.sv.html
index c4c15f9bbf7..e1bafb5e4c6 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_trigger.sv.html
index 3105b0ac3f1..88b4fb3b615 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_dma_ctrl.sv.html
index c6c0e369cb7..cd6e2a0b379 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_exu.sv.html
index 5facbe7c64b..c8e2699443c 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_exu_alu_ctl.sv.html
index 91d5e9f527b..0984d48c00d 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_exu_div_ctl.sv.html
index 641c775b1ec..4828ab2b88b 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_exu_mul_ctl.sv.html
index e27b66a0859..399b1625612 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu.sv.html
index 7064d2211e3..4958e2f832d 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_aln_ctl.sv.html
index afccf9d5cbf..5167b105aee 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_bp_ctl.sv.html
index fc1f6721a63..e01737570b3 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_compress_ctl.sv.html
index 46a276dc3a6..6fd42a6dc9e 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ic_mem.sv.html
index 3f8f39bcbf0..7c49aea3da8 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_iccm_mem.sv.html
index fbafb46a5dd..f57ac95e9c4 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ifc_ctl.sv.html
index 5df405e8b50..d75ef2b18be 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_mem_ctl.sv.html
index d5944b32fc4..edb8e017c0e 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lib.sv.html
index e45844f0126..40321d1aaed 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu.sv.html
index c8925304a1d..d92ccf95a33 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_addrcheck.sv.html
index 360c54e15a9..8872a5e40d0 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_buffer.sv.html
index 54ac2cfa718..de1f2613336 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_intf.sv.html
index f7f0785781b..9db877b325a 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_clkdomain.sv.html
index 4876f7cec70..c57afc4a4ee 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_ctl.sv.html
index 98226cbe0ed..d0de498b46c 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_mem.sv.html
index 3c8ea520177..bffb5926a91 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_ecc.sv.html
index 84978dbc3fd..23494284bc1 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_lsc_ctl.sv.html
index c0b29bb5b20..810d9d48f0f 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_stbuf.sv.html
index d0aa348b9a5..9b89d089681 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_trigger.sv.html
index b52985e8354..f7fe48fdb52 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_mem.sv.html
index f9c70e217f7..7b369cd8def 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_mem_if.sv.html
index fa57a351f97..ff3bb8c60c6 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_pic_ctrl.sv.html
index 27aefc8938f..1a67ce8b1d0 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_pmp.sv.html
index 5e88fbb8595..e823cc22fe5 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_veer.sv.html
index 13ad5f0f550..561f797348d 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscof_/index_el2_veer_wrapper.sv.html
index 78460b3b1a8..46cc5ee19ea 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscof_/index_mem_lib.sv.html
index 6952ab9eadc..2ab6186b442 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscof_/index_rvjtag_tap.v.html
index 044cfacd3c3..3957973710f 100644
--- a/html/main/coverage_dashboard/all_riscof_/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscof_/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index.html b/html/main/coverage_dashboard/all_riscof_u/index.html
index ced1331a284..fd923200ea7 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design.html
index ac74d83065b..20f5f990e55 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dbg.html
index 085e82b718d..cf7b9833055 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dec.html
index e66342c130e..2ee4cabc9fa 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dmi.html
index 441427321d9..a91a3023f39 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_exu.html
index 826664b140e..f5711dd9542 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_ifu.html
index b3ee1a5aa6a..f168ace0e6f 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_include.html
index fc7b665be92..7e613a2bfc2 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lib.html
index f5fab9cd3e0..65453eb1820 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lsu.html
index b673b874f12..5e8106bbad1 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_beh_lib.sv.html
index 121abf48beb..bc8658ffeb2 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscof_u/index_dmi_jtag_to_core_sync.v.html
index 75ac7efec38..3c3daa2462f 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscof_u/index_dmi_mux.v.html
index 9337072c7f0..539748a69cf 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscof_u/index_dmi_wrapper.v.html
index 2627c3e5429..f85b5775907 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dbg.sv.html
index 06c9048c16d..9b52bbe2d1b 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec.sv.html
index 1592d8b1fd1..eedc261df49 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_csr_equ_m.svh.html
index 8eeae4ae090..b9ae4f8729f 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_decode_ctl.sv.html
index 69f100077a2..ef35ebc8e9c 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_gpr_ctl.sv.html
index cd48c7ea69c..b99e34c3096 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_ib_ctl.sv.html
index 1fe32ce2e7d..a826ec05888 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_pmp_ctl.sv.html
index c97407ae78e..aeec21af049 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_tlu_ctl.sv.html
index cbcb4e9914f..81cee3e353e 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_trigger.sv.html
index 6b1fda11f3d..db0fef58870 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_dma_ctrl.sv.html
index 7191d08595d..d67ee30ae45 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu.sv.html
index 226f09c6e9d..b0ddddd856d 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_alu_ctl.sv.html
index 1d95598f60c..acdea6103f7 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_div_ctl.sv.html
index b4ff6a2739c..1521c319498 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_mul_ctl.sv.html
index cd1ad5cf8c7..05513c24040 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu.sv.html
index 7ffb1817e0a..d994449e4d3 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_aln_ctl.sv.html
index 1d9b601f598..098091b6b6b 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_bp_ctl.sv.html
index 491f7be84c0..79b5cf7c61a 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_compress_ctl.sv.html
index 2d6f2c4c3bd..344f78d56dc 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ic_mem.sv.html
index 4e788c3ff7a..784927efa4a 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_iccm_mem.sv.html
index f4cdc9f96f4..aee7da621ab 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ifc_ctl.sv.html
index 6ef4132ae69..566e3aa39b7 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_mem_ctl.sv.html
index 25b90e0c24a..efc5c297e42 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lib.sv.html
index 83953efad70..709d507b02f 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu.sv.html
index 14eb10ee3bf..07166f67c17 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_addrcheck.sv.html
index 9e2eaaa6689..a5e1f431dfe 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_buffer.sv.html
index ede40155011..98f5224ec65 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_intf.sv.html
index 34bb8a7d4d8..5a2f32565fd 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_clkdomain.sv.html
index d7a27f663f4..bf1965303ca 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_ctl.sv.html
index 6e30c560ebd..3a2c53788cb 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_mem.sv.html
index 5ad2b83b502..9ed45165177 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_ecc.sv.html
index d43e1776f41..3726e137ce4 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_lsc_ctl.sv.html
index ea0defcda53..9e5dac33b2c 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_stbuf.sv.html
index 04d7e901790..1bf1e28815d 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_trigger.sv.html
index 2978f8463ab..0b91464d3c7 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_mem.sv.html
index 0ca21a5a626..4935c32bea1 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_mem_if.sv.html
index 80b394ad915..a88f0a7525b 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_pic_ctrl.sv.html
index 82e14b3ee97..e27e1b44a10 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_pmp.sv.html
index 5c031bba814..5d4fdac4a19 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_veer.sv.html
index e1b7ef34763..090580749a6 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_el2_veer_wrapper.sv.html
index c2e0856618c..31d70937882 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscof_u/index_mem_lib.sv.html
index 9262dd1c54c..cfde20570f8 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscof_u/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscof_u/index_rvjtag_tap.v.html
index 3f008d4e51f..6725be10228 100644
--- a/html/main/coverage_dashboard/all_riscof_u/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscof_u/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index.html
index d64f5cc23db..1dc58917195 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        67.2%
+    
+        65.9%
     
     
-        615
+        603
     
     
         915
@@ -167,19 +167,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    58.6%
+                    51.4%
                 
             
 
             
-                41
+                36
                 /
                 70
             
@@ -303,19 +303,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    85.2%
+                    79.5%
                 
             
 
             
-                104
+                97
                 /
                 122
             
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html
index 38440b9eeec..ab1cbe2e3c7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        58.6%
+    
+        51.4%
     
     
-        41
+        36
     
     
         70
@@ -371,19 +371,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    49.0%
+                    39.2%
                 
             
 
             
-                25
+                20
                 /
                 51
             
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html
index 4d091a593b9..215ef2d299e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html
index 2042df85183..6916e2a150e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        85.2%
+    
+        79.5%
     
     
-        104
+        97
     
     
         122
@@ -235,19 +235,19 @@
                     
                     
 
-                    
 
+                    
 
                     

                 

             
 
-            
+            
                 
-                    82.9%
+                    76.2%
                 
             
 
             
-                87
+                80
                 /
                 105
             
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html
index 9f2c27ab250..823fb523236 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html
index 0dd2a4b41f2..9cf9d23b9af 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html
index 8e2937f0446..0897f662073 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html
index bacee3bbe26..3674f4d508c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html
index 1aaaac57a5d..c506cae614d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html
index 4e222ed72c8..29496f0a07f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_beh_lib.sv.html
index 138bdf70ceb..4c97d3eacaf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -139,11 +139,11 @@
       35              :    end
       36              : `endif
       37              : 
-      38       399594 :    always_ff @(posedge clk or negedge rst_l) begin
+      38       286289 :    always_ff @(posedge clk or negedge rst_l) begin
       39           30 :       if (rst_l == 0)
       40           30 :         dout[WIDTH-1:0] <= 0;
       41              :       else
-      42       399564 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
+      42       286259 :         dout[WIDTH-1:0] <= din[WIDTH-1:0];
       43              :    end
       44              : 
       45              : end
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html
index 564d23bc7ff..f0e94fc4980 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -150,14 +150,14 @@
       46              : 
       47              : 
       48              : // synchronizers  
-      49       399594 : always @ ( posedge clk or negedge rst_n) begin
+      49       286289 : always @ ( posedge clk or negedge rst_n) begin
       50           12 :     if(!rst_n) begin
       51           12 :         rden <= '0;
       52           12 :         wren <= '0;
       53              :     end
-      54       399582 :     else begin
-      55       399582 :         rden <= {rden[1:0], rd_en};
-      56       399582 :         wren <= {wren[1:0], wr_en};
+      54       286277 :     else begin
+      55       286277 :         rden <= {rden[1:0], rd_en};
+      56       286277 :         wren <= {wren[1:0], wr_en};
       57              :     end
       58              : end
       59              : 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_mux.v.html
index a9f7fcc8ce5..4f53fe661a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_wrapper.v.html
index e8b6420ca10..af1240fca5b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dbg.sv.html
index e6befb7b7fe..71a35b80b65 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -575,10 +575,10 @@
      471            6 :       sb_abmem_data_done_en   = 1'b0;
      472              : 
      473            6 :        case (dbg_state)
-     474       399600 :             IDLE: begin
-     475       399600 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
-     476       399600 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
-     477       399600 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
+     474       286295 :             IDLE: begin
+     475       286295 :                      dbg_nxtstate         = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING;         // initiate the halt command to the core
+     476       286295 :                      dbg_state_en         = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only;      // when the jtag writes the halt bit in the DM register, OR when the status indicates H
+     477       286295 :                      dbg_halt_req         = dmcontrol_reg[31];               // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
      478              :             end
      479            0 :             HALTING : begin
      480            0 :                      dbg_nxtstate         = HALTED;                                 // Goto HALTED once the core sends an ACK
@@ -705,13 +705,13 @@
      601            6 :       sbcs_sberror_din[2:0]  = 3'b0;
      602            6 :       sbaddress0_reg_wren1   = 1'b0;
      603            6 :       case (sb_state)
-     604       399600 :             SBIDLE: begin
-     605       399600 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
-     606       399600 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
-     607       399600 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
-     608       399600 :                      sbcs_sbbusy_din        = 1'b1;
-     609       399600 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
-     610       399600 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+     604       286295 :             SBIDLE: begin
+     605       286295 :                      sb_nxtstate            = sbdata0wr_access ? WAIT_WR : WAIT_RD;
+     606       286295 :                      sb_state_en            = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
+     607       286295 :                      sbcs_sbbusy_wren       = sb_state_en;                                                 // set the single read bit if it is a singlread command
+     608       286295 :                      sbcs_sbbusy_din        = 1'b1;
+     609       286295 :                      sbcs_sberror_wren      = sbcs_wren & (|dmi_reg_wdata[14:12]);                                            // write to clear the error bits
+     610       286295 :                      sbcs_sberror_din[2:0]  = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
      611              :             end
      612            0 :             WAIT_RD: begin
      613            0 :                      sb_nxtstate           = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec.sv.html
index 8317de8c115..73b308b6d6d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_csr_equ_m.svh.html
index d73670488e5..74ef1745fb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html
index 58ae141369c..1eb8c615f7f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        82.9%
+    
+        76.2%
     
     
-        87
+        80
     
     
         105
@@ -631,14 +631,14 @@
      527              : 
      528            6 :    always_comb begin
      529            6 :       i0_dp = i0_dp_raw;
-     530           10 :       if (i0_br_error_all | i0_instr_error) begin
-     531           10 :          i0_dp          =   '0;
-     532           10 :          i0_dp.alu      = 1'b1;
-     533           10 :          i0_dp.rs1      = 1'b1;
-     534           10 :          i0_dp.rs2      = 1'b1;
-     535           10 :          i0_dp.lor      = 1'b1;
-     536           10 :          i0_dp.legal    = 1'b1;
-     537           10 :          i0_dp.postsync = 1'b1;
+     530        86500 :       if (i0_br_error_all | i0_instr_error) begin
+     531            5 :          i0_dp          =   '0;
+     532            5 :          i0_dp.alu      = 1'b1;
+     533            5 :          i0_dp.rs1      = 1'b1;
+     534            5 :          i0_dp.rs2      = 1'b1;
+     535            5 :          i0_dp.lor      = 1'b1;
+     536            5 :          i0_dp.legal    = 1'b1;
+     537            5 :          i0_dp.postsync = 1'b1;
      538              :       end
      539              :    end
      540              : 
@@ -710,15 +710,15 @@
      606            6 :       for (int i=0; i<NBLOAD_SIZE; i++) begin
      607            6 :          if (~found) begin
      608            0 :             if (~cam[i].valid) begin
-     609       399612 :                cam_wen[i] = cam_write;
-     610       399612 :                found = 1'b1;
+     609       286307 :                cam_wen[i] = cam_write;
+     610       286307 :                found = 1'b1;
      611              :             end
      612            0 :             else begin
      613            0 :                cam_wen[i] = 0;
      614              :             end
      615              :          end
      616              :          else
-     617      1198836 :             cam_wen[i] = 0;
+     617       858921 :             cam_wen[i] = 0;
      618              :       end
      619              :    end
      620              : 
@@ -756,7 +756,7 @@
      652              : 
      653           24 :          cam[i] = cam_raw[i];
      654              : 
-     655      1598400 :          if (cam_data_reset_val[i])
+     655      1145180 :          if (cam_data_reset_val[i])
      656            0 :            cam[i].valid = 1'b0;
      657              : 
      658           24 :          cam_in[i] = '0;
@@ -767,17 +767,17 @@
      663            0 :             cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
      664            0 :             cam_in[i].rd[4:0]  = nonblock_load_rd[4:0];
      665              :          end
-     666      1598448 :          else if ( (cam_inv_reset_val[i]) |
+     666      1145228 :          else if ( (cam_inv_reset_val[i]) |
      667              :                    (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
      668            0 :            cam_in[i].valid = 1'b0;
      669              :          else
-     670      1598448 :            cam_in[i] = cam[i];
+     670      1145228 :            cam_in[i] = cam[i];
      671              : 
-     672      1598448 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
+     672      1145228 :          if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
      673            0 :            cam_in[i].wb = 1'b1;
      674              : 
      675              :          // force debug halt forces cam valids to 0; highest priority
-     676      1598400 :          if (dec_tlu_force_halt)
+     676      1145180 :          if (dec_tlu_force_halt)
      677            0 :            cam_in[i].valid = 1'b0;
      678              :       end
      679              : 
@@ -847,26 +847,26 @@
      743            6 :    always_comb begin
      744            6 :       i0_itype = NULL_OP;
      745              : 
-     746        75790 :       if (i0_legal_decode_d) begin
-     747         7008 :          if (i0_dp.mul)                  i0_itype = MUL;
-     748        75790 :          if (i0_dp.load)                 i0_itype = LOAD;
-     749          392 :          if (i0_dp.store)                i0_itype = STORE;
-     750        14756 :          if (i0_dp.pm_alu)               i0_itype = ALU;
-     751        75790 :          if (i0_dp.zbb | i0_dp.zbs |
+     746        54661 :       if (i0_legal_decode_d) begin
+     747         4959 :          if (i0_dp.mul)                  i0_itype = MUL;
+     748        54661 :          if (i0_dp.load)                 i0_itype = LOAD;
+     749          390 :          if (i0_dp.store)                i0_itype = STORE;
+     750        10168 :          if (i0_dp.pm_alu)               i0_itype = ALU;
+     751        54661 :          if (i0_dp.zbb | i0_dp.zbs |
      752              :              i0_dp.zbe | i0_dp.zbc |
      753              :              i0_dp.zbp | i0_dp.zbr |
      754              :              i0_dp.zbf | i0_dp.zba)
      755            0 :                                          i0_itype = BITMANIPU;
-     756           26 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
-     757           42 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
-     758        75790 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
-     759        75790 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
+     756           22 :          if ( csr_read & ~csr_write)     i0_itype = CSRREAD;
+     757           36 :          if (~csr_read &  csr_write)     i0_itype = CSRWRITE;
+     758        37898 :          if ( csr_read &  csr_write)     i0_itype = CSRRW;
+     759        54661 :          if (i0_dp.ebreak)               i0_itype = EBREAK;
      760            6 :          if (i0_dp.ecall)                i0_itype = ECALL;
-     761        75790 :          if (i0_dp.fence)                i0_itype = FENCE;
-     762        75790 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
+     761        54661 :          if (i0_dp.fence)                i0_itype = FENCE;
+     762        54661 :          if (i0_dp.fence_i)              i0_itype = FENCEI;  // fencei will set this even with fence attribute
      763            6 :          if (i0_dp.mret)                 i0_itype = MRET;
-     764           34 :          if (i0_dp.condbr)               i0_itype = CONDBR;
-     765           32 :          if (i0_dp.jal)                  i0_itype = JAL;
+     764           23 :          if (i0_dp.condbr)               i0_itype = CONDBR;
+     765           31 :          if (i0_dp.jal)                  i0_itype = JAL;
      766              :       end
      767              :    end
      768              : 
@@ -963,27 +963,27 @@
      859            6 :    always_comb  begin
      860            6 :       lsu_p = '0;
      861              : 
-     862       399600 :       if (dec_extint_stall) begin
+     862       286295 :       if (dec_extint_stall) begin
      863            0 :          lsu_p.load = 1'b1;
      864            0 :          lsu_p.word = 1'b1;
      865            0 :          lsu_p.fast_int = 1'b1;
      866            0 :          lsu_p.valid = 1'b1;
      867              :       end
-     868       399600 :       else begin
-     869       399600 :          lsu_p.valid = lsu_decode_d;
+     868       286295 :       else begin
+     869       286295 :          lsu_p.valid = lsu_decode_d;
      870              : 
-     871       399600 :          lsu_p.load                         =  i0_dp.load ;
-     872       399600 :          lsu_p.store                        =  i0_dp.store;
-     873       399600 :          lsu_p.by                           =  i0_dp.by   ;
-     874       399600 :          lsu_p.half                         =  i0_dp.half ;
-     875       399600 :          lsu_p.word                         =  i0_dp.word ;
-     876       399600 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
+     871       286295 :          lsu_p.load                         =  i0_dp.load ;
+     872       286295 :          lsu_p.store                        =  i0_dp.store;
+     873       286295 :          lsu_p.by                           =  i0_dp.by   ;
+     874       286295 :          lsu_p.half                         =  i0_dp.half ;
+     875       286295 :          lsu_p.word                         =  i0_dp.word ;
+     876       286295 :          lsu_p.stack                        = (i0r.rs1[4:0]==5'd2);   // stack reference
      877              : 
-     878       399600 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
-     879       399600 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
-     880       399600 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
+     878       286295 :          lsu_p.load_ldst_bypass_d          =  load_ldst_bypass_d ;
+     879       286295 :          lsu_p.store_data_bypass_d         =  store_data_bypass_d;
+     880       286295 :          lsu_p.store_data_bypass_m         =  store_data_bypass_m;
      881              : 
-     882       399600 :          lsu_p.unsign  =  i0_dp.unsign;
+     882       286295 :          lsu_p.unsign  =  i0_dp.unsign;
      883              :       end
      884              :    end
      885              : 
@@ -1380,7 +1380,7 @@
     1276            6 :       r_t_in.i0trigger[3:0]              = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
     1277            6 :       r_t_in.pmu_lsu_misaligned          = lsu_pmu_misaligned_r;   // only valid if a load/store is valid in DC3 stage
     1278              : 
-    1279           28 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
+    1279           23 :       if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
     1280              : 
     1281              :    end
     1282              : 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html
index aef1243a98d..fc89e7adf72 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html
index 0b317945387..8c4119de233 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html
index 0b708e07e19..301d0f8f014 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html
index ae6909bf41c..02989c9dca0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html
index 6adf3cdfe58..9bb37fa5436 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html
index 8aae30e290f..c8c82b50df3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu.sv.html
index 923d892f7f3..7844b69f9d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html
index 780192d55c2..f6837e3c98b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -443,8 +443,8 @@
      339              : 
      340            6 :         for (int i=0; i<32; i++) begin
      341            0 :           if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
-     342     12787584 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
-     343     12787584 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
+     342      9161824 :               bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
+     343      9161824 :               bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
      344              :            end
      345              :            else
      346            0 :               found=1'b1;
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html
index 3a7ce90af48..877f8934b95 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html
index a6ad2a2fb11..ec0d44bd796 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -310,10 +310,10 @@
      206            6 :        for (bcompress_i=0; bcompress_i<32; bcompress_i++)
      207          192 :          begin
      208          192 :              bcompress_test_bit_d              =  rs2_in[bcompress_i];
-     209        87232 :              if (bcompress_test_bit_d)
-     210        87232 :                begin
-     211        87232 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
-     212        87232 :                   bcompress_j                  =  bcompress_j + 1;
+     209        57760 :              if (bcompress_test_bit_d)
+     210        57760 :                begin
+     211        57760 :                   bcompress_d[bcompress_j]     =  rs1_in[bcompress_i];
+     212        57760 :                   bcompress_j                  =  bcompress_j + 1;
      213              :                end  // IF  bcompress_test_bit
      214              :          end        // FOR bcompress_i
      215              :      end            // ALWAYS_COMB
@@ -337,10 +337,10 @@
      233            6 :        for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
      234          192 :          begin
      235          192 :              bdecompress_test_bit_d            =  rs2_in[bdecompress_i];
-     236        87232 :              if (bdecompress_test_bit_d)
-     237        87232 :                begin
-     238        87232 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
-     239        87232 :                   bdecompress_j                =  bdecompress_j + 1;
+     236        57760 :              if (bdecompress_test_bit_d)
+     237        57760 :                begin
+     238        57760 :                   bdecompress_d[bdecompress_i] =  rs1_in[bdecompress_j];
+     239        57760 :                   bdecompress_j                =  bdecompress_j + 1;
      240              :                end  // IF  bdecompress_test_bit
      241              :          end        // FOR bdecompress_i
      242              :      end            // ALWAYS_COMB
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu.sv.html
index 1d66592dda2..7b8a36b3640 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html
index 03bde16d9df..6cb0ab4ae9c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html
index 89677ef52b9..9d0c4b46d9f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -777,18 +777,18 @@
      673            6 :         btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] = '0 ;
      674              : 
      675            6 :         for (int j=0; j< LRU_SIZE; j++) begin
-     676       399600 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     676       286295 :           if (btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      677              : 
-     678       399600 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     679       399600 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     678       286295 :            btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     679       286295 :            btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      680              : 
      681              :           end
      682              :         end
      683            6 :         for (int j=0; j< LRU_SIZE; j++) begin
-     684       399600 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
+     684       286295 :           if (btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == (pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1)'(j)) begin
      685              : 
-     686       399600 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
-     687       399600 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
+     686       286295 :            btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way0_out[j];
+     687       286295 :            btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0] =  btb_bank0_rd_data_way1_out[j];
      688              : 
      689              :           end
      690              :         end
@@ -978,12 +978,12 @@
      874            6 :      bht_bank1_rd_data_f[1:0] = '0 ;
      875            6 :      bht_bank0_rd_data_p1_f[1:0] = '0 ;
      876            6 :      for (int j=0; j< pt.BHT_ARRAY_DEPTH; j++) begin
-     877       399600 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     878       399600 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
-     879       399600 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
+     877       286295 :        if (bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     878       286295 :          bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[0][j];
+     879       286295 :          bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[1][j];
      880              :        end
-     881       399600 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
-     882       399600 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
+     881       286295 :        if (bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] == (pt.BHT_ADDR_HI-pt.BHT_ADDR_LO+1)'(j)) begin
+     882       286295 :          bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[0][j];
      883              :        end
      884              :       end
      885              :     end // block: BHT_rd_mux
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html
index c52d7835d7e..b976183fe85 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html
index c9f303bd002..2b8ed1dcd10 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html
index 9758d9e3dd5..92aec183aeb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html
index 5569f6dc19d..9d1e0536205 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html
index fcbcaf4e67d..3d7af2b6146 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -587,21 +587,21 @@
      483            6 :       miss_nxtstate   = IDLE;
      484            6 :       miss_state_en   = 1'b0;
      485            6 :       case (miss_state)
-     486        92228 :          IDLE: begin : idle
-     487        92228 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
-     488        92228 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
+     486        66092 :          IDLE: begin : idle
+     487        66092 :                   miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;
+     488        66092 :                   miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;
      489              :          end
-     490       184590 :          CRIT_BYP_OK: begin : crit_byp_ok
-     491       184590 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
-     492       184590 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
-     493       184590 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
-     494       184590 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
-     495       184590 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     496       184590 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     497       184590 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
-     498       184590 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
-     499       184590 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
-     500       184590 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
+     490       132274 :          CRIT_BYP_OK: begin : crit_byp_ok
+     491       132274 :                   miss_nxtstate =  (dec_tlu_force_halt ) ?                                                                             IDLE :
+     492       132274 :                                   ( ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff) ? IDLE :
+     493       132274 :                                   ( ic_byp_hit_f &  ~last_data_recieved_ff                                &  uncacheable_miss_ff) ? MISS_WAIT :
+     494       132274 :                                   (~ic_byp_hit_f &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       &  uncacheable_miss_ff) ? CRIT_WRD_RDY :
+     495       132274 :                                   (                                      (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     496       132274 :                                   ( ic_byp_hit_f  &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     497       132274 :                                   ( bus_ifu_wr_en_ff &  ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)       & ~ifu_bp_hit_taken_q_f   & ~uncacheable_miss_ff) ? STREAM :
+     498       132274 :                                   (~ic_byp_hit_f  &  ~exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & ~uncacheable_miss_ff) ? IDLE :
+     499       132274 :                                   ( (exu_flush_final | ifu_bp_hit_taken_q_f)  & ~(bus_ifu_wr_en_ff & last_beat)                      ) ? HIT_U_MISS : IDLE;
+     500       132274 :                   miss_state_en =  dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff)  ;
      501              :          end
      502            0 :          CRIT_WRD_RDY: begin : crit_wrd_rdy
      503            0 :                   miss_nxtstate =  IDLE ;
@@ -611,14 +611,14 @@
      507            0 :                   miss_nxtstate =  ((exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
      508            0 :                   miss_state_en =    exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      509              :          end
-     510       122726 :          MISS_WAIT: begin : miss_wait
-     511       122726 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
-     512       122726 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
+     510        87877 :          MISS_WAIT: begin : miss_wait
+     511        87877 :                   miss_nxtstate =  (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS  : IDLE ;
+     512        87877 :                   miss_state_en =   exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;
      513              :          end
-     514           52 :          HIT_U_MISS: begin : hit_u_miss
-     515           52 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
-     516           52 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
-     517           52 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
+     514           48 :          HIT_U_MISS: begin : hit_u_miss
+     515           48 :                   miss_nxtstate =  ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :
+     516           48 :                                    ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE  ;
+     517           48 :                   miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;
      518              :          end
      519            0 :          SCND_MISS: begin : scnd_miss
      520            0 :                   miss_nxtstate   = dec_tlu_force_halt ? IDLE  :
@@ -1046,10 +1046,10 @@
      942            6 :       perr_sb_write_status     = 1'b0;
      943              : 
      944            6 :     case (perr_state)
-     945       399600 :       ERR_IDLE: begin : err_idle
-     946       399600 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
-     947       399600 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
-     948       399600 :         perr_sb_write_status = perr_state_en;
+     945       286295 :       ERR_IDLE: begin : err_idle
+     946       286295 :         perr_nxtstate        = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
+     947       286295 :         perr_state_en        = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+     948       286295 :         perr_sb_write_status = perr_state_en;
      949              :       end
      950            0 :       IC_WFF: begin : icache_wff    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      951            0 :         perr_nxtstate       = ERR_IDLE;
@@ -1091,9 +1091,9 @@
      987            6 :       iccm_correction_state        = 1'b0;
      988              : 
      989            6 :       case (err_stop_state)
-     990       399600 :          ERR_STOP_IDLE: begin : err_stop_idle
-     991       399600 :                   err_stop_nxtstate         =  ERR_FETCH1;
-     992       399600 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
+     990       286295 :          ERR_STOP_IDLE: begin : err_stop_idle
+     991       286295 :                   err_stop_nxtstate         =  ERR_FETCH1;
+     992       286295 :                   err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
      993              :          end
      994            0 :          ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
      995            0 :                   err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
@@ -1547,8 +1547,8 @@
     1443            6 :   always_comb begin : way_status_out_mux
     1444            6 :       way_status[pt.ICACHE_STATUS_BITS-1:0] = '0 ;
     1445            6 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : status_mux_loop
-    1446       399600 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
-    1447       399600 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
+    1446       286295 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : mux_out
+    1447       286295 :          way_status[pt.ICACHE_STATUS_BITS-1:0] =  way_status_out[j];
     1448              :         end
     1449              :       end
     1450              :   end
@@ -1610,9 +1610,9 @@
     1506            6 :   always_comb begin : tag_valid_out_mux
     1507            6 :       ic_tag_valid_unq[pt.ICACHE_NUM_WAYS-1:0] = '0;
     1508            6 :       for (int j=0; j< pt.ICACHE_TAG_DEPTH; j++) begin : tag_valid_loop
-    1509       399600 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
-    1510       399600 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
-    1511       799200 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
+    1509       286295 :         if (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO)'(j)) begin : valid_out
+    1510       286295 :            for ( int k=0; k<pt.ICACHE_NUM_WAYS; k++) begin
+    1511       572590 :              ic_tag_valid_unq[k] |= ic_tag_valid_out[k][j];
     1512              :         end
     1513              :       end
     1514              :       end
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lib.sv.html
index 0f9e62b28c6..ba5ee6f7f01 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu.sv.html
index 278d8b338b3..2b2c0889c32 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html
index 2db27fb0e84..a6715b8cc0a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html
index 8a0aa4ced95..2e22cab5b7e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -445,15 +445,15 @@
      341              :    //------------------------------------------------------------------------------
      342              : 
      343              :    // Function to do 8 to 3 bit encoding
-     344      1198824 :    function automatic logic [2:0] f_Enc8to3;
+     344       858909 :    function automatic logic [2:0] f_Enc8to3;
      345              :       input logic [7:0] Dec_value;
      346              : 
      347              :       logic [2:0]       Enc_value;
-     348      1198824 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
-     349      1198824 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
-     350      1198824 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
+     348       858909 :       Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
+     349       858909 :       Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
+     350       858909 :       Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
      351              : 
-     352      1198824 :       return Enc_value[2:0];
+     352       858909 :       return Enc_value[2:0];
      353              :    endfunction // f_Enc8to3
      354              : 
      355              :    // Buffer hit logic for bus load forwarding
@@ -663,20 +663,20 @@
      559              : 
      560              :       // Find first write pointer
      561            6 :       for (int i=0; i<DEPTH; i++) begin
-     562           42 :          if (~found_wrptr0) begin
-     563           42 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     564           42 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     565           42 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     562           60 :          if (~found_wrptr0) begin
+     563           60 :             WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     564           60 :             found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     565           60 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      566              :          end
      567              :       end
      568              : 
      569              :       // Find second write pointer
      570            6 :       for (int i=0; i<DEPTH; i++) begin
-     571           60 :          if (~found_wrptr1) begin
-     572           60 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
-     573           60 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
-     574           60 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
-     575           60 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+     571           87 :          if (~found_wrptr1) begin
+     572           87 :             WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
+     573           87 :             found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i))                                               |
+     574           87 :                                                       (lsu_busreq_m & (WrPtr0_m == i))                                         |
+     575           87 :                                                       (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
      576              :          end
      577              :       end
      578              :    end
@@ -758,51 +758,51 @@
      654           24 :          buf_ldfwdtag_in[i]       = '0;
      655              : 
      656           24 :          case (buf_state[i])
-     657      1597000 :             IDLE: begin
-     658      1597000 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
-     659      1597000 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
-     660      1597000 :                                        (ibuf_drain_vld & (i == ibuf_tag));
-     661      1597000 :                      buf_wr_en[i]    = buf_state_en[i];
-     662      1597000 :                      buf_data_en[i]  = buf_state_en[i];
-     663      1597000 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
-     664      1597000 :                      buf_cmd_state_bus_en[i]  = '0;
+     657      1143784 :             IDLE: begin
+     658      1143784 :                      buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
+     659      1143784 :                      buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
+     660      1143784 :                                        (ibuf_drain_vld & (i == ibuf_tag));
+     661      1143784 :                      buf_wr_en[i]    = buf_state_en[i];
+     662      1143784 :                      buf_data_en[i]  = buf_state_en[i];
+     663      1143784 :                      buf_data_in[i]   = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
+     664      1143784 :                      buf_cmd_state_bus_en[i]  = '0;
      665              :             end
      666            0 :             START_WAIT: begin
      667            0 :                      buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
      668            0 :                      buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
      669            0 :                      buf_cmd_state_bus_en[i]  = '0;
      670              :             end
-     671         1000 :             CMD: begin
-     672         1000 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
-     673         1000 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
-     674         1000 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
-     675         1000 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     676         1000 :                      buf_ldfwd_in[i]          = 1'b1;
-     677         1000 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
-     678         1000 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
-     679         1000 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
-     680         1000 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
-     681         1000 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
+     671          999 :             CMD: begin
+     672          999 :                      buf_nxtstate[i]          = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
+     673          999 :                      buf_cmd_state_bus_en[i]  = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ;  // Just use the recently written obuf_valid
+     674          999 :                      buf_state_bus_en[i]      = buf_cmd_state_bus_en[i];
+     675          999 :                      buf_state_en[i]          = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     676          999 :                      buf_ldfwd_in[i]          = 1'b1;
+     677          999 :                      buf_ldfwd_en[i]          = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
+     678          999 :                      buf_ldfwdtag_in[i]       = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
+     679          999 :                      buf_data_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
+     680          999 :                      buf_error_en[i]          = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
+     681          999 :                      buf_data_in[i]           = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
      682              :             end
-     683          400 :             RESP: begin
-     684          400 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
-     685          400 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
-     686          400 :                                                            (buf_ldfwd[i] | any_done_wait_state |
-     687          400 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
-     688          400 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
-     689          400 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
-     690          400 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
-     691          400 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     692          400 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
-     693          400 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
-     694          400 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
-     695          400 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
+     683          397 :             RESP: begin
+     684          397 :                      buf_nxtstate[i]           = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE :    // Side-effect writes will be non-posted
+     685          397 :                                                       (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
+     686          397 :                                                            (buf_ldfwd[i] | any_done_wait_state |
+     687          397 :                                                             (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
+     688          397 :                                                              (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
+     689          397 :                      buf_resp_state_bus_en[i]  = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
+     690          397 :                                                  (bus_rsp_read  & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
+     691          397 :                                                                    (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     692          397 :                                                                    (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
+     693          397 :                      buf_state_bus_en[i]       = buf_resp_state_bus_en[i];
+     694          397 :                      buf_state_en[i]           = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+     695          397 :                      buf_data_en[i]            = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
      696              :                       // Need to capture the error for stores as well for AXI
-     697          400 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
-     698          400 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
-     699          400 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
-     700          400 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
-     701          400 :                      buf_cmd_state_bus_en[i]  = '0;
+     697          397 :                      buf_error_en[i]           = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error  & (bus_rsp_read_tag  == (pt.LSU_BUS_TAG)'(i))) |
+     698          397 :                                                                                          (bus_rsp_read_error  & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
+     699          397 :                                                                                          (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
+     700          397 :                      buf_data_in[i][31:0]      = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
+     701          397 :                      buf_cmd_state_bus_en[i]  = '0;
      702              :             end
      703            0 :             DONE_PARTIAL: begin   // Other part of dual load hasn't returned
      704            0 :                      buf_nxtstate[i]           = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html
index c4143e59c1c..95bab9e6298 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html
index b85367e34a6..616881419bb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html
index 8568d4e5b9e..529f05df9b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html
index f786ec29235..13281bf7a37 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html
index a7b1e6d3d1e..a731c6bedb8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html
index 210ca509765..7d4f81a9d61 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html
index fb7bcec35b2..1e8eac04ee9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html
index 9ba99ad80fd..4598b31fda9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem.sv.html
index 8fe89e174f5..dcb4d72b97a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem_if.sv.html
index 4e26a67772a..fcfad707e33 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html
index ebcde0f2af4..7d5ed6412a1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -601,13 +601,13 @@
      497            6 :          intpriority_rd_out =  '0 ;
      498            6 :          gw_config_rd_out =  '0 ;
      499            6 :          for (int i=0; i<pt.PIC_TOTAL_INT_PLUS1; i++) begin
-     500     12787200 :               if (intenable_reg_re[i]) begin
+     500      9161440 :               if (intenable_reg_re[i]) begin
      501            0 :                intenable_rd_out    =  intenable_reg[i]  ;
      502              :               end
-     503     12787200 :               if (intpriority_reg_re[i]) begin
+     503      9161440 :               if (intpriority_reg_re[i]) begin
      504            0 :                intpriority_rd_out  =  intpriority_reg[i] ;
      505              :               end
-     506     12787200 :               if (gw_config_reg_re[i]) begin
+     506      9161440 :               if (gw_config_reg_re[i]) begin
      507            0 :                gw_config_rd_out  =  gw_config_reg[i] ;
      508              :               end
      509              :          end
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pmp.sv.html
index 46adfe2d7e6..2bfeb560a33 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -79,11 +79,11 @@
     
         Branch
     
-    
-        49.0%
+    
+        39.2%
     
     
-        25
+        20
     
     
         51
@@ -234,13 +234,13 @@
      130              : 
      131              :   // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
      132              :   // behaviour before Smepmp was added.
-     133     19181376 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
+     133     13742736 :   function automatic logic orig_perm_check(logic pmp_cfg_lock,
      134              :                                            logic priv_mode,
      135              :                                            logic permission_check);
      136              :     // For M-mode, any region which matches with the L-bit clear, or with sufficient
      137              :     // access permissions will be allowed.
      138              :     // For other modes, the lock bit doesn't matter
-     139     19181376 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
+     139     13742736 :     return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);
      140              :   endfunction
      141              : 
      142              :   // Access fault determination / prioritization
@@ -270,9 +270,9 @@
      166              :     // PMP entries are statically prioritized, from 0 to N-1
      167              :     // The lowest-numbered PMP entry which matches an address determines accessibility
      168           18 :     for (int r = 0; r < pt.PMP_ENTRIES; r++) begin
-     169       832962 :       if (!matched && match_all[r]) begin
-     170       832962 :         access_fail = ~final_perm_check[r];
-     171       832962 :         matched = 1'b1;
+     169      4727505 :       if (!matched && match_all[r]) begin
+     170       416481 :         access_fail = ~final_perm_check[r];
+     171       416481 :         matched = 1'b1;
      172              :       end
      173              :     end
      174           18 :     return access_fail;
@@ -348,12 +348,12 @@
      244          288 :       always_comb begin
      245          288 :         region_match_all[c][r] = 1'b0;
      246          288 :         unique case (pmp_pmpcfg[r].mode)
-     247     17984664 :           OFF:     region_match_all[c][r] = 1'b0;
+     247     13144092 :           OFF:     region_match_all[c][r] = 1'b0;
      248            0 :           NA4:     region_match_all[c][r] = region_match_eq[c][r];
      249            0 :           NAPOT:   region_match_all[c][r] = region_match_eq[c][r];
-     250      1196136 :           TOR: begin
-     251      1196136 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
-     252      1196136 :                                      region_match_lt[c][r];
+     250       598068 :           TOR: begin
+     251       598068 :             region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
+     252       598068 :                                      region_match_lt[c][r];
      253              :           end
      254            0 :           default: region_match_all[c][r] = 1'b0;
      255              :         endcase
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer.sv.html
index dfa5687074c..fcec6c91a18 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html
index 61023088deb..ef32b5b48f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_mem_lib.sv.html
index 583f9c8c50e..3a3d2841d2f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -212,7 +212,7 @@
      108              : `EL2_RAM(32768, 39)
      109              : `EL2_RAM(16384, 39)
      110              : `EL2_RAM(8192, 39)
-     111      6393572 : `EL2_RAM(4096, 39)
+     111      4580692 : `EL2_RAM(4096, 39)
      112              : `EL2_RAM(3072, 39)
      113              : `EL2_RAM(2048, 39)
      114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
@@ -276,7 +276,7 @@
      172              : `EL2_RAM_BE(4096, 142)
      173              : `EL2_RAM_BE(2048, 142)
      174              : `EL2_RAM_BE(1024, 142)
-     175      1598440 : `EL2_RAM_BE(512, 142)
+     175      1145220 : `EL2_RAM_BE(512, 142)
      176              : `EL2_RAM_BE(256, 142)
      177              : `EL2_RAM_BE(128, 142)
      178              : `EL2_RAM_BE(64, 142)
@@ -309,7 +309,7 @@
      205              : `EL2_RAM_BE(1024, 52)
      206              : `EL2_RAM_BE(512, 52)
      207              : `EL2_RAM_BE(256, 52)
-     208       799220 : `EL2_RAM_BE(128, 52)
+     208       572610 : `EL2_RAM_BE(128, 52)
      209              : `EL2_RAM_BE(64, 52)
      210              : `EL2_RAM_BE(32, 52)
      211              : `EL2_RAM_BE(4096, 104)
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_rvjtag_tap.v.html
index 18eb68b68c0..165fbaafd07 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_arithmetic_basic_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index.html
index 70182a4dc62..bf952fdae53 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html
index 99a38ebcb7b..9b0855d33d5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index 69856694950..3b0a5af3333 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dec.html
index 9b3240d312b..5324b3bfbed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dmi.html
index aaf314740d3..5064fee665b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_exu.html
index 08601ba5894..7695e375282 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_ifu.html
index ed185739282..352e7abc9c6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_include.html
index 28c792cb9a8..5eeb917a6c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lib.html
index e42867cc91e..f307f9c7a5e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lsu.html
index 86bf81f4cec..1129f65bdb2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_beh_lib.sv.html
index 926770937cd..bd4573a0779 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_jtag_to_core_sync.v.html
index 12c25a9fe07..c4e8f4eeb47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_mux.v.html
index 056b3d4a9a6..637f0a9930e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_wrapper.v.html
index 3af001b568c..83f17544b24 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dbg.sv.html
index 6d939a4c72b..109e0e2046a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec.sv.html
index 6d4a8080d81..88dc64a9f2a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_csr_equ_m.svh.html
index 57edc9a45d0..bb032060d57 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_decode_ctl.sv.html
index 749b7b4e35f..d3bcf6f37e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html
index fde20281f3e..6434d8533de 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html
index 17f5ed182f2..5f89cfc2540 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html
index 193008f856a..0d71862d86e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html
index d221ab8cedc..e3761b134a0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html
index 0a02d706e15..67cc9f5c216 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html
index bffe2a77898..50e662a24c4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html
index 5eaf2ee008c..d1024eff569 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html
index d30fe28050f..11eee97bf97 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html
index a967745166a..ee86f103550 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html
index f3abb1defbc..a6662c0d157 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html
index 1e90649990c..3e4694418f8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html
index 10c7c8d06b7..3de3938f977 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html
index 7478f6f26e8..264ff50305a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html
index 2ce3de77199..d55a71ade8a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html
index c156baa12db..0d83d5f669f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html
index 1ef0675ee57..b9576a57ed8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html
index 272a909cb99..b08783ae844 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html
index f13ca02b789..066a110904f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html
index 7253304c8f5..8b9f944b5e5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html
index 3875c27edde..3699b7c711c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html
index 004179d11b1..e66d8cf0eee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html
index bb505e8ed3e..38797c366e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html
index 8aff2ca153b..d08c6302edd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html
index de015912d5a..0f28a641793 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 879e94dd6ff..f282bcb97b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html
index 569ccd999b8..8cbdea1ad66 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_ecc.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 81183bd3d5d..ca5bd03d096 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_mem_if.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_veer.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html
index fb2b11ca5f1..be59346732f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html
index 40fa8506146..72f91e0ffb8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html
index 3d0d99d382b..477edd72af2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index.html
index 7b8e98889b0..85816bc3958 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html
index 44597f31c73..6ab51496f72 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index 91be113e120..de210c1ce03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html
index b82c49881a8..e444e607c6a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html
index 56d7fa201fc..3df8396cadf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html
index 71e93b4d3bb..4f6c3ab7308 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html
index b98a7a6ad3a..420eccbcf7e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html
index c578f4d3cf6..c213f03afe6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html
index 6f11c188ddb..8a3519b89de 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html
index cf6277c2493..5c946c40783 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_beh_lib.sv.html
index 701161aa1e0..4b922d9fc3e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html
index 45241908f7a..88480c35026 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_mux.v.html
index 8fdf22a4d03..8dbaeb11a2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html
index 0d0f97e1428..bec340a8477 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html
index 02ff6b46b4b..58da43061d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec.sv.html
index 4007b3c4571..d28ddac2a13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_m.svh.html
index 8237d41f492..de47f4f3f1c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html
index 095501377ef..e28e5163542 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html
index fe87d7387c9..b9c1b148eea 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html
index 25c000e8f05..2e388cf995b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html
index 34eefdd9673..f842ed4ee47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html
index 92752d43f0b..8b94f541eda 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html
index b204a89d5c2..267b6bb0a47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html
index 82c26023835..3ab6b58949c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu.sv.html
index 2c792ee5239..ce1e16c9425 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html
index 0223d1eef4d..3bd8a0ec4b9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html
index 57f1c3a1845..60b727d628e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html
index baaf2098c7b..3ad0d36b1bd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html
index 7d8f2dda7c8..4766ed7543d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html
index 8f8c5b54551..2c51d289f5e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html
index 7134d7b10cd..c677859c888 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html
index 6c846803c9d..47184a4cd93 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html
index 33104459478..1a1ab1265a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html
index 63c0a889013..e57fe9a4c4b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html
index b5430afd2e1..0fe3213d93b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html
index 6943ab41e4d..37cff52948f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lib.sv.html
index 9458e6933d1..8ffe449f3ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html
index af9eb2dba6f..7e0056a0a75 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html
index 463ae2398c5..a1ade76ad9e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html
index f13fd1cb97f..7c6457ac4e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html
index c39fc76ca03..cccc0def7cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html
index 5bfc98ef54e..845f0473258 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 4f9f42a5d71..38f6c90f7d5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html
index a808fed262c..e7812f8ec49 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html
index 40359ce8002..7b0c86d5620 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 37eee7f3949..2c77e727246 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html
index 63357b64b7d..ac344956d5d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html
index 0a9b6f3b8ee..dfba56635d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem.sv.html
index b79bf691900..2a96cdc591d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html
index ee985136146..88bfb60ac89 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html
index f8248b2b38c..4e0d079d4e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html
index efb027bcd23..b0df7518e47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer.sv.html
index 3314f0f60b2..03bdcb18467 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html
index 843f7bd0a0d..8b69145b6b5 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_mem_lib.sv.html
index 914b3e33f43..329fe405128 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html
index 984eb2addbe..e2e640a5424 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index.html
index 3a30d721653..f16132d829a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html
index 7c72e3182c5..029a8618a87 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html
index cdfa0246987..3977fcccffd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html
index b345d946318..70c196e8c81 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html
index 3393941aa27..4c2e70aeb15 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html
index 9a8bdc0112e..2208d3d878b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html
index bb8621a075d..f6635b21acf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html
index 44ba3012840..8063aa7c7d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html
index 0b8c0411459..04e935e14e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html
index 63857782032..752bbbe228b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_beh_lib.sv.html
index 3b63f89a2d3..1c1bd0090a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html
index c0656653fa9..f761d608338 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_mux.v.html
index 8418b7a993a..62b12d20998 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html
index f64d7b23197..5dd7185fd33 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html
index 749aeb6f41d..12f0d25d8ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec.sv.html
index 3fb160fcf20..d6514fc9221 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_m.svh.html
index de4d0f4bf1b..10b6f90feed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html
index 7bea1f016ec..f017e242a96 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html
index a4b57ecf71b..25b7ca8b256 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html
index 3f95a1977df..46b0231400e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html
index fbbaa9fd1d8..b73a66625b9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html
index cf73cc683d0..7ed192bb570 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html
index ab86b063272..bc8822e3ce3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html
index 3ca9dfe5f09..ce05f8a4caa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu.sv.html
index 9e341ff4fce..0439dbe3cdc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html
index dd9af5964f9..eccc669e9e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html
index bc026ed34fc..4a2a0e78747 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html
index 95557b8bb8e..e7a5a289679 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html
index ab2e4f9f689..a6cf9b1746e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html
index 890501bf509..1ed7bfdebc4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html
index bacfc94c68d..9d1fcd908d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html
index 0d3167c9019..8f5ee62bf2f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html
index dec15b57598..12df45ff64f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html
index 5e1727a9346..108e64a375b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html
index 7962179f61d..6dc5e02ff86 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html
index e993505280f..dcae7218ea4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lib.sv.html
index 43985730247..b39a1deb6e3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html
index ccb2891fdfa..eda2994da5c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html
index 774f9a455fb..3d6211fd105 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html
index 105f506ce06..53e146279d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html
index ddefc597426..eef91504bbc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html
index 95413a2a08a..9c190080364 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html
index e2432495825..e387762816b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html
index 0df1f343769..5cbfc153c17 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html
index 195771a926e..4d90503fde6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html
index 1c567f80fc7..7ab8d33412a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html
index 2651ea45c57..d72555043b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html
index 7fbc4bf51d4..ebe177d32b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem.sv.html
index a390debd131..14d332f6458 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html
index d12996b1c08..9eae5bf2f52 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html
index e719033a39a..472043bf783 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html
index f1a4f5a8171..e4f2168c7c8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer.sv.html
index 29c479808e9..993b0315efe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html
index 80659f6edf1..4d7237a71dc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_mem_lib.sv.html
index 9a79e53a746..49180331a4a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html
index 90cf1cc3767..5625450c636 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index.html
index 3eebc846d27..a9577534f79 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design.html
index 00d6a4dbf48..161f68e1a2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html
index 343c8eed81e..d7c17b5f424 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html
index 9aa1fed590c..1dcf775aefd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html
index 8bdc49d2f84..1735d119b18 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html
index f0fc111e2ed..d5eb07b2c8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html
index 794e3ffabd7..df669b64f86 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html
index 225da061b26..68a3b6d3294 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html
index df38a8bc2fc..f6653b50117 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html
index 7b552d0d712..6251fa23e24 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_beh_lib.sv.html
index 7d15fdfc699..07430e13858 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html
index 0acdb379c44..1aa1564def6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_mux.v.html
index 47ea2832a76..8e6889bb1d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_wrapper.v.html
index 9db87136830..540323331b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dbg.sv.html
index 57718389649..db1afd7e0dd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec.sv.html
index 79988d90d2d..ac013437afd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_csr_equ_m.svh.html
index 7b77b86062d..c8aaca2aaeb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html
index a7005c6fa83..6ad1446cbce 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html
index 22bf7015d29..d8388c17539 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html
index eaef55dd095..9d444cf3494 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html
index 09f29fd2179..37b112488ce 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html
index 3f03fc00f82..7bcc0d3dc19 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_trigger.sv.html
index 08bc251f6d3..22055d3766d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dma_ctrl.sv.html
index 07c1c45f68f..45f66feed42 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu.sv.html
index 1d1cbba5e6e..56a3e215c84 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html
index dedea329b4a..c95228bc44a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_div_ctl.sv.html
index 9d027c8a3da..c1620c01b58 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html
index 9ae4ea7943f..4d916fbe10d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu.sv.html
index d41f2507516..da443b87ec8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html
index 0af276c0371..ad80bd5c252 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html
index fe43f2aae61..9fe14f6225a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html
index 1bc6bd7d7ad..567b037946c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html
index 2477e8eccbd..5e7c4e80701 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html
index 737740fc048..a05fc22d191 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html
index f0e9c28d9d8..6475ce8b9f6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html
index 6c6d97ee1af..c01e58261ce 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lib.sv.html
index 670b8477ad4..534a109f95c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu.sv.html
index 047dd59234f..45f699e7020 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html
index 32f891f70ed..9353059a608 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html
index 2382e4d9187..f32db064dbc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html
index feff421bfbd..8e89d6cabbb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html
index 3670ce69750..091e3842f5f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html
index e8ebc1063be..57e3fbc305c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html
index cc136a401da..768a6089e3c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_ecc.sv.html
index 9dd8572a1b8..5f59a16b30b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html
index 9f6ce2bfec2..af58072c7cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_stbuf.sv.html
index fd6348bfa61..14d5ce7f869 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_trigger.sv.html
index b78d150270f..ee44a9d63ea 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem.sv.html
index 345eaafbb86..9874b556744 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem_if.sv.html
index bb66d0a5ef1..064ffec695e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pic_ctrl.sv.html
index 9160145e4fa..1f9a8d43ccf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pmp.sv.html
index c3fcf0eecbb..af1f177232a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer.sv.html
index d2316657256..056e45117ed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer_wrapper.sv.html
index 050308b5494..b0a57464417 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_mem_lib.sv.html
index 9d34703bf0b..c5cc5ef7bfd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_rvjtag_tap.v.html
index 5c67628737f..016b4284655 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_ebreak_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index.html
index 13a4852388d..37011684f76 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html
index 45de5d94d55..95c65cd8d75 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html
index d543ee23603..e92f3ad1e75 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html
index dfb698b0f51..207402cb3b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html
index 256470b06c5..ded17907f72 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html
index c5e2fd86a67..d5864339f3e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html
index afbf7360be1..f7f22d67ee5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html
index 1437d589bbe..9be919f6595 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html
index 283193ff9ba..8db66897b19 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html
index a19b9e1b30e..75f2b064ed4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_beh_lib.sv.html
index d0fc7c2a5c7..22c02106bbb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html
index 6842f874b21..ed2117e70b7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_mux.v.html
index cc71a638041..4476eab7fc3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_wrapper.v.html
index 3fc5aab1ab7..5106e5920a6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dbg.sv.html
index 4e3f9d6972b..028f4df7e27 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec.sv.html
index 448715d03e4..81bce6f2637 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_csr_equ_m.svh.html
index 765b92f768d..c2e789611ca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html
index 706a15ab15d..f3bc2f2b14e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html
index 4566dfa9af3..8ced2702255 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html
index c1bb5c547fe..bde2a35eee2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html
index 4ec06f68d5e..652181c8eca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html
index 44658fe6b47..9a52affd1d8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_trigger.sv.html
index 00a1a752c85..9919b750a2d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html
index 85fe0e1b736..9322a2c50e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu.sv.html
index 88d376c8027..5b0de49777b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html
index 997b173f08d..89155fc21a7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html
index 1479334c99a..0bcaf4e78fd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html
index 1640a81c2a5..14e5d903005 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu.sv.html
index 9ae96574558..807b2341508 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html
index 4a45190d059..0a1d94f3114 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html
index 7b3ba285d62..e74a3e7d0b4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html
index a85b3fc80a8..27bbb4242f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html
index a8028c6fc58..4f4bca92b7e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html
index 8fd9a87baca..e4aec2f755b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html
index 12978716e79..60a8f1cd32d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html
index ce3e1ae3a91..c1490587789 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lib.sv.html
index d045a7d7ad7..77800682ae3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu.sv.html
index f237660c944..c85d4dfd601 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html
index a2147bafb9e..b4ca864105a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html
index 9f4712bf06c..dfcf9b5f929 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html
index 9592fc10936..80675827c60 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html
index cd276f9c476..f14397939f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html
index 4dd1966f13e..14d36c8f35b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html
index f1da3d74143..2c58bf08c52 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html
index bd7141b47b5..ef241950871 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html
index da84108e6cd..e4a47662218 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html
index bbe3e03a364..6796337fb5e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html
index 451c8982f0a..32600fda1a3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem.sv.html
index 4a97c4ca538..320a1cc707d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem_if.sv.html
index 2e64406dfcf..65c8b7523c7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html
index 0dcf6a61322..8eb61561feb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pmp.sv.html
index 509a56ec627..76bb8a1578c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer.sv.html
index cfe6b787c7c..493b686dba1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html
index 32ca9d21088..b0171b18537 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_mem_lib.sv.html
index 8dfff092509..e5f90260aae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_rvjtag_tap.v.html
index 70df98e42a0..3d32f463f6f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_full_interrupt_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index.html
index 298bfecd047..50b77b4acf2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html
index 385857717be..854f5c92335 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index 282e8fa9ba5..ece64f07d11 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html
index e4c6244c5fe..e87c1a830ca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index 42984671ca6..77d28c5be62 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html
index 0c369d76c97..49afd44d02f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index 898edd3136e..b948b9aef1d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html
index a45a9d8e93c..48184824f8c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html
index 10117a4ef34..7286fa2af36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index 85796678dad..ee0153d1d88 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_beh_lib.sv.html
index 4912404944f..23d5abfdabb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html
index 5a171eee924..800d18f4774 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_mux.v.html
index 554c0c3b59d..dd7168e343e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_wrapper.v.html
index 43835c4fddc..ae9bc8736be 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dbg.sv.html
index 0853db42902..b1bc6a7119f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec.sv.html
index 0dfdbbc6317..1955e3c57d4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_csr_equ_m.svh.html
index 229065743b6..8b79f8d0720 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html
index 6c477304377..9eea03cba4b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html
index b34eb173439..729e15dcca8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html
index 3cdb79de421..490885cd326 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html
index d0a0219087c..112adbafe9a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html
index 23be24ce7e1..235b032c092 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_trigger.sv.html
index 010e5aba994..6ce34c7fc51 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dma_ctrl.sv.html
index 01ef37b3f5e..2959820ef7e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu.sv.html
index 13b4201a35f..750e4b9185e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html
index 12ea73c0186..280d418297b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html
index a244574334d..8d9f0d373e4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html
index e29a65c0234..b53f2fe3c21 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu.sv.html
index 70164fcad13..65073640322 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html
index 60636488d40..82af1ad40bf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html
index 47ed0a5f5a1..944b00f3a32 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html
index 6465d4cce15..d46d3809d5b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html
index 18079712588..2ddbd226c4a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html
index d9c4fc9a788..eb78839f83c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html
index 00bbfbede72..a40ab379675 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html
index e3e1746bbad..420ffe3f1bf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lib.sv.html
index c9be18fe91b..f4c8c3228a5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu.sv.html
index c9c127cec53..e4269bc60f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html
index c01351b307a..6c61c889983 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html
index 78651fc64a5..d6c7a88b95d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html
index 466bae68bf9..63f88be8140 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html
index adbd7ed6bd7..6e6d267964b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html
index db3a047079a..6843c6cbc4d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html
index 95dc7fba700..49b55c626cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_ecc.sv.html
index 048c2b0b128..1f50f56e24f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html
index 847308c9f7f..304a11873b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html
index 2593e8541fd..9759785adec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_trigger.sv.html
index fbfaef2f179..4006513dd08 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem.sv.html
index c40008b9ed9..4c05ec84263 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem_if.sv.html
index b728cda506d..b3d766ebcae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pic_ctrl.sv.html
index 67d629ea225..e73b6bd5820 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pmp.sv.html
index 3785952c09c..3e72ddf439c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer.sv.html
index 4202f3c260c..8e89bfd7cb1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer_wrapper.sv.html
index f176c36a0f0..0b570e2d0c5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_mem_lib.sv.html
index e63fa3d2ea4..a59b694459e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_rvjtag_tap.v.html
index 412283e3984..bb659e7306b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_hint_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index.html
index d28131157c6..3b7bc7434f8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html
index 1803a149da7..9bb12493071 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index c421f041f82..2107334f8c5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html
index f22d6762530..3263aa8ade1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index 09bf9e57ec6..4d599988374 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html
index 300f85ce456..d1e35254cd6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index 31591b050fd..ede438c631a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html
index 4c2972422bd..342522aab6f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html
index 94bc6014035..6e2ea1b78f4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index e0ba261c2c5..c79792a8e5a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_beh_lib.sv.html
index 256ccab4075..e6bbc298df1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html
index 42868202629..dc53daed5fa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_mux.v.html
index c30618699e9..5c38ad6f38d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_wrapper.v.html
index 594fb2e0979..cb544763891 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dbg.sv.html
index 181c5f84152..587445a840e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec.sv.html
index 91e6f906704..1e0e7a77393 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_csr_equ_m.svh.html
index 3cd915eb76b..ba4ed3ab60d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html
index 402c44da26b..df5b5ff0451 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html
index 3ddc80929c3..b36da590385 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html
index 05e19ff1a9c..b737bb60fbc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html
index d8269aedb85..0fa7124b03c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html
index ce79b626fcf..059a076b875 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_trigger.sv.html
index d7ecb511b3e..6487ba5f1f8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html
index ab3c7d6341f..6ae1cbcb9b4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu.sv.html
index 893c91d779e..9d7574b4e53 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html
index 4315d984b88..5a3c72852de 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html
index 0825a027e49..101fee9ea03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html
index 6ddf574e19a..29c928baa20 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu.sv.html
index edfd393df9a..a6c5293c86d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html
index 6e7c48aecb8..73f8d8f0b17 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html
index e10c0ca57b5..f714271eb07 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html
index 20ccb3733eb..72df46a44fb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html
index c96e2b59f31..a4fb12d4c7f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html
index 28afbc785d4..907b3efb381 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html
index 75ffbdc1f17..12526874b69 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html
index 39caaee604b..77aa266b2d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lib.sv.html
index 9d48f9c8428..ca2b433081a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu.sv.html
index 6129d66e551..96cbec04f17 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html
index c6679ad1e95..37391d88f61 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html
index b9c5b32fe27..21875bac54f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html
index a859815656e..d513b93b276 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html
index 9ab5f1916fe..409ea07ee28 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html
index fe71873b27d..37de5a8b111 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html
index 95fbe43a8c8..67e1c3ffc44 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html
index aaf95abf70a..ac9409ba215 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html
index db0855961e8..9cdbe932eef 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html
index 9140b5e6692..e1f0446f40b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html
index f6eac2b8d0b..9220beea954 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem.sv.html
index 09591bcff52..67829a475a1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem_if.sv.html
index 775b20bd236..ca8dc66e5ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html
index cf69dc171ca..de084d4feb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pmp.sv.html
index b6d8ceac6af..078b16b86e6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer.sv.html
index ff9be714f50..95ad934c52e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html
index b2866adf687..22d6923c7a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_mem_lib.sv.html
index 78799deb83e..d8e5cb3f26d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_rvjtag_tap.v.html
index 5af02723a44..decb1526f05 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_illegal_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index.html
index 5fa5c5c03a7..55075282efa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html
index 8981959d530..5a5480b3e4c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html
index b116fcfa217..32f56a59489 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html
index bfec8d4a358..69adb0db7b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html
index 2de02e43457..4f36528a7c6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html
index 7c9a724c9bc..ab98cc48426 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html
index e29aecaeb9c..17a131c3d0d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html
index ec0357d9632..9755bcbefc8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html
index a96c4325acb..2df25d7e682 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html
index 91fc622d6cf..14d22eb56a7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_beh_lib.sv.html
index e457dfde380..fb0f5bbf17a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html
index 4e2005ff16f..87aaa86803c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_mux.v.html
index 72cfe8db5d7..d04ddf56408 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_wrapper.v.html
index 2bcb90094e1..5bcdd7eab25 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dbg.sv.html
index 47246bc1baf..332bcb5e069 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec.sv.html
index 8490e2948d2..7f1d28ccaea 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_csr_equ_m.svh.html
index 468c6ddd425..6ed1398d3bb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html
index a2e14cafc9c..1b8129d224a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html
index d458f2223e8..07d2e1e509c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html
index de104f7b35b..58f693786ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html
index 39a031d4e19..0e9c9c6dc9f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html
index d8533219117..234ff3c3928 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_trigger.sv.html
index 7025ac7950a..4e44cd3f0fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dma_ctrl.sv.html
index 15d9f58a0ad..e6a8ebe2dfe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu.sv.html
index 29ecb8ade61..7ca196d6cd8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html
index 5d4ff766265..6277f64de45 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html
index 2afbfa4111e..159a84aa2ac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html
index 58a04ea1fd2..7175e1b745a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu.sv.html
index fe70377cf24..b6cec895779 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html
index a62c14127b8..70c8abf2763 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html
index 20ca86a6d2c..706a0fadefb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html
index 898daf63d2a..cb1d8a5d4a3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html
index 968b5232437..fc667dc448e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html
index 0ff20c8614f..eba15d17128 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html
index 2fd6a60dd54..840b70be805 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html
index 15bc3d94173..87818c8c691 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lib.sv.html
index 6b561a0eb57..acc202705d4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu.sv.html
index 0404bd8e3e2..745d89d6d67 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html
index 7b0a40d68e6..48ba7adc0ac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html
index c96e8497cf3..99386fd28e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html
index 1159154f269..964dd6a7797 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html
index 47a42d57986..1c5059017e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html
index 56da9f52af3..97a7c8cd459 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html
index 83c0815cfaa..338d6839c24 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_ecc.sv.html
index b30d80e90e2..b1e6ed45c72 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html
index 34daa81fb86..9e02879ed3b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html
index 80bbdb20f70..7cf0fa11ce1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_trigger.sv.html
index 0961a83f865..f82502034f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem.sv.html
index 29ef32a261b..4773fa4aa99 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem_if.sv.html
index 61dde53956f..1de9fb9b6ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pic_ctrl.sv.html
index 885dfcc9b92..b42f55ec385 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pmp.sv.html
index e73fa146bd3..34f11b9f2ac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer.sv.html
index 19e4518b907..8f20c769ba4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer_wrapper.sv.html
index 72aeade41c9..68d01bac86f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_mem_lib.sv.html
index 05d978d4c10..40a1b74beb0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_rvjtag_tap.v.html
index 56f9750ccc0..e3a2fc913c9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_jump_stress_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index.html
index 6b7e33531da..1caf4da6af9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design.html
index e71be4e20c3..f2db34e0fd7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html
index 03278e11ba8..c13fabde61f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html
index 2f59cd48234..ba466748dac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html
index c3712954a5a..d88d69b54ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html
index 5b5ba463b16..88efcc2a198 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html
index 616bdd9d2a4..93c9c99edda 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_include.html
index 80cf316cc76..0581c1e6983 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html
index 822a5584483..db6b5a4f267 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html
index 57c36ae2996..140f0729693 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_beh_lib.sv.html
index 7b4b92ce5c3..797b4ba56c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_jtag_to_core_sync.v.html
index 0a870cc2e19..91653195fac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_mux.v.html
index 21109de8f0b..de60bc11c8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_wrapper.v.html
index 3296494c9ea..b8cc2ea2fb1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dbg.sv.html
index abfef6e31f7..54bc758776b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec.sv.html
index 23dd1e6e15e..e5ab127b60c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_csr_equ_m.svh.html
index f6fc67a71a7..9e767db9f0f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_decode_ctl.sv.html
index efc1dfcfc24..12445d802b6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_gpr_ctl.sv.html
index c1ef90fbcef..2be4ac34641 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_ib_ctl.sv.html
index 482d5914f62..4815fefaf1d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_pmp_ctl.sv.html
index 39591a173e1..254a5cb6ba0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_tlu_ctl.sv.html
index 3c2900b0b1c..c6bf99ca411 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_trigger.sv.html
index 8a44c3e55a0..9f78addeee6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dma_ctrl.sv.html
index 89f77a8e831..10fb9f6770c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu.sv.html
index f17d5b7fb90..0ef00f17409 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_alu_ctl.sv.html
index b28e5a3cf45..6571a7b1421 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_div_ctl.sv.html
index 98ead76d5b5..abe2df5d651 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_mul_ctl.sv.html
index 7847151b478..29e92e1601a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu.sv.html
index 1299612de2d..e23dd974f24 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_aln_ctl.sv.html
index 56e815fb983..6dbf760ec4b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_bp_ctl.sv.html
index 0f713a5d740..acf57dec55e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_compress_ctl.sv.html
index e93861b8718..69b347da3a1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ic_mem.sv.html
index 7c6740deb51..cebfb0e9fc3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_iccm_mem.sv.html
index e61a14a25e0..2959904ae65 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html
index 6f0be52972a..289b8274f66 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_mem_ctl.sv.html
index f20cc8a509c..3e2b1cd7280 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lib.sv.html
index b04e9a42ba8..2a5ace3fadf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu.sv.html
index 47748c13d32..172cde88f76 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_addrcheck.sv.html
index 9472724ed32..5238e022cf1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_buffer.sv.html
index a6852ed7ccb..185c638b9ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_intf.sv.html
index ef8c9f361a1..8b852f0df67 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_clkdomain.sv.html
index 108d1e3719e..365aa6bb576 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html
index 83e0ac4bbb1..a565144244d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_mem.sv.html
index 2c0efaf441a..75988d37653 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_ecc.sv.html
index 1cc2646a4f8..a98f4f17b9c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html
index 1ba6af66a11..da8877d43d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_stbuf.sv.html
index d80202c5f21..6e0a55fef2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_trigger.sv.html
index 61c3822025f..50ac890ff1d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem.sv.html
index 492774fc379..f0cbd3703f1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem_if.sv.html
index c68274a4963..58574988663 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pic_ctrl.sv.html
index 199eefbde9e..82bb99df505 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pmp.sv.html
index 643471b324d..1f978f530b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer.sv.html
index faea8c5c4a4..1b797a08f46 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer_wrapper.sv.html
index 5927eaffde6..c1be9f5e77b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_mem_lib.sv.html
index 3bcc67ab45a..c1e1641a500 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_rvjtag_tap.v.html
index de8199172cb..e278123d36b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_loop_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index.html
index 85bd7fa1696..8d80279a586 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html
index e7e2c268ade..e8ac5388ba5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html
index 5defa5d76a2..2bce25982ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html
index 74be4eb7d18..9b1c603a817 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html
index 813dddf7ab8..cd35bce1dcd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html
index 2a64ba0ef6c..65fb7ee77fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html
index 675ad17f732..aa89a3e063d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html
index 9d4e62edeee..be3cf7a797e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html
index 417d80d5cb2..7cd12a972b6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html
index 0527ce0bbbe..c8934570a60 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_beh_lib.sv.html
index c44ec8d17b2..781561e302f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html
index d5f1bf8ce70..5b692866f74 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_mux.v.html
index 05f0d48ef86..5ef2ac8c8ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_wrapper.v.html
index 7639a683fde..41723faa401 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dbg.sv.html
index 1fb001ba4ba..048b9248a5b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec.sv.html
index 4594e9fb73b..4611889b5f9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_csr_equ_m.svh.html
index d00bd0eb84f..0df890f5e95 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html
index 832ec0562ed..46d7d755483 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html
index 04eeaa83a18..37e39bd4981 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html
index 6963dbd51c0..4e6ec4f6d8d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html
index 9f7bfd42104..037ac8e2f7d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html
index c6490f3282d..06a3ab51b6e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_trigger.sv.html
index 0cccc36fe2e..077ad9c2f55 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html
index c2c437c8593..2bff6fcb0eb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu.sv.html
index aa92bc4af94..06a93b1d15b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html
index f2fdc11e6d9..51c95e1f305 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html
index 94d5a782ed7..52e630c29e3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html
index d0b6dc1b0a0..f2bf8520e7c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu.sv.html
index 4dcd6d6ee6c..894c804e867 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html
index 4642c079e16..f06144f1236 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html
index a85a64d0e54..71f95216df6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html
index fdd8202af93..86ead1773ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html
index 9927c9fac8a..412f94fb6fc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html
index 59bb0f0f875..c9303e292ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html
index 22ef498e37d..637458890fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html
index 06cc48f0187..e8d3a6617b4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lib.sv.html
index 378d10bc257..9db59952fee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu.sv.html
index e61e487890e..ca8ad56120a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html
index ec2965bcfe0..9490cbb6c86 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html
index addb6c258eb..6fe3bf1d34a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html
index 74888a6ed51..d9dda0fc29e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html
index 20d375d6399..d959fdf769f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html
index efe77200f81..daf918291e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html
index 6d1f737cfcd..bb49066bd4d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html
index b0bd012800d..0fa5dbc562b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html
index f8fffa2099a..4b2656212a6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html
index 7fd06c203f9..6c862811f80 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html
index e63673c77b0..0771af384ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem.sv.html
index 972643d6732..d8020001030 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem_if.sv.html
index e76d8107e8b..e67876d4581 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html
index 5fdc9bf5861..19b516a4e8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pmp.sv.html
index 5cb1f5f80c8..2d6e44514b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer.sv.html
index 098b01cec25..695aec69037 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html
index 95ec51d24f6..04347e5aeb5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_mem_lib.sv.html
index 4b7ed4007c6..8ca81146f80 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_rvjtag_tap.v.html
index a6939d173c2..14907a896e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_mmu_stress_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index.html
index 161a7347991..caf307aadee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design.html
index 313680b9806..3c71d6050d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html
index ad1f51f7db0..6ef9bfbbbf9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html
index d044f17dca9..5e2d04f28b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html
index bd588cb7f5b..9aeefcea548 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html
index b47a0fe6eca..c86ff8853f9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html
index 2bf69e1e1bc..d6fe1f5610b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html
index 68b607d1dea..1d774d7e42a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html
index b25e772ffba..09e8421b82f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html
index 3d3a49a3119..9fa4eb4f360 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_beh_lib.sv.html
index 05842a00c10..8038e02cf33 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html
index eba7a3c57ac..9d469569b20 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_mux.v.html
index 4d1e7ddbed3..55cb5e45abb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_wrapper.v.html
index 1d2396a452c..77146ac93c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dbg.sv.html
index 28d70ebc8dc..6ac8817a3c8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec.sv.html
index 00fdf4fed53..b86562c09cb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_csr_equ_m.svh.html
index 97d71c0109d..aa877e33eec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html
index 6b2f4ef4717..09bc8a7eb1a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html
index a667817e7f3..58e1d254e8c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html
index 3178fbe6f1b..ce105bf7064 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html
index 93d052a8160..907a3f52597 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html
index 32bc4960673..73d805069ee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_trigger.sv.html
index 61b76d1d7b4..744043552e0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dma_ctrl.sv.html
index 442048d2496..fbe7408685a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu.sv.html
index 90c6daed1b6..6a3d5074398 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html
index 3a00917cf41..5d72d1a49f4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_div_ctl.sv.html
index a7d90379286..6609c8119b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html
index 1f2832cfa2b..8fbf9ae4ffa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu.sv.html
index 508e7714d00..ce77206f846 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html
index 2a8ca8f909c..32be4a3c4cd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html
index cd5c8f8d5a5..42b4aa6712a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html
index ed880f913a3..e004d12c54a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html
index bbcc4c7386b..fd2e1661afa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html
index 0b03c9a8433..f4d19214e3a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html
index a02a80eda0f..be2fd86e9dd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html
index bc7daf1c985..f947a78cf49 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lib.sv.html
index d2caf5bba01..5ce0fd96a97 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu.sv.html
index a76512cd8d2..025dbd2d372 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html
index fd8e6e0f61c..538e440a1cd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html
index 1f26612efd0..4bb6eaa83b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html
index e1c48325343..2d2a0862107 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html
index 144890d7cd9..fe564f52078 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html
index 635f7dba69f..078705ca61b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html
index a6af5a0eed1..8b15fc47b11 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_ecc.sv.html
index 17acffe4f73..4712b53ed26 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html
index f53c5cd3683..d86b75b8836 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_stbuf.sv.html
index ce4f75c46ff..f98d5c59867 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_trigger.sv.html
index 88d4439a537..c30b55a6406 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem.sv.html
index 1ae2ed305d5..c75199c41e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem_if.sv.html
index 9871c52babb..128e7c3e5fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pic_ctrl.sv.html
index 93fb4d0e245..a4147db0480 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pmp.sv.html
index 0fe113d1cc8..e502f8f8f07 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer.sv.html
index f5668db3b82..be1c1475789 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer_wrapper.sv.html
index 4143234e233..0d46c91c10e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_mem_lib.sv.html
index 3a53cc57d5d..cd61218734f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_rvjtag_tap.v.html
index f414a3f8160..0d6c2a615f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_no_fence_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index.html
index 92a7b3bc316..c5335d38608 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html
index 39ab3e31b26..73f21dbfbe1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index b97b62d52a0..e76b8e60229 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html
index a50321e478a..aac7ff4a3e6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index a2a8c1dc1f7..214914ce196 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html
index 979714d9d75..3b858405586 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index f32ce209e52..7e5f832749f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html
index cc26608313c..3985e98c207 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html
index 399991cdd0d..248a3db8d3f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index afc6835ee30..7819564a9ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_beh_lib.sv.html
index dd3297f8993..dfb52cd6270 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html
index c6fb18e8f7b..8d13643b698 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_mux.v.html
index 29ccba0070f..8dd439dcf4f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_wrapper.v.html
index b0a44dd68b6..ba94f117607 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dbg.sv.html
index e1ea310cb13..2038642a646 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec.sv.html
index 3dcc512d60c..2118f8d701b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_csr_equ_m.svh.html
index ba09bc2e9cb..e66d590e373 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html
index 3d8f1231236..da152700660 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html
index 6cf28142bac..becf217027f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html
index 440940c50f9..283f207db1c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html
index f52f71b5574..369af95b8d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html
index 30baed7307f..c32e2303fa9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html
index a580b1d5cb9..12228cc1f71 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html
index ced442b28e1..e4bccfe1c0f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu.sv.html
index 831670da2f1..643ed0f21df 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html
index a27ec8760c8..02b3799890e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html
index 9ca3b8e8909..433e5381168 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html
index 1a0a368602b..0e27db1ec3e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu.sv.html
index c47b1542b1b..d2935a52727 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html
index ff2ca19f995..fbc8e2f8198 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html
index 4110d6241e8..bf1ba8d3c30 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html
index 1c7426ce530..cc8b63391b7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html
index 940f6401d12..14a4d2aca1a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html
index 0353e1bb149..3d248067611 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html
index e7cedb76c83..b5facb6b0fd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html
index d0a8df9a3dc..352d98fe2b3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lib.sv.html
index 17eea7272c4..52727108b7a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu.sv.html
index 6c6e20555d7..50818963a93 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html
index 1fdb8380474..b6e29f88561 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html
index c7af6e6869d..ce0ac6091a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html
index 943f4f22ae1..9e200fffe1d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html
index a62bd2c3a4b..0164b602c70 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html
index 060c1b5d78b..9c93259aa95 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html
index cc643fa2421..5537ec26ae3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html
index 5e5d050207d..c7ba0387d4b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html
index 10ce1fea0d7..37e689796dc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html
index c702bacc1f1..ac4ad16ef50 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html
index d2d0690fd30..517560b3ffa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem.sv.html
index f8f60ba41ed..b702f745ace 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem_if.sv.html
index 3db945677d6..d6b4215c891 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html
index c8604b18ed8..44e7608c391 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pmp.sv.html
index 181942e0a57..f03cd3af770 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer.sv.html
index 3774a5486c3..a40b6da46e3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html
index 77f0db854fa..d697b1458e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_mem_lib.sv.html
index d850a1f18e4..40b62f7e55a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_rvjtag_tap.v.html
index d0db371593b..ef28e3048ca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_non_compressed_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index.html
index 7b84c7b2258..6ff21f43499 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html
index b3933d003bc..f5f42b5aee1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index 206c64eabb5..fe1ae63127f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dec.html
index 4bdd697f4ef..b178c338f18 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_exu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_include.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lib.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_beh_lib.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_jtag_to_core_sync.v.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_csr_equ_m.svh.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_decode_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_gpr_ctl.sv.html
index 12d96b510c7..856a54c0ec9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_ib_ctl.sv.html
index 8a3936a3d31..db8a1a548f9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html
index f72afdee3ea..2efd203f43e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html
index b2768e361bd..3554c100523 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html
index 765e6837d9c..84397d83262 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html
index 1a90368dcee..8c1a875f15d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html
index 9b4a2315839..30f8f8ce274 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html
index 48260879941..310f1c07953 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html
index 2039535103b..3a655cdd296 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html
index a5c3796843d..2b1d8a92fd7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html
index 58aaefd9ba1..00774cc5d68 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html
index 65884bf11f7..7d4f1e16304 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html
index 3d9615284ff..49bf16aa284 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html
index 93746f1b74c..8eb4bf33777 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html
index 9655072aecb..e58f31ce817 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html
index 50fbb80c7a5..5b3ea6db47d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html
index ebecab4246a..c9a6931d6f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html
index 9ff846ba881..b55c372eb8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html
index 82737eb7356..209cd7e940b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html
index 881e405605c..9a6914577ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html
index ea635df7d89..86d0c9f6dc6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html
index 3a317b2760a..4be67a1e58d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html
index ff84ac649d6..dcaac7bfc8a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html
index bf6ddf61d40..b2e72096414 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 7fd844e55e9..a2e59cee439 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html
index 60bd5add7eb..a02766df9d8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html
index ec80564832c..35670a79c82 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 56dbdd49acb..5ca0fd240b3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html
index 9c33f899fde..87414706d9d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html
index f4b5072bdea..1b91a02007f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html
index 8048f4df579..7444d3df1b9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html
index 33b40ef9abe..e6bbefcecc4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html
index de67a45a57c..c377f0c3a3a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html
index 7b12ef785d6..e207d59a232 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html
index c4c03a2c6e0..42875499652 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html
index a429fbb4f1a..8677974ac39 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html
index 767b5707c33..e8819cc1310 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html
index 7d1e3997405..039637c0416 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index.html
index 839e77fdc3f..bcfc421e68f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html
index c599f07634d..93c37e6757b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index aa2b14683de..37965b4c044 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dec.html
index 94c40d32571..1a3518caf10 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html
index b2ba46a339e..043a73490e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_exu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html
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--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lib.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_beh_lib.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_jtag_to_core_sync.v.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_mux.v.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_wrapper.v.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dbg.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_csr_equ_m.svh.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_decode_ctl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html
index f45bf7ec72f..942d354126d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html
index 9531faaeeaf..539eb9e6ad4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html
index d4fd74a4e4f..d9e5d992959 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html
index bc30f0d2e33..958f40d6932 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html
index 4ed982dede2..140b358bb60 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html
index 27898b2a563..27ad389f2df 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu.sv.html
index d1c4e9564ab..5124219a92b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html
index ee60ed66ce1..12a714eca37 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html
index 25fee169079..ebfe97480a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html
index 6c9707053ef..0ef43cb33fb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html
index 2ed4a5b9f1d..1d79033fdcb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html
index 4c661138350..cf8e8fa423a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html
index 96fb3495bfe..fc86d8d31d0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html
index ed5e8743d5f..1609359e2ad 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html
index f0b4183fbe9..5ec215e29a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html
index c4df433ee93..a57fcef1249 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html
index 1b7a069dd6f..a711d7e2854 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html
index 86e4848a472..4ac6ccf5e0b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lib.sv.html
index 2c788ee3b9d..0ccb81945b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html
index d50eabc8e5c..2e110c4cbc4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html
index 219239e0aa6..a1d4d5198b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html
index 83126218468..873372637f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html
index 28402733b2d..daae9d2ee0d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html
index 0b677d9a5f6..652e647de4b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 7eca156a307..8bb2f2e4b7b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html
index 54a4d32a018..c9bd7c416cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html
index 0176c648236..830d0d42645 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 90ad5bee7bc..b607e8e101b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_lsc_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_stbuf.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_trigger.sv.html
index 77419cdc308..bdcc6be4387 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem.sv.html
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--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem_if.sv.html
index 2f832a82db2..ec7958f576b 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html
index ec808d62b03..0ddc914a570 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pmp.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_veer.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_el2_veer_wrapper.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_mem_lib.sv.html
index 1d516c5042a..8ea4fc0a5f9 100644
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_rvjtag_tap.v.html
index a241a4ee8af..b5f561a461d 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_full_random_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index.html
index a2468b291b4..02f12ffb4ed 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dbg.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dec.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_exu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_include.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lib.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_csr_equ_m.svh.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_decode_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html
index 6ffda795ac4..48959ec0aed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html
index ef66726e24b..1085be396d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html
index 614b51b411c..1eaa85b01a8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html
index da343399e38..dc4bc1bec2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html
index e3b0e7aa713..61f70751147 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html
index 90415061810..8a6477e7919 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html
index 7d0e565632b..a8ff6b7b8e7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html
index b9416f9e51d..46e5fd90284 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html
index 3eeec9daccd..8618a94545f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html
index b3a44b166f0..3b5a79145d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html
index 861536a59fa..72bbee8c78d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html
index dcad5eff509..1f5166a42b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html
index 21eaf69de00..2174973c57c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html
index aac3fca2bc5..37da2e8eec3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html
index 9e91638b914..95349452d89 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html
index 49f00b1d871..06a9e310b99 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html
index 924576ec1de..6c63ecaaa80 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html
index 57f7e2baee3..3ec7213b910 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html
index af0167fd0d2..f6c0ce22041 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html
index f4b27ebb36d..3f708cd4737 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html
index f91630a7223..116d8b80bdd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html
index 8a630cd8bec..953e80c96e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html
index 419e272e495..7699a982432 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html
index 2fb1da14dc1..928ebe9039d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html
index ce79a2f21c4..491785ccb9a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html
index 5c60adf90c5..0f11fe2b830 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html
index a35cc8fcc56..d12d30ff396 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_lsc_ctl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_stbuf.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_trigger.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_mem.sv.html
index dc931a9ed77..1c4a1cc2a63 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_mem_if.sv.html
index 0b1cdf84427..6b1367fab61 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html
index b3c26ecdb00..339834f6b68 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_pmp.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_veer.sv.html
index 5038323b1d0..96709f1cbd4 100644
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_veer_wrapper.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_mem_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_rvjtag_tap.v.html
index 803af05572f..49b39446a00 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_out_of_bounds_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dbg.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dec.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_exu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_include.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lib.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_csr_equ_m.svh.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_decode_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html
index 3016ecf3b55..f70afae07a7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html
index d6af1c7311c..805d16986ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html
index 3687f187308..7753fb19619 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html
index 6d5df9151ee..174113c3646 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html
index 4b2fd3fefe0..8dfd290409e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html
index 2801f0b294b..56f02e51cfa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html
index 913b2184e38..171f53020b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html
index bb6c8e74e88..162273d6dc7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html
index 1dc0c7922fe..4677763e059 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html
index 941a716ffd4..a208b30cebc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html
index 37c77e88854..4802777e974 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html
index 85388e043a8..e56fe4824fc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html
index 0163375169b..236af51f59e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html
index b20a4191042..a8f048e9495 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html
index 7f85536c9ad..62a4489bfc4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html
index 41662839133..171b2a607b7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html
index d62abf7ead1..af1afdedfb1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html
index b03150ae1d2..ae5cf2f36bc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html
index db91995a33a..845896207e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html
index b7a04c908e2..ed7f4faaefd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html
index 91aec061387..6c86a0cfc63 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html
index 31204a1302e..076b7f5b948 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html
index 1ffe6444430..6605823be00 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html
index 9884c1f799e..92e4834982e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html
index f9c1cf2bec0..f391f4b47b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html
index ebc76ce96c7..a1f4af3f89a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html
index 0732e964dac..51959453775 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 468829d297d..eebf566bd74 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html
index c077f1f42aa..3d43cee7909 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html
index b0a66187c17..009a2769a19 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html
index 06c58d5bf23..883b9ed5399 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html
index 3902d78098d..64d423eeb64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html
index a0accd296eb..91baf8a1bbd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html
index 2570da10727..e0f54285d8f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html
index 6e5e0ad467d..a5ef1d2202c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html
index 9b537d89614..6f411a4471d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html
index 4607360dd55..dc032aaf379 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html
index 9bc0a6a3310..49f44da15ef 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index.html
index 0856dfc027a..4d785afaa8f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design.html
index c8990828228..6ecddb8ae27 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html
index d8698aabf64..758cf91d913 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html
index e9b3a28f5c4..e7a482bb06b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html
index d3bbbce6bfc..9b156312d03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html
index e5d9c7edab2..b8415812e10 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html
index ec97b552065..85a8c1dd311 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html
index a8ba83911f3..7c8c3519027 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html
index 1309d1b81aa..faf6dbc2de5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html
index 4beacaedae6..685447eaa1c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_beh_lib.sv.html
index 366ff854afc..7a3bb62a40b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html
index 9a01dce7a80..dc81cf2d021 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_mux.v.html
index 4551b2f47b1..feb00d08735 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_wrapper.v.html
index 065a9523226..379bda6ea77 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dbg.sv.html
index 75dcf0b844a..a2673081609 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec.sv.html
index cce644c33da..49d08e55c06 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_csr_equ_m.svh.html
index f087785386e..dfac59df5a6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_decode_ctl.sv.html
index 5a7d7cde02f..b45aaab7e31 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html
index bf71bcd56ea..c22b5e8b818 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_ib_ctl.sv.html
index 377bc6e2cf3..74352efd590 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html
index f6fe1322d48..e71794bb259 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html
index e89b73265c5..70fe74a4890 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_trigger.sv.html
index cff42c6c889..60238c8badd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dma_ctrl.sv.html
index 153421733fe..ac458608eac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu.sv.html
index 45188fb012f..00977c0c68b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_alu_ctl.sv.html
index 0285cae59f9..818156878e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_div_ctl.sv.html
index 0a1d1153e2b..94ae0556b9d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_mul_ctl.sv.html
index 15b56e12c70..db91024cdb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu.sv.html
index 4a9a131cb54..4ee47010d1c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html
index 7d1e767a391..75a870ab372 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html
index da761134230..a5dac5e9338 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html
index a605d75da3b..b8a9198133c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ic_mem.sv.html
index 225b20ca59a..462c81e285c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html
index 41108bfb3e4..f569d0ad5ab 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html
index b998d658f7d..1130b6840b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html
index 83b6685662e..aeac8a610c2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lib.sv.html
index 3b3f085bdbf..824928a852f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu.sv.html
index 5c6b7f484c1..e4df0b0619a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_addrcheck.sv.html
index 619234b3ac3..45fef1cd185 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html
index 6b77f56e132..cb0430250da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_intf.sv.html
index b1d9204e38c..4fbe9a58564 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_clkdomain.sv.html
index 531c08e7502..c66ee08ff2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html
index 41d8360b0aa..bbd9bdd173c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html
index ed6b43744cd..0299618dc39 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_ecc.sv.html
index e0eff07c9c5..826e4e807f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html
index c04a2463bd2..9ad1f56673a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_stbuf.sv.html
index dda93524d4c..e663706b0b3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_trigger.sv.html
index 43a9390c428..59f7f589d90 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem.sv.html
index e470da6f4ea..ccb79037b69 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem_if.sv.html
index 1d5d6a7b9b7..5726cad5d05 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pic_ctrl.sv.html
index 21a456f6c88..bbb1b5708ad 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pmp.sv.html
index 38027df5540..dd6dd020c20 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer.sv.html
index 60f33670a3f..bd9f8234521 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer_wrapper.sv.html
index 4c871089f95..c48bb50e854 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_mem_lib.sv.html
index 229d80c0457..274a19abe34 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_rvjtag_tap.v.html
index c922012d00e..5a1897abd27 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_pmp_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index.html
index 65db764ab25..0e1c0eabfca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html
index f9c758554cc..8dd1cd1a8b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index a7d74fdaa51..2c7c4443497 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html
index 0cf6f371f52..8476ad1b858 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index a38f0fa786e..4735513930d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html
index 0165199380d..35bb1a04b0f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index 25e4b60d8e2..9ba1596a26f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html
index 01aafe2a956..d19d5ce275c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html
index 55302e4e57e..f0225a7fb4e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index b7798582475..06ca4941c55 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_beh_lib.sv.html
index 06dd3e0e656..3001d89c8ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html
index 2e21d96db96..b54b3a265ef 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_mux.v.html
index d334324071d..0b5fe7cc10b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_wrapper.v.html
index 8114c6efac8..4c7934790ee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dbg.sv.html
index 0744d07d781..41790f95e9e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec.sv.html
index 93f3d139d15..5f9ec38afdf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_csr_equ_m.svh.html
index 34cb3923845..a81920d101d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html
index 96f77d7ebd5..13361b8890a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html
index af40ea9cfc3..458b15fec16 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html
index 674ba42cdbe..939de45b5cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html
index 6db9650d4e4..d14bf06fd13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html
index 26a013cb76d..1a0b93b26bd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_trigger.sv.html
index 9852368b7b8..f7562ce4184 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dma_ctrl.sv.html
index ed3b982c53a..b21e38bdfe7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu.sv.html
index 27bf7accdb3..56a64f7d027 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html
index 8fa0efe72d3..686f711d08d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html
index 90c7924c485..d163244cc00 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html
index 8ee1ba2d2ee..52f579ad1e0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu.sv.html
index f56556f997e..bfffec5f7a8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html
index 62e0c5c621a..ddfa913d8a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html
index 9e043f4a21c..06040dcbacc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html
index ecb987b0ccf..5dc2fde76d4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html
index 1462d55ad91..59a69fa095b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html
index 5ab45f0853c..be39087a56c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html
index 6ccfc44f478..93de8196bc1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html
index c9a7061b6d4..0744880c88b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lib.sv.html
index ae0ae16a544..e709af7ffc9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu.sv.html
index 6a4884b9feb..41f77652ac1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html
index ece8360a6df..df70ea57389 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html
index 192d45385a0..b6c25c691ed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html
index 540f1a9d68a..0a91a1051aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html
index b36dbb11ec8..9144fcf148c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html
index 9eed3bea6d4..bbe2a2eb853 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html
index 8bd4b60660b..11018ca3b51 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_ecc.sv.html
index f823307ffbd..f4dc12d0473 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html
index c74019a54f8..cad9cfa8c2e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html
index 31e533955bd..c1282edddf5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_trigger.sv.html
index b45506009c6..10106680d44 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem.sv.html
index 5ff81e2403a..c7e54bf934a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem_if.sv.html
index 409f08acccd..b37e4a1b431 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pic_ctrl.sv.html
index f7495ec4cf7..35bdcdf13e3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pmp.sv.html
index b504be0b665..b3e6a474ef6 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer.sv.html
index d928ff2d9ed..a92f3e4d378 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer_wrapper.sv.html
index 35d98d966a7..d2be026046f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_mem_lib.sv.html
index de66a46497a..78f10f1b070 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_rvjtag_tap.v.html
index 94f136a00af..fe9db68f8cb 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index.html
index 14f994cd756..17003694538 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html
index 8767cddb08c..ef8021f2a85 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html
index 973a5a7692b..9529da15c6d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html
index a215d0e6d93..68f321771f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html
index 8f84272ab27..baf45ff515d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html
index 0794181b970..873f441e057 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html
index 78f3c585d40..e35b27b8dcb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html
index 2364c8c051b..8c4a2f5cd24 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html
index 93592317a89..a10054da159 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html
index f005e16f195..cbf2517c861 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_beh_lib.sv.html
index fe1e06b5e63..8901b6535f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html
index bcb6231a409..9c1a7a8b168 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_mux.v.html
index b0577311139..cffd1f48bdd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_wrapper.v.html
index 2e503dc5296..2afc08a8fd5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dbg.sv.html
index 939347cf70b..a01447685a8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec.sv.html
index 45938b25890..13f3e4cd451 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_csr_equ_m.svh.html
index a130f1b3bdc..9815a245658 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html
index 4e074b90f7e..c13ebf27d37 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html
index bb3a3a34e5d..9db99b1e984 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html
index 5af2ac4f0f0..49be4556662 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html
index 6091aafddf1..2c1146402c2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html
index 7c4c30770a2..f8a06a4b96d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_trigger.sv.html
index 4d00fcc2458..0d2406a18a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dma_ctrl.sv.html
index 905581bc7ab..c0156c9fdba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu.sv.html
index bef4e3187cc..51d1384a5aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html
index 69c06dd0f59..234feca3a25 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html
index d7d0f4aa455..9ea7d749772 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html
index 1b33127d9fb..3fafb4addb7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu.sv.html
index 03a5bf59194..081c4f2cf46 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html
index c84530ba84a..fb832309809 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html
index 197144f3ffc..15d1394a057 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html
index 31cfbdb2aa2..e61139cec6a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html
index 4398a2228ab..49dc7cac730 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html
index 70aee312667..f46a29dcf3c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html
index 0b0e01d5355..95e6edd6d13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html
index be8f3cb072d..5b1d7ffb804 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lib.sv.html
index 37708d65e8f..f1f08f64354 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu.sv.html
index 4ab6eee6f5f..8276fda3c3b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html
index dbc8dc88579..e28ff24ac64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html
index f39bca6fa55..c279850b8dc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html
index 94156bbb5dd..5a79976f1cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html
index 06e713639af..93cd2ea732d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html
index fc49d1aba84..4c510c2ad9a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html
index ad487dcc381..60c327ae1f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_ecc.sv.html
index 567c5d993c7..7a39e42821f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html
index 1383747b76d..e0200bb0c7a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html
index 20d2851ad86..34a96e7b861 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_trigger.sv.html
index df07ba53c3a..06a0c69322b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem.sv.html
index 330a6a13df2..f0b794fe1d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem_if.sv.html
index 2d46bd0fe23..63533ef20e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pic_ctrl.sv.html
index 7292935db8e..777ea9fe994 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pmp.sv.html
index 4035f57f210..2ab12bd3012 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer.sv.html
index 5e76e040725..1a77670fb1d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer_wrapper.sv.html
index 16b2e3e6c58..0be8dac2142 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_mem_lib.sv.html
index 990c2bdab39..1721443c1ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_rvjtag_tap.v.html
index 8feab7e16fd..ec7b2a0364e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_rand_jump_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index.html
index 64774154b4d..da2d06e5571 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html
index f8e6ae90885..4305c045c36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html
index c5f6aa3f9ad..d4351093bbe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html
index 7b7bf47ec51..62ff2dafe41 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html
index c04b7b50eb8..e92d59267f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html
index 7f1f12a28ec..095ee905311 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html
index 3728eecfa5d..9edf2c812af 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html
index cf87bcba739..1bcb42616b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html
index e46c6197087..f6d6e46f78d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html
index cae56a3b648..c861a362447 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_beh_lib.sv.html
index 96bfd95bbde..2b3e1cba6cb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html
index 7707c3506d4..739b887bee7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_mux.v.html
index ed96ac6b59d..2e173d19dd4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_wrapper.v.html
index 7a56af4be30..221c26e8878 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dbg.sv.html
index 003d3dd77f8..3ba11ab7438 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec.sv.html
index fa9df65c492..f3ee3513342 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_csr_equ_m.svh.html
index a379bb0ebbe..f9e002f8dcb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html
index 8942bffb854..78ffb6086a0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html
index b274bbb7554..4be27f5dac2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html
index dbd3ecc62b5..65dfb830a44 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html
index 595543be07a..5e2e2b46cc2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html
index 72139d24795..4d63e4cf958 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html
index 69601f0228b..a1cfaecc811 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html
index 8b5cf6eadaa..3248e8a9ce9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu.sv.html
index f1783e3aede..b9d88bc1b87 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html
index e43451811df..e1b79e05afc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html
index 4b758814b1b..affb4ad6684 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html
index d6f3208aefc..4b1d9cb5515 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu.sv.html
index 37d875413cf..2970a51f720 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html
index 587aafd7860..f3b7144e3af 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html
index 34db6d17e5a..bcb56fcf896 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html
index 6df3f81ae01..eb0e9ff7a97 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html
index f75118d3cb6..37e4de3a3d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html
index af150a67f56..2ef670b7824 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html
index 9e5c1b7961b..38843cdbca6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html
index 3bba6765154..1877ebf2ae3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lib.sv.html
index 5251c0d9353..c872618b147 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu.sv.html
index 78001e527fa..dcc4dce25ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html
index cb1904336be..b42ab7195aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html
index a14395e5588..e168a69ba93 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html
index e6508327a6c..e9949f10450 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html
index d21aa262535..77d1083e84d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html
index 192295d8237..899f182376d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html
index 6823689cf06..c1fd6370312 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html
index 4233178c4aa..392877b855a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html
index fc644f94f5c..da0b3797dc7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html
index 16403c4da9d..d96e3ee78f0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html
index 0096ff07e65..3ff3d798bb8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem.sv.html
index c5fa8aa1d8c..9a0397a747a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem_if.sv.html
index 32daa3951b2..23eef488644 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html
index b87223461a0..6e5a20c8738 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pmp.sv.html
index 0f69fdd0663..334cb872bbc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer.sv.html
index c5b196c2ea7..646d0211094 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html
index 8de2f247882..5c99e2e9ff4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_mem_lib.sv.html
index d0d33a25b5d..e81d75717a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_rvjtag_tap.v.html
index 9f8ce7a1d36..a7ae3a59966 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_unaligned_load_store_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index.html
index 7f122f97127..55fe900282f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html
index 1e18c80d353..8c9fd41541a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html
index 84264208869..07da48292ed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html
index 41c3fcc6794..e1527b6d415 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html
index a7774918329..98d2a8ad861 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html
index 4387f79c8a5..8bb25053c6e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html
index 3af1960e279..c84683b21d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html
index 955a5c8938b..21e7f4d59d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html
index 3934ca5b3f3..01db9a1b0c1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html
index 5a113862330..daf5a88adcc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_beh_lib.sv.html
index 9cee6eebf84..7ff01209ba0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html
index 7ec7103bf1e..e35e06301bf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_mux.v.html
index a6ed2e5524d..e00948ca337 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_wrapper.v.html
index 3d90be9eb52..e8eaaf4aec2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dbg.sv.html
index fe2711854e6..a7a1fac90a7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec.sv.html
index e451abf4270..c01aa4053a5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_csr_equ_m.svh.html
index 5ae3a1035bb..5dde4f2a9d8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html
index e5c2794d7c0..bd6eea70eb5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html
index 7c60bc39c25..cf6772542c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html
index b22abf3fa4c..240e261a0b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html
index 17db417bcb7..8df04b5dfdc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html
index d793fdc278a..aeff69001e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html
index 1bacb6a76d0..853f208a02d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html
index 0a9d3514c11..1cddc601139 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu.sv.html
index 0859950b987..a7a5c63cb1a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html
index fe1c8e6b92c..972c2397331 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html
index e8c4fa5e7d2..a08c5c4abdd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html
index c2a22465bf7..5876060f3a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu.sv.html
index 36fdabee37e..e8a14f103ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html
index e6b5ade745c..a7ae84d5b21 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html
index af73d4cec30..26416319967 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html
index 9776eaaf0c8..21b1d4d7e29 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html
index 787881f386f..5612c48b917 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html
index e2a10583c01..95f107b5048 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html
index 5fe3d563948..73725646406 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html
index d802507341a..9152571a485 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lib.sv.html
index 77854a2cac9..5a55bb884db 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu.sv.html
index a8bebf1e4ca..4e044ce813e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html
index 2bca9128e07..ed8f5751206 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html
index 240e1e6fe9e..4e1bf5180fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html
index fd19cb2ba54..7ede92dcd95 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html
index ee968558050..4aa26876e24 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html
index 25c1c26a077..ec2a996ad7a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html
index 7ec2ba2e2f9..314e555c04e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html
index ac900247ec3..a9729e47f13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html
index 80eacd265f4..75c3d10e5b4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html
index 3ab0272e7fb..6b3be8139e5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html
index 3fe8d8a9c4b..25d157dc115 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem.sv.html
index 821fd63a7ab..c7715f638c2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem_if.sv.html
index e7ffa0e989f..1630e90228a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html
index 1d02b39c57f..b9fbbcfdb8e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pmp.sv.html
index c34e9cb65e5..622e424aa5c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer.sv.html
index 21c3809da87..ae087813a6e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html
index 481cf1666d0..ca6b5db1b86 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_mem_lib.sv.html
index ea1f8d1ad06..79e3327e163 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_rvjtag_tap.v.html
index 168499567eb..20547b6b17e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv__riscv_user_mode_rand_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index.html
index c6b36374fa9..864c300e0e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html
index e04f133850d..d11064275d0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html
index f1c7fe6db56..798e3b80ba7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html
index 068f66411e0..2dfb95ac6e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html
index 082e8540f3a..329d02ea5e3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html
index 0c72afd89ef..3f1b278f783 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html
index 0d60ff4ac96..db80047e40d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html
index 3e8c78882be..c3c66d7242f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html
index a7e1aac229c..53451b7cd8e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html
index 5006c08a85a..2a76eb8a24f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_beh_lib.sv.html
index ecc323e90dd..931cd001139 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html
index c133b869b20..a569390fc0d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_mux.v.html
index 8c09c42a355..0c7aa49f9dc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_wrapper.v.html
index cf98ab70166..305b86fd7e0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dbg.sv.html
index b91a13e42b6..fd0758be90c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec.sv.html
index 496916691dd..0493a65302f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_csr_equ_mu.svh.html
index dfcb41fb3f8..129a193f6a6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html
index d541b4c8bd2..43ba5a9f94f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html
index e7770d0bfb4..998c5f2984d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html
index c42f1fa2197..772d2964967 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html
index b53a826e1ce..31d1f9f713b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html
index 836adb3bea2..61bb6b05bc3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html
index 45574359443..c31505ec2eb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html
index a9e893cc0c9..c06502658e4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu.sv.html
index 5c3402fd793..9572dd36b78 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html
index d1da4a2a4ea..3361901dd71 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html
index 41b5dccc8b4..405800bf708 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html
index 716ff21aaf8..b5efd74c0cb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu.sv.html
index fb73a877f83..357f88c5bca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html
index 335ae8813f3..c5d174d0974 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html
index 9cdf3d7a226..9c83a9a03f0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html
index 95295af07ab..215e3a916bc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html
index b8edd88717e..77f6cd7c2d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html
index 4e8bd32ae08..dd9aaa3b7ce 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html
index 29a4b031d61..7bb79512c85 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html
index 3378fdbf78b..385acaf63af 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lib.sv.html
index 1b1b4732777..fc751ffa6c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu.sv.html
index 718a4686c3c..38e315f3819 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html
index 15a14126561..51b73bc56f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html
index 9a6e4c656f6..209804a8d13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html
index 26ab01877ab..df07730f336 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html
index 620048e4b7e..edcd5be6dfc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html
index 8c87e070071..4218376daf4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html
index 278b90d5f48..f97ef42d325 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html
index 40c156da22e..cecbe85cf08 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html
index 4b947d564b5..9809fa84687 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html
index 74f858e70cf..8b44d2f764f 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html
index c002c8d8b0e..081a35c928a 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem.sv.html
index 93f9ecff2ae..be86719626c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem_if.sv.html
index eba03c00b03..13f0a2593f0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html
index bd5854e5091..c653180a286 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pmp.sv.html
index 170582c45bc..d2df10c617f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_veer.sv.html
index 2d5c7ba902c..1f00c262be9 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html
index 5d8a89bbc10..23156653e02 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_mem_lib.sv.html
index 089fbde037c..e330cb781f0 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_rvjtag_tap.v.html
index d7de30792e8..85bbc400d8a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_arithmetic_basic_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index.html
index 7199f47be37..0d28a1ecf3c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html
index eacfc4e77da..5da21e3b4a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index c574d836103..8701cf43328 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dbg.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dec.html
index 507320f523a..5c18f08fd50 100644
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_exu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_include.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lib.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_csr_equ_mu.svh.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_decode_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html
index e745f2b8ff9..1de36504804 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html
index 20129938942..d8db098a1b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html
index fc1ae623bff..cb7bb4ebe3c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html
index 7061f7d4059..91003d119f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html
index 809a69987f7..9db6ba41163 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html
index a05c7ea93d9..c695833d5c4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html
index cb4ab518b1d..6b5003f8111 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html
index d8e2839abf2..bbcabb82396 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html
index 3afe6124f54..33b36be4348 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html
index 4d4fb0a5b09..1e69d60cfcb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html
index 85a349bc508..af0d1a3ab85 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html
index 68d6efab506..644bb6f885e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html
index 5b4b771ac13..fb1aad00eaa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html
index 794280a9900..4f7dc6fbdec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html
index 7dc5717a36e..79c58f4b46e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html
index 9b8e9768ea1..dbfcaad3997 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html
index 6ce3b98d5d0..a8431c1e1d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html
index 75dab5f9ea6..86700ac141e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html
index 8ae1bab264e..00aab32da28 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html
index e33df105cf1..a27e2dc5a78 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html
index 896c05ce4c4..dd988f14350 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html
index aa619930744..97535d7d4b6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html
index fef3d4b7330..e0483594424 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html
index 942a8525ab4..048d24a6f8a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html
index a65ee383f88..8113b0b0b41 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html
index b72248a1149..1681078f458 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_ecc.sv.html
index 6cabc899920..92d2f3a4251 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 6115d9d50d6..4ba04bf592f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html
index 058cb277031..6724d6d4c91 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html
index 4e37b1e2320..83c3d22f75e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html
index 32aa482ba45..2ed74c541c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem_if.sv.html
index e55f69ccc6d..38f957dc794 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html
index 02de0935e18..60df2fd9fdd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html
index 5b8da7a0811..dcc3f45d521 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer.sv.html
index cc03f5f947a..b919ca5ed8e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html
index 7efc6af07a5..75edf7b3af1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html
index 8564f6d4cd7..70982da4aaa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html
index c7e0a8cc6a4..c60da73cf9e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_balanced_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index.html
index 95822942fb7..74255c797e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html
index b183ad084a8..56126f1065f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index 8a61270a32e..fada6362e43 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html
index ccf3a074372..0a38d6487c0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html
index 49f27c0c6ad..5e2f888a3a0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html
index 281bc3b6ffc..c5722706de2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html
index 35516211cc0..f247084cc90 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_beh_lib.sv.html
index 3bb9ac9a637..1e9db8b3f2e 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_mux.v.html
index 111f20da6bd..19edc4642f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_mu.svh.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html
index c7777f7508a..91a7d7adbaf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html
index 9d57d6d2ab8..9bb1f5f407c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html
index 1a540749bbb..f3607eeb47f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html
index bf459336be6..d43380091bc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html
index 6a7ce3d9e2e..9639e0c44f9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html
index df3d3ad7695..15006507bde 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu.sv.html
index 53d3e321b40..8adc6156beb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html
index 1a04ef996a0..89db2b608e7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html
index e3320354c8f..df069014872 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html
index 5d5f1f8c040..b8638831115 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html
index d8b9ec3db9d..0a181dc7337 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html
index 9b46fc4d376..0ed16118d40 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html
index cd93c0092f7..ad7220e8e36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html
index d975d45ed97..83328e2f077 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html
index 5dd5cc8b981..acbf5b147a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html
index 4aa9be26425..f9209554b2c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html
index 20063e8e027..b6678495003 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html
index 027274db443..3311c69284b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lib.sv.html
index 3a985a623ca..2bde78a665d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html
index 21250108b58..817cb88f6bd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html
index e29761f06fd..843620217c1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html
index 63271617564..1abeecb1940 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html
index f972c6054ae..63861b4bf83 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html
index a92b38a1768..2e5eab96685 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 1d2fd704d08..94804eacfc8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html
index a94fa6b66c5..841be2d3355 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html
index 0e81f5cbcfc..9581722f7e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 5dac679a9e4..fdad0a5af75 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html
index f0ca253890b..275ce22fcbd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html
index e9436462247..a7c565a18bb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem.sv.html
index 24479b1b43e..c37ab9f2422 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html
index 6fe8b025927..647986c131f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html
index 2cf2c7f4bbc..7cf71b22d0e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html
index 0b005909fe6..78c0ecd99cf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer.sv.html
index f65f5ad79ba..f333b5ccef9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html
index c852870a9cd..df4190ac74a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_mem_lib.sv.html
index eb6dfa27fcd..4f589e7c1f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html
index 2dd0a080d31..4e2e7400630 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_bitmanip_full_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index.html
index 02dcfd08d5b..15146c9ed1f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html
index f5b7ac16eb4..a4738fa84ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html
index 60728f3021b..5fffbc84878 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html
index c26af52b53e..e5d5e8d48e0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html
index 697c5b54bcf..64c4a57618a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html
index 4bc9e5034dc..b294b6b0cd4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html
index 02936d439b6..979356ce070 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html
index b903159ff6d..44f0b08fe27 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html
index f3b09767f83..1091014e18c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html
index ade6e9f40b7..b6c89223647 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_beh_lib.sv.html
index 80f39fa2732..f8d02d52b10 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html
index 36577802a1c..30cb364439a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_mux.v.html
index cde06c78bb2..13f941eb1bf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html
index 41dafcb9973..5243de55bb8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html
index b8d45ca1daf..86ff855f46a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec.sv.html
index 5500e47d1d6..615dcc648c7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_mu.svh.html
index 20fd98de2a8..d8ddf1a42fd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html
index 8982715d2e0..b96786a19e4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html
index 284b8460a8f..53f2b39e4f8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html
index ec52f50f16f..a9c8db078d1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html
index 366d5ac4981..d3cf98c8bca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html
index 6185ef1ad05..02d80c39316 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html
index 073ece3e082..33bfafe014a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html
index ee4346cd476..530540230aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu.sv.html
index 9e109a84cad..502af6f7334 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html
index 7329ba387bf..361e8e91504 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html
index 7ecb8161a10..beaeff5becc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html
index 92c5bf8d03f..1b7dacf8b2a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html
index 2609af7ce39..1e5f26c8721 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html
index 27ab349590b..755fc35e420 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html
index ffb597b923f..791b447a174 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html
index 528233de4cf..9094053771a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html
index 76c6806ba5d..f08bd622ef8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html
index a9648c823ad..565d6815466 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html
index da1d137611c..9d14893bc3f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html
index cd7bc86bd78..3916e44484b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lib.sv.html
index b0db2eedc3f..3f4f3a62c97 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html
index 440521bcfa4..2326b0fa934 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html
index aec79acf1ed..36078a3081f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html
index 276cf38549c..866ef494f00 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html
index 4d5091970d3..e54ee8cc480 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html
index 15490ef1011..f68f5453dcf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html
index dc1f76e9478..8bf4531d1a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html
index 97e3b05b1e3..fa020b26673 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html
index d6d8c31bcd4..1eb67b18bed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html
index 742d3462e1f..8d51ddb9319 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html
index bdcbc16f827..cee8b2355c8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html
index aa144436614..ce5ef8c93b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem.sv.html
index f6a42b5bef0..9faec757c09 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html
index 01b009174f2..b58020f648e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html
index e0719369d9b..7d412b102fc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html
index 4241c85ee75..e25e8f91285 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer.sv.html
index d197a6559e3..c906d066e23 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html
index cb71d07e7d1..bff4211e3c4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_mem_lib.sv.html
index 526a68c40d7..353f2476710 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html
index 6994c85216d..c8b5e0b0995 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_debug_mode_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index.html
index 82a2bcebb9c..2c6ad53aae7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design.html
index afd04e6af90..8ebb1b67fdc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html
index 2f53d5ed8d0..b4dc834fc15 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html
index c41397e2880..fc0f8f5c1a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html
index 5174408e1fa..6d1aa8d772c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html
index 02dfb3fb43e..91be0fe8e6c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html
index 0c8f7adb314..34883ba4a8c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html
index ce8d68d5f40..223c2ee86f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html
index d5d48017682..4cf1f00ce69 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html
index 43416e65159..3b259ddec82 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_beh_lib.sv.html
index b689ab5f7c3..dfeab077705 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html
index 820a3c2815f..b88ed13be11 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_mux.v.html
index 6db1c3d58e9..1c3a0de385a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_wrapper.v.html
index 231634a83e8..747b9a53e6e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dbg.sv.html
index 0364e606c68..da78576dad0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec.sv.html
index c8e23e6cfcf..20f076d79e5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_csr_equ_mu.svh.html
index 4201db6e2cd..6629aa14e33 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html
index ef4690d1106..0cca38005d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html
index cd0d75f49d0..704508bc732 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html
index f84819f06e1..4c611aa1510 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html
index ec0dee870a5..e5ea9470199 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html
index c46923660f3..862a06b383e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_trigger.sv.html
index 9ac2caf9862..cb3c2aac1cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dma_ctrl.sv.html
index b5211ae751f..e8aebdf4517 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu.sv.html
index e1a3ef1c843..68849c0e353 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html
index 05d321d34d1..d825f72d21c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_div_ctl.sv.html
index 4f49afd2afc..a8f4e4c392b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html
index 48eb5b91824..c8075bf87d5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu.sv.html
index 4493ff71591..dd7027f7b54 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html
index b671068ce42..4544f28afa7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html
index e844d06d74f..bbf9149befb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html
index 9067c18c692..85f45b7288c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html
index 30080073afa..175890dd672 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html
index 8483de5e7a7..166dc8ee575 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html
index 182eb167ac1..7caa69a41cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html
index a7ce620264d..ebf2cf46713 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lib.sv.html
index bec31093f41..389894b3851 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu.sv.html
index 7df3ef99ddb..47b819485ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html
index d50096964a9..485d0267363 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html
index 60fd431d2ef..6a2ad097517 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html
index 45371cb4a51..69e0eda4ef1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html
index b0242722c99..656486fd57e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html
index 753f4af73a7..c6f29286f2f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html
index f03f1954c4f..ee3d6775207 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_ecc.sv.html
index 2d3e56d2b22..3fffef846f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html
index c1132a3ba31..21eaf406ce8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_stbuf.sv.html
index 92018c774fd..23ee2eade2e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_trigger.sv.html
index 35f55c6a4a1..33303d9fe7d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem.sv.html
index a9b5fdd74c0..117bd175cde 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem_if.sv.html
index 431b3ac93ba..3e772fcb555 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pic_ctrl.sv.html
index d89b7ee67be..9bc0573d78b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pmp.sv.html
index 1cecdbf6923..1bd750768cf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer.sv.html
index 96fadb34337..54d57a0651c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer_wrapper.sv.html
index e633e5f895d..951fdfc172c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_mem_lib.sv.html
index 0fd09285199..a39a094cd64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_rvjtag_tap.v.html
index 33f3ecd894b..df1cc0c3454 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_ebreak_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index.html
index a767e54aa8b..30ee99b8546 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html
index 9579825c116..e83a7652118 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html
index 8782f2d93aa..e17c4e0e56e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html
index 31f7e9f180b..50178f638ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html
index 653466753cd..c07170709d0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html
index f07b0b497ac..6b6d62118f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html
index aba99705adc..94a97ed3b61 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html
index 915ab4a72e5..346300f84c8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html
index be3c929fd57..844db7b3cd1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html
index 94d79518b4e..0f965f3825b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_beh_lib.sv.html
index 37344fd27f2..256266ad0c9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html
index 46459caa914..afa9be9a168 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_mux.v.html
index ad474c2218e..3a3e510f0a3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_wrapper.v.html
index 45c559795da..736b5b6ecc0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dbg.sv.html
index d0d3df3e3a8..a4b440f64f0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec.sv.html
index 9d8f568b011..54e4037ced8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_csr_equ_mu.svh.html
index a516030a9f1..536014ce23c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html
index d26a9cafb6a..68b511c3938 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html
index 4a4bdbae585..25c9e487304 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html
index 0bd5069dc5f..e6d11740fb2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html
index caf7c54c998..ad4629c0866 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html
index d39ad142fcc..0be357cea0f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_trigger.sv.html
index 164b96315a0..0c659d835c8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html
index f1d270cae7c..f0fc9ab6e2c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu.sv.html
index 8467329641a..60ffc81e24a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html
index 6ced7a33b55..3eb452befd8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html
index 165a99cfc2a..408b6172795 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html
index 8b314ae537a..2eba620c3be 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu.sv.html
index 4e3107f6cd5..f6830df7f30 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html
index c6a570da59b..aee5aeaf9f4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html
index 2df3d7074cb..bf04b236e48 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html
index a0c96ab9a18..58cf41bc389 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html
index 7573fc33e38..72a41d64d59 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html
index 466c7996153..b91d5af1097 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html
index 6bbee37f43e..38f409e09cf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html
index de6520170eb..505abc92dfa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lib.sv.html
index ee35b68f831..2436367e0d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu.sv.html
index 9aeb4e16518..189031f553f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html
index 92354a7fe12..bf39fdbf917 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html
index 168f1655c44..38cbb7a5583 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html
index 47176e77b10..850bb647e68 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html
index 889ae2d37ae..56bd01fc9c6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html
index 9ac79f3c4f6..ba2ddfb4f47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html
index 321334d79c3..d6d694ee0ee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html
index 89a1e296abe..7e2904a3d06 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html
index b72af87e4ed..c015b331dac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html
index 1ed63567afd..bb4f082c3fb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html
index 03f23c818d4..60b4a4bc961 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem.sv.html
index 6da18a6191b..7a4cdc14992 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem_if.sv.html
index 42df1df046b..4307e8c9f28 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html
index 4080faad40f..fc3b397a74f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pmp.sv.html
index 5b5c5289dfa..ca790cdd5d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer.sv.html
index cf2ecf79376..656eeec5c40 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html
index fc16deee2ae..1dea1a79a8d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_mem_lib.sv.html
index acdfffd7ec3..13842151744 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_rvjtag_tap.v.html
index b122d181f0f..6266af61142 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_full_interrupt_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index.html
index 6721ac4fb33..ded4fdf0699 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html
index 2171684079e..98e4e251c66 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index d9e4cc916ec..70571d8c461 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html
index ee1b936b872..6aca7b2fb5b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index 9d8d4622900..6ed48d2e90d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html
index 0409a7105d6..16f73cfbdf5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index 1cfc888fd6a..80fd88d072d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html
index 6afd5bf9c87..dd624e2bea5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html
index 0c5f1670221..340f710a174 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index 21381e1ea03..e2fb1010320 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_beh_lib.sv.html
index 01302ae5394..0b0bc944e51 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html
index 103fd954bbe..f8121883048 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_mux.v.html
index 1dacce9d148..fe30e5bef8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_wrapper.v.html
index f8adca46d9c..3b3183a9d0d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dbg.sv.html
index 11ce6288863..8cf69495af3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec.sv.html
index 905d92fe501..bfb085c5506 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_csr_equ_mu.svh.html
index af6b54d6a3e..f84cf386980 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html
index 2474771b9ca..f85275b0754 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html
index d84e505abcb..c38779ff218 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html
index a03be345ca4..55f3603caa5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html
index b7ea43dba59..67e889efc5f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html
index fa691e33be9..7f8aac39fde 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_trigger.sv.html
index 0cd41473b81..e7a4725ef19 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dma_ctrl.sv.html
index ff9b59d0b98..18c726ea29e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu.sv.html
index f4702798c64..8646c9e9375 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html
index 052557a336b..00345d4c26a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html
index 2dd8efbac88..315eef49dae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html
index 9c5bd887c70..0186e8226db 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu.sv.html
index 310ba277d05..15be614dcb2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html
index db1a352f108..e9bd09079ea 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html
index a178fa0631e..1cd800cbdb8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html
index 2f87093ae86..e58eadfa995 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html
index 581f9d14c60..01455d4de82 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html
index 1eb0fe3fd82..325e3fec9eb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html
index 65768fe34a7..2452eb24c10 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html
index 85ca6711761..9dd137d1db3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lib.sv.html
index 508758849a3..d53d58f082e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu.sv.html
index d6ae26d6dd7..c089004a58d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html
index 27a94061cc2..370a50117b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html
index 26a149709ac..c10dcae75d5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html
index e6d7ec37a55..e62172de7ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html
index 6a0b5d1b44f..48d90b61f7b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html
index fddcf896aff..8eb35ad59ed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html
index ea2594678fc..00e19453947 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_ecc.sv.html
index 9b36515b112..17ea11b1374 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html
index e84df3e9e01..81ad9174efc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html
index 5ebf6f8f454..14f7dd5017a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_trigger.sv.html
index 210c6d85332..1cac67a857c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem.sv.html
index c0a9c6eb3c3..dc067fabd59 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem_if.sv.html
index ff39069b994..3bdd03373ea 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pic_ctrl.sv.html
index f203203fe0a..1b1b733a13c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pmp.sv.html
index 21cc19023bc..af7c9b68244 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer.sv.html
index b5fa791eedd..0d46ca0779a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer_wrapper.sv.html
index 34ddd0bf81b..95320a45c8f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_mem_lib.sv.html
index 9bafa38aa4b..15229460694 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_rvjtag_tap.v.html
index 0c6ae242c26..674fbe65180 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_hint_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index.html
index f0a9c4bb27a..c558c77e0cc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html
index b1ffc91b033..9715a1062c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index 14b95075820..7d5f1553fb3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html
index beccd7a4eca..f9733dab388 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index 682591341cc..62ecf17f839 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html
index d9149b7d8c7..aa9735b416a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index 5cd50e18f89..dc2b6bef2e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html
index 3bc45f4c919..914c534bb04 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html
index e206d76f5e7..569e84032a6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index fb7af476125..380ffa65e82 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_beh_lib.sv.html
index 555d446a099..4f37488e8b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html
index 00f338558cf..3517b2f2a54 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_mux.v.html
index 3e7370758e1..cd152258022 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_wrapper.v.html
index 973cb47335e..88366d1a229 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dbg.sv.html
index 0cc1de5eb05..d6a6cfbf38c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec.sv.html
index 2e23e5a9ec2..8e99b83b026 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_csr_equ_mu.svh.html
index cb4019e2314..66c40e5dc73 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html
index a18fb115110..5601308e263 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html
index 1082eede527..379213f56da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html
index 260390dd375..0b34a2039d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html
index 193d2e4f593..20db23c2bdc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html
index 7df92ecea2a..ae36920d1b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_trigger.sv.html
index 2d3f90e9f35..33287b1bd8f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html
index 9e0dbe84fc4..4d967290624 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu.sv.html
index 998fab5b18d..20c29d656c9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html
index 559d91fd95a..bb998b0e4c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html
index d9d30852c76..706ea0f1491 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html
index 68ffbf27754..e5ccf132af4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu.sv.html
index 68bedbc1201..9d393cf272d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html
index c43c05b62a7..e03494897b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html
index f076b975e2a..e626e4154d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html
index 249060ac182..232817184dd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html
index 5f202ff8a86..4adbf9e6663 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html
index 5891459d7ed..5c8a6d946f4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html
index 8d3fdbde3ff..4cdf55025e6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html
index 60e6ba145bc..4c94e7a03cb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lib.sv.html
index 1620a1c49d1..df2a3870df8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu.sv.html
index 6ab897ec8a0..a15bc0ddcaa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html
index 0c0925848c3..10ba93fef56 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html
index df37ae14a57..0239419ea5f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html
index 1d139d8a240..8058eea7a64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html
index 4a53d97a5ab..f00c58a9683 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html
index bcaf06f35b2..0c8fe42f88b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html
index cd3f2e3946b..2eb43d0ce8c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html
index 3d557e0ffe3..c145ae461a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html
index bb9f94845c6..22bb3534901 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html
index 17d0f74706c..ecef1ffbb47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html
index e6dee3514c7..fabe3813ddc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem.sv.html
index 8b4c4595a1c..6c7d1875772 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem_if.sv.html
index f05d4fdc21f..4a021d82aa4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html
index 976935d4f94..b3d0391bb8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pmp.sv.html
index b03762c2447..672dbf56bf1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer.sv.html
index c9bf08abfab..5cd0b49efbd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html
index 270066a1c95..04db2b72328 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_mem_lib.sv.html
index ffaed879e20..e9b6e391403 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_rvjtag_tap.v.html
index 748a83d69a6..3be620884f7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_illegal_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index.html
index 293e8759524..92657fd7e6c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html
index e8f4652996c..fecfedd8d85 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html
index 60644416fa8..c7eeb28610d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html
index c3a083083be..1e66d2e170a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html
index 2f8bd0a4717..a696b3e1c9c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html
index 64a3414df0b..5d5495deeed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html
index 9afbb5e4846..24271ef22bf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html
index 262681248a5..cca03c6fa91 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html
index dc9cb53a60d..b570f046a72 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html
index d67638aebee..f2a99bd96ce 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_beh_lib.sv.html
index 2a270822888..78cd83256b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html
index 74995e72ea3..8c30e99da7d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_mux.v.html
index f3bbf38ea94..4659bb293fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_wrapper.v.html
index 0879e41ff6f..8f65a8c6f32 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dbg.sv.html
index 110322ffd5b..2416ce7fbcd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec.sv.html
index 11f600061b5..6b501cca56c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_csr_equ_mu.svh.html
index 86ea53c61dc..900f54b5c3c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html
index b5fae019ac1..2c6a7fb4e58 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html
index 3bb2ab03342..3697a35a4b7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html
index c0fa73ad385..e40e39b409d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html
index 075bedfa539..af185468aed 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html
index e1768fe6b69..f1f094e376b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_trigger.sv.html
index f4206b3dcbc..b455d785bc8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dma_ctrl.sv.html
index 44a12dfeb41..057c23471c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu.sv.html
index 870cf06e818..7450c8abf29 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html
index f3d9b70f087..3dbdc8a76a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html
index d6ed2c89279..74cf063ff2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html
index 37737b5ff2b..60af3567bb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu.sv.html
index 52ecaa24f51..ece7b529418 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html
index bff07bb9ac5..945fedd0ed4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html
index 4e8a3356e86..a994f3f7c7a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html
index 6d875d0bb71..12519d6fdb5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html
index 551a419fa25..f948901400b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html
index 0c3ce18ece2..db56fb7ac73 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html
index 73dafc7b831..2e233df2977 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html
index 811d205b8e7..d67f1608885 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lib.sv.html
index a8f69dc3ae0..a7ac60f99d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu.sv.html
index fea2fab1d26..85170ce0ead 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html
index 911c4ef0145..214be6b98eb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html
index 63f70098cec..df36fb9d20f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html
index 58d6c0a6c4a..6e312cbe3d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html
index a2cc3468031..2fe6a9d4e14 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html
index 856215d6f9f..d214990a393 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html
index 8012917bd09..22891798048 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_ecc.sv.html
index d8c6eb13c07..93a1d4b4f41 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html
index b3c8de95f31..df897ae4739 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html
index 1aefb609b0e..d44e41686d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_trigger.sv.html
index 11308617cc5..70fd1c4067b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem.sv.html
index 9e02daa86d9..35e7969f5b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem_if.sv.html
index 74b14b72236..e795a16b7fd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pic_ctrl.sv.html
index bc4d8921167..71d1b9d62f2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pmp.sv.html
index a0e977e0dc0..4bf96c9c7b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer.sv.html
index 68009651380..d0873ad659e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer_wrapper.sv.html
index 4e29aba05dd..b92330a603c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_mem_lib.sv.html
index 05e919fd7b1..831a0131fd4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_rvjtag_tap.v.html
index bcaa0aa2fea..ae69cac6a67 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_jump_stress_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index.html
index 51f98c539f1..f214f9ef495 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design.html
index 663db4e1d4c..9f4aebaf568 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html
index 97eb357084d..3b72f1c181f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html
index e439aba80ed..9172491affc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html
index f18df49dbcb..6f92eede188 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html
index 3fbbb3e5c88..b68660759b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html
index 74ebcb37708..58fa08f1f95 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_include.html
index 87c28c3898d..1a27d090802 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html
index 1974dd1de27..8d1a4f1ca5a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html
index 4088bd9c96e..a9db10808b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_beh_lib.sv.html
index c989578040d..c1ed8dca280 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_jtag_to_core_sync.v.html
index a0a7a6ec55c..84bcf4111a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_mux.v.html
index 7cb2cbce168..25ceb1f8c30 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_wrapper.v.html
index 042f4ba95c4..5f5d318acca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dbg.sv.html
index 08b218966e4..85f5b734124 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec.sv.html
index b0a2c0d8a39..86c2359f5b6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_csr_equ_mu.svh.html
index c9a0435db35..d7c777147aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_decode_ctl.sv.html
index b16e1a50798..15fa9743c58 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_gpr_ctl.sv.html
index 315d496b2c7..3531f5aef0b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_ib_ctl.sv.html
index d5c1a9ed246..16c4538ce36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_pmp_ctl.sv.html
index e8b5a1e0471..49620a9c749 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_tlu_ctl.sv.html
index f3e441580a9..f45a3172129 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_trigger.sv.html
index f437891dd9a..17873742142 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dma_ctrl.sv.html
index 76dccfcc524..8574b0f06d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu.sv.html
index 8148e8746f8..6438ba2dbc6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_alu_ctl.sv.html
index 2d608b4ad46..ec8e0463ad3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_div_ctl.sv.html
index 191ede306ba..4a8decca1be 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_mul_ctl.sv.html
index b0c4529c84f..019a820c05d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu.sv.html
index 723415e3681..20b9d28c92b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_aln_ctl.sv.html
index adcbf47442d..f3a38d554e6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_bp_ctl.sv.html
index bbcc17c2dc0..e106e919625 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_compress_ctl.sv.html
index 988f1991cfc..d5524e24f21 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ic_mem.sv.html
index 5da8ec0d3ef..8bbb6905c47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_iccm_mem.sv.html
index 736b0b66e34..ab29b032846 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html
index bdeb4476481..f01cf850af6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_mem_ctl.sv.html
index 08268c65ace..df29eac5ea5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lib.sv.html
index e03af9ca4ea..981867992f6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu.sv.html
index 266a75102b1..35beab070da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_addrcheck.sv.html
index 0f45d596f71..b5b08e6922b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_buffer.sv.html
index 8c88372f8ab..f64b163f8dd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_intf.sv.html
index 9aa33edb9e2..530f9588a83 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_clkdomain.sv.html
index 7e091c6a6cc..64d504d53e9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html
index 71ab66654f4..4410c608bc4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_mem.sv.html
index ba7b03fcaa0..dd33d833d03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_ecc.sv.html
index 4de2ea4f4c9..9135503f147 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html
index a6764adc8fd..2db55bc3649 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_stbuf.sv.html
index 6b68ae3d0b4..ce488fa4f46 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_trigger.sv.html
index a98b17a29f0..a0097e99384 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem.sv.html
index 4fbb9e0cca3..b13adfe040c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem_if.sv.html
index 16fa859b594..5e64c79091b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pic_ctrl.sv.html
index 55646315122..c865687a1c3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pmp.sv.html
index 918cc09a85d..8e5793e64b8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer.sv.html
index b573d9d00ee..e4a6ec5ff54 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer_wrapper.sv.html
index 3170a1e041b..8829d6b6f48 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_mem_lib.sv.html
index dee837db823..41386693e13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_rvjtag_tap.v.html
index 04b9dc3eb36..9790bca709d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_loop_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index.html
index 745405f498e..280a6b09423 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html
index 51787ea79f7..868004d6838 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html
index 397f940a7b8..8f8e2b4d6f6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html
index 93672a38389..90ccb714943 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html
index 67d8b9a8316..bcd8743c5ce 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html
index 6732bc4714b..8c0624dacd7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html
index 09cfecc1621..1615e12679b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html
index 976c5ea5719..12912489647 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html
index b7de1825ca5..7333037e70a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html
index f824e6563f6..bead1db81ef 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_beh_lib.sv.html
index 5bf442103a9..6788c8dfd8d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html
index dd265672228..97d1278cbe7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_mux.v.html
index 3aa684bb457..614a418c337 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_wrapper.v.html
index 821250497c7..687c3c74b57 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dbg.sv.html
index 242353b4132..a66c499d450 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec.sv.html
index f8b832bafb7..1930fcd8d3e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_csr_equ_mu.svh.html
index 31423b8b1a3..b4009c1a570 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html
index feda41fbbcb..2cfe8c21774 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html
index 3513629a6a4..e0b55cf5a25 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html
index e4e0335bf70..0c64dfba8f1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html
index 27a9d2181af..2c1ab4b722c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html
index c1262df4aaa..3234658e95b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_trigger.sv.html
index 9a2861a49a0..b03b6c2ab0a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html
index 30f4ee29949..a9a8b9ec405 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu.sv.html
index 6d8f9096a6f..dd3d1d76380 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html
index a038e26c38f..b0fbff84470 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html
index 8bcf47e60da..e84dda64a5b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html
index 387ac64b32d..cf0d07a940f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu.sv.html
index eb26e400bae..10d6787969d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html
index 9d0f72c3342..07c5c00bed5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html
index e7aede42d44..fe1b7ccb7b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html
index 592a041d70e..fdb3cd66b3c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html
index bc26904bfd6..6dbb4eedc92 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html
index a7700683731..1304a6d9c22 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html
index 3732e9dc60e..0c76a011729 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html
index 811315b6847..4465f6ffc94 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lib.sv.html
index ae021e8ce2c..a47cff03d45 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu.sv.html
index 1d948ce183a..acdc3225a25 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html
index fafe87f3150..9dda18263a7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html
index 8605c40474e..4f69e27a8d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html
index c9ecedadbd4..a4c3cb78621 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html
index 2916b15705a..c242851b7b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html
index 39e933b2549..e668f54bd4b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html
index e94eac413a5..d858b4e5beb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html
index 0a90221a0dc..3e394d000fc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html
index 9e357f60c96..872aa01214e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html
index e035698cd89..f6e1ceeb2df 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html
index 4746a942577..0e89b14e6f6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem.sv.html
index 19e9881993c..1e472deb99b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem_if.sv.html
index 32f4fb55c10..a100606817f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html
index 0fa5242606c..fbbffcebcb9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pmp.sv.html
index 54f296b23a8..f50cf815578 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer.sv.html
index 0cd2b4c069c..a53af53c98e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html
index c3d6d7b37cf..4fd5a32d8a8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_mem_lib.sv.html
index 0554a12b6bd..f5a0606d335 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_rvjtag_tap.v.html
index ec63c490e0c..cfe8f1a6219 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_mmu_stress_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index.html
index 2a38faa358e..1c90b5d4712 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design.html
index df66cd9f8d7..bd4183da284 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html
index cf5368fd1cd..3a108dff64b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html
index 90c42be4c96..924c40d3acb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html
index af97dd66e6d..b75b6789069 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html
index 0ccd37d33cb..255bc841577 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html
index 91e999fce71..e9a77ae5a9d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html
index c315436ad42..b79cef8989e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html
index 5b96cf5c727..2f463701970 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html
index 11aac260ce5..ccef413e4c2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_beh_lib.sv.html
index 2210b51986f..ab609027cde 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html
index 0df67025f3b..33832556e0d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_mux.v.html
index 70cd4ac4cca..612d3a1f454 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_wrapper.v.html
index cb3a6d2f16f..1107466e91d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dbg.sv.html
index 62f1f72bff8..f20c3b390af 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec.sv.html
index 488d28a9416..b2f79b7d251 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_csr_equ_mu.svh.html
index f2b259025ba..63396a13e75 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html
index 97547036137..f534d51003a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html
index 0dc93ff6605..150e30a9464 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html
index 8df36b67cd3..a453a53b456 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html
index 963e0f05a5a..c219cd245d1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html
index 25fa6e46a34..399d7935f64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_trigger.sv.html
index b5963e98add..14843327c57 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dma_ctrl.sv.html
index 64d48c7a215..4b064093a8a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu.sv.html
index f38453bdcfa..0269339edc9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html
index 1ecae5c39e0..33543bb3256 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_div_ctl.sv.html
index 60e433cebe4..266b404a681 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html
index c0881989b71..2a02d88fb9d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu.sv.html
index 8c4c629f25d..f5cfe603b90 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html
index 3331b742de9..cc75c1f6189 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html
index bb21b169d8a..b5a4e4a6f36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html
index 2047d09a9bb..3a70848d8ee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html
index 66f82727e95..e22db3a89fb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html
index 81afede4d7c..ad4603f8979 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html
index 0101fed1d42..edb06d8ddd0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html
index c3d26c4a5ca..649e2a6b275 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lib.sv.html
index 68c60908133..8c2ae5227a5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu.sv.html
index c6bf0f00e1d..abb81589525 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html
index ebb0054b7f3..ffed91b51b6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html
index 4b91b94808d..5bd077b817f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html
index 0b4a31065b1..4a6c03c2b0c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html
index 2c76a6cb0bf..0c2ddc4b29b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html
index eb57768dec4..f25001e3527 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html
index 8a4438acf0b..cb88f034653 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_ecc.sv.html
index 558de1ccbe0..21b3e82893e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html
index f60be0671f7..8c2e88c1f08 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_stbuf.sv.html
index 0e6e7998c15..03a9486175d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_trigger.sv.html
index 6bb11e60a57..154501474ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem.sv.html
index e7d7181a870..693ac5fd657 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem_if.sv.html
index 0c3494fbdde..51ab9459d7f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pic_ctrl.sv.html
index 78515377738..2fe8f87d903 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pmp.sv.html
index fba498da079..473c9115358 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer.sv.html
index 727d5dd7850..70ae7467aa3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer_wrapper.sv.html
index bb6d2b0afc2..78afc21f94d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_mem_lib.sv.html
index da5ded05d89..9a8ea71d08f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_rvjtag_tap.v.html
index 799b955bdb6..1b12ae68e43 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_no_fence_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index.html
index 7b152ede14e..10c1a372c7d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html
index 3dc6ddc7250..b62c8369782 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index 1279c372210..96c792a906a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html
index 68c6f1bfcfc..e6e50e5f9c7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index 1d2f69ebb71..5eb6d35962f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html
index 1b0a6da642d..e6dbe10f310 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index 534e144b1c0..a3aa50fd08e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html
index bae20f9c37e..a42181b04ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html
index fec76173215..0ddffe8e9b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index 9be3ec5944f..d8efd0aff13 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_beh_lib.sv.html
index 199160b5444..711ac4eb00d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html
index 65302e60d20..afbd17ff0d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_mux.v.html
index 51f0016feeb..bf788fc0b14 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_wrapper.v.html
index 877341ca9aa..4a7a19dc2d1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dbg.sv.html
index f05ada4a6ed..51c818e5da7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec.sv.html
index 2c4093b3cdd..64fad4002df 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_csr_equ_mu.svh.html
index 2f1a1e9014e..e6907bff192 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html
index 7512569aa45..814102b3f81 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html
index c49b7567980..905574c08f7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html
index 660c2cb7079..ddbcedcbcf8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html
index 58d0861a934..c2980005bdf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html
index 264f0ef0cf4..7215e707443 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html
index 9a3bf01aae2..772cc52ccb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html
index ceaf93dfc36..a93534de370 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu.sv.html
index d58d6a3f68b..d3f9f4a5e29 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html
index dcf8cf71501..d6fa0c8c41a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html
index 75cff8f5209..45e5c4507a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html
index 1abc0deaefc..b3d760a1f48 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu.sv.html
index 3ace363e45d..b33fbbcc878 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html
index 89480f6d151..0b3f3f61209 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html
index 5ebacbf535a..2ed43464828 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html
index 62317fa571d..c2d921b7743 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html
index 6c44230d879..b0b59f9ab82 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html
index 02fe7d5e5ca..c3c5e5fc04d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html
index d7f00eb9ab3..e386c2f9179 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html
index b63c51327ba..1f05e964652 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lib.sv.html
index 936fe8e30ba..a36476cbd3b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu.sv.html
index bd10f0ad54e..f43b6cef967 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html
index 3c9b5936794..4216dd98aff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html
index 859e6209b2d..d21b4284048 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html
index bfcc005ebde..ae5644f3b4f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html
index ff4a663bc56..5d17a46527e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html
index 8effdef5b8a..0a17a8ea0d4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html
index 11191e05be8..f7c307818b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html
index d959e028f07..1088b19f13d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html
index 8c06868135f..bb4f43c808a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html
index e9776aa31aa..a4e9573d9bf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html
index b1d30b3687b..2b8994addc6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem.sv.html
index db6c5e4f610..2eea1e40d36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem_if.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_pmp.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_veer.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html
index 3c920ebf091..aea31d2ee61 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_mem_lib.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_rvjtag_tap.v.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_non_compressed_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html
index 35490e65196..ea57108030c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dec.html
index 1ce6246d397..40cf1b30fb6 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_exu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_include.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lib.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_csr_equ_mu.svh.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_decode_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_gpr_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_ib_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html
index 56461eabab4..e8b6f7a01ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html
index a790ed5836d..b1f0c63b154 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html
index 5658a64a68a..da8d53ac84b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html
index f582e5c4695..5862f48d72a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html
index 6b6a3b5c8ec..5017229e51f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html
index be622d4d44c..351fcdc56da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html
index e303c967062..b2a4ab11564 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html
index bd923f23fb8..8b6c39b7a6f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html
index 1c5c42926cb..bffe7ce4391 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html
index ce1acced96d..fc48a26b317 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html
index 1f6d6880d4e..5432a6184b2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html
index d1bdbd139b2..b2b60169b07 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html
index d62f4c0cb25..c6744b70475 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html
index be057164b3b..0933924a7dc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html
index 0f46a4e5593..5f922c9c2ba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html
index 05856fdc49a..c84c807f7a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html
index b6ec8c876ff..042cc26b304 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html
index e1dd5c20d76..a308e3caa04 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html
index 4d8b390a81f..dc0e133c8c2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html
index ccf34a97974..0c856cbb2b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html
index decffb64ebd..95f9e3fb234 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html
index 804ad55ac0f..0c64890193e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 040b54ce109..b25cc98705d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html
index b53fbdf9059..0155e4b1953 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html
index 2fa2fc3b2cd..5d424b6f4e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html
index 8e2084162b8..341b5583fc6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html
index 958fa47a5e8..d78cc7787d6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html
index 27118114e32..5d52efea907 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html
index afe79933bf2..88bd5e45580 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html
index 28ca8dc035e..0d7df692591 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html
index 639deb7da6d..5f90211ee79 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html
index 1340cd65f90..e9004656634 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_disable_all_regions_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index.html
index 7026a3ed744..451787c178e 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dec.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_exu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lib.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_csr_equ_mu.svh.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_decode_ctl.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html
index fe2c7e0ea1c..32b8a0688d5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html
index 2e29f86e79c..070ce803583 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html
index 000f4d91f6d..0be6ed38e22 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html
index 6a01394069c..70714ba884e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html
index b8710cc2479..38e65a772d4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html
index f2244e9191a..0ab413dfa19 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu.sv.html
index 33acbac6b8f..e2e0b0247bb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html
index aae0cc0ef83..dc7122971e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html
index 3486acc2947..378c0cc8c56 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html
index ef0ea3b9d7e..7cf78195624 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html
index 5d90b810065..1e8f76c0eeb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html
index 8304f9f1848..6b275e82f05 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html
index ee9b765d5d1..b7b6ea2b6b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html
index be9ff07fe79..f3f87ed6ba6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html
index 63cde6aff57..b1a1a9fbafb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html
index 842f21c17c3..25447bc8961 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html
index ac9f019ac95..4b3dac1c653 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html
index fcba41e692b..d2756dd8621 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lib.sv.html
index 020bb747b6c..fe83b55e610 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html
index 9e743f903be..72a07a22bf0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html
index ddfdc9fff4e..64f61c062fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html
index c22e1a334a8..d83dab368aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html
index daaefaad330..378275af511 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html
index 7d75d801b1b..f8bd536e18f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html
index 5133333b535..0bbb562b4ac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html
index eb4dd1aa57e..12a7457ff25 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html
index d38ade530e7..12bae5e2efa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_lsc_ctl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_stbuf.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_trigger.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_mem.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_mem_if.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_pmp.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_veer.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_veer_wrapper.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_mem_lib.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_full_random_test_veer/index_rvjtag_tap.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dbg.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dec.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_exu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_include.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lib.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_csr_equ_mu.svh.html
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-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_decode_ctl.sv.html
index debc4680415..6df420d7a68 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html
index 583472c6bef..f5edab9b941 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html
index 5d025387ef6..1dc68c0c34c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html
index 2ea26728ef3..43b7aa92062 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html
index 4eb6461665b..a2bba0c8c00 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html
index 56f98057b5f..eaafbad0c47 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html
index d021001036c..15732267068 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html
index 56fc1470db8..78b14ac5e6d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html
index 267fa0ea7be..8d1a6318138 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html
index d8cc24130e4..4ca9dbf4b41 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html
index 3e6b8965e74..4bf6958d539 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html
index faf52052e32..2034ca3bb36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html
index 280491f9114..4009179e05c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html
index 14c08fd3f6a..3fc30696688 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html
index e76aab71c93..2ec856bc9e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html
index cf68a51c4bc..f2ca4889225 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html
index 84619c31284..ced4c7d1293 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html
index ae86bc58256..6f9aefe65fd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html
index fe882d278c7..725a74999fc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html
index 1eb1f00e6a4..6a1e96f5b63 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html
index 6781463f7f9..83a1de27dd3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html
index 1878bfd501b..f1fd31bc032 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html
index 57726ea497d..92fb79d2f20 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html
index ec3c49b306e..a3e6df544b9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html
index f6757b7b0b0..83ab535aa97 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html
index b6778cc4e21..3bdebfb8675 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html
index 5d72af0e46a..8e72bda1b3d 100644
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_lsc_ctl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_stbuf.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_trigger.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_mem.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_mem_if.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_pmp.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_veer.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_el2_veer_wrapper.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_mem_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_out_of_bounds_test_veer/index_rvjtag_tap.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dbg.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dec.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dmi.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_exu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_ifu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_include.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lib.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_Cores-VeeR-EL2_design_lsu.html
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@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_beh_lib.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_dmi_jtag_to_core_sync.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_dmi_mux.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_dmi_wrapper.v.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
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diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dbg.sv.html
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@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec.sv.html
index 9991c0a1add..5dfbefdad76 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_csr_equ_mu.svh.html
index fbd0bef0119..8b0ed9a65a9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_decode_ctl.sv.html
index c2b4cfdf2ef..593a19b304a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html
index b4329aeaba0..0bed09daa3b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html
index 75f389deb65..a7b4a4b23a6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html
index 67df0de01e1..97f541aa4ee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html
index 0d4819914a0..248b348d452 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html
index 3febb34bb78..9777fc62748 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html
index 624494ac679..4ffc88be320 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html
index 751b2efdc96..8bc7ac63191 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html
index b7aeccabb0c..9cf3566e41c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html
index d92ed0defa9..a85e1d97eab 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html
index 9c72ac28c52..b784424772e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html
index e00b604798c..97dc74a7b65 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html
index 4aa42aafd95..69ec4ba3827 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html
index a781b58ed25..c16902ba657 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html
index 1f211dbbee3..50bd88bf047 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html
index 5cc5b4f1d1e..29df7b2d909 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html
index 8c540b3262c..444c043dc34 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html
index f4b338639c9..9d980ff0c3a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html
index 2b86e06db64..18007f4bb86 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html
index 3c96e7d0580..21d9e709d89 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html
index ac66c7d1249..9a0516296fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html
index 78cf813b248..3e923201624 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html
index 31e9cc3cc5b..2c8c081e8da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html
index 85f133e8e86..266d3c27b39 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html
index d8c1e3254c3..99ed1badb1a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html
index b9cadff57fd..5d5ddd31052 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html
index aa5ed9ff137..4a997fc7abb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html
index 0916cf2e904..e2d05944b55 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html
index a9de014bc1d..d1f28108620 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html
index f141eacc459..1ef5fa35a66 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html
index b0159283835..68c2b4ecd2b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html
index 3f744417390..e1915ed41e6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html
index 62f1ca22868..96f4dcfb041 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html
index 3196e0bc55a..8c82c7ba216 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html
index a9433b373a4..d013f967308 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html
index 9fe016c9283..0851e35fedc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html
index 47d214f5e06..917bc7a2ac3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html
index 5d2ce413ac1..f3386f79ed1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html
index edc0e908bef..b85c1603241 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_region_exec_test_veer/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index.html
index 40e09ea2531..cc0e7db10db 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design.html
index a75215dc7f0..a676fe7dcd5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html
index a97218dfa41..adcecb754cf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html
index 35c1e574a40..f0aceaeec55 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html
index 077852a7a1d..f301c13094f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html
index 3ada2690480..6c273600089 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_beh_lib.sv.html
index 327c20ffdb9..048282ea56f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html
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--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_mux.v.html
index fe15bd56846..69a60748fd4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_wrapper.v.html
index af7b3ab5612..84e470634c5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dbg.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec.sv.html
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+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_csr_equ_mu.svh.html
index 5d89384d282..5bca27efe31 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_decode_ctl.sv.html
index d4112c3d931..b170a97a989 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html
index 8dc90f9230d..6bf80932496 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_ib_ctl.sv.html
index 4e834427a77..22b97b896f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html
index 21cca6c4914..e034ed72ddb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html
index 82164f665a6..1e0baa9fea0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_trigger.sv.html
index 10acf8d7392..bbc823e18ad 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dma_ctrl.sv.html
index 91afa743db6..e811ba1f6c0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu.sv.html
index d8d9a042e5e..1cb210a7905 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_alu_ctl.sv.html
index 4ee07e0fa1a..bb9ea550759 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_div_ctl.sv.html
index 1513b3a406d..3b8be21523f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_mul_ctl.sv.html
index 86c854e7a19..fed294915e6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu.sv.html
index 8297a617fe2..5e048acef68 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html
index 4a0cab3136b..cba5e2abaef 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html
index 2c2ed1b824a..b0ed029b3d2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html
index 097f0575fe8..4d36f77d860 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ic_mem.sv.html
index 5adc887d00c..93d40d1cb11 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html
index d737664ddd4..e3a31a6600e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html
index 548ce98d5c1..789106ea624 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html
index c332d98c2a0..aa49c56e2da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lib.sv.html
index 8ba79a0e6a6..dcefa1efe36 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu.sv.html
index 3fc7ad26b29..87db36b4e7d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_addrcheck.sv.html
index 9a7d9f0a546..8c3ed89f95a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html
index 6fbaf8fd8a1..352c492cc60 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_intf.sv.html
index 48886ac24db..148483a73d4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_clkdomain.sv.html
index 38e0ee06231..0cf334931f6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html
index 427c89aa06a..35e2529a882 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html
index 968de9a4e38..4f5c6adc930 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_ecc.sv.html
index 013323b2581..ccf89f0f904 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html
index 8df0108e4dc..c3c28171a2c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_stbuf.sv.html
index ff17b683501..6d7dde81cc4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_trigger.sv.html
index fa4d9d1ef07..6c60cbf39da 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem.sv.html
index 2233980f94f..c6744bad63c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem_if.sv.html
index 29e30431d7e..06fbe10d0f7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pic_ctrl.sv.html
index da853cea2c0..f669bd947ab 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pmp.sv.html
index d5aee517131..02ec5b061d6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer.sv.html
index d231f650d1c..96a6945ee01 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer_wrapper.sv.html
index d45cb6f764b..acd710b0c03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_mem_lib.sv.html
index 74689bd33c8..8073af81bb3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_rvjtag_tap.v.html
index 8fc76f7c5ac..204ec664c3b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_pmp_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index.html
index 950b488935d..d8bb65ab5c7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html
index c2882172a4b..92b13b9793a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html
index 9ea301d92d7..b60dc8e5cb9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html
index e36a118bac3..a670c53360d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html
index e5ca884f327..3ceb90eb488 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html
index e083af7a30f..08d48797830 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html
index ad664bcf352..1c129b13177 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html
index c189d8d428d..65ff2247072 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html
index 0f574b1c639..cacfcc063dd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html
index cf992f8b628..97e489eb45f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_beh_lib.sv.html
index 7e7d979c47d..eac584c10d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html
index 0b925e5c348..66698bfe9a3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_mux.v.html
index bce8a3f3b02..6cfc93cddc6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_wrapper.v.html
index 7a32cc20309..0e03ab16be3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dbg.sv.html
index 204c5480dc0..f5ea33d4698 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec.sv.html
index 5576445bc91..d205a1aa250 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_csr_equ_mu.svh.html
index 7fb608a7c5f..aa535bbd265 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html
index 00d6f68477b..4cde60157f3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html
index 6d0de40f375..a926dfcee11 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html
index 5b4ea54756a..d024b2f8f62 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html
index 46194cb3264..785b6efed63 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html
index 8e053c42ceb..5158f3c7667 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_trigger.sv.html
index dfd35cb9894..d4f9f48248b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dma_ctrl.sv.html
index 5099467896a..f1de339c95d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu.sv.html
index 313f2d1617d..04a5073d48f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html
index 2a8fdc46394..ea500b8ec07 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html
index c201a0cfa7d..2a8af040cf0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html
index 303cdbfac5a..7bbb8035b03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu.sv.html
index 55e465d56ba..9c6c04918e8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html
index 1f705d7c890..661c7eb27b0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html
index c501823366a..65064b83f96 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html
index 1c29856c6e1..bd497c24042 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html
index b91baec1ba2..546609f39fa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html
index f725d571d3d..c598f4d3e65 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html
index e3eb7ef1441..4e7e79534b7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html
index 4c362f24080..afe9d901e54 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lib.sv.html
index 4ff4106c4fa..26c971fe688 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu.sv.html
index 99c5e2d6c06..ffc51abf14e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html
index 57becf0e0e5..cfd74f927aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html
index b2b1c36f2d7..3faa2a59eb2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html
index 3dcd76ab105..c17da59972e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html
index a8d43f115e7..bc90945399f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html
index 851d2fec53e..ddda4bbcb7b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html
index 9333f64f9ed..f17f8ef0812 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_ecc.sv.html
index f6e31f61e80..28a13fa997c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html
index 7713b30f183..72a3d64df64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html
index 908c270c03b..cdfa958ed1a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_trigger.sv.html
index f659afff1a6..465c7f60030 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem.sv.html
index a9f7f6f32c8..bb4c29e37be 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem_if.sv.html
index 4171af4b5dd..2ad8eaaa3ec 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pic_ctrl.sv.html
index fad136b4bd8..38f32630276 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pmp.sv.html
index 66ce90f1c94..b0537117cf0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer.sv.html
index ee1bf1c416f..b6cbed5b57e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer_wrapper.sv.html
index d44853b4be0..9c4cde83736 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_mem_lib.sv.html
index b94c3ea5bc1..2f2d18a2020 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_rvjtag_tap.v.html
index 1ad897a62c8..9f7c4ccdbfa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_instr_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index.html
index d1315ec85e9..031bf9ac29e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html
index 62d6053b67c..952ba3840d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html
index 52215567ea5..8f1183631a4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html
index f2e5d8e11ac..69a28e53e8b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html
index 6e1e5214d11..b617f0fa90c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html
index d764d490133..4f0efe180b5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html
index 5a34a31974e..348a24704e1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html
index b7b1c5a51ba..fef94f049bc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html
index de85363174c..b94f89c249c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html
index b536436b45e..9bd21990690 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_beh_lib.sv.html
index e2de49b1ad3..97493addbfa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html
index e7850dbdbee..6291ff9d338 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_mux.v.html
index bc3278e4606..300f76fb87c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_wrapper.v.html
index 40326b7bc76..4b3da6a3508 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dbg.sv.html
index dce1be1fa46..01931139c4d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec.sv.html
index 38720a89444..5ab7b0286df 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_csr_equ_mu.svh.html
index a486cb5c2da..1c62b98f750 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html
index 32601c9a88e..65ad40d6f05 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html
index 7c7d657df6b..9d54a3f1a54 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html
index 004791f9b8d..aa70de9977b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html
index d1e423b440d..85b001c6bf6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html
index 3ccb539b471..01e4b768cee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_trigger.sv.html
index c7b55eb88d1..5cefa65149c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dma_ctrl.sv.html
index a174a751729..53dc8e61aa0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu.sv.html
index 864a0bfdf9c..24c3d9a973f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html
index d25065639aa..f3b3b657f97 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html
index 82c6ad48055..bc22688a6ee 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html
index ad8ce759cd1..f372f780c5e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu.sv.html
index 8c091719915..84cfde3313f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html
index 5d71546f0c5..a477eaa80f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html
index ce20c0045e4..e4df3e27f35 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html
index 1a23fbc7705..e87979bb272 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html
index d2a2af9b065..c682a155b8a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html
index 079e8455064..de64c3930dd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html
index 8c34c2e5bbc..b7320382a2f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html
index a6f96e3552c..bb1a820323e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lib.sv.html
index 3f2e253ad81..b76a66b8bdd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu.sv.html
index 03da5546cd8..9b7b3abefca 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html
index a8c94ffaef4..a42ce8143fa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html
index 5ee42a473dd..56a75424c51 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html
index 29525c7cdfc..6e59a723c0b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html
index 6f2c067125f..2e4ed0116ae 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html
index ce826cd698d..b619b44892c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html
index 0d5dcdb7781..73633fcc4ac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_ecc.sv.html
index 141b14bc10f..8f0e877275b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html
index 550fd4db5c4..5b9fe7f273f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html
index 3b4365a7fe5..25081de0267 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_trigger.sv.html
index be9cf7f8f91..a44e658eebc 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem.sv.html
index b2d4ea483b8..3c487936d4c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem_if.sv.html
index 52369422dac..3281bf7df04 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pic_ctrl.sv.html
index b1cac79891f..65e8ee46746 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pmp.sv.html
index 9b79c720594..5994276b11d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer.sv.html
index 018def7f3ea..2a0deb5b70c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer_wrapper.sv.html
index 521140b6cfb..e6e02b47529 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_mem_lib.sv.html
index 08a796aa22a..bfd215a42aa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_rvjtag_tap.v.html
index db7128b903a..d39d2b6b48c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_rand_jump_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index.html
index f3fc737bfe6..f7abb9205a3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html
index df9e78b80df..ee9f805fd43 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html
index 2c23523f4fc..071fe1bb2c1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html
index 35f957a71ec..064af28a9d7 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html
index 64997582e77..6162924cffd 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html
index b3986f104e6..3037663136b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html
index 999915fe93c..16994f40528 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html
index ae8ca1200d3..0ccfbe3fc76 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html
index c2f912f17db..363031ba0e4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html
index 441b6577564..8ae4c8be9f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_beh_lib.sv.html
index aa24733e6b0..02eabc89f2a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html
index c6f99a01c7d..6cf03f52bb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_mux.v.html
index 719fd882d16..7439fa9deb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_wrapper.v.html
index 8197a562a73..7b75cf13aa2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dbg.sv.html
index 0215aaee98b..3a802f5c19b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec.sv.html
index b8671fb28f6..4289636f3d6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_csr_equ_mu.svh.html
index f55a22ad3b3..ce2e52d884e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html
index 20be4a90e08..90ebd78c138 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html
index 2cd013c7fb5..8454b4b3237 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html
index caa5021f951..2619857c276 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html
index 831a407f138..b106872c690 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html
index cfca7eebe22..11ca0ebffb6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html
index 5f218f552ee..3ca518620d6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html
index 7968b4d3c77..42447646425 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu.sv.html
index 0ec2d41e91e..0f36b41613e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html
index f41f870e9b8..7be6fe9288c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html
index ce5e009ed84..a788a2c7ec1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html
index c92757c16f3..9e881f34af9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu.sv.html
index 57041706839..54f3324a549 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html
index 511a6ecefd8..3f4b76d6151 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html
index afb42b93936..bcadbf38baa 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html
index 092506d464a..d158d334774 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html
index 219f66788d9..b1e66936f70 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html
index 23b5fafe509..c37ddc94f2e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html
index 0121a87673f..794b044eae2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html
index 5b097c7a377..155a0739754 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lib.sv.html
index b4f006d6c8d..49edc5de4a2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu.sv.html
index 2c443f1002e..037afd0b918 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html
index ca6f30557a3..c35cf185f0e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html
index 099a985f700..94f1e6692a3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html
index 4100fb991f9..81dcda9701b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html
index e621cea4827..be978b4fadf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html
index 29dfc98bc2d..b61ae828fe8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html
index 0ca7054dac0..9fa174f07e4 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html
index d7b37f850e0..be1bf9ee9fe 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html
index bc57d6aede0..2e8bdffe97b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html
index f40c4d95b8e..44d90625189 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html
index 7ab1efb1be6..5d266b9af88 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem.sv.html
index a18b0a1c3c8..93d4784c622 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem_if.sv.html
index 87a57eee316..72c12520d3b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html
index 4ca9ab9fc56..37f1a0dc48e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pmp.sv.html
index 785050317d9..453e439831a 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer.sv.html
index ddffbc4a987..3543709b96e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html
index 70e8a77e58d..589d81a9b67 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_mem_lib.sv.html
index e412f3bc5e3..618086691db 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_rvjtag_tap.v.html
index 7693d61996b..6c7b0fca055 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_unaligned_load_store_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index.html
index b41a14e72d0..a5ac297b4e3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html
index 3e9e62dba3c..777e149ff0c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html
index 3c2ea3a82b0..02f59be8f49 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html
index 4ce4a571879..68db2ac8b12 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html
index 5ed2e446b94..e2463139eac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html
index b51c9f06c03..f6e0922a407 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html
index 95e560d944b..5632bc92224 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html
index cb1771711d5..20ad1b56527 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html
index 86d478bdb67..4f64ab6fa6e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html
index ec37f3f510f..6018ffe3dde 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_beh_lib.sv.html
index 5df878aa4fb..2ccdaf11750 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html
index 03999be0dad..a4e01dc3bbf 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_mux.v.html
index 8d90c48942d..ec45e376b0e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_wrapper.v.html
index 4948753ffae..fb7067e9afb 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dbg.sv.html
index fd53bc66fcd..26c38789169 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec.sv.html
index 998a2fb082f..e741fe82e06 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_csr_equ_mu.svh.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_csr_equ_mu.svh.html
index c1464a489fe..36cc4ef7427 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_csr_equ_mu.svh.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_csr_equ_mu.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html
index fc2ce373522..1b44cd96d95 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html
index 952015688f0..4660bd0b3b1 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html
index f09ce05e4e4..4319e816f5e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html
index 763f6b71045..721360508ab 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html
index c8f46f483e3..e2d66c0129f 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html
index 306965a9b22..439e126a2af 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html
index 872d329eb58..1743ec96cba 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu.sv.html
index 93ab979b0c3..9d49aeb04f8 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html
index abaeed8b0b0..b26cef79df5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html
index fc45303edc4..02202796884 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html
index e4fdb26ae2b..d2fda4f50ff 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu.sv.html
index 21fa0eba2eb..c644a9d959b 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html
index cf7b0bc4904..97b244192d3 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html
index 34ac30df9e2..f8ff97d0682 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html
index 48529c8023e..ab8a7720c0c 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html
index ebc386acd67..febe03999f6 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html
index aff10ca4ed1..a69621d62d9 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html
index 098deb9678e..c0fca9723e2 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html
index 680b0557eb0..79a9bd75b64 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lib.sv.html
index f7074352dfc..905634abb03 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu.sv.html
index 4e4ec67da94..a1c96250991 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html
index 57579b38ca1..3184d009405 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html
index b39d4636c54..b29a3cba547 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html
index c5020399481..d4cf12b5858 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html
index f9e279a5081..a47bfa80e92 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html
index 15c8f441303..dda61be2360 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html
index 3aea24412a9..019bc840f5e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html
index 0f5b9f8f2a3..b7969181b2e 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html
index dfc7cbfbc88..bec2282f18d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html
index 8b5dfa0519a..7847d19c2e0 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html
index 47600676e2a..2089efed13d 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem.sv.html
index 59e61cc6bc4..d31a58bcbac 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem_if.sv.html
index 63f180cc16e..26fb39d68f5 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html
index c80ce9b7761..396e850b181 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pmp.sv.html
index 912a4cb43a2..569c767d487 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer.sv.html
index f620d7d0123..bed0dda6033 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html
index 09da1df7dc2..b1e452b6524 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_mem_lib.sv.html
index e83c9d10b23..a1107445184 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_rvjtag_tap.v.html
index 5ed24b7fed2..f78dfa83529 100644
--- a/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_riscv-dv_u_riscv_user_mode_rand_test/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index.html b/html/main/coverage_dashboard/all_test_pyuvm/index.html
index 4cc2fc5fc73..2ec02b71961 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design.html
index 179ffa60bef..98067f95df0 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dbg.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dbg.html
index 5bcc2de945a..f3177da9d37 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dbg.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dbg.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dec.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dec.html
index 827c135b286..c40676a047e 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dec.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dec.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dmi.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dmi.html
index 88a0d1edc37..5cf0ed19f7b 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dmi.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_dmi.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_exu.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_exu.html
index 094f83dbcb9..aecf9976f65 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_exu.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_exu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_ifu.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_ifu.html
index 8b0d8ce7568..bcc74df12cc 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_ifu.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_ifu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_include.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_include.html
index e29a2b56a1f..75a82a79a8e 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_include.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_include.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lib.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lib.html
index 72f81cfa3f5..6fac2ab70d8 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lib.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lib.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lsu.html b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lsu.html
index 7a58b8bd411..7cc73e06ff3 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lsu.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_Cores-VeeR-EL2_design_lsu.html
@@ -51,7 +51,7 @@
       
         Test Date:
         
-          19-09-2024
+          25-09-2024
         
         
         
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_beh_lib.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_beh_lib.sv.html
index 70735a6e3dc..ebad1eaf0c4 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_beh_lib.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_beh_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -521,7 +521,7 @@
      417              :    (
      418           48 :      input  logic                 clk,
      419            0 :      input  logic                 rst_l,
-     420            9 :      input  logic [WIDTH-1:0]     din,
+     420            6 :      input  logic [WIDTH-1:0]     din,
      421            0 :      output logic [WIDTH-1:0]     dout
      422              :      );
      423              : 
@@ -538,7 +538,7 @@
      434         1488 :      input  logic                 rawclk,
      435           62 :      input  logic                 clken,
      436            0 :      input  logic                 rst_l,
-     437            8 :      input  logic [WIDTH-1:0]     din,
+     437           10 :      input  logic [WIDTH-1:0]     din,
      438            0 :      output logic [WIDTH-1:0]     dout
      439              :      );
      440              : 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_jtag_to_core_sync.v.html b/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_jtag_to_core_sync.v.html
index 8b06b4de210..086c0aede36 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_jtag_to_core_sync.v.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_jtag_to_core_sync.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_mux.v.html b/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_mux.v.html
index 186a0a27d60..67bfc48de25 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_mux.v.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_mux.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_wrapper.v.html b/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_wrapper.v.html
index f8466a36f82..3026aabb336 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_wrapper.v.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_dmi_wrapper.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dbg.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dbg.sv.html
index 0398b124b3c..270bd2557b9 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dbg.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dbg.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec.sv.html
index 70f951a34ee..a774dfff17e 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -153,7 +153,7 @@
       49            0 :     input logic        rst_l,   // reset, active low
       50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
       51              : 
-      52            9 :     input logic        nmi_int,  // NMI pin
+      52            8 :     input logic        nmi_int,  // NMI pin
       53            0 :     input logic [31:1] nmi_vec,  // NMI vector, from pins
       54              : 
       55            0 :     input logic i_cpu_halt_req,  // Asynchronous Halt request to CPU
@@ -272,8 +272,8 @@
      168            0 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
      169              : 
      170            0 :     input logic mexintpend,  // External interrupt pending
-     171           13 :     input logic timer_int,   // Timer interrupt pending (from pin)
-     172           11 :     input logic soft_int,    // Software interrupt pending (from pin)
+     171            9 :     input logic timer_int,   // Timer interrupt pending (from pin)
+     172            9 :     input logic soft_int,    // Software interrupt pending (from pin)
      173              : 
      174            0 :     input logic [7:0] pic_claimid,  // PIC claimid
      175            0 :     input logic [3:0] pic_pl,       // PIC priv level
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_csr_equ_m.svh.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_csr_equ_m.svh.html
index aa723596f10..c68752ef850 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_csr_equ_m.svh.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_csr_equ_m.svh.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_decode_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_decode_ctl.sv.html
index 280c2644cad..47af5976b83 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_decode_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_decode_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_gpr_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_gpr_ctl.sv.html
index 2e53c992f14..95d1cfefa3b 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_gpr_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_gpr_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_ib_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_ib_ctl.sv.html
index 9db8056b048..be9b52fba16 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_ib_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_ib_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_pmp_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_pmp_ctl.sv.html
index 7d4a034051a..d8204936a59 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_pmp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_pmp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -248,10 +248,10 @@
      144              :    for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
      145              :       logic pmpaddr_lock;
      146              :       logic pmpaddr_lock_next;
-     147              :       assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)
-     148              :                                   ? (entry_lock_eff[entry_idx+1]
-     149              :                                      & pmp_pmpcfg[entry_idx+1].mode == TOR)
-     150              :                                   : 1'b0);
+     147              :       if (entry_idx+1 < pt.PMP_ENTRIES)
+     148              :          assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;
+     149              :       else
+     150              :          assign pmpaddr_lock_next = 1'b0;
      151              :       assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;
      152              :       assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
      153              :       rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_tlu_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_tlu_ctl.sv.html
index 5ea47c36916..d07e95ee05f 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_tlu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_tlu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -140,7 +140,7 @@
       36            0 :    input logic scan_mode,
       37              : 
       38            0 :    input logic [31:1] rst_vec, // reset vector, from core pins
-      39            9 :    input logic        nmi_int, // nmi pin
+      39            8 :    input logic        nmi_int, // nmi pin
       40            0 :    input logic [31:1] nmi_vec, // nmi vector
       41            0 :    input logic  i_cpu_halt_req,    // Asynchronous Halt request to CPU
       42            0 :    input logic  i_cpu_run_req,     // Asynchronous Restart request to CPU
@@ -262,8 +262,8 @@
      158            0 :    input logic       mhwakeup, // high priority external int, wakeup if halted
      159              : 
      160            0 :    input logic mexintpend, // external interrupt pending
-     161           13 :    input logic timer_int, // timer interrupt pending
-     162           11 :    input logic soft_int, // software interrupt pending
+     161            9 :    input logic timer_int, // timer interrupt pending
+     162            9 :    input logic soft_int, // software interrupt pending
      163              : 
      164            0 :    output logic o_cpu_halt_status, // PMU interface, halted
      165            0 :    output logic o_cpu_halt_ack, // halt req ack
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_trigger.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_trigger.sv.html
index db831ef6913..c9521ae8b9d 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dec_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dma_ctrl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dma_ctrl.sv.html
index 2a83c89721d..ef3956c2ee5 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dma_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_dma_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu.sv.html
index aa7c609b50e..f2259233e4f 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_alu_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_alu_ctl.sv.html
index 1268876aaca..c0cb06426f0 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_alu_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_alu_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_div_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_div_ctl.sv.html
index c1db942013d..2d1e291e785 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_div_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_div_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_mul_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_mul_ctl.sv.html
index 8aeceb2b3c7..d187e32a52f 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_mul_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_exu_mul_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu.sv.html
index 0eb63d1c83b..b05d397a95e 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_aln_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_aln_ctl.sv.html
index d50f25166a9..65a808fbc76 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_aln_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_aln_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_bp_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_bp_ctl.sv.html
index 2b6893f080b..4620a36c580 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_bp_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_bp_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_compress_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_compress_ctl.sv.html
index bf67184fea5..4e90ba4f0a4 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_compress_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_compress_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ic_mem.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ic_mem.sv.html
index 25e000948f4..b6a7152939b 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ic_mem.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ic_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_iccm_mem.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_iccm_mem.sv.html
index ba41448c892..c22a26078dc 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_iccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_iccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ifc_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ifc_ctl.sv.html
index 2e7e07f94b3..542ca096a3c 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ifc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_ifc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_mem_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_mem_ctl.sv.html
index e6f462360ef..d2cf94d5ee3 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_mem_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_ifu_mem_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lib.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lib.sv.html
index 4d8f5b20006..96d1c2fe29e 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lib.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu.sv.html
index 29ab111926d..dd0bf28b543 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_addrcheck.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_addrcheck.sv.html
index f9cf707c839..5d558a66598 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_addrcheck.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_addrcheck.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_buffer.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_buffer.sv.html
index c4cca41f186..1911c434952 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_buffer.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_buffer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_intf.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_intf.sv.html
index eac9d5b90d9..98094cc3478 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_intf.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_bus_intf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_clkdomain.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_clkdomain.sv.html
index b999dfb24da..1808284ae24 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_clkdomain.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_clkdomain.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_ctl.sv.html
index 040e6446036..8338e05ffdd 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_mem.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_mem.sv.html
index d204abccace..9a0fe9b5893 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_mem.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_dccm_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_ecc.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_ecc.sv.html
index d18d62d9099..c2a8bf35bd8 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_ecc.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_ecc.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_lsc_ctl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_lsc_ctl.sv.html
index 58ba8aa5040..a8eebe7a104 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_lsc_ctl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_lsc_ctl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_stbuf.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_stbuf.sv.html
index edb60605d96..e5dac247f19 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_stbuf.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_stbuf.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_trigger.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_trigger.sv.html
index dffa2a6ebd7..4239df062d8 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_trigger.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_lsu_trigger.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem.sv.html
index 6eb14bbb25f..d31d3f034f3 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem_if.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem_if.sv.html
index c221808e5c2..d4ffd6cda98 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem_if.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_mem_if.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pic_ctrl.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pic_ctrl.sv.html
index b8bc863d6e5..b7701f1f067 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pic_ctrl.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pic_ctrl.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -666,7 +666,7 @@
      562         1488 :                              input logic rawclk,
      563           62 :                              input logic clken,
      564            0 :                              input logic rst_l,
-     565            8 :                              input logic extintsrc_req ,
+     565           10 :                              input logic extintsrc_req ,
      566            0 :                              input logic meigwctrl_polarity ,
      567            0 :                              input logic meigwctrl_type ,
      568            0 :                              input logic meigwclr ,
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pmp.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pmp.sv.html
index ca51fbe3331..306e90cb89e 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pmp.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_pmp.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer.sv.html
index 5912f9a7621..b4cd0454157 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -134,7 +134,7 @@
       30            0 :    input logic                  rst_l,
       31            0 :    input logic                  dbg_rst_l,
       32            0 :    input logic [31:1]           rst_vec,
-      33            9 :    input logic                  nmi_int,
+      33            8 :    input logic                  nmi_int,
       34            0 :    input logic [31:1]           nmi_vec,
       35            0 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
       36              : 
@@ -488,8 +488,8 @@
      384            0 :    output logic                 dccm_ecc_double_error,
      385              : 
      386            0 :    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
-     387           13 :    input logic                   timer_int,
-     388           11 :    input logic                   soft_int,
+     387            9 :    input logic                   timer_int,
+     388            9 :    input logic                   soft_int,
      389            0 :    input logic                   scan_mode
      390              : );
      391              : 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer_wrapper.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer_wrapper.sv.html
index 4bfd03df585..3a9c54fbe42 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer_wrapper.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_el2_veer_wrapper.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
@@ -135,7 +135,7 @@
       31            0 :    input logic                             rst_l,
       32            0 :    input logic                             dbg_rst_l,
       33            0 :    input logic [31:1]                      rst_vec,
-      34            9 :    input logic                             nmi_int,
+      34            8 :    input logic                             nmi_int,
       35            0 :    input logic [31:1]                      nmi_vec,
       36            0 :    input logic [31:1]                      jtag_id,
       37              : 
@@ -406,8 +406,8 @@
      302            0 :    input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
      303            0 :    input                                   el2_ic_tag_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
      304              : 
-     305           13 :    input logic                             timer_int,
-     306           11 :    input logic                             soft_int,
+     305            9 :    input logic                             timer_int,
+     306            9 :    input logic                             soft_int,
      307            0 :    input logic [pt.PIC_TOTAL_INT:1]        extintsrc_req,
      308              : 
      309            0 :    output logic                            dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_mem_lib.sv.html b/html/main/coverage_dashboard/all_test_pyuvm/index_mem_lib.sv.html
index 262e50b71b7..08d86c8a30c 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_mem_lib.sv.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_mem_lib.sv.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024
                 
                 
                 
diff --git a/html/main/coverage_dashboard/all_test_pyuvm/index_rvjtag_tap.v.html b/html/main/coverage_dashboard/all_test_pyuvm/index_rvjtag_tap.v.html
index bd6f2269221..2bdb4703030 100644
--- a/html/main/coverage_dashboard/all_test_pyuvm/index_rvjtag_tap.v.html
+++ b/html/main/coverage_dashboard/all_test_pyuvm/index_rvjtag_tap.v.html
@@ -51,7 +51,7 @@
             
                 Test Date:
                 
-                    19-09-2024
+                    25-09-2024