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exclude signals from coverage: propagate form axi4_to_ahb.sv
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@wsipak
wsipak committed Oct 4, 2024
1 parent cc36216 commit 3c44036
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6 changes: 6 additions & 0 deletions design/el2_veer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -374,8 +374,11 @@ import el2_pkg::*;

//// AHB LITE BUS
output logic [31:0] haddr,
/* exclude signals that are tied to constant value in axi4_to_ahb.sv */
/*verilator coverage_off*/
output logic [2:0] hburst,
output logic hmastlock,
/*verilator coverage_on*/
output logic [3:0] hprot,
output logic [2:0] hsize,
output logic [1:0] htrans,
Expand Down Expand Up @@ -404,8 +407,11 @@ import el2_pkg::*;

//System Bus Debug Master
output logic [31:0] sb_haddr,
/* exclude signals that are tied to constant value in axi4_to_ahb.sv */
/*verilator coverage_off*/
output logic [2:0] sb_hburst,
output logic sb_hmastlock,
/*verilator coverage_on*/
output logic [3:0] sb_hprot,
output logic [2:0] sb_hsize,
output logic [1:0] sb_htrans,
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9 changes: 9 additions & 0 deletions design/el2_veer_wrapper.sv
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Expand Up @@ -294,8 +294,11 @@ import el2_pkg::*;
`ifdef RV_BUILD_AHB_LITE
//// AHB LITE BUS

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Raw Output:
design/el2_veer_wrapper.sv:295:- //// AHB LITE BUS
design/el2_veer_wrapper.sv:296:-   output logic [31:0]                     haddr,
design/el2_veer_wrapper.sv:297:-   /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
design/el2_veer_wrapper.sv:298:-   /*verilator coverage_off*/
design/el2_veer_wrapper.sv:299:-   output logic [2:0]                      hburst,
design/el2_veer_wrapper.sv:300:-   output logic                            hmastlock,
design/el2_veer_wrapper.sv:301:-   /*verilator coverage_on*/
design/el2_veer_wrapper.sv:302:-   output logic [3:0]                      hprot,
design/el2_veer_wrapper.sv:303:-   output logic [2:0]                      hsize,
design/el2_veer_wrapper.sv:304:-   output logic [1:0]                      htrans,
design/el2_veer_wrapper.sv:305:-   output logic                            hwrite,
design/el2_veer_wrapper.sv:306:-
design/el2_veer_wrapper.sv:307:-   input logic [63:0]                      hrdata,
design/el2_veer_wrapper.sv:308:-   input logic                             hready,
design/el2_veer_wrapper.sv:309:-   input logic                             hresp,
design/el2_veer_wrapper.sv:310:-
design/el2_veer_wrapper.sv:311:-   // LSU AHB Master
design/el2_veer_wrapper.sv:312:-   output logic [31:0]                     lsu_haddr,
design/el2_veer_wrapper.sv:313:-   /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
design/el2_veer_wrapper.sv:314:-   /*verilator coverage_off*/
design/el2_veer_wrapper.sv:315:-   output logic [2:0]                      lsu_hburst,
design/el2_veer_wrapper.sv:316:-   output logic                            lsu_hmastlock,
design/el2_veer_wrapper.sv:317:-   /*verilator coverage_on*/
design/el2_veer_wrapper.sv:318:-   output logic [3:0]                      lsu_hprot,
design/el2_veer_wrapper.sv:319:-   output logic [2:0]                      lsu_hsize,
design/el2_veer_wrapper.sv:320:-   output logic [1:0]                      lsu_htrans,
design/el2_veer_wrapper.sv:321:-   output logic                            lsu_hwrite,
design/el2_veer_wrapper.sv:322:-   output logic [63:0]                     lsu_hwdata,
design/el2_veer_wrapper.sv:323:-
design/el2_veer_wrapper.sv:324:-   input logic [63:0]                      lsu_hrdata,
design/el2_veer_wrapper.sv:325:-   input logic                             lsu_hready,
design/el2_veer_wrapper.sv:326:-   input logic                             lsu_hresp,
design/el2_veer_wrapper.sv:327:-   // Debug Syster Bus AHB
design/el2_veer_wrapper.sv:328:-   output logic [31:0]                     sb_haddr,
design/el2_veer_wrapper.sv:329:-   /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
design/el2_veer_wrapper.sv:330:-   /*verilator coverage_off*/
design/el2_veer_wrapper.sv:331:-   output logic [2:0]                      sb_hburst,
design/el2_veer_wrapper.sv:332:-   output logic                            sb_hmastlock,
design/el2_veer_wrapper.sv:333:-   /*verilator coverage_on*/
design/el2_veer_wrapper.sv:334:-   output logic [3:0]                      sb_hprot,
design/el2_veer_wrapper.sv:335:-   output logic [2:0]                      sb_hsize,
design/el2_veer_wrapper.sv:336:-   output logic [1:0]                      sb_htrans,
design/el2_veer_wrapper.sv:337:-   output logic                            sb_hwrite,
design/el2_veer_wrapper.sv:338:-   output logic [63:0]                     sb_hwdata,
design/el2_veer_wrapper.sv:339:-
design/el2_veer_wrapper.sv:340:-   input  logic [63:0]                     sb_hrdata,
design/el2_veer_wrapper.sv:341:-   input  logic                            sb_hready,
design/el2_veer_wrapper.sv:342:-   input  logic                            sb_hresp,
design/el2_veer_wrapper.sv:343:-
design/el2_veer_wrapper.sv:344:-   // DMA Slave
design/el2_veer_wrapper.sv:345:-   input logic                             dma_hsel,
design/el2_veer_wrapper.sv:346:-   input logic [31:0]                      dma_haddr,
design/el2_veer_wrapper.sv:347:-   input logic [2:0]
output logic [31:0] haddr,
/* exclude signals that are tied to constant value in axi4_to_ahb.sv */
/*verilator coverage_off*/
output logic [2:0] hburst,
output logic hmastlock,
/*verilator coverage_on*/
output logic [3:0] hprot,
output logic [2:0] hsize,
output logic [1:0] htrans,
Expand All @@ -307,8 +310,11 @@ import el2_pkg::*;

// LSU AHB Master
output logic [31:0] lsu_haddr,
/* exclude signals that are tied to constant value in axi4_to_ahb.sv */
/*verilator coverage_off*/
output logic [2:0] lsu_hburst,
output logic lsu_hmastlock,
/*verilator coverage_on*/
output logic [3:0] lsu_hprot,
output logic [2:0] lsu_hsize,
output logic [1:0] lsu_htrans,
Expand All @@ -320,8 +326,11 @@ import el2_pkg::*;
input logic lsu_hresp,
// Debug Syster Bus AHB
output logic [31:0] sb_haddr,
/* exclude signals that are tied to constant value in axi4_to_ahb.sv */
/*verilator coverage_off*/
output logic [2:0] sb_hburst,
output logic sb_hmastlock,
/*verilator coverage_on*/
output logic [3:0] sb_hprot,
output logic [2:0] sb_hsize,
output logic [1:0] sb_htrans,
Expand Down

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