From d63c76ddd2e40e85f5ea9e310eb7ce71cb7a9035 Mon Sep 17 00:00:00 2001
From: Wojciech Sipak <wsipak@antmicro.com>
Date: Thu, 3 Oct 2024 17:47:46 +0200
Subject: [PATCH] el2_veer_wrapper: propagate excluding signals from el2_dbg.sv
 [skip ci]

The signals are excluded from coverage in el2_dbg.sv,
we need to exclude them here, too.

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
---
 design/el2_veer_wrapper.sv | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv
index d34b97ab96c..d4cd2d42885 100644
--- a/design/el2_veer_wrapper.sv
+++ b/design/el2_veer_wrapper.sv
@@ -144,16 +144,25 @@ import el2_pkg::*;
    // AXI Write Channels
    output logic                            sb_axi_awvalid,
    input  logic                            sb_axi_awready,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic [pt.SB_BUS_TAG-1:0]        sb_axi_awid,
+   /*verilator coverage_on*/
    output logic [31:0]                     sb_axi_awaddr,
    output logic [3:0]                      sb_axi_awregion,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic [7:0]                      sb_axi_awlen,
+   /*verilator coverage_on*/
    output logic [2:0]                      sb_axi_awsize,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic [1:0]                      sb_axi_awburst,
    output logic                            sb_axi_awlock,
    output logic [3:0]                      sb_axi_awcache,
    output logic [2:0]                      sb_axi_awprot,
    output logic [3:0]                      sb_axi_awqos,
+   /*verilator coverage_on*/
 
    output logic                            sb_axi_wvalid,
    input  logic                            sb_axi_wready,
@@ -169,19 +178,31 @@ import el2_pkg::*;
    // AXI Read Channels
    output logic                            sb_axi_arvalid,
    input  logic                            sb_axi_arready,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic [pt.SB_BUS_TAG-1:0]        sb_axi_arid,
+   /*verilator coverage_on*/
    output logic [31:0]                     sb_axi_araddr,
    output logic [3:0]                      sb_axi_arregion,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic [7:0]                      sb_axi_arlen,
+   /*verilator coverage_on*/
    output logic [2:0]                      sb_axi_arsize,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic [1:0]                      sb_axi_arburst,
    output logic                            sb_axi_arlock,
    output logic [3:0]                      sb_axi_arcache,
    output logic [2:0]                      sb_axi_arprot,
    output logic [3:0]                      sb_axi_arqos,
+   /*verilator coverage_on*/
 
    input  logic                            sb_axi_rvalid,
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    output logic                            sb_axi_rready,
+   /*verilator coverage_on*/
    input  logic [pt.SB_BUS_TAG-1:0]        sb_axi_rid,
    input  logic [63:0]                     sb_axi_rdata,
    input  logic [1:0]                      sb_axi_rresp,
@@ -623,10 +644,16 @@ import el2_pkg::*;
    // AXI Write Channels
    wire                            sb_axi_awvalid;
    wire                            sb_axi_awready;
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    wire [pt.SB_BUS_TAG-1:0]        sb_axi_awid;
+   /*verilator coverage_on*/
    wire [31:0]                     sb_axi_awaddr;
    wire [3:0]                      sb_axi_awregion;
+   /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
+   /*verilator coverage_off*/
    wire [7:0]                      sb_axi_awlen;
+   /*verilator coverage_on*/
    wire [2:0]                      sb_axi_awsize;
    wire [1:0]                      sb_axi_awburst;
    wire                            sb_axi_awlock;