v1.0.0

First release of the open source OmniXtend endpoint.

• AXI memory controllers (e.g., DDR 4/5, HBM).
• Full Tilelink 1.8.0 feature set.
• Variable length requests.
• Multiple TileLink messages per Ethernet frame.
• Written in Bluespec.
• Compiles to Verilog, usable in most Hardware tool flows.

We provide four different versions of the endpoint in Verilog:

• OmniXtend 1.0.3 with BRAM intended for simulation. One message per frame and 1500 Byte maximum frame size.
• OmniXtend 1.1 with BRAM intended for simulation. Up to 64 message per frame and 9000 Byte maximum frame size.
• OmniXtend 1.0.3 with AXI interface intended for FPGA/ASIC. One message per frame and 1500 Byte maximum frame size.
• OmniXtend 1.1 with AXI interface intended for FPGA/ASIC. Up to 64 message per frame and 9000 Byte maximum frame size.