Merge pull request #3802 from alainmarcel/alainmarcel-patch-1

unsized bug

CMakeLists.txt

@@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
 # Version changes whenever some new features accumulated, or the
 # grammar or the cache format changes to make sure caches
 # are invalidated.
-project(SURELOG VERSION 1.72)
+project(SURELOG VERSION 1.73)
 
 # Detect build type, fallback to release and throw a warning if use didn't
 # specify any

tests/BitSelectPartSelectInFunction/BitSelectPartSelectInFunction.sl

@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin

tests/BitSelectPartSelectInFunction/dut.sv

@@ -0,0 +1,14 @@
+module top(output int o);
+   typedef logic [4:0][1:0] box_t;
+
+   assign o = int'(iota('1));
+
+   function automatic logic [1:0] iota(box_t state);
+      box_t result;
+      result[0][1:0] = state[0][1:0];
+      return result[0];
+   endfunction : iota
+
+endmodule
+
+

third_party/tests/CoresSweRVMP/CoresSweRVMP.log

@@ -11,7 +11,7 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
   CMake that the project does not need compatibility with older versions.
 
 
--- Configuring done (0.0s)
+-- Configuring done (0.1s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser
 [100%] Generating preprocessing
@@ -134,18 +134,18 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
 -- Configuring done (0.0s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[  6%] Generating 11_ifu_bp_ctl.sv
-[ 12%] Generating 10_lsu_bus_intf.sv
-[ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 13_ifu_mem_ctl.sv
+[  6%] Generating 10_lsu_bus_intf.sv
+[ 12%] Generating 12_beh_lib.sv
+[ 18%] Generating 13_ifu_mem_ctl.sv
+[ 25%] Generating 11_ifu_bp_ctl.sv
 [ 31%] Generating 14_mem_lib.sv
 [ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
-[ 56%] Generating 1_lsu_stbuf.sv
+[ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
 [ 62%] Generating 3_rvjtag_tap.sv
-[ 68%] Generating 5_lsu_bus_buffer.sv
-[ 75%] Generating 4_dec_tlu_ctl.sv
+[ 68%] Generating 4_dec_tlu_ctl.sv
+[ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
 [ 87%] Generating 7_axi4_to_ahb.sv
 [ 93%] Generating 8_ifu_aln_ctl.sv