Create SystemVerilog Constraints Model

[alaindargelas]

Capture all the objects, classes, groups pertinent to the SystemVerilog Constraints in the yaml format.
Create UHDM unit tests (C++) showing proper representation of common constraints constructs (Use existing unit tests as reference, or use Google UnitTest framework to capture unit tests).

[alaindargelas]

In https://github.com/alainmarcel/UHDM, read:
README.md
UHDM Presentation
How to create the model (presentation)
Use the following material to ensure compliance to the standard:
Verilog_Object_Model.pdf - Object Model section of the the standard
SystemVerilog 2017 - The standard
includes/vpi_user.h - The VPI Interface
includes/sv_vpi_user.h - The SystemVerilog extensions to the VPI Interface