User/dev/kupadhyayula/ntt masking

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-214c0b1444725dc142a4361e20d2d37423221cc10eda63949e445a2a06f3f8f61abeb3d4d18dd6fc0a2618cd920e4a51
+61ff2cd5f5fc580fa4d885c8026ab0a4e3bb62ffd6a16b562da228e85b6af89fc13267658403e2388a14cad520c74d34

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1731643612
+1732130263

src/abr_libs/config/abr_libs.vf

@@ -17,11 +17,17 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv

src/abr_libs/config/compile.yml

@@ -21,11 +21,16 @@ targets:
       - $COMPILE_ROOT/rtl/abr_ahb_defines_pkg.sv
       - $COMPILE_ROOT/rtl/abr_ahb_slv_sif.sv
       - $COMPILE_ROOT/rtl/abr_masked_AND.sv
+      - $COMPILE_ROOT/rtl/abr_delay_masked_shares.sv
+      - $COMPILE_ROOT/rtl/abr_masked_add_sub_mod_Boolean.sv
+      - $COMPILE_ROOT/rtl/abr_masked_MUX.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_sub.sv
       - $COMPILE_ROOT/rtl/abr_masked_full_adder.sv
       - $COMPILE_ROOT/rtl/abr_masked_A2B_conv.sv
       - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_adder.sv
       - $COMPILE_ROOT/rtl/abr_masked_B2A_conv.sv
       - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult_two_share.sv
       - $COMPILE_ROOT/rtl/abr_adder.sv
       - $COMPILE_ROOT/rtl/abr_add_sub_mod.sv
   rtl:
@@ -45,11 +50,17 @@ targets:
       - $COMPILE_ROOT/rtl/abr_ahb_defines_pkg.sv
       - $COMPILE_ROOT/rtl/abr_ahb_slv_sif.sv
       - $COMPILE_ROOT/rtl/abr_masked_AND.sv
+      - $COMPILE_ROOT/rtl/abr_delay_masked_shares.sv
+      - $COMPILE_ROOT/rtl/abr_masked_add_sub_mod_Boolean.sv
+      - $COMPILE_ROOT/rtl/abr_masked_MUX.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_sub.sv
       - $COMPILE_ROOT/rtl/abr_masked_full_adder.sv
       - $COMPILE_ROOT/rtl/abr_masked_A2B_conv.sv
       - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_adder.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_Arith_adder.sv
       - $COMPILE_ROOT/rtl/abr_masked_B2A_conv.sv
       - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult_two_share.sv
       - $COMPILE_ROOT/rtl/abr_adder.sv
       - $COMPILE_ROOT/rtl/abr_add_sub_mod.sv
 ---
@@ -60,20 +71,26 @@ targets:
     directories: [$COMPILE_ROOT/rtl]
     files:
       - $COMPILE_ROOT/rtl/abr_masked_AND.sv
+      - $COMPILE_ROOT/rtl/abr_delay_masked_shares.sv
+      - $COMPILE_ROOT/rtl/abr_masked_add_sub_mod_Boolean.sv
+      - $COMPILE_ROOT/rtl/abr_masked_MUX.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_sub.sv
       - $COMPILE_ROOT/rtl/abr_masked_full_adder.sv
       - $COMPILE_ROOT/rtl/abr_masked_A2B_conv.sv
       - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_adder.sv
       - $COMPILE_ROOT/rtl/abr_masked_B2A_conv.sv
       - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult.sv
+      - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult_two_share.sv
   tb:
     directories: [$COMPILE_ROOT/tb]
     files:
       - $COMPILE_ROOT/tb/abr_masked_A2B_conv_tb.sv
       - $COMPILE_ROOT/tb/abr_masked_N_bit_Boolean_adder_tb.sv
       - $COMPILE_ROOT/tb/abr_masked_B2A_conv_tb.sv
       - $COMPILE_ROOT/tb/abr_masked_N_bit_mult_tb.sv
+      - $COMPILE_ROOT/tb/abr_masked_N_bit_mult_two_share_tb.sv
 
-    tops: [abr_masked_N_bit_mult_tb]
+    tops: [abr_masked_N_bit_mult_two_share_tb]
 ---
 provides: [mldsa_uvm_lib]
 schema_version: 2.4.0

src/abr_libs/config/masking_tb.vf

@@ -4,9 +4,15 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv

src/abr_libs/rtl/abr_delay_masked_shares.sv

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// abr_delay_masked_shares
+// Buffers the masked shares for the N cycle
+//======================================================================
+
+module abr_delay_masked_shares
+#(
+    parameter WIDTH = 46,  // Width of the input array
+    parameter N = 5        // Number of cycles to delay
+)
+(
+    input  wire clk,
+    input  wire rst_n,
+    input  wire zeroize,
+    input  wire [1:0] input_reg [WIDTH-1:0], // Input signal
+    output logic [1:0] delayed_reg [WIDTH-1:0] // Delayed output
+);
+
+    // Create an array of shift registers to store the delayed values
+    logic [N-1:0][WIDTH-1:0][1:0] shift_reg ;
+
+    // Use an always_ff block to implement the shift register
+    always_ff @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            // Reset all shift register values to 0
+            for (int j = 0; j < N; j = j + 1) begin
+                shift_reg[j] <= '0;
+            end
+        end
+        else if (zeroize) begin
+            // Reset all shift register values to 0
+            for (int j = 0; j < N; j = j + 1) begin
+                shift_reg[j] <= '0;
+            end
+        end
+        else begin
+            // Shift the values through the registers
+            for (int j = 0; j < N-1; j = j + 1) begin
+                shift_reg[j+1] <= shift_reg[j];
+            end
+
+            // Load the input values into the first shift register stage
+            for (int i = 0; i < WIDTH; i = i + 1) begin
+                shift_reg[0][i] <= input_reg[i];
+            end
+        end
+    end
+
+    // Assign the output to the last stage of the shift register
+    always_comb begin
+        for (int i = 0; i < WIDTH; i = i + 1) begin
+            delayed_reg[i] = shift_reg[N-1][i];
+        end
+    end
+
+endmodule: abr_delay_masked_shares

src/abr_libs/rtl/abr_masked_A2B_conv.sv

@@ -42,11 +42,11 @@
 );
 
     // Internal signals
-    logic [1:0] carry [WIDTH:0]; // Carry signals for each stage
-    logic [1:0] sum [WIDTH-1:0]; // Sum signals for each stage
-    logic [1:0] x_reg [WIDTH-1:0][WIDTH-1:0]; // Pipeline registers for x
-    logic [1:0] y_reg [WIDTH-1:0][WIDTH-1:0]; // Pipeline registers for y
-    logic [1:0] sum_reg [WIDTH-1:0][WIDTH-1:0]; // Pipeline registers for sum
+    logic  [WIDTH:0] [1:0] carry; // Carry signals for each stage
+    logic  [WIDTH-1:0] [1:0] sum; // Sum signals for each stage
+    logic  [WIDTH-1:0][WIDTH-1:0][1:0] x_reg; // Pipeline registers for x
+    logic  [WIDTH-1:0][WIDTH-1:0][1:0] y_reg; // Pipeline registers for y
+    logic  [WIDTH-1:0][WIDTH-1:0][1:0] sum_reg; // Pipeline registers for sum
     logic [1:0] the_last_sum;
 
     // Initialize the first carry input to 0
@@ -59,16 +59,12 @@
             // Pipeline registers for x and y inputs
             always_ff @(posedge clk or negedge rst_n) begin
                 if (!rst_n) begin
-                    for (int j = 0; j < WIDTH; j = j + 1) begin
-                        x_reg[i][j] <= 2'b00;
-                        y_reg[i][j] <= 2'b00;
-                    end
+                    x_reg[i] <= '0;
+                    y_reg[i] <= '0;
                 end
                 else if (zeroize) begin
-                    for (int j = 0; j < WIDTH; j = j + 1) begin
-                        x_reg[i][j] <= 2'b00;
-                        y_reg[i][j] <= 2'b00;
-                    end
+                    x_reg[i] <= '0;
+                    y_reg[i] <= '0;
                 end
                 else begin
                     for (int j = 0; j < WIDTH; j = j + 1) begin
@@ -87,14 +83,10 @@
             // Pipeline registers for sum output
             always_ff @(posedge clk or negedge rst_n) begin
                 if (!rst_n) begin
-                    for (int j = 0; j < WIDTH; j = j + 1) begin
-                        sum_reg[i][j] <= 2'b00;
-                    end
+                    sum_reg[i] <= '0;
                 end
                 else if (zeroize) begin
-                    for (int j = 0; j < WIDTH; j = j + 1) begin
-                        sum_reg[i][j] <= 2'b00;
-                    end
+                    sum_reg[i] <= '0;
                 end
                 else begin
                     for (int j = i; j < WIDTH; j = j + 1) begin
@@ -116,8 +108,8 @@
                     .clk(clk),              // Connect clk to clk
                     .rst_n(rst_n),          // Connect rst_n to rst_n
                     .zeroize(zeroize),      // Connect zeroize to zeroize
-                    .x(x_reg[i][i]),  // Connect x to the last stage of the x pipeline
-                    .y(y_reg[i][i]),  // Connect y to the last stage of the y pipeline
+                    .x(x_reg[i][i]),        // Connect x to the last stage of the x pipeline
+                    .y(y_reg[i][i]),        // Connect y to the last stage of the y pipeline
                     .c_in(carry[i]),        // Connect c_in to carry[i]
                     .rnd(rnd[i]),           // Connect rnd to corresponding random bit
                     .s(sum[i]),             // Connect sum to sum[i]

src/abr_libs/rtl/abr_masked_B2A_conv.sv

@@ -30,7 +30,7 @@
 //    outputs A and r.
 //
 //======================================================================
-
+`define DEBUG_MASKING 1
  module abr_masked_B2A_conv #(
     parameter WIDTH = 8 // Default width is 8 bits
 )(
@@ -48,6 +48,20 @@
     logic unsigned [1:0]       x_arith_next [WIDTH-1:0];
     wire [WIDTH-1:0]   Gamma;
     assign Gamma = rnd;
+`ifdef DEBUG_MASKING
+    logic [WIDTH-1:0] actual_input, actual_input0, actual_input1, exp_output, actual_output;
+    always_comb begin
+        for (int i = 0; i < WIDTH; i++) begin
+            actual_input[i] = x_boolean[i][0] ^ x_boolean[i][1];
+        end
+        exp_output = actual_input1;
+    end
+    always_ff @(posedge clk) begin
+        actual_input0 <= actual_input;
+        actual_input1 <= actual_input0;
+        actual_output <= A2 + x1;
+    end
+`endif
 
      // Register inputs
     always_ff @ (posedge clk or negedge rst_n) begin            
@@ -80,16 +94,16 @@
     // Combinational logic
     always_comb begin
 
-            T0               = x0 ^ Gamma_reg;           // T = x' ⊕ Γ
-            T1               = T0 - Gamma_reg;            // T = T - Γ
-            T2               = T1 ^ x0;                   // T = T ⊕ x'
-            Gamma_reg2       = Gamma_reg ^ x1;           // Γ = Γ ⊕ r
-            A0               = x0 ^ Gamma_reg2;          // A = x' ⊕ Γ
-            A1               = A0 - Gamma_reg2;           // A = A - Γ
-            A2               = A1 ^ T2;                    // A = A ⊕ T
+            T0               = x0 ^ Gamma_reg;              // T = x' ⊕ Γ
+            T1               = T0 - Gamma_reg;              // T = T - Γ
+            T2               = T1 ^ x0;                     // T = T ⊕ x'
+            Gamma_reg2       = Gamma_reg ^ x1;              // Γ = Γ ⊕ r
+            A0               = x0 ^ Gamma_reg2;             // A = x' ⊕ Γ
+            A1               = A0 - Gamma_reg2;             // A = A - Γ
+            A2               = A1 ^ T2;                     // A = A ⊕ T
         for (int i = 0; i < WIDTH; i++) begin
-            x_arith_next[i][0]  = A2[i];                  // Assign A to the output
-            x_arith_next[i][1]  = x1[i];                 // Assign r to the output
+            x_arith_next[i][0]  = A2[i];                    // Assign A to the output
+            x_arith_next[i][1]  = x1[i];                    // Assign r to the output
         end
     end