Maybe zbb instead of b

chipsalliance · Nov 25, 2024 · 9269929 · 9269929
1 parent 1cbb4b1
commit 9269929
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Showing 3 changed files with 3 additions and 5 deletions.
diff --git a/emulator/compliance-test/dut-plugin/sail_cSim/riscof_sail_cSim.py b/emulator/compliance-test/dut-plugin/sail_cSim/riscof_sail_cSim.py
@@ -99,8 +99,6 @@ def build(self, isa_yaml, platform_yaml):
             self.isa += 'f'
         if 'D' in ispec['ISA']:
             self.isa += 'd'
-        if 'B' in ispec['ISA']:
-            self.isa += 'b'
         if shutil.which(self.objdump_path) is None:
             logger.error(self.objdump_path + \
                 ': executable not found. Please check environment setup.')

diff --git a/emulator/compliance-test/dut-plugin/spike/riscof_spike.py b/emulator/compliance-test/dut-plugin/spike/riscof_spike.py
@@ -138,8 +138,8 @@ def build(self, isa_yaml, platform_yaml):
             self.isa += 'd'
         if 'C' in ispec['ISA']:
             self.isa += 'c'
-        if 'B' in ispec['ISA']:
-            self.isa += 'b'
+        if 'Zbb' in ispec['ISA']:
+            self.isa += '_zbb'
         if 'Zicsr' in ispec['ISA']:
             self.isa += '_zicsr'
         if 'Zifencei' in ispec['ISA']:

diff --git a/emulator/compliance-test/dut-plugin/spike/spike_isa.yaml b/emulator/compliance-test/dut-plugin/spike/spike_isa.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMCBUZicsr_Zifencei
+  ISA: RV32IMCUZbb_Zicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: "2.3"
   supported_xlen: [32]