From fb5dde19aa5001c8e23f0df15fa23e5dc73f51ce Mon Sep 17 00:00:00 2001 From: Kor Nielsen Date: Thu, 22 Feb 2024 15:35:08 -0800 Subject: [PATCH] Move hw-latest/{fpga,verilated} to hw/ Also, move hw-latest/caliptra-rtl to hw/latest/rtl. This is in preparation of moving the current caliptra-rtl submodule from hw/latest/rtl to hw/1.0/rtl, and replacing hw/latest/rtl with the 1.1 caliptra-rtl branch. --- .github/workflows/build-test-verilator.yml | 4 +-- .github/workflows/fpga.yml | 25 +++++++++--------- .github/workflows/nightly-release.yml | 2 +- .github/workflows/rtl-repo-sync.yml | 2 +- .gitmodules | 4 +-- Cargo.toml | 4 +-- README.md | 2 +- ci-tools/file-header-fix/src/main.rs | 2 ++ ci-tools/release/build_release.sh | 6 ++--- hw-model/c-binding/examples/Makefile | 2 +- {hw-latest => hw}/fpga/FPGA_Instructions.md | 4 +-- {hw-latest => hw}/fpga/fpga_configuration.tcl | 2 +- .../fpga/images/Caliptra_FPGA_PMOD_JTAG.svg | 0 .../fpga/images/zynq_boot_switch.jpg | Bin {hw-latest => hw}/fpga/io_module/.gitignore | 0 {hw-latest => hw}/fpga/io_module/Makefile | 0 {hw-latest => hw}/fpga/io_module/io_module.c | 0 {hw-latest => hw}/fpga/openocd_caliptra.txt | 0 .../fpga/rom_backdoor/.gitignore | 0 {hw-latest => hw}/fpga/rom_backdoor/Makefile | 0 .../fpga/rom_backdoor/rom_backdoor.c | 0 {hw-latest => hw}/fpga/src/axi4lite_intf.sv | 0 .../fpga/src/caliptra_fpga_realtime_regs.rdl | 0 .../fpga/src/caliptra_fpga_realtime_regs.sv | 0 .../src/caliptra_fpga_realtime_regs_pkg.sv | 0 .../fpga/src/caliptra_package_top.v | 0 .../fpga/src/caliptra_veer_sram_export.sv | 0 .../fpga/src/caliptra_wrapper_top.sv | 0 {hw-latest => hw}/fpga/src/constraints.xdc | 0 .../fpga/src/ecc_ram_tdp_file.sv | 0 {hw-latest => hw}/fpga/src/fpga_icg.sv | 0 {hw-latest => hw}/fpga/src/gen.sh | 0 .../fpga/src/jtag_constraints.xdc | 0 {hw-latest => hw}/fpga/src/kv_reg.sv | 0 hw-latest/caliptra-rtl => hw/latest/rtl | 0 {hw-latest => hw}/verilated/.gitignore | 0 {hw-latest => hw}/verilated/Cargo.toml | 0 {hw-latest => hw}/verilated/Makefile | 4 +-- {hw-latest => hw}/verilated/README.md | 2 +- {hw-latest => hw}/verilated/build.rs | 2 +- .../verilated/caliptra_verilated.cpp | 0 .../verilated/caliptra_verilated.h | 0 .../verilated/caliptra_verilated.sv | 0 .../verilated/generate_rust_bindings.sh | 0 .../verilated/src/bindings/mod.rs | 0 .../verilated/src/bindings/real.rs | 0 {hw-latest => hw}/verilated/src/lib.rs | 0 libcaliptra/Makefile | 2 +- libcaliptra/examples/generic/main.mk | 2 +- registers/README.md | 4 +-- registers/update.sh | 4 +-- 51 files changed, 40 insertions(+), 39 deletions(-) rename {hw-latest => hw}/fpga/FPGA_Instructions.md (98%) rename {hw-latest => hw}/fpga/fpga_configuration.tcl (99%) rename {hw-latest => hw}/fpga/images/Caliptra_FPGA_PMOD_JTAG.svg (100%) rename {hw-latest => hw}/fpga/images/zynq_boot_switch.jpg (100%) rename {hw-latest => hw}/fpga/io_module/.gitignore (100%) rename {hw-latest => hw}/fpga/io_module/Makefile (100%) rename {hw-latest => hw}/fpga/io_module/io_module.c (100%) rename {hw-latest => hw}/fpga/openocd_caliptra.txt (100%) rename {hw-latest => hw}/fpga/rom_backdoor/.gitignore (100%) rename {hw-latest => hw}/fpga/rom_backdoor/Makefile (100%) rename {hw-latest => hw}/fpga/rom_backdoor/rom_backdoor.c (100%) rename {hw-latest => hw}/fpga/src/axi4lite_intf.sv (100%) rename {hw-latest => hw}/fpga/src/caliptra_fpga_realtime_regs.rdl (100%) rename {hw-latest => hw}/fpga/src/caliptra_fpga_realtime_regs.sv (100%) rename {hw-latest => hw}/fpga/src/caliptra_fpga_realtime_regs_pkg.sv (100%) rename {hw-latest => hw}/fpga/src/caliptra_package_top.v (100%) rename {hw-latest => hw}/fpga/src/caliptra_veer_sram_export.sv (100%) rename {hw-latest => hw}/fpga/src/caliptra_wrapper_top.sv (100%) rename {hw-latest => hw}/fpga/src/constraints.xdc (100%) rename {hw-latest => hw}/fpga/src/ecc_ram_tdp_file.sv (100%) rename {hw-latest => hw}/fpga/src/fpga_icg.sv (100%) rename {hw-latest => hw}/fpga/src/gen.sh (100%) rename {hw-latest => hw}/fpga/src/jtag_constraints.xdc (100%) rename {hw-latest => hw}/fpga/src/kv_reg.sv (100%) rename hw-latest/caliptra-rtl => hw/latest/rtl (100%) rename {hw-latest => hw}/verilated/.gitignore (100%) rename {hw-latest => hw}/verilated/Cargo.toml (100%) rename {hw-latest => hw}/verilated/Makefile (95%) rename {hw-latest => hw}/verilated/README.md (92%) rename {hw-latest => hw}/verilated/build.rs (96%) rename {hw-latest => hw}/verilated/caliptra_verilated.cpp (100%) rename {hw-latest => hw}/verilated/caliptra_verilated.h (100%) rename {hw-latest => hw}/verilated/caliptra_verilated.sv (100%) rename {hw-latest => hw}/verilated/generate_rust_bindings.sh (100%) rename {hw-latest => hw}/verilated/src/bindings/mod.rs (100%) rename {hw-latest => hw}/verilated/src/bindings/real.rs (100%) rename {hw-latest => hw}/verilated/src/lib.rs (100%) diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml index 20fb694dd2..acbd65d47d 100644 --- a/.github/workflows/build-test-verilator.yml +++ b/.github/workflows/build-test-verilator.yml @@ -99,7 +99,7 @@ jobs: - name: Check that generated register code matches caliptra-rtl submodule run: | - cargo run --locked -p caliptra_registers_generator -- --check hw-latest/caliptra-rtl registers/bin/extra-rdl registers/src + cargo run --locked -p caliptra_registers_generator -- --check hw/latest/rtl registers/bin/extra-rdl registers/src - name: Build run: | @@ -117,7 +117,7 @@ jobs: export RUSTC_WRAPPER=~/.cargo/bin/sccache export CXX="sccache g++" (cd hw-model && cargo --config "$EXTRA_CARGO_CONFIG" test --locked --release --features verilator) - (cd hw-latest/verilated && cargo --config "$EXTRA_CARGO_CONFIG" test --locked --release --features verilator) + (cd hw/verilated && cargo --config "$EXTRA_CARGO_CONFIG" test --locked --release --features verilator) - name: Check source-code formatting (run "cargo fmt" if this fails) run: | diff --git a/.github/workflows/fpga.yml b/.github/workflows/fpga.yml index c6287dfce0..cec4b0db37 100644 --- a/.github/workflows/fpga.yml +++ b/.github/workflows/fpga.yml @@ -36,8 +36,7 @@ jobs: runs-on: ubuntu-22.04 env: - # Change this to a new random value if you suspect the cache is corrupted - CACHE_BUSTER: 9ff0db888988 + CACHE_BUSTER: 79cee50b6134 outputs: rtl_cache_key: ${{ steps.cache_key.outputs.rtl_cache_key }} @@ -54,11 +53,11 @@ jobs: - name: Compute cache-keys id: cache_key run: | - # Compute the key from the tree hash of the fpga directory and the caliptra-rtl + # Compute the key from the tree hash of the fpga directory and the rtl # root directory. - echo "rtl_cache_key=$(git rev-parse HEAD:hw-latest/fpga/src)-$(git hash-object hw-latest/fpga/fpga_configuration.tcl)-$(cd hw-latest/caliptra-rtl && git rev-parse HEAD:)-${{ inputs.fpga-itrng }}-${{ env.CACHE_BUSTER }}" >> $GITHUB_OUTPUT + echo "rtl_cache_key=$(git rev-parse HEAD:hw/fpga/src)-$(git hash-object hw/fpga/fpga_configuration.tcl)-$(cd hw/latest/rtl && git rev-parse HEAD:)-${{ inputs.fpga-itrng }}-${{ env.CACHE_BUSTER }}" >> $GITHUB_OUTPUT - echo "kmod_cache_key=fpga-kernel-modules-$(git rev-parse HEAD:hw-latest/fpga/io_module)-$(git rev-parse HEAD:hw-latest/fpga/rom_backdoor)-${{ env.CACHE_BUSTER }}" >> $GITHUB_OUTPUT + echo "kmod_cache_key=fpga-kernel-modules-$(git rev-parse HEAD:hw/fpga/io_module)-$(git rev-parse HEAD:hw/fpga/rom_backdoor)-${{ env.CACHE_BUSTER }}" >> $GITHUB_OUTPUT - name: Restore FPGA bitstream from cache uses: actions/cache/restore@v3 @@ -230,14 +229,14 @@ jobs: run: | SYSROOT="${GITHUB_WORKSPACE}/sysroot" KERNEL=5.15.0-1015-xilinx-zynqmp - sudo chroot "${SYSROOT}" bash -c "cd /home/${USER}/caliptra-sw/hw-latest/fpga/rom_backdoor && make KERNEL=${KERNEL}" - sudo chroot "${SYSROOT}" bash -c "cd /home/${USER}/caliptra-sw/hw-latest/fpga/io_module && make KERNEL=${KERNEL}" - sudo ls -l "${SYSROOT}/home/${USER}/caliptra-sw/hw-latest/fpga/io_module" - sudo ls -l "${SYSROOT}/home/${USER}/caliptra-sw/hw-latest/fpga/rom_backdoor" + sudo chroot "${SYSROOT}" bash -c "cd /home/${USER}/caliptra-sw/hw/fpga/rom_backdoor && make KERNEL=${KERNEL}" + sudo chroot "${SYSROOT}" bash -c "cd /home/${USER}/caliptra-sw/hw/fpga/io_module && make KERNEL=${KERNEL}" + sudo ls -l "${SYSROOT}/home/${USER}/caliptra-sw/hw/fpga/io_module" + sudo ls -l "${SYSROOT}/home/${USER}/caliptra-sw/hw/fpga/rom_backdoor" mkdir /tmp/caliptra-fpga-kmod - cp "${SYSROOT}/home/${USER}/caliptra-sw/hw-latest/fpga/io_module/io_module.ko" /tmp/caliptra-fpga-kmod/ - cp "${SYSROOT}/home/${USER}/caliptra-sw/hw-latest/fpga/rom_backdoor/rom_backdoor.ko" /tmp/caliptra-fpga-kmod/ + cp "${SYSROOT}/home/${USER}/caliptra-sw/hw/fpga/io_module/io_module.ko" /tmp/caliptra-fpga-kmod/ + cp "${SYSROOT}/home/${USER}/caliptra-sw/hw/fpga/rom_backdoor/rom_backdoor.ko" /tmp/caliptra-fpga-kmod/ - name: Save kernel modules to cache uses: actions/cache/save@v3 @@ -272,7 +271,7 @@ jobs: - name: Build FPGA bitstream run: | - cd hw-latest/fpga + cd hw/fpga mkdir caliptra_build if [ "${{ inputs.fpga-itrng }}" == "false" ]; then ITRNG=FALSE @@ -289,7 +288,7 @@ jobs: uses: actions/upload-artifact@v4 with: name: caliptra-fpga-bitstream${{ inputs.artifact-suffix }} - path: hw-latest/fpga/caliptra_build/caliptra_fpga.bin + path: hw/fpga/caliptra_build/caliptra_fpga.bin cache_fpga_bitstream_artifact: runs-on: ubuntu-22.04 diff --git a/.github/workflows/nightly-release.yml b/.github/workflows/nightly-release.yml index d58383b4d5..a690042bc0 100644 --- a/.github/workflows/nightly-release.yml +++ b/.github/workflows/nightly-release.yml @@ -44,7 +44,7 @@ jobs: while git tag | grep ${TAG_BASE}${INDEX}; do ((INDEX+=1)) done - git submodule update --remote hw-latest/caliptra-rtl + git submodule update --remote hw/latest/rtl CHECK_RELEASE_SYNC=$(git status --porcelain | head -1) MOST_RECENT_RELEASE=None if git tag | grep ${TAG_PREFIX} > /dev/null; then diff --git a/.github/workflows/rtl-repo-sync.yml b/.github/workflows/rtl-repo-sync.yml index 8f9345a58d..2fb7156de9 100644 --- a/.github/workflows/rtl-repo-sync.yml +++ b/.github/workflows/rtl-repo-sync.yml @@ -28,7 +28,7 @@ jobs: - name: Update the Caliptra RTL submodule and rebuild registers run: | echo "RTL-REPO-SYNC: release_ref=$(git rev-parse HEAD)" - git submodule update --remote hw-latest/caliptra-rtl + git submodule update --remote hw/latest/rtl ./registers/update.sh - name: Find available branch name diff --git a/.gitmodules b/.gitmodules index 661947b4d7..7f63f76352 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,8 @@ # Typical firmware development will not need this submodule. Future # commits should only use it when running verilated test cases or updating # the caliptra-registers crate. -[submodule "hw-latest/caliptra-rtl"] - path = hw-latest/caliptra-rtl +[submodule "hw/latest/rtl"] + path = hw/latest/rtl url = https://github.com/chipsalliance/caliptra-rtl branch = main [submodule "dpe"] diff --git a/Cargo.toml b/Cargo.toml index 78ee3710b4..00b2fb4fe0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -39,7 +39,7 @@ members = [ "drivers/test-fw/scripts/vector_gen", "fmc", "fmc/test-fw/test-rt", - "hw-latest/verilated", + "hw/verilated", "hw-model", "hw-model/test-fw", "hw-model/types", @@ -125,7 +125,7 @@ caliptra-systemrdl = { path = "systemrdl" } caliptra-test = { path = "test" } caliptra-test-harness = { path = "test-harness" } caliptra-test-harness-types = { path = "test-harness/types" } -caliptra-verilated = { path = "hw-latest/verilated", features = ["verilator"] } +caliptra-verilated = { path = "hw/verilated", features = ["verilator"] } caliptra-x509 = { path = "x509", default-features = false } cbc = "0.1.2" cbindgen = { version = "0.24.0", default-features = false } diff --git a/README.md b/README.md index 3f8cd9624b..c73e074bcf 100644 --- a/README.md +++ b/README.md @@ -90,7 +90,7 @@ high-fidelity simulation based on this environment can reveal bugs in the firmware, hardware, and the integration between the two. -If you don't have verilator 5.004 or later installed, follow [these directions](/hw-latest/verilated). +If you don't have verilator 5.004 or later installed, follow [these directions](/hw/verilated). To run all the tests in verilator (this will take several hours): diff --git a/ci-tools/file-header-fix/src/main.rs b/ci-tools/file-header-fix/src/main.rs index 3f3e89a11c..54597486e7 100644 --- a/ci-tools/file-header-fix/src/main.rs +++ b/ci-tools/file-header-fix/src/main.rs @@ -14,6 +14,8 @@ const IGNORED_PATHS: &[&str] = &[ "./sw-emulator/compliance-test/target-files/link.ld", "./runtime/dpe", "./hw-latest/fpga/caliptra_build", + "./hw/fpga/caliptra_build", + "./hw/latest/rtl", "./ci-tools/fpga-boss/image/mnt", "./ci-tools/fpga-image/out", ]; diff --git a/ci-tools/release/build_release.sh b/ci-tools/release/build_release.sh index bf9567bee2..e44850e9de 100755 --- a/ci-tools/release/build_release.sh +++ b/ci-tools/release/build_release.sh @@ -41,11 +41,11 @@ cp -a target/riscv32imc-unknown-none-elf/firmware/caliptra-fmc $WORKSPACE_DIR/fa cp -a target/riscv32imc-unknown-none-elf/firmware/caliptra-runtime $WORKSPACE_DIR/fake-caliptra-runtime.elf # Copy RTL -cp -rf hw-latest/caliptra-rtl $WORKSPACE_DIR/caliptra-rtl +cp -rf hw/latest/rtl $WORKSPACE_DIR/caliptra-rtl # Copy libcaliptra cp -rf libcaliptra $WORKSPACE_DIR/libcaliptra # Copy FPGA Model -cp -rf hw-latest/fpga $WORKSPACE_DIR/fpga +cp -rf hw/fpga $WORKSPACE_DIR/fpga # Calculate RTL hash # Generate file list (excluding files integrators will modify) @@ -64,7 +64,7 @@ cp $release_scripts_path/tools/rtl_hash.sh $WORKSPACE_DIR/ # Generate Notes echo -e "Caliptra HW Release Note " > $WORKSPACE_DIR/release_notes.txt echo -e "Nightly $1" >> $WORKSPACE_DIR/release_notes.txt -echo -e "Caliptra-RTL Rev: $(git rev-parse HEAD:hw-latest/caliptra-rtl)" >> $WORKSPACE_DIR/release_notes.txt +echo -e "Caliptra-RTL Rev: $(git rev-parse HEAD:hw/latest/rtl)" >> $WORKSPACE_DIR/release_notes.txt echo -e "Caliptra-SW Rev: $(git rev-parse HEAD)" >> $WORKSPACE_DIR/release_notes.txt echo -e "RTL hash (see rtl_hash.sh): $rtl_hash" >> $WORKSPACE_DIR/release_notes.txt echo -e "Content:" >> $WORKSPACE_DIR/release_notes.txt diff --git a/hw-model/c-binding/examples/Makefile b/hw-model/c-binding/examples/Makefile index 51e3d9d3c2..67af094a07 100644 --- a/hw-model/c-binding/examples/Makefile +++ b/hw-model/c-binding/examples/Makefile @@ -16,7 +16,7 @@ EXTRA_CARGO_CONFIG = target.'cfg(all())'.rustflags = [\"-Dwarnings\"] OUT = out TARGET = $(OUT)/smoke_test -RTL_SOC_IFC_INCLUDE_PATH = ../../../hw-latest/caliptra-rtl/src/soc_ifc/rtl +RTL_SOC_IFC_INCLUDE_PATH = ../../../hw/latest/rtl/src/soc_ifc/rtl BUILDER_PATH = ../../../builder CALIPTRA_MODEL_PATH = ../out CFLAGS += -I$(RTL_SOC_IFC_INCLUDE_PATH) -I$(CALIPTRA_MODEL_PATH) diff --git a/hw-latest/fpga/FPGA_Instructions.md b/hw/fpga/FPGA_Instructions.md similarity index 98% rename from hw-latest/fpga/FPGA_Instructions.md rename to hw/fpga/FPGA_Instructions.md index d6a648665f..f1dbb68e4b 100644 --- a/hw-latest/fpga/FPGA_Instructions.md +++ b/hw/fpga/FPGA_Instructions.md @@ -107,10 +107,10 @@ Serial port settings for connection over USB. - `sudo fpgautil -b caliptra_fpga_project_bd_wrapper.bin -f Full -n Full` 1. Insert kernel modules for IO access - As root: - - `cd hw-latest/fpga/rom_backdoor` + - `cd hw/fpga/rom_backdoor` - `make` - `insmod rom_backdoor.ko` - - `cd hw-latest/fpga/io_module` + - `cd hw/fpga/io_module` - `make` - `insmod io_module.ko` - `chmod 666 /dev/uio4` diff --git a/hw-latest/fpga/fpga_configuration.tcl b/hw/fpga/fpga_configuration.tcl similarity index 99% rename from hw-latest/fpga/fpga_configuration.tcl rename to hw/fpga/fpga_configuration.tcl index e5ff8033a8..f4cd063c0b 100644 --- a/hw-latest/fpga/fpga_configuration.tcl +++ b/hw/fpga/fpga_configuration.tcl @@ -10,7 +10,7 @@ file mkdir $packageDir file mkdir $adapterDir # Path to rtl -set rtlDir $fpgaDir/../caliptra-rtl +set rtlDir $fpgaDir/../latest/rtl # Simplistic processing of command line arguments to enable different features # Defaults: diff --git a/hw-latest/fpga/images/Caliptra_FPGA_PMOD_JTAG.svg b/hw/fpga/images/Caliptra_FPGA_PMOD_JTAG.svg similarity index 100% rename from hw-latest/fpga/images/Caliptra_FPGA_PMOD_JTAG.svg rename to hw/fpga/images/Caliptra_FPGA_PMOD_JTAG.svg diff --git a/hw-latest/fpga/images/zynq_boot_switch.jpg b/hw/fpga/images/zynq_boot_switch.jpg similarity index 100% rename from hw-latest/fpga/images/zynq_boot_switch.jpg rename to hw/fpga/images/zynq_boot_switch.jpg diff --git a/hw-latest/fpga/io_module/.gitignore b/hw/fpga/io_module/.gitignore similarity index 100% rename from hw-latest/fpga/io_module/.gitignore rename to hw/fpga/io_module/.gitignore diff --git a/hw-latest/fpga/io_module/Makefile b/hw/fpga/io_module/Makefile similarity index 100% rename from hw-latest/fpga/io_module/Makefile rename to hw/fpga/io_module/Makefile diff --git a/hw-latest/fpga/io_module/io_module.c b/hw/fpga/io_module/io_module.c similarity index 100% rename from hw-latest/fpga/io_module/io_module.c rename to hw/fpga/io_module/io_module.c diff --git a/hw-latest/fpga/openocd_caliptra.txt b/hw/fpga/openocd_caliptra.txt similarity index 100% rename from hw-latest/fpga/openocd_caliptra.txt rename to hw/fpga/openocd_caliptra.txt diff --git a/hw-latest/fpga/rom_backdoor/.gitignore b/hw/fpga/rom_backdoor/.gitignore similarity index 100% rename from hw-latest/fpga/rom_backdoor/.gitignore rename to hw/fpga/rom_backdoor/.gitignore diff --git a/hw-latest/fpga/rom_backdoor/Makefile b/hw/fpga/rom_backdoor/Makefile similarity index 100% rename from hw-latest/fpga/rom_backdoor/Makefile rename to hw/fpga/rom_backdoor/Makefile diff --git a/hw-latest/fpga/rom_backdoor/rom_backdoor.c b/hw/fpga/rom_backdoor/rom_backdoor.c similarity index 100% rename from hw-latest/fpga/rom_backdoor/rom_backdoor.c rename to hw/fpga/rom_backdoor/rom_backdoor.c diff --git a/hw-latest/fpga/src/axi4lite_intf.sv b/hw/fpga/src/axi4lite_intf.sv similarity index 100% rename from hw-latest/fpga/src/axi4lite_intf.sv rename to hw/fpga/src/axi4lite_intf.sv diff --git a/hw-latest/fpga/src/caliptra_fpga_realtime_regs.rdl b/hw/fpga/src/caliptra_fpga_realtime_regs.rdl similarity index 100% rename from hw-latest/fpga/src/caliptra_fpga_realtime_regs.rdl rename to hw/fpga/src/caliptra_fpga_realtime_regs.rdl diff --git a/hw-latest/fpga/src/caliptra_fpga_realtime_regs.sv b/hw/fpga/src/caliptra_fpga_realtime_regs.sv similarity index 100% rename from hw-latest/fpga/src/caliptra_fpga_realtime_regs.sv rename to hw/fpga/src/caliptra_fpga_realtime_regs.sv diff --git a/hw-latest/fpga/src/caliptra_fpga_realtime_regs_pkg.sv b/hw/fpga/src/caliptra_fpga_realtime_regs_pkg.sv similarity index 100% rename from hw-latest/fpga/src/caliptra_fpga_realtime_regs_pkg.sv rename to hw/fpga/src/caliptra_fpga_realtime_regs_pkg.sv diff --git a/hw-latest/fpga/src/caliptra_package_top.v b/hw/fpga/src/caliptra_package_top.v similarity index 100% rename from hw-latest/fpga/src/caliptra_package_top.v rename to hw/fpga/src/caliptra_package_top.v diff --git a/hw-latest/fpga/src/caliptra_veer_sram_export.sv b/hw/fpga/src/caliptra_veer_sram_export.sv similarity index 100% rename from hw-latest/fpga/src/caliptra_veer_sram_export.sv rename to hw/fpga/src/caliptra_veer_sram_export.sv diff --git a/hw-latest/fpga/src/caliptra_wrapper_top.sv b/hw/fpga/src/caliptra_wrapper_top.sv similarity index 100% rename from hw-latest/fpga/src/caliptra_wrapper_top.sv rename to hw/fpga/src/caliptra_wrapper_top.sv diff --git a/hw-latest/fpga/src/constraints.xdc b/hw/fpga/src/constraints.xdc similarity index 100% rename from hw-latest/fpga/src/constraints.xdc rename to hw/fpga/src/constraints.xdc diff --git a/hw-latest/fpga/src/ecc_ram_tdp_file.sv b/hw/fpga/src/ecc_ram_tdp_file.sv similarity index 100% rename from hw-latest/fpga/src/ecc_ram_tdp_file.sv rename to hw/fpga/src/ecc_ram_tdp_file.sv diff --git a/hw-latest/fpga/src/fpga_icg.sv b/hw/fpga/src/fpga_icg.sv similarity index 100% rename from hw-latest/fpga/src/fpga_icg.sv rename to hw/fpga/src/fpga_icg.sv diff --git a/hw-latest/fpga/src/gen.sh b/hw/fpga/src/gen.sh similarity index 100% rename from hw-latest/fpga/src/gen.sh rename to hw/fpga/src/gen.sh diff --git a/hw-latest/fpga/src/jtag_constraints.xdc b/hw/fpga/src/jtag_constraints.xdc similarity index 100% rename from hw-latest/fpga/src/jtag_constraints.xdc rename to hw/fpga/src/jtag_constraints.xdc diff --git a/hw-latest/fpga/src/kv_reg.sv b/hw/fpga/src/kv_reg.sv similarity index 100% rename from hw-latest/fpga/src/kv_reg.sv rename to hw/fpga/src/kv_reg.sv diff --git a/hw-latest/caliptra-rtl b/hw/latest/rtl similarity index 100% rename from hw-latest/caliptra-rtl rename to hw/latest/rtl diff --git a/hw-latest/verilated/.gitignore b/hw/verilated/.gitignore similarity index 100% rename from hw-latest/verilated/.gitignore rename to hw/verilated/.gitignore diff --git a/hw-latest/verilated/Cargo.toml b/hw/verilated/Cargo.toml similarity index 100% rename from hw-latest/verilated/Cargo.toml rename to hw/verilated/Cargo.toml diff --git a/hw-latest/verilated/Makefile b/hw/verilated/Makefile similarity index 95% rename from hw-latest/verilated/Makefile rename to hw/verilated/Makefile index b56d8c8458..5940d056c1 100644 --- a/hw-latest/verilated/Makefile +++ b/hw/verilated/Makefile @@ -15,7 +15,7 @@ VERILATOR = verilator VERILATED_DIR := $(dir $(realpath $(lastword $(MAKEFILE_LIST)))) -CALIPTRA_RTL_DIR := $(realpath $(VERILATED_DIR)../caliptra-rtl) +CALIPTRA_RTL_DIR := $(realpath $(VERILATED_DIR)../latest/rtl) CFLAGS := -std=c++11 -fno-exceptions -fPIC VERILATOR_MAKE_FLAGS = OPT_FAST="-Os" @@ -26,7 +26,7 @@ VERILATOR_OBJS = out/verilated_threads.o out/verilated.o out/verilated_vcd_c.o LIB_OBJS = out/caliptra_verilated.o -export CALIPTRA_ROOT = $(realpath ../caliptra-rtl) +export CALIPTRA_ROOT = $(realpath ../latest/rtl) suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED diff --git a/hw-latest/verilated/README.md b/hw/verilated/README.md similarity index 92% rename from hw-latest/verilated/README.md rename to hw/verilated/README.md index cc45b665b3..6d84493fb8 100644 --- a/hw-latest/verilated/README.md +++ b/hw/verilated/README.md @@ -22,7 +22,7 @@ sudo make install ```shell git submodule update --init" # Needed the first time -(cd hw-latest/verilated && cargo test --features verilator) +(cd hw/verilated && cargo test --features verilator) (cd hw-model && cargo test --features verilator) ``` diff --git a/hw-latest/verilated/build.rs b/hw/verilated/build.rs similarity index 96% rename from hw-latest/verilated/build.rs rename to hw/verilated/build.rs index 4ee325c8fe..365ba0588c 100644 --- a/hw-latest/verilated/build.rs +++ b/hw/verilated/build.rs @@ -46,7 +46,7 @@ fn add_filename(filename: &Path) -> impl FnOnce(std::io::Error) -> std::io::Erro fn sv_files(manifest_dir: &Path) -> Result, std::io::Error> { let mut result = vec![]; - let filename = manifest_dir.join("../caliptra-rtl/src/integration/config/caliptra_top_tb.vf"); + let filename = manifest_dir.join("../latest/rtl/src/integration/config/caliptra_top_tb.vf"); for line in BufReader::new(File::open(&filename).map_err(add_filename(&filename))?).lines() { let line = line?; if line.starts_with('+') { diff --git a/hw-latest/verilated/caliptra_verilated.cpp b/hw/verilated/caliptra_verilated.cpp similarity index 100% rename from hw-latest/verilated/caliptra_verilated.cpp rename to hw/verilated/caliptra_verilated.cpp diff --git a/hw-latest/verilated/caliptra_verilated.h b/hw/verilated/caliptra_verilated.h similarity index 100% rename from hw-latest/verilated/caliptra_verilated.h rename to hw/verilated/caliptra_verilated.h diff --git a/hw-latest/verilated/caliptra_verilated.sv b/hw/verilated/caliptra_verilated.sv similarity index 100% rename from hw-latest/verilated/caliptra_verilated.sv rename to hw/verilated/caliptra_verilated.sv diff --git a/hw-latest/verilated/generate_rust_bindings.sh b/hw/verilated/generate_rust_bindings.sh similarity index 100% rename from hw-latest/verilated/generate_rust_bindings.sh rename to hw/verilated/generate_rust_bindings.sh diff --git a/hw-latest/verilated/src/bindings/mod.rs b/hw/verilated/src/bindings/mod.rs similarity index 100% rename from hw-latest/verilated/src/bindings/mod.rs rename to hw/verilated/src/bindings/mod.rs diff --git a/hw-latest/verilated/src/bindings/real.rs b/hw/verilated/src/bindings/real.rs similarity index 100% rename from hw-latest/verilated/src/bindings/real.rs rename to hw/verilated/src/bindings/real.rs diff --git a/hw-latest/verilated/src/lib.rs b/hw/verilated/src/lib.rs similarity index 100% rename from hw-latest/verilated/src/lib.rs rename to hw/verilated/src/lib.rs diff --git a/libcaliptra/Makefile b/libcaliptra/Makefile index 242830bd21..7b1d6bd7cf 100644 --- a/libcaliptra/Makefile +++ b/libcaliptra/Makefile @@ -5,7 +5,7 @@ AR=$(CROSS_COMPILE)ar ifneq ($(MAKECMDGOALS),clean) ifndef RTL_SOC_IFC_INCLUDE_PATH -RTL_SOC_IFC_INCLUDE_PATH ?= ../hw-latest/caliptra-rtl/src/soc_ifc/rtl +RTL_SOC_IFC_INCLUDE_PATH ?= ../hw/latest/rtl/src/soc_ifc/rtl $(warning RTL_SOC_IFC_INCLUDE_PATH must be defined and point to a location where caliptra_top_reg.h can be found) $(warning Defaulting to $(RTL_SOC_IFC_INCLUDE_PATH)) diff --git a/libcaliptra/examples/generic/main.mk b/libcaliptra/examples/generic/main.mk index 4189f757c9..0e6e35b327 100644 --- a/libcaliptra/examples/generic/main.mk +++ b/libcaliptra/examples/generic/main.mk @@ -11,7 +11,7 @@ LIBCALIPTRA_INC = $(LIBCALIPTRA_ROOT)/inc OBJS := $(patsubst %.c,%.o, $(filter %.c,$(SOURCE))) # SOC REFERENCE -RTL_SOC_IFC_INCLUDE_PATH = ../../../hw-latest/caliptra-rtl/src/soc_ifc/rtl +RTL_SOC_IFC_INCLUDE_PATH = ../../../hw/latest/rtl/src/soc_ifc/rtl # INCLUDES INCLUDES += -I$(RTL_SOC_IFC_INCLUDE_PATH) -I$(LIBCALIPTRA_INC) diff --git a/registers/README.md b/registers/README.md index f6f5505989..1645b2ab84 100644 --- a/registers/README.md +++ b/registers/README.md @@ -5,7 +5,7 @@ To update the register definitions (and RTL submodule) to the latest version of ```console ~/git/caliptra-sw$ git submodule update --init # If you haven't already populated the submodule -~/git/caliptra-sw$ (cd hw-latest/caliptra-rtl/ && git checkout main && git pull --rebase) +~/git/caliptra-sw$ (cd hw/latest/rtl/ && git checkout main && git pull --rebase) ~/git/caliptra-sw$ registers/update.sh Compiling caliptra_registers_generator (~/git/caliptra-sw/registers/bin/generator) Running `~/git/caliptra-sw/target/release/caliptra_registers_generator ../../rtl-caliptra src/` @@ -18,5 +18,5 @@ Writing to "src/sha256.rs" Writing to "src/mbox.rs" Writing to "src/soc_ifc.rs" -~/git/caliptra-sw$ git commit -a -m "Updated hw-latest/caliptra-rtl to $(cd hw-latest/caliptra-rtl && git rev-parse HEAD)" +~/git/caliptra-sw$ git commit -a -m "Updated hw/latest/rtl to $(cd hw/latest/rtl && git rev-parse HEAD)" ``` diff --git a/registers/update.sh b/registers/update.sh index 07da528494..afbfc7f651 100755 --- a/registers/update.sh +++ b/registers/update.sh @@ -2,10 +2,10 @@ cd "$(dirname "${BASH_SOURCE[0]}")" -if [[ ! -f "../hw-latest/caliptra-rtl/.git" ]]; then +if [[ ! -f "../hw/latest/rtl/.git" ]]; then echo "caliptra-rtl submodule is not populated" echo "Please run 'git submodule update --init'" exit 1 fi -cargo run --manifest-path bin/generator/Cargo.toml -- ../hw-latest/caliptra-rtl bin/extra-rdl/ src/ +cargo run --manifest-path bin/generator/Cargo.toml -- ../hw/latest/rtl bin/extra-rdl/ src/