From 8b5d41507338484b1a66f65e79630698c986551f Mon Sep 17 00:00:00 2001
From: unlsycn <unlsycn@unlsycn.com>
Date: Mon, 4 Nov 2024 11:02:26 +0000
Subject: [PATCH] feat: add CIRCTSRAMInterface

---
 .../experimental/CIRCTSRAMInterface.scala     | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala

diff --git a/src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala b/src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala
new file mode 100644
index 0000000000..900d6d274e
--- /dev/null
+++ b/src/main/scala/chisel3/util/experimental/CIRCTSRAMInterface.scala
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.util.experimental
+
+import chisel3._
+import chisel3.experimental.BaseModule
+import chisel3.experimental.hierarchy.Instance
+import chisel3.util.log2Ceil
+
+import scala.collection.immutable.SeqMap
+
+object CIRCTSRAMParameter {
+  implicit val rw: upickle.default.ReadWriter[CIRCTSRAMParameter] = upickle.default.macroRW
+}
+
+case class CIRCTSRAMParameter(
+  moduleName:      String,
+  read:            Int,
+  write:           Int,
+  readwrite:       Int,
+  depth:           Int,
+  width:           Int,
+  maskGranularity: Int) {
+  def masked: Boolean = maskGranularity != 0
+}
+
+class CIRCTSRAMInterface(memoryParameter: CIRCTSRAMParameter) extends Record {
+
+  class R extends Record {
+    lazy val clock = Input(Clock())
+    lazy val address = Input(UInt(log2Ceil(memoryParameter.depth).W))
+    lazy val data = Output(UInt(memoryParameter.width.W))
+    lazy val enable = Input(Bool())
+
+    val elements: SeqMap[String, Data] = SeqMap(
+      "clk" -> clock,
+      "addr" -> address,
+      "data" -> data,
+      "en" -> enable
+    )
+  }
+  class W extends Record {
+    lazy val clock = Input(Clock())
+    lazy val address = Input(UInt(log2Ceil(memoryParameter.depth).W))
+    lazy val data = Input(UInt(memoryParameter.width.W))
+    lazy val mask = Input(UInt(memoryParameter.width.W))
+    lazy val enable = Input(Bool())
+
+    val elements: SeqMap[String, Data] = SeqMap(
+      "clk" -> clock,
+      "addr" -> address,
+      "data" -> data,
+      "en" -> enable
+    ) ++ Option.when(memoryParameter.masked)("mask" -> mask)
+  }
+  class RW extends Record {
+    lazy val clock = Input(Clock())
+    lazy val address = Input(UInt(log2Ceil(memoryParameter.depth).W))
+    lazy val writeData = Input(UInt(memoryParameter.width.W))
+    lazy val writeMask = Input(UInt(memoryParameter.width.W))
+    lazy val writeEnable = Input(Bool())
+    lazy val readData = Output(UInt(memoryParameter.width.W))
+    lazy val enable = Input(Bool())
+
+    val elements: SeqMap[String, Data] = SeqMap(
+      "clk" -> clock,
+      "addr" -> address,
+      "wdata" -> writeData,
+      "wmode" -> writeEnable,
+      "rdata" -> readData,
+      "en" -> enable
+    ) ++ Option.when(memoryParameter.masked)("wmask" -> writeMask)
+  }
+
+  def R(idx:  Int): R = elements(s"R$idx").asInstanceOf[R]
+  def W(idx:  Int): W = elements(s"W$idx").asInstanceOf[W]
+  def RW(idx: Int): RW = elements(s"RW$idx").asInstanceOf[RW]
+
+  val elements: SeqMap[String, Data] =
+    (Seq.tabulate(memoryParameter.read)(i => s"R$i" -> new R) ++
+      Seq.tabulate(memoryParameter.write)(i => s"W$i" -> new W) ++
+      Seq.tabulate(memoryParameter.readwrite)(i => s"RW$i" -> new RW))
+      .to(SeqMap)
+}
+
+abstract class CIRCTSRAM[T <: RawModule](memoryParameter: CIRCTSRAMParameter)
+    extends FixedIORawModule[CIRCTSRAMInterface](new CIRCTSRAMInterface(memoryParameter)) {
+  override def desiredName: String = memoryParameter.moduleName
+  val memoryInstance: Instance[_ <: BaseModule]
+}