From db3a5a755f77c6054fed8cdd2eab93abca3418dd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 2 Dec 2019 16:50:22 -0800 Subject: [PATCH 01/11] add flag to clear mimpid, marchid, mvendorid --- src/dromajo_main.cpp | 14 +++++++++++--- src/machine.h | 3 +++ src/riscv_cpu.cpp | 14 ++++++++++---- src/riscv_machine.cpp | 3 +++ src/riscv_machine.h | 3 +++ 5 files changed, 30 insertions(+), 7 deletions(-) diff --git a/src/dromajo_main.cpp b/src/dromajo_main.cpp index fe45349f..b01dca16 100644 --- a/src/dromajo_main.cpp +++ b/src/dromajo_main.cpp @@ -609,11 +609,12 @@ static void usage(const char *prog, const char *msg) " --bootrom load in a bootrom img file (default is dromajo bootrom)\n" " --dtb load in a dtb file (default is dromajo dtb)\n" " --compact_bootrom have dtb be directly after bootrom (default 256B after boot base)\n" - " --reset_vector set reset vector (default 0x%lx)\n" + " --reset_vector set reset vector for all cores (default 0x%lx)\n" " --mmio_range START:END [START,END) mmio range for cosim (overridden by config file)\n" " --plic START:SIZE set PLIC start address and size (defaults to 0x%lx:0x%lx)\n" " --clint START:SIZE set CLINT start address and size (defaults to 0x%lx:0x%lx)\n" - " --custom_extension add X extension to isa\n", + " --custom_extension add X extension to misa for all cores\n" + " --clear_ids clear mvendorid, marchid, mimpid for all cores\n", msg, prog, (long)BOOT_BASE_ADDR, (long)RAM_BASE_ADDR, @@ -671,6 +672,7 @@ RISCVMachine *virt_machine_main(int argc, char **argv) uint64_t clint_base_addr_override = 0; uint64_t clint_size_override = 0; bool custom_extension = false; + bool clear_ids = false; dromajo_stdout = stdout; dromajo_stderr = stderr; @@ -698,6 +700,7 @@ RISCVMachine *virt_machine_main(int argc, char **argv) {"plic", required_argument, 0, 'p' }, // CFG {"clint", required_argument, 0, 'C' }, // CFG {"custom_extension", no_argument, 0, 'u' }, // CFG + {"clear_ids", no_argument, 0, 'L' }, // CFG {0, 0, 0, 0 } }; @@ -837,6 +840,10 @@ RISCVMachine *virt_machine_main(int argc, char **argv) custom_extension = true; break; + case 'L': + clear_ids = true; + break; + default: usage(prog, "I'm not having this argument"); } @@ -1000,8 +1007,9 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (clint_size_override) p->clint_size = clint_size_override; - // ISA modifications + // core modifications p->custom_extension = custom_extension; + p->clear_ids = clear_ids; RISCVMachine *s = virt_machine_init(p); if (!s) diff --git a/src/machine.h b/src/machine.h index 2e505a18..6de5995c 100644 --- a/src/machine.h +++ b/src/machine.h @@ -160,6 +160,9 @@ typedef struct { /* Add to misa custom extensions */ bool custom_extension; + /* Clear mimpid, marchid, mvendorid */ + bool clear_ids; + uint64_t physical_addr_len; char *logfile; // If non-zero, all output goes here, stderr and stdout diff --git a/src/riscv_cpu.cpp b/src/riscv_cpu.cpp index 454eccb0..43d79041 100644 --- a/src/riscv_cpu.cpp +++ b/src/riscv_cpu.cpp @@ -1898,10 +1898,16 @@ RISCVCPUState *riscv_cpu_init(RISCVMachine *machine, int hartid) if (machine->custom_extension) s->misa |= MCPUID_X; - s->mvendorid = 11 * 128 + 101; // Esperanto JEDEC number 101 in bank 11 (Change for your own) - s->marchid = (1ULL << 63) | 2; - s->mimpid = 1; - s->mhartid = hartid; + if (machine->clear_ids) { + s->mvendorid = 0; + s->marchid = 0; + s->mimpid = 0; + } else { + s->mvendorid = 11 * 128 + 101; // Esperanto JEDEC number 101 in bank 11 (Change for your own) + s->marchid = (1ULL << 63) | 2; + s->mimpid = 1; + } + s->mhartid = hartid; s->tselect = 0; for (int i = 0; i < MAX_TRIGGERS; ++i) { diff --git a/src/riscv_machine.cpp b/src/riscv_machine.cpp index 5983bbdf..f0e6e8d6 100644 --- a/src/riscv_machine.cpp +++ b/src/riscv_machine.cpp @@ -1071,6 +1071,9 @@ RISCVMachine *virt_machine_init(const VirtMachineParams *p) /* add custom extension bit to misa */ s->custom_extension = p->custom_extension; + /* clear mimpid, marchid, mvendorid */ + s->clear_ids = p->clear_ids; + if (MAX_CPUS < s->ncpus) { fprintf(stderr, "ERROR: ncpus:%d exceeds maximum MAX_CPU\n", s->ncpus); exit(3); diff --git a/src/riscv_machine.h b/src/riscv_machine.h index 3d9bad85..2135bfc7 100644 --- a/src/riscv_machine.h +++ b/src/riscv_machine.h @@ -100,6 +100,9 @@ struct RISCVMachine { /* Append to misa custom extensions */ bool custom_extension; + /* Clear mimpid, marchid, mvendorid */ + bool clear_ids; + /* Extension state, not used by Dromajo itself */ void *ext_state; }; From c77213d0aea2899e04c6d7e01d9725c14d45cea6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Dec 2019 10:31:32 -0800 Subject: [PATCH 02/11] [cosim] add memory override hook --- src/dromajo_cosim.cpp | 68 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/src/dromajo_cosim.cpp b/src/dromajo_cosim.cpp index cb19b626..820b8e36 100644 --- a/src/dromajo_cosim.cpp +++ b/src/dromajo_cosim.cpp @@ -360,3 +360,71 @@ int dromajo_cosim_step(dromajo_cosim_state_t *state, return exit_code; } + +/* + * dromajo_cosim_override_mem -- + * + * DUT sets Dromajo memory. Used so that other devices (i.e. block device, accelerators, can write to memory). + */ +int dromajo_cosim_override_mem(dromajo_cosim_state_t *state, int hartid, target_ulong dut_paddr, mem_uint_t dut_val, int size_log2) +{ + RISCVMachine *r = (RISCVMachine *)state; + RISCVCPUState *s = r->cpu_state[hartid]; + + uint8_t *ptr; + target_ulong offset; + PhysMemoryRange *pr = get_phys_mem_range(s->mem_map, dut_paddr); + + if (!pr) { +#ifdef DUMP_INVALID_MEM_ACCESS + fprintf(dromajo_stderr, "riscv_cpu_write_memory: invalid physical address 0x%016" PRIx64 "\n", dut_paddr); +#endif + return 1; + } else if (pr->is_ram) { + phys_mem_set_dirty_bit(pr, dut_paddr - pr->addr); + ptr = pr->phys_mem + (uintptr_t)(dut_paddr - pr->addr); + switch (size_log2) { + case 0: + *(uint8_t *)ptr = dut_val; + break; + case 1: + *(uint16_t *)ptr = dut_val; + break; + case 2: + *(uint32_t *)ptr = dut_val; + break; +#if MLEN >= 64 + case 3: + *(uint64_t *)ptr = dut_val; + break; +#endif +#if MLEN >= 128 + case 4: + *(uint128_t *)ptr = dut_val; + break; +#endif + default: + abort(); + } + } else { + offset = dut_paddr - pr->addr; + if (((pr->devio_flags >> size_log2) & 1) != 0) { + pr->write_func(pr->opaque, offset, dut_val, size_log2); + } +#if MLEN >= 64 + else if ((pr->devio_flags & DEVIO_SIZE32) && size_log2 == 3) { + /* emulate 64 bit access */ + pr->write_func(pr->opaque, offset, + dut_val & 0xffffffff, 2); + pr->write_func(pr->opaque, offset + 4, + (dut_val >> 32) & 0xffffffff, 2); + } +#endif + else { +#ifdef DUMP_INVALID_MEM_ACCESS + fprintf(dromajo_stderr, "unsupported device write access: addr=0x%016" PRIx64 " width=%d bits\n", dut_paddr, 1 << (3 + size_log2)); +#endif + } + } + return 0; +} From 300073743616a47f5d98f524813b5bd8134f137c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 8 Dec 2019 21:42:31 -0800 Subject: [PATCH 03/11] [cosim] add func proto and clean up --- src/dromajo_cosim.cpp | 34 +++++++++++++++++----------------- src/dromajo_cosim.h | 12 ++++++++++++ 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/src/dromajo_cosim.cpp b/src/dromajo_cosim.cpp index 820b8e36..d5c5c99b 100644 --- a/src/dromajo_cosim.cpp +++ b/src/dromajo_cosim.cpp @@ -366,7 +366,7 @@ int dromajo_cosim_step(dromajo_cosim_state_t *state, * * DUT sets Dromajo memory. Used so that other devices (i.e. block device, accelerators, can write to memory). */ -int dromajo_cosim_override_mem(dromajo_cosim_state_t *state, int hartid, target_ulong dut_paddr, mem_uint_t dut_val, int size_log2) +int dromajo_cosim_override_mem(dromajo_cosim_state_t *state, int hartid, uint64_t dut_paddr, uint64_t dut_val, int size_log2) { RISCVMachine *r = (RISCVMachine *)state; RISCVCPUState *s = r->cpu_state[hartid]; @@ -384,27 +384,27 @@ int dromajo_cosim_override_mem(dromajo_cosim_state_t *state, int hartid, target_ phys_mem_set_dirty_bit(pr, dut_paddr - pr->addr); ptr = pr->phys_mem + (uintptr_t)(dut_paddr - pr->addr); switch (size_log2) { - case 0: - *(uint8_t *)ptr = dut_val; + case 0: + *(uint8_t *)ptr = dut_val; + break; + case 1: + *(uint16_t *)ptr = dut_val; + break; + case 2: + *(uint32_t *)ptr = dut_val; break; - case 1: - *(uint16_t *)ptr = dut_val; - break; - case 2: - *(uint32_t *)ptr = dut_val; - break; #if MLEN >= 64 - case 3: - *(uint64_t *)ptr = dut_val; - break; + case 3: + *(uint64_t *)ptr = dut_val; + break; #endif #if MLEN >= 128 - case 4: - *(uint128_t *)ptr = dut_val; - break; + case 4: + *(uint128_t *)ptr = dut_val; + break; #endif - default: - abort(); + default: + abort(); } } else { offset = dut_paddr - pr->addr; diff --git a/src/dromajo_cosim.h b/src/dromajo_cosim.h index 6705ac3e..3195cce8 100644 --- a/src/dromajo_cosim.h +++ b/src/dromajo_cosim.h @@ -74,6 +74,18 @@ int dromajo_cosim_step(dromajo_cosim_state_t *state, void dromajo_cosim_raise_trap(dromajo_cosim_state_t *state, int hartid, int64_t cause); + +/* + * dromajo_cosim_override_mem -- + * + * DUT sets Dromajo memory. Used so that other devices (i.e. block device, accelerators, can write to memory). + */ +int dromajo_cosim_override_mem(dromajo_cosim_state_t *state, + int hartid, + uint64_t dut_paddr, + uint64_t dut_val, + int size_log2); + #ifdef __cplusplus } // extern C #endif From 46c55ffd15015e8b60d8422518bace2d7537cf4b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 Jan 2020 16:22:36 -0800 Subject: [PATCH 04/11] print all --- src/riscv_cpu.cpp | 4 ++-- src/riscv_cpu.h | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/riscv_cpu.cpp b/src/riscv_cpu.cpp index 43d79041..52217cf7 100644 --- a/src/riscv_cpu.cpp +++ b/src/riscv_cpu.cpp @@ -1628,14 +1628,14 @@ static void raise_exception2(RISCVCPUState *s, uint64_t cause, }; if (cause & CAUSE_INTERRUPT) - fprintf(dromajo_stderr, "hartid=%d: exception interrupt #%d, epc 0x%016jx\n", + fprintf(dromajo_stderr, "hartid=%d: exception interrupt #%ld, epc 0x%016jx\n", (int)s->mhartid, cause & 63, (uintmax_t)s->pc); else if (cause <= CAUSE_STORE_PAGE_FAULT) { fprintf(dromajo_stderr, "hartid=%d priv: %d exception %s, epc 0x%016jx\n", (int)s->mhartid, s->priv, cause_s[cause], (uintmax_t)s->pc); fprintf(dromajo_stderr, "hartid=%d0 tval 0x%016jx\n", (int)s->mhartid, (uintmax_t)tval); } else { - fprintf(dromajo_stderr, "hartid=%d: exception %d, epc 0x%016jx\n", + fprintf(dromajo_stderr, "hartid=%d: exception %ld, epc 0x%016jx\n", (int)s->mhartid, cause, (uintmax_t)s->pc); fprintf(dromajo_stderr, "hartid=%d: tval 0x%016jx\n", (int)s->mhartid, (uintmax_t)tval); } diff --git a/src/riscv_cpu.h b/src/riscv_cpu.h index 9a30a1c1..b073ebe9 100644 --- a/src/riscv_cpu.h +++ b/src/riscv_cpu.h @@ -56,11 +56,11 @@ #define DUMP_INVALID_MEM_ACCESS #define DUMP_MMU_EXCEPTIONS -//#define DUMP_INTERRUPTS +#define DUMP_INTERRUPTS #define DUMP_INVALID_CSR -//#define DUMP_ILLEGAL_INSTRUCTION -//#define DUMP_EXCEPTIONS -//#define DUMP_CSR +#define DUMP_ILLEGAL_INSTRUCTION +#define DUMP_EXCEPTIONS +#define DUMP_CSR #define CONFIG_LOGFILE #define CONFIG_SW_MANAGED_A_AND_D 1 #define CONFIG_ALLOW_MISALIGNED_ACCESS 0 From cbee88dc6ccab5a451ba6c8da60e504a5772d328 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 13 Mar 2020 14:27:31 -0700 Subject: [PATCH 05/11] match rc interrupts --- src/dromajo_cosim.cpp | 9 ++++++++- src/riscv_cpu.cpp | 42 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/src/dromajo_cosim.cpp b/src/dromajo_cosim.cpp index 58619b28..e8a3b2b0 100644 --- a/src/dromajo_cosim.cpp +++ b/src/dromajo_cosim.cpp @@ -302,12 +302,19 @@ int dromajo_cosim_step(dromajo_cosim_state_t *state, } } - if (r->common.pending_interrupt != -1) + if (r->common.pending_interrupt != -1) { riscv_cpu_set_mip(s, riscv_cpu_get_mip(s) | 1 << r->common.pending_interrupt); + fprintf(dromajo_stderr, "[DEBUG] Interrupt: MIP <- %d: Now MIP = %x\n", r->common.pending_interrupt, riscv_cpu_get_mip(s)); + } if (riscv_cpu_interp64(s, 1) != 0) { iregno = riscv_get_most_recently_written_reg(s); fregno = riscv_get_most_recently_written_fp_reg(s); + + //// ABE: I think this is the solution + //r->common.pending_interrupt = -1; + //r->common.pending_exception = -1; + break; } diff --git a/src/riscv_cpu.cpp b/src/riscv_cpu.cpp index 535b4851..e85d4fd3 100644 --- a/src/riscv_cpu.cpp +++ b/src/riscv_cpu.cpp @@ -1739,6 +1739,12 @@ static inline uint32_t get_pending_irq_mask(RISCVCPUState *s) { uint32_t pending_ints, enabled_ints; +#ifdef DUMP_INTERRUPTS + fprintf(dromajo_stderr, + "get_irq_mask: mip=0x%x mie=0x%x mideleg=0x%x\n", + s->mip, s->mie, s->mideleg); +#endif + pending_ints = s->mip & s->mie; if (pending_ints == 0) return 0; @@ -1762,6 +1768,39 @@ static inline uint32_t get_pending_irq_mask(RISCVCPUState *s) return pending_ints & enabled_ints; } +static inline int8_t get_irq_platspecific(uint32_t mask) { + uint32_t local_ints = mask & ((-1) << 12); + + // get irq number from plat specific section (priority to MSB) + for (int8_t i = 31; i > 0; --i) { + if ( (local_ints >> i) & 0x1 ) { + return i; + } + } + + // unknown value (expected a valid mask in the region) + return -1; +} + +// matches how rocket-chip determines interrupt priorities +static inline int8_t get_irq_num(uint32_t mask) { + // check if the int. is in the plat. specific region + if (mask >= (1 << 12)) { + return get_irq_platspecific(mask); + } + else { + // get int. from the other priorities + uint8_t priorities[] = {11, 3, 7, 10, 2, 6, 9, 1, 5, 8, 0, 4}; + for (uint8_t i = 0; i < 12; ++i) { + if ( (mask >> priorities[i]) & 0x1 ) { + return priorities[i]; + } + } + // should match by now + return -1; + } +} + static __exception int raise_interrupt(RISCVCPUState *s) { uint32_t mask; @@ -1770,7 +1809,8 @@ static __exception int raise_interrupt(RISCVCPUState *s) mask = get_pending_irq_mask(s); if (mask == 0) return 0; - irq_num = ctz32(mask); + + irq_num = get_irq_num(mask); #ifdef DUMP_INTERRUPTS fprintf(dromajo_stderr, "raise_interrupt: irq=%d priv=%d pc=%llx hartid=%d\n", From 33ddb649b2510aa85aa5924684c9e9eddbd51525 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 17 Mar 2020 20:04:12 +0000 Subject: [PATCH 06/11] extra debugging --- src/dromajo_cosim.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/dromajo_cosim.cpp b/src/dromajo_cosim.cpp index e8a3b2b0..c62b1a7c 100644 --- a/src/dromajo_cosim.cpp +++ b/src/dromajo_cosim.cpp @@ -200,9 +200,10 @@ void dromajo_cosim_raise_trap(dromajo_cosim_state_t *state, int hartid, int64_t if (cause < 0) { assert(m->pending_interrupt == -1); m->pending_interrupt = cause & 63; - fprintf(dromajo_stderr, "DUT raised interrupt %d\n", m->pending_interrupt); + fprintf(dromajo_stderr, "[DEBUG] DUT raised interrupt %d\n", m->pending_interrupt); } else { m->pending_exception = cause; + fprintf(dromajo_stderr, "[DEBUG] DUT raised exception %d\n", m->pending_exception); } } @@ -281,7 +282,7 @@ int dromajo_cosim_step(dromajo_cosim_state_t *state, /* On the DUT, the interrupt can race the exception. Let's try to match that behavior */ - fprintf(dromajo_stderr, "DUT also raised exception %d\n", r->common.pending_exception); + fprintf(dromajo_stderr, "[DEBUG] DUT also raised exception %d\n", r->common.pending_exception); riscv_cpu_interp64(s, 1); // Advance into the exception int cause = s->priv == PRV_S ? s->scause : s->mcause; @@ -343,7 +344,8 @@ int dromajo_cosim_step(dromajo_cosim_state_t *state, if (verbose) fprintf(dromajo_stderr, "f%-2d 0x%016" PRIx64, fregno, emu_wdata); } else - fprintf(dromajo_stderr, " "); + if (verbose) + fprintf(dromajo_stderr, " "); if (verbose) fprintf(dromajo_stderr, " DASM(0x%08x)\n", emu_insn); From ae09bb14b22217710f1ae498ff13c60f38e8172f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 17 Mar 2020 19:19:37 -0700 Subject: [PATCH 07/11] properly parse the memory size --- src/dromajo_main.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/dromajo_main.cpp b/src/dromajo_main.cpp index b01dca16..147613f8 100644 --- a/src/dromajo_main.cpp +++ b/src/dromajo_main.cpp @@ -611,8 +611,8 @@ static void usage(const char *prog, const char *msg) " --compact_bootrom have dtb be directly after bootrom (default 256B after boot base)\n" " --reset_vector set reset vector for all cores (default 0x%lx)\n" " --mmio_range START:END [START,END) mmio range for cosim (overridden by config file)\n" - " --plic START:SIZE set PLIC start address and size (defaults to 0x%lx:0x%lx)\n" - " --clint START:SIZE set CLINT start address and size (defaults to 0x%lx:0x%lx)\n" + " --plic START:SIZE set PLIC start address and size in B (defaults to 0x%lx:0x%lx)\n" + " --clint START:SIZE set CLINT start address and size in B (defaults to 0x%lx:0x%lx)\n" " --custom_extension add X extension to misa for all cores\n" " --clear_ids clear mvendorid, marchid, mimpid for all cores\n", msg, @@ -754,7 +754,9 @@ RISCVMachine *virt_machine_main(int argc, char **argv) break; case 'M': - memory_size_override = atoi(optarg); + if (optarg[0] != '0' || optarg[1] != 'x') + usage(prog, "--memory_size expects argument to start with 0x... "); + memory_size_override = strtoll(optarg + 2, NULL, 16); break; case 'A': From 56e2ff46b70521916c362799517f4ed8e67e9e88 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 Apr 2020 15:59:04 -0700 Subject: [PATCH 08/11] fix strtok seg. fault errors by duplicating str in args --- src/dromajo_main.cpp | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/dromajo_main.cpp b/src/dromajo_main.cpp index 147613f8..8750afac 100644 --- a/src/dromajo_main.cpp +++ b/src/dromajo_main.cpp @@ -791,7 +791,8 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (!strchr(optarg, ':')) usage(prog, "--mmio_range expects an argument like START:END"); - char *mmio_start = strtok(optarg, ":"); + char *copy = strdup(optarg); + char *mmio_start = strtok(copy, ":"); char *mmio_end = strtok(NULL, ":"); if (mmio_start[0] != '0' || mmio_start[1] != 'x') @@ -801,6 +802,8 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (mmio_end[0] != '0' || mmio_end[1] != 'x') usage(prog, "--mmio_range END address must begin with 0x..."); mmio_end_override = strtoll(mmio_end+2, NULL, 16); + + free(copy); } break; @@ -808,7 +811,8 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (!strchr(optarg, ':')) usage(prog, "--plic expects an argument like START:SIZE"); - char *plic_base_addr = strtok(optarg, ":"); + char *copy = strdup(optarg); + char *plic_base_addr = strtok(copy, ":"); char *plic_size = strtok(NULL, ":"); if (plic_base_addr[0] != '0' || plic_base_addr[1] != 'x') @@ -818,6 +822,8 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (plic_size[0] != '0' || plic_size[1] != 'x') usage(prog, "--plic SIZE must begin with 0x..."); plic_size_override = strtoll(plic_size+2, NULL, 16); + + free(copy); } break; @@ -825,7 +831,8 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (!strchr(optarg, ':')) usage(prog, "--clint expects an argument like START:SIZE"); - char *clint_base_addr = strtok(optarg, ":"); + char *copy = strdup(optarg); + char *clint_base_addr = strtok(copy, ":"); char *clint_size = strtok(NULL, ":"); if (clint_base_addr[0] != '0' || clint_base_addr[1] != 'x') @@ -835,6 +842,8 @@ RISCVMachine *virt_machine_main(int argc, char **argv) if (clint_size[0] != '0' || clint_size[1] != 'x') usage(prog, "--clint SIZE must begin with 0x..."); clint_size_override = strtoll(clint_size+2, NULL, 16); + + free(copy); } break; From 09fbef4565429f641a7eb93f190ad0e45e11d7f8 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 19:40:41 +0000 Subject: [PATCH 09/11] Add __STDC_FORMAT_MACROS define for old glibc versions --- src/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Makefile b/src/Makefile index 8f7d4170..d81eac96 100644 --- a/src/Makefile +++ b/src/Makefile @@ -43,7 +43,7 @@ VERSION=Dromajo-0.1 CXX=g++ CFLAGS_OPT=-Ofast CXXFLAGS=$(CFLAGS_OPT) -Wall -std=c++11 -g -Wno-parentheses -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -MMD -CXXFLAGS+=-D_GNU_SOURCE -DCONFIG_VERSION=\"$(VERSION)\" +CXXFLAGS+=-D_GNU_SOURCE -DCONFIG_VERSION=\"$(VERSION)\" -D__STDC_FORMAT_MACROS #CXXFLAGS+=-DLIVECACHE LDFLAGS= From 88340a3c9bfdfe60a15caa6fd2c91813c17721bc Mon Sep 17 00:00:00 2001 From: Jennifer Zhou Date: Tue, 30 Aug 2022 10:06:50 -0700 Subject: [PATCH 10/11] saturn PA --- src/dromajo_cosim.cpp | 7 +++++-- src/riscv_machine.cpp | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/dromajo_cosim.cpp b/src/dromajo_cosim.cpp index c62b1a7c..e5400191 100644 --- a/src/dromajo_cosim.cpp +++ b/src/dromajo_cosim.cpp @@ -110,7 +110,7 @@ static inline bool is_mmio_load(RISCVCPUState *s, uint64_t va = riscv_get_reg_previous(s, reg) + offset; if(!riscv_cpu_get_phys_addr(s, va, ACCESS_READ, &pa) && - mmio_start <= pa && pa < mmio_end) { + (mmio_start <= pa && pa < mmio_end) ||(pa == 0x4000) ) { return true; } @@ -196,7 +196,8 @@ static inline void handle_dut_overrides(RISCVCPUState *s, void dromajo_cosim_raise_trap(dromajo_cosim_state_t *state, int hartid, int64_t cause) { VirtMachine *m = (VirtMachine *)state; - + fprintf(dromajo_stderr, "cause %lx\n", cause); + fprintf(dromajo_stderr, "m->pending_interrupt: %x \n", m->pending_interrupt); if (cause < 0) { assert(m->pending_interrupt == -1); m->pending_interrupt = cause & 63; @@ -222,6 +223,8 @@ void dromajo_cosim_raise_trap(dromajo_cosim_state_t *state, int hartid, int64_t * time, and instret. For all these cases the model will override * with the expected values. */ + +//look here int dromajo_cosim_step(dromajo_cosim_state_t *state, int hartid, uint64_t dut_pc, diff --git a/src/riscv_machine.cpp b/src/riscv_machine.cpp index ab24d495..81f140d6 100644 --- a/src/riscv_machine.cpp +++ b/src/riscv_machine.cpp @@ -1068,6 +1068,7 @@ void virt_machine_set_defaults(VirtMachineParams *p) RISCVMachine *virt_machine_init(const VirtMachineParams *p) { + //setting up SoC VIRTIODevice *blk_dev; int irq_num, i; VIRTIOBusDef vbus_s, *vbus = &vbus_s; @@ -1114,6 +1115,7 @@ RISCVMachine *virt_machine_init(const VirtMachineParams *p) /* RAM */ cpu_register_ram(s->mem_map, 0, 4096, 0); // Have memory at 0 for uaccess-etcsr to pass + cpu_register_ram(s->mem_map, 16384, 8192, 0); cpu_register_ram(s->mem_map, s->ram_base_addr, s->ram_size, 0); cpu_register_ram(s->mem_map, ROM_BASE_ADDR, ROM_SIZE, 0); From 20720e9f59c60abb74cd24df6a53882d861008d1 Mon Sep 17 00:00:00 2001 From: Jennifer Zhou Date: Mon, 19 Sep 2022 15:12:17 -0700 Subject: [PATCH 11/11] pmp and other CSRs --- src/dromajo_cosim.cpp | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/dromajo_cosim.cpp b/src/dromajo_cosim.cpp index e5400191..7610fa11 100644 --- a/src/dromajo_cosim.cpp +++ b/src/dromajo_cosim.cpp @@ -155,11 +155,32 @@ static inline void handle_dut_overrides(RISCVCPUState *s, * hpmoverflows, mip, and sip. * If the destination register is x0 then it is actually a csr-write */ + bool is_pmp = (csrno == CSR_PMPCFG(0)) || + (csrno == CSR_PMPCFG(2)) || + (csrno == CSR_PMPADDR(0)) || + (csrno == CSR_PMPADDR(1)) || + (csrno == CSR_PMPADDR(2)) || + (csrno == CSR_PMPADDR(3)) || + (csrno == CSR_PMPADDR(4)) || + (csrno == CSR_PMPADDR(5)) || + (csrno == CSR_PMPADDR(6)) || + (csrno == CSR_PMPADDR(7)) || + (csrno == CSR_PMPADDR(8)) || + (csrno == CSR_PMPADDR(9)) || + (csrno == CSR_PMPADDR(10)) || + (csrno == CSR_PMPADDR(11)) || + (csrno == CSR_PMPADDR(12)) || + (csrno == CSR_PMPADDR(13)) || + (csrno == CSR_PMPADDR(14)) || + (csrno == CSR_PMPADDR(15)); if (opcode == 0x73 && rd != 0 && (0xB00 <= csrno && csrno < 0xB20 || 0xC00 <= csrno && csrno < 0xC20 || (csrno == 0x344 /* mip */ || - csrno == 0x144 /* sip */))) + csrno == 0x144 /* sip */|| + csrno == 0x306 /* mcounteren */|| + csrno == 0x106 /* scounteren */|| + is_pmp))) riscv_set_reg(s, rd, dut_wdata); /* Catch loads and amo from MMIO space */