Summary: creating single boot ROM for multicore configs #80
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The motive for this commit is explained in Issue 79 on the Chips Alliance Dromajo GitHub page: chipsalliance#79. This pull request introduces the implementation for the enhancement. When the checkpoint is saved, a single boot ROM is generated for N cores. The boot code is divided into N sections, where N represents the number of cores. Each core will generate its own recovery code and write it to its designated section. In addition to the recovery code, each core initializes with a preamble code that reads the hart_id and calculates the program counter (PC) based on the id.
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The motive for this PR is explained in #79.
This pull request introduces the implementation for the enhancement. When the checkpoint is saved, a single boot ROM is generated for N cores. The boot code is divided into N sections, where N represents the number of cores. Each core will generate its own recovery code and write it to its designated section. In addition to the recovery code, each core initializes with a preamble code that reads the hart_id and calculates the program counter (PC) based on the id.
Please let me know what you think.