From d10b6bda6c271f836ad98cb42ec0e0dff9219ec3 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 17 May 2021 10:33:06 +0100 Subject: [PATCH 1/3] device: Move wire types to tile Signed-off-by: gatecat --- interchange/DeviceResources.capnp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/interchange/DeviceResources.capnp b/interchange/DeviceResources.capnp index e2edd20..0670b59 100644 --- a/interchange/DeviceResources.capnp +++ b/interchange/DeviceResources.capnp @@ -141,6 +141,7 @@ struct Device { wires @2 : List(StringIdx) $stringRef(); pips @3 : List(PIP); constants @4 : List(WireConstantSources); + wireTypes @5 : List(WireTypeIdx); } ####################################### @@ -216,7 +217,7 @@ struct Device { struct Wire { tile @0 : StringIdx $stringRef(); wire @1 : StringIdx $stringRef(); - type @2 : WireTypeIdx $wireTypeRef(); + deleted @2 : Void; } enum WireCategory { From da28f1dbfbe65c7af83c67fcb0ca611ec5b0edd2 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 17 May 2021 10:41:51 +0100 Subject: [PATCH 2/3] device: Split flat wires/nodes into its own schema Signed-off-by: gatecat --- cmake/cxx_static/CMakeLists.txt | 2 +- interchange/DeviceResources.capnp | 22 ++----------- interchange/FlatWiresNodes.capnp | 53 +++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 21 deletions(-) create mode 100644 interchange/FlatWiresNodes.capnp diff --git a/cmake/cxx_static/CMakeLists.txt b/cmake/cxx_static/CMakeLists.txt index 196c328..f8556ed 100644 --- a/cmake/cxx_static/CMakeLists.txt +++ b/cmake/cxx_static/CMakeLists.txt @@ -1,5 +1,5 @@ find_package(CapnProto REQUIRED) -set(PROTOS LogicalNetlist.capnp PhysicalNetlist.capnp DeviceResources.capnp References.capnp) +set(PROTOS LogicalNetlist.capnp PhysicalNetlist.capnp DeviceResources.capnp FlatWiresNodes.capnp References.capnp) set(INTERCHANGE_SCHEMA_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../interchange) diff --git a/interchange/DeviceResources.capnp b/interchange/DeviceResources.capnp index 0670b59..bfe7be1 100644 --- a/interchange/DeviceResources.capnp +++ b/interchange/DeviceResources.capnp @@ -50,14 +50,6 @@ struct BELPinRef { annotation belPinRef(*) :BELPinRef; using BELPinIdx = UInt32; -struct WireRef { - type @0 :Ref.ReferenceType = parent; - field @1 :Text = "wires"; - depth @2 :Int32 = 1; -} -annotation wireRef(*) :WireRef; -using WireIdx = UInt32; - struct WireTypeRef { type @0 :Ref.ReferenceType = parent; field @1 :Text = "wireTypes"; @@ -86,8 +78,8 @@ struct Device { siteTypeList @2 : List(SiteType); tileTypeList @3 : List(TileType); tileList @4 : List(Tile); - wires @5 : List(Wire); - nodes @6 : List(Node); + deleted0 @5 : Void; + deleted1 @6 : Void; primLibs @7 : Dir.Netlist; # Netlist libraries of Unisim primitives and macros exceptionMap @8 : List(PrimToMacroExpansion); # Prims to macros expand w/same name, except these cellBelMap @9 : List(CellBelMapping); @@ -214,12 +206,6 @@ struct Device { # Inter-site routing resources ###################################### - struct Wire { - tile @0 : StringIdx $stringRef(); - wire @1 : StringIdx $stringRef(); - deleted @2 : Void; - } - enum WireCategory { # general interconnect, usually with many uphill and downhill pips and spanning multiple tiles general @0; @@ -238,10 +224,6 @@ struct Device { category @1 : WireCategory; } - struct Node { - wires @0 : List(WireIdx) $wireRef(); - } - struct PIP { wire0 @0 : WireIDInTileType; wire1 @1 : WireIDInTileType; diff --git a/interchange/FlatWiresNodes.capnp b/interchange/FlatWiresNodes.capnp new file mode 100644 index 0000000..10100b1 --- /dev/null +++ b/interchange/FlatWiresNodes.capnp @@ -0,0 +1,53 @@ +# Copyright 2020-2021 Xilinx, Inc. and Google, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +@0x9d262c6ba6512325; +using Java = import "/capnp/java.capnp"; +using Ref = import "References.capnp"; +$Java.package("com.xilinx.rapidwright.interchange"); +$Java.outerClassname("FlatWiresNodes"); + +using Cxx = import "/capnp/c++.capnp"; +$Cxx.namespace("FlatWiresNodes"); + +struct StringRef { + type @0 :Ref.ReferenceType = rootValue; + field @1 :Text = "strList"; +} +annotation stringRef(*) :StringRef; +using StringIdx = UInt32; + +struct WireRef { + type @0 :Ref.ReferenceType = parent; + field @1 :Text = "wires"; + depth @2 :Int32 = 1; +} +annotation wireRef(*) :WireRef; +using WireIdx = UInt32; + +# This structure describes a flat wire-node mapping with no folding or deduplication +struct FlatWiresNodes { + wires @0 : List(Wire); + nodes @1 : List(Node); + + struct Wire { + tile @0 : StringIdx $stringRef(); + wire @1 : StringIdx $stringRef(); + } + + struct Node { + wires @0 : List(WireIdx) $wireRef(); + } + +} From e686931d72d60ca1e8a16e2301bbd732f1fb8a72 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 17 May 2021 10:46:35 +0100 Subject: [PATCH 3/3] Add a deduplicated-wires structure as another routing example Signed-off-by: gatecat --- cmake/cxx_static/CMakeLists.txt | 2 +- interchange/DedupWiresNodes.capnp | 61 +++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) create mode 100644 interchange/DedupWiresNodes.capnp diff --git a/cmake/cxx_static/CMakeLists.txt b/cmake/cxx_static/CMakeLists.txt index f8556ed..5259e4c 100644 --- a/cmake/cxx_static/CMakeLists.txt +++ b/cmake/cxx_static/CMakeLists.txt @@ -1,5 +1,5 @@ find_package(CapnProto REQUIRED) -set(PROTOS LogicalNetlist.capnp PhysicalNetlist.capnp DeviceResources.capnp FlatWiresNodes.capnp References.capnp) +set(PROTOS LogicalNetlist.capnp PhysicalNetlist.capnp DeviceResources.capnp DedupWiresNodes.capnp FlatWiresNodes.capnp References.capnp) set(INTERCHANGE_SCHEMA_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../interchange) diff --git a/interchange/DedupWiresNodes.capnp b/interchange/DedupWiresNodes.capnp new file mode 100644 index 0000000..d594ce8 --- /dev/null +++ b/interchange/DedupWiresNodes.capnp @@ -0,0 +1,61 @@ +# Copyright 2020-2021 Xilinx, Inc. and Google, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +@0x9d262c6ba6512325; +using Java = import "/capnp/java.capnp"; +using Ref = import "References.capnp"; +$Java.package("com.xilinx.rapidwright.interchange"); +$Java.outerClassname("DedupWiresNodes"); + +using Cxx = import "/capnp/c++.capnp"; +$Cxx.namespace("DedupWiresNodes"); + +struct StringRef { + type @0 :Ref.ReferenceType = rootValue; + field @1 :Text = "strList"; +} +annotation stringRef(*) :StringRef; +using StringIdx = UInt32; + +struct NodeShapeRef { + type @0 :Ref.ReferenceType = parent; + field @1 :Text = "nodeShapes"; + depth @2 :Int32 = 1; +} +annotation nodeShapeRef(*) :NodeShapeRef; +using NodeShapeIdx = UInt32; + +# This structure describes a deduplicated wire-node mapping, as an interim step between a flat graph and a fully folded graph. +# It requires a full list of nodes in the device and their "shape", but not a full list of wires within those nodes as nodes +# with the same "shape", using relative coordinates, only have their list of constituent wires stored once. +struct DedupWiresNodes { + nodes @0 : List(Node); + nodeShapes @1 : List(NodeShape); + + struct Node { + rootTile @0 : StringIdx $stringRef(); + shape @1 : NodeShapeIdx $nodeShapeRef(); + } + + struct NodeWire { + dx @0 : Int16; # wire.x = rootTile.x + dx + dy @1 : Int16; # wire.y = rootTile.y + dy + wire @2 : StringIdx $stringRef(); + } + + struct NodeShape { + wires @0 : List(NodeWire); + } + +}