diff --git a/rocketv/src/FPU.scala b/rocketv/src/FPU.scala
index c980908d4..999634312 100644
--- a/rocketv/src/FPU.scala
+++ b/rocketv/src/FPU.scala
@@ -5,11 +5,18 @@
 package org.chipsalliance.rocketv
 
 import chisel3._
-import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.experimental.{BaseModule, SerializableModule, SerializableModuleParameter}
+import chisel3.probe.{define, Probe, ProbeValue}
 import chisel3.util._
 import chisel3.util.circt.ClockGate
 
+class FPUProbe(param: FPUParameter) extends Bundle {
+  val rfWen:   Bool = Bool()
+  val rfWaddr: UInt = UInt(5.W)
+  val rfWdata: UInt = UInt((param.fLen + 1).W)
+}
+
 object FPUParameter {
   implicit def rwP: upickle.default.ReadWriter[FPUParameter] = upickle.default.macroRW[FPUParameter]
 }
@@ -32,6 +39,7 @@ class FPUInterface(parameter: FPUParameter) extends Bundle {
   val core = new FPUCoreIO(parameter.hartIdLen, parameter.xLen, parameter.fLen)
   val cp_req = Flipped(Decoupled(new FPInput(parameter.fLen))) //cp doesn't pay attn to kill sigs
   val cp_resp = Decoupled(new FPResult(parameter.fLen))
+  val fpuProbe = Output(new FPUProbe(parameter))
 }
 
 // TODO: all hardfloat module can be replaced by DWBB?
@@ -415,6 +423,14 @@ class FPU(val parameter: FPUParameter)
       wen.orR || divSqrt_inFlight || // post-WB stage
       io.core.dmem_resp_val // load writeback
 
+    // probe defination
+    val probeWire = Wire(new FPUProbe(parameter))
+    define(io.fpuProbe, ProbeValue(probeWire))
+
+    probeWire.rfWen := load_wb || (!wbInfo(0).cp && wen(0)) || divSqrt_wen
+    probeWire.rfWaddr := Mux(load_wb, load_wb_tag, waddr)
+    probeWire.rfWdata := Mux(load_wb, recode(load_wb_data, load_wb_typeTag), wdata)
+
   } // leaving gated-clock domain
   val fpuImpl = withClockAndReset(gated_clock, io.reset) { new FPUImpl }
 }
diff --git a/t1rocket/src/T1RocketTile.scala b/t1rocket/src/T1RocketTile.scala
index 9699eea05..b52ab5588 100644
--- a/t1rocket/src/T1RocketTile.scala
+++ b/t1rocket/src/T1RocketTile.scala
@@ -9,7 +9,7 @@ import chisel3.util.experimental.BitSet
 import chisel3.util.log2Ceil
 import chisel3.probe.{Probe, ProbeValue, define}
 import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4ROIrrevocable, AXI4RWIrrevocable}
-import org.chipsalliance.rocketv.{BHTParameter, FPU, FPUParameter, Frontend, FrontendParameter, HellaCache, HellaCacheArbiter, HellaCacheArbiterParameter, HellaCacheParameter, PTW, PTWParameter, Rocket, RocketParameter, RocketTileParameter, RocketProbe}
+import org.chipsalliance.rocketv.{BHTParameter, FPU, FPUParameter, Frontend, FrontendParameter, HellaCache, HellaCacheArbiter, HellaCacheArbiterParameter, HellaCacheParameter, PTW, PTWParameter, Rocket, RocketParameter, RocketTileParameter, RocketProbe, FPUProbe}
 import org.chipsalliance.rvdecoderdb.Instruction
 import org.chipsalliance.t1.rtl.decoder.T1CustomInstruction
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -426,6 +426,7 @@ case class T1RocketTileParameter(
 
 class T1RocketProbe(parameter: T1RocketTileParameter) extends Bundle {
   val rocketProbe: RocketProbe = Output(new RocketProbe(parameter.rocketParameter))
+  val fpuProbe: Option[FPUProbe] = Option.when(parameter.fpuParameter.isDefined)(Output(new FPUProbe(parameter.fpuParameter.get))).getOrElse(null)
   val t1Probe: T1Probe = Output(new T1Probe(parameter.t1Parameter))
 }
 
@@ -559,4 +560,5 @@ class T1RocketTile(val parameter: T1RocketTileParameter)
   define(io.t1RocketProbe, ProbeValue(probeWire))
   probeWire.rocketProbe := probe.read(rocket.io.rocketProbe)
   probeWire.t1Probe := probe.read(t1.io.t1Probe)
+  probeWire.fpuProbe := fpu.map(fpu => probe.read(fpu.io.fpuProbe)).getOrElse(null)
 }
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
index 0509f1395..66250d0f6 100644
--- a/t1rocketemu/src/TestBench.scala
+++ b/t1rocketemu/src/TestBench.scala
@@ -159,6 +159,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
 
   // probes
   val t1RocketProbe = probe.read(dut.io.t1RocketProbe)
+  val fpuprobe = t1RocketProbe.fpuprobe.suggestName(s"fpuprobe")
   val rocketProbe = t1RocketProbe.rocketProbe.suggestName(s"rocketProbe")
   val t1Probe = t1RocketProbe.t1Probe.suggestName(s"t1Probe")
   val lsuProbe = t1Probe.lsuProbe.suggestName(s"t1LSUProbe")
@@ -211,6 +212,15 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
     )
   )
 
+  // [[option]] rocket fpu reg write 
+  fpuProbe.foreach { fpu =>
+    when(fpu.rfWen)(
+      printf(
+        cf"""{"event":"RegWrite","idx":${rfWaddr},"data":"${rfWdata}%x","cycle":${simulationTime}}\n"""
+      )
+    )
+  }
+
   // t1 vrf write
   laneVrfProbes.zipWithIndex.foreach {
     case (lane, i) =>