[rtl] disable chaining.

chipsalliance · Nov 20, 2024 · 7db7dcd · 7db7dcd
1 parent 966738e
commit 7db7dcd
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -657,10 +657,8 @@ class T1(val parameter: T1Parameter)
     )
   )
 
-  val freeOR: Bool = VecInit(slots.map(_.state.idle)).asUInt.orR
-
   /** slot is ready to accept new instructions. */
-  val slotReady: Bool = Mux(specialInstruction, slots.map(_.state.idle).last, freeOR)
+  val slotReady: Bool = VecInit(slots.map(_.state.idle)).asUInt.andR
 
   val source1Select: UInt =
     Mux(