diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
index a91055507..e193ccbcd 100644
--- a/t1/src/vrf/VRF.scala
+++ b/t1/src/vrf/VRF.scala
@@ -505,7 +505,11 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
   val recordFFO:  UInt = ffo(freeRecord)
   val recordEnq:  UInt = Wire(UInt((parameter.chainingSize + 1).W))
   val olderCheck = chainingRecord
-    .map(re => !re.valid || instIndexL(re.bits.instIndex, instructionWriteReport.bits.instIndex))
+    .map(re =>
+      !re.valid ||
+        (instIndexL(re.bits.instIndex, instructionWriteReport.bits.instIndex) &&
+          ((re.bits.instIndex >> 1).asUInt =/= (instructionWriteReport.bits.instIndex >> 1).asUInt))
+    )
     .reduce(_ && _)
   // handle VRF hazard
   // @todo @Clo91eaf VRF ready signal for performance.