From a80342c72be193dbfcd872f03a4eb5169abad557 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Wed, 14 Aug 2024 16:10:23 +0800 Subject: [PATCH] [rocketv] Now setvl does not need to be sent to t1. --- rocketv/src/RocketCore.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala index 911df4dbf..e679aacf1 100644 --- a/rocketv/src/RocketCore.scala +++ b/rocketv/src/RocketCore.scala @@ -1346,7 +1346,9 @@ class Rocket(val parameter: RocketParameter) // T1 Issue val maxCount: Int = 32 val t1IssueQueue = Module(new Queue(chiselTypeOf(t1.issue.bits), maxCount)) - t1IssueQueue.io.enq.valid := wbRegValid && !replayWbCommon && wbRegDecodeOutput(parameter.decoderParameter.vector) + t1IssueQueue.io.enq.valid := + wbRegValid && !replayWbCommon && wbRegDecodeOutput(parameter.decoderParameter.vector) && + !wbRegDecodeOutput(parameter.decoderParameter.vectorLSU) t1IssueQueue.io.enq.bits.instruction := wbRegInstruction t1IssueQueue.io.enq.bits.rs1Data := wbRegWdata t1IssueQueue.io.enq.bits.rs2Data := wbRegRS2