diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
index e15c74a03..20d342fa0 100644
--- a/t1/src/Lane.scala
+++ b/t1/src/Lane.scala
@@ -67,7 +67,7 @@ class LaneProbe(parameter: LaneParameter) extends Bundle {
   // @todo @Clo91eaf change to occupied for each slot.
   val lastSlotOccupied:    Bool = Bool()
   val instructionFinished: UInt = UInt(parameter.chainingSize.W)
-  val instructionValid:    UInt = UInt(parameter.chainingSize.W)
+  val instructionValid:    UInt = UInt((2 * parameter.chainingSize).W)
 
   val crossWriteProbe: Vec[ValidIO[LaneWriteProbe]] = Vec(2, Valid(new LaneWriteProbe(parameter.instructionIndexBits)))
 
@@ -275,9 +275,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   /** for each instruction in the slot, response to top when instruction is finished in this lane. */
   @public
-  val instructionFinished: UInt = IO(Output(UInt(parameter.chainingSize.W)))
+  val instructionFinished: UInt = IO(Output(UInt((2 * parameter.chainingSize).W)))
   @public
-  val vxsatReport:         UInt = IO(Output(UInt(parameter.chainingSize.W)))
+  val vxsatReport:         UInt = IO(Output(UInt((2 * parameter.chainingSize).W)))
 
   /** V0 update in the lane should also update [[T1.v0]] */
   @public
@@ -300,15 +300,11 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     * is finished.
     */
   @public
-  val lsuLastReport: UInt = IO(Input(UInt(parameter.chainingSize.W)))
-
-  /** If lsu changes the mask group, you need to tell vrf */
-  @public
-  val lsuMaskGroupChange: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val lsuLastReport: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
   /** for RaW, VRF should wait for buffer to be empty. */
   @public
-  val loadDataInLSUWriteQueue: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val loadDataInLSUWriteQueue: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
   /** How many dataPath will writ by instruction in this lane */
   @public
@@ -512,14 +508,14 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   val slot0EnqueueFire: Bool = Wire(Bool())
 
   /** assert when a instruction is valid in the slot. */
-  val instructionValid:     UInt = Wire(UInt(parameter.chainingSize.W))
+  val instructionValid:     UInt = Wire(UInt((2 * parameter.chainingSize).W))
   val instructionValidNext: UInt = RegNext(instructionValid, 0.U)
 
-  val vxsatResult: UInt = RegInit(0.U(parameter.chainingSize.W))
+  val vxsatResult: UInt = RegInit(0.U((2 * parameter.chainingSize).W))
   vxsatReport := vxsatResult
 
   // Overflow occurs
-  val vxsatEnq: Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt(parameter.chainingSize.W)))
+  val vxsatEnq: Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt((2 * parameter.chainingSize).W)))
   // vxsatEnq and instructionFinished cannot happen at the same time
   vxsatResult := (vxsatEnq.reduce(_ | _) | vxsatResult) & (~instructionFinished).asUInt
 
@@ -780,7 +776,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     vxsatEnq(index)             := Mux(
       executionUnit.dataResponse.valid &&
         (executionUnit.dataResponse.bits.clipFail ## executionUnit.dataResponse.bits.vxsat).orR,
-      UIntToOH(executionUnit.responseIndex(parameter.instructionIndexBits - 2, 0)),
+      indexToOH(executionUnit.responseIndex, parameter.chainingSize),
       0.U(parameter.chainingSize.W)
     )
     AssertProperty(BoolSequence(!executionUnit.dequeue.valid || stage2.dequeue.valid))
@@ -1166,7 +1162,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   // clear record by instructionFinished
   vrf.instructionLastReport                 := instructionFinished
   vrf.lsuLastReport                         := lsuLastReport
-  vrf.lsuMaskGroupChange                    := lsuMaskGroupChange
   vrf.loadDataInLSUWriteQueue               := loadDataInLSUWriteQueue
   vrf.dataInLane                            := instructionValid
   instructionFinished                       := (~instructionValid).asUInt & instructionValidNext
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index 8e52e136a..14d1209e3 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -775,7 +775,7 @@ class T1(val parameter: T1Parameter)
     lsu.offsetReadIndex(index)        := lane.maskUnitRequest.bits.index
 
     instructionFinished(index).zip(slots.map(_.record.instructionIndex)).foreach { case (d, f) =>
-      d := (UIntToOH(f(parameter.instructionIndexBits - 2, 0)) & lane.instructionFinished).orR
+      d := ohCheck(lane.instructionFinished, f, parameter.chainingSize)
     }
     vxsatReportVec(index)             := lane.vxsatReport
     lane.maskInput                    := maskUnit.laneMaskInput(index)
@@ -785,7 +785,6 @@ class T1(val parameter: T1Parameter)
 
     lane.lsuLastReport := lsu.lastReport | maskUnit.lastReport
 
-    lane.lsuMaskGroupChange      := lsu.lsuMaskGroupChange
     lane.loadDataInLSUWriteQueue := lsu.dataInWriteQueue(index)
     // 2 + 3 = 5
     val rowWith: Int = log2Ceil(parameter.datapathWidth / 8) + log2Ceil(parameter.laneNumber)
@@ -977,7 +976,7 @@ class T1(val parameter: T1Parameter)
     }
     probeWire.instructionValid   := maskAnd(
       !slots.last.state.wMaskUnitLast && !slots.last.state.idle,
-      indexToOH(slots.last.record.instructionIndex, parameter.chainingSize * 2)
+      indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)
     ).asUInt
     probeWire.responseCounter    := responseCounter
     probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) }
diff --git a/t1/src/laneStage/MaskedWrite.scala b/t1/src/laneStage/MaskedWrite.scala
index 858189e2b..3d4a50306 100644
--- a/t1/src/laneStage/MaskedWrite.scala
+++ b/t1/src/laneStage/MaskedWrite.scala
@@ -33,8 +33,6 @@ class MaskedWrite(parameter: LaneParameter) extends Module {
       new VRFReadRequest(parameter.vrfParam.regNumBits, parameter.vrfOffsetBits, parameter.instructionIndexBits)
     )
   )
-  @public
-  val maskedWrite1H:  UInt                         = IO(Output(UInt(parameter.chainingSize.W)))
 
   /** VRF read result for each slot, 3 is for [[source1]] [[source2]] [[source3]]
     */
@@ -111,7 +109,7 @@ class MaskedWrite(parameter: LaneParameter) extends Module {
   vrfReadPipe.enq.valid := readDataValid
   vrfReadPipe.enq.bits  := vrfReadResult
 
-  maskedWrite1H := dataInS3 | dataInS2 | dataInS1 | dataInQueue
+  val maskedWrite1H = dataInS3 | dataInS2 | dataInS1 | dataInQueue
 
   val maskFill: UInt = FillInterleaved(8, s3Pipe.mask)
   val readDataSelect = Mux(fwd3, s3BypassData, vrfReadPipe.deq.bits)
diff --git a/t1/src/laneStage/SlotTokenManager.scala b/t1/src/laneStage/SlotTokenManager.scala
index f7893a926..252832de6 100644
--- a/t1/src/laneStage/SlotTokenManager.scala
+++ b/t1/src/laneStage/SlotTokenManager.scala
@@ -103,13 +103,13 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
   val maskWriteDeq: ValidIO[UInt] = IO(Flipped(Valid(UInt(parameter.instructionIndexBits.W))))
 
   @public
-  val instructionValid: UInt = IO(Output(UInt(parameter.chainingSize.W)))
+  val instructionValid: UInt = IO(Output(UInt((2 * parameter.chainingSize).W)))
 
   @public
-  val dataInWritePipe: UInt = IO(Output(UInt(parameter.chainingSize.W)))
+  val dataInWritePipe: UInt = IO(Output(UInt((2 * parameter.chainingSize).W)))
 
   @public
-  val maskUnitLastReport: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val maskUnitLastReport: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
   def tokenUpdate(tokenData: Seq[UInt], enqWire: UInt, deqWire: UInt): UInt = {
     tokenData.zipWithIndex.foreach { case (t, i) =>
@@ -140,7 +140,7 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
   }
 
   val instructionInSlot: UInt = enqReports.zipWithIndex.map { case (enqReport, slotIndex) =>
-    val writeToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+    val writeToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize * 2)(_ => RegInit(0.U(tokenWith.W)))
 
     val enqOH = indexToOH(enqReport.bits.instructionIndex, parameter.chainingSize)
 
@@ -157,22 +157,15 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
         indexToOH(slotWriteReport(slotIndex).bits, parameter.chainingSize)
       ).asUInt
 
-    val writeEnqSelect: UInt = Wire(UInt(parameter.chainingSize.W))
+    val writeEnqSelect: UInt = Wire(UInt((2 * parameter.chainingSize).W))
 
     val pendingSlotWrite = tokenUpdate(writeToken, writeEnqSelect, writeDoDeq)
 
     if (slotIndex == 0) {
-      val responseToken:      Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
-      val feedbackToken:      Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
-      val crossWriteTokenLSB: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
-      val crossWriteTokenMSB: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
-
-      // Feedback is not accurate (index load/store may have already finished the instruction)
-      val responseIndexQueue =
-        Queue.io(UInt(parameter.instructionIndexBits.W), parameter.chainingSize + 1, flow = true)
-      responseIndexQueue.enq.valid := responseReport.valid
-      responseIndexQueue.enq.bits  := responseReport.bits
-      responseIndexQueue.deq.ready := responseFeedbackReport.valid
+      val responseToken:      Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+      val feedbackToken:      Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+      val crossWriteTokenLSB: Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+      val crossWriteTokenMSB: Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
 
       // cross write update
       val crossWriteDoEnq: UInt =
@@ -210,7 +203,7 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
   }.reduce(_ | _)
 
   // write pipe token
-  val writePipeToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+  val writePipeToken: Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
   val writePipeEnq:   UInt      =
     maskAnd(writePipeEnqReport.valid, indexToOH(writePipeEnqReport.bits, parameter.chainingSize)).asUInt
   val writePipeDeq:   UInt      =
@@ -219,8 +212,11 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
   val instructionInWritePipe: UInt = tokenUpdate(writePipeToken, writePipeEnq, writePipeDeq)
 
   // lsu & mask write token
-  val lsuWriteToken:  Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
-  val maskWriteToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+  val lsuWriteToken:  Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+  val maskWriteToken: Seq[UInt] = Seq.tabulate(2 * parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+
+  val topWriteDoEnq: UInt      =
+    maskAnd(topWriteEnq.valid, indexToOH(topWriteEnq.bits, parameter.chainingSize)).asUInt
 
   val lsuWriteDoEnq: UInt =
     maskAnd(topWriteEnq.valid && !fromMask, indexToOH(topWriteEnq.bits, parameter.chainingSize)).asUInt
diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
index 614ccfb2e..459970455 100644
--- a/t1/src/lsu/LSU.scala
+++ b/t1/src/lsu/LSU.scala
@@ -164,7 +164,7 @@ class LSU(param: LSUParameter) extends Module {
   )
 
   @public
-  val dataInWriteQueue: Vec[UInt] = IO(Output(Vec(param.laneNumber, UInt(param.chainingSize.W))))
+  val dataInWriteQueue: Vec[UInt] = IO(Output(Vec(param.laneNumber, UInt((2 * param.chainingSize).W))))
 
   /** the CSR interface from [[V]], CSR will be latched in MSHR. TODO: merge to [[LSURequest]]
     */
@@ -182,10 +182,7 @@ class LSU(param: LSUParameter) extends Module {
 
   /** interface to [[V]], indicate a MSHR slots is finished, and corresponding instruction can commit. */
   @public
-  val lastReport: UInt = IO(Output(UInt(param.chainingSize.W)))
-
-  @public
-  val lsuMaskGroupChange: UInt = IO(Output(UInt(param.chainingSize.W)))
+  val lastReport: UInt = IO(Output(UInt((2 * param.chainingSize).W)))
 
   @public
   val writeReadyForLsu: Bool = IO(Input(Bool()))
@@ -258,8 +255,6 @@ class LSU(param: LSUParameter) extends Module {
 
   // write vrf
   val otherTryToWrite: UInt      = Mux(otherUnit.vrfWritePort.valid, otherUnit.status.targetLane, 0.U)
-  // Permission to enter the queue TODO: Investigate why this happens
-  val canEnterQueue:   Vec[Bool] = Wire(Vec(param.laneNumber, Bool()))
   // other 优先级更高
   otherUnit.vrfWritePort.ready := (otherUnit.status.targetLane & VecInit(writeQueueVec.map(_.enq.ready)).asUInt).orR
   writeQueueVec.zipWithIndex.foreach { case (write, index) =>
@@ -293,10 +288,10 @@ class LSU(param: LSUParameter) extends Module {
       // The load unit becomes idle when it writes vrf for the last time.
       maskAnd(
         !loadUnit.status.idle || VecInit(loadUnit.vrfWritePort.map(_.valid)).asUInt.orR,
-        indexToOH(loadUnit.status.instructionIndex, 2 * param.chainingSize)
+        indexToOH(loadUnit.status.instructionIndex, param.chainingSize)
       ).asUInt |
-        maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt |
-        maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt
+        maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, param.chainingSize)).asUInt |
+        maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, param.chainingSize)).asUInt
   }
 
   vrfWritePort.zip(writeQueueVec).foreach { case (p, q) =>
@@ -308,18 +303,18 @@ class LSU(param: LSUParameter) extends Module {
   val dataInMSHR: UInt =
     Mux(
       loadUnit.status.idle,
-      0.U(param.chainingSize.W),
+      0.U((2 * param.chainingSize).W),
       indexToOH(loadUnit.status.instructionIndex, param.chainingSize)
     ) |
       Mux(
         otherUnit.status.idle || otherUnit.status.isStore,
-        0.U(param.chainingSize.W),
+        0.U((2 * param.chainingSize).W),
         indexToOH(otherUnit.status.instructionIndex, param.chainingSize)
       )
 
   // Record whether there is data for the corresponding instruction in the queue
-  writeQueueVec.zip(dataInWriteQueue).zipWithIndex.foreach { case ((q, p), queueIndex) =>
-    val queueCount: Seq[UInt] = Seq.tabulate(param.chainingSize) { _ =>
+  writeQueueVec.zip(dataInWriteQueue).foreach { case (q, p) =>
+    val queueCount: Seq[UInt] = Seq.tabulate(2 * param.chainingSize) { _ =>
       RegInit(0.U(log2Ceil(param.toVRFWriteQueueSize).W))
     }
     val enqOH:      UInt      = indexToOH(q.enq.bits.data.instructionIndex, param.chainingSize)
@@ -332,18 +327,6 @@ class LSU(param: LSUParameter) extends Module {
       }
     }
     p := VecInit(queueCount.map(_ =/= 0.U)).asUInt | dataInMSHR
-    val dataTag    = VecInit(Seq.tabulate(param.chainingSize) { _ =>
-      RegInit(false.B)
-    })
-    val nextTag    = q.enq.bits.data.instructionIndex.asBools.last
-    val currentTag = (dataTag.asUInt & enqOH).orR
-    // same tage or nothing in queue
-    canEnterQueue(queueIndex) := (nextTag === currentTag) || !p
-    dataTag.zipWithIndex.foreach { case (d, i) =>
-      when(q.deq.fire && enqOH(i)) {
-        d := nextTag
-      }
-    }
   }
 
   val sourceQueue = Queue.io(UInt(param.mshrParam.sourceWidth.W), param.sourceQueueSize)
@@ -437,9 +420,6 @@ class LSU(param: LSUParameter) extends Module {
   // gather last signal from all MSHR to notify LSU
   lastReport                 :=
     unitVec.map(m => Mux(m.status.last, indexToOH(m.status.instructionIndex, param.chainingSize), 0.U)).reduce(_ | _)
-  lsuMaskGroupChange         := unitVec
-    .map(m => Mux(m.status.changeMaskGroup, indexToOH(m.status.instructionIndex, param.chainingSize), 0.U))
-    .reduce(_ | _)
   tokenIO.offsetGroupRelease := otherUnit.offsetRelease.asUInt
   loadUnit.writeReadyForLsu  := writeReadyForLsu
   storeUnit.vrfReadyToStore  := vrfReadyToStore
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
index fa71fc1c8..bb523f260 100644
--- a/t1/src/mask/MaskUnit.scala
+++ b/t1/src/mask/MaskUnit.scala
@@ -90,7 +90,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val writeRD: ValidIO[UInt] = IO(Valid(UInt(parameter.datapathWidth.W)))
 
   @public
-  val lastReport: UInt = IO(Output(UInt(parameter.chainingSize.W)))
+  val lastReport: UInt = IO(Output(UInt((2 * parameter.chainingSize).W)))
 
   // mask
   @public
diff --git a/t1/src/package.scala b/t1/src/package.scala
index 33bd0f728..13bde15a9 100644
--- a/t1/src/package.scala
+++ b/t1/src/package.scala
@@ -48,7 +48,7 @@ package object rtl {
   }
 
   def indexToOH(index: UInt, chainingSize: Int): UInt = {
-    UIntToOH(index(log2Ceil(chainingSize) - 1, 0))
+    UIntToOH(index(log2Ceil(chainingSize), 0))
   }
 
   def ohCheck(lastReport: UInt, index: UInt, chainingSize: Int): Bool = {
diff --git a/t1/src/sequencer/T1TokenManager.scala b/t1/src/sequencer/T1TokenManager.scala
index a46c19bda..3da10f909 100644
--- a/t1/src/sequencer/T1TokenManager.scala
+++ b/t1/src/sequencer/T1TokenManager.scala
@@ -30,10 +30,10 @@ class T1TokenManager(parameter: T1Parameter) extends Module {
   val issueAllow: Bool = IO(Output(Bool()))
 
   @public
-  val instructionFinish: Vec[UInt] = IO(Vec(parameter.laneNumber, Input(UInt(parameter.chainingSize.W))))
+  val instructionFinish: Vec[UInt] = IO(Vec(parameter.laneNumber, Input(UInt((2 * parameter.chainingSize).W))))
 
   @public
-  val v0WriteValid = IO(Output(UInt(parameter.chainingSize.W)))
+  val v0WriteValid = IO(Output(UInt((2 * parameter.chainingSize).W)))
 
   @public
   val maskUnitFree: Bool = IO(Input(Bool()))
@@ -42,7 +42,7 @@ class T1TokenManager(parameter: T1Parameter) extends Module {
 
   // Boolean type token clear & set
   def updateBooleanToken(set: UInt, clear: UInt): UInt = {
-    VecInit(Seq.tabulate(parameter.chainingSize) { chainingIndex =>
+    VecInit(Seq.tabulate(2 * parameter.chainingSize) { chainingIndex =>
       val res = RegInit(false.B)
       when(set(chainingIndex) || clear(chainingIndex)) {
         res := set(chainingIndex)
diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
index 7e59380eb..f0b43f7b5 100644
--- a/t1/src/vrf/VRF.scala
+++ b/t1/src/vrf/VRF.scala
@@ -222,16 +222,14 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
 
   /** similar to [[flush]]. */
   @public
-  val instructionLastReport: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val instructionLastReport: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
   @public
-  val lsuLastReport: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val lsuLastReport: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
   @public
-  val dataInLane: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val dataInLane: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
-  @public
-  val lsuMaskGroupChange: UInt = IO(Input(UInt(parameter.chainingSize.W)))
   @public
   val writeReadyForLsu:   Bool = IO(Output(Bool()))
   @public
@@ -242,7 +240,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
 
   /** we can only chain LSU instructions, after [[LSU.writeQueueVec]] is cleared. */
   @public
-  val loadDataInLSUWriteQueue: UInt = IO(Input(UInt(parameter.chainingSize.W)))
+  val loadDataInLSUWriteQueue: UInt = IO(Input(UInt((2 * parameter.chainingSize).W)))
 
   @public
   val vrfProbe = IO(Output(Probe(new VRFProbe(parameter), layers.Verification)))