diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala
index 3a58046f3..51811ab60 100644
--- a/t1/src/laneStage/LaneExecutionBridge.scala
+++ b/t1/src/laneStage/LaneExecutionBridge.scala
@@ -105,6 +105,7 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd
   val doubleExecutionInRecord: Bool =
     executionRecord.decodeResult(Decoder.crossWrite) ||
       executionRecord.decodeResult(Decoder.crossRead) ||
+      // Type widenReduce instructions occupy double the data registers because they need to retain the carry bit.
       executionRecord.decodeResult(Decoder.widenReduce)
 
   // data in executionRecord is narrow type