From fc2d24689dbec9df612490fd774f4189ce20361f Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Sun, 25 Aug 2024 21:01:43 +0800 Subject: [PATCH] [rtl] fix responseFinish in Execution unit. --- t1/src/laneStage/LaneExecutionBridge.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala index e1ecbcdcc..b038599e5 100644 --- a/t1/src/laneStage/LaneExecutionBridge.scala +++ b/t1/src/laneStage/LaneExecutionBridge.scala @@ -86,9 +86,12 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd // execution result from execute unit val executionResult = RegInit(0.U(parameter.datapathWidth.W)) val crossWriteLSB: Option[UInt] = Option.when(isLastSlot)(RegInit(0.U(parameter.datapathWidth.W))) - val responseFinish: Bool = RegInit(true.B) + val outStandingRequestSize: Int = 4 max parameter.vfuInstantiateParameter.maxLatency + 3 + val outStanding: UInt = RegInit(0.U(log2Ceil(outStandingRequestSize).W)) + val outStandingUpdate: UInt = Mux(vfuRequest.fire, 1.U(outStanding.getWidth.W), (-1.S(outStanding.getWidth.W)).asUInt) + val responseFinish: Bool = outStanding === 0.U when(vfuRequest.fire ^ dataResponse.fire) { - responseFinish := dataResponse.fire + outStanding := outStanding + outStandingUpdate } /** mask format result for current `mask group` */