From 2bd2ec38f19d335d21d214fe57bbffc2b376ce82 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Tue, 2 Apr 2024 18:54:47 +0200 Subject: [PATCH] projects: add Synlig Signed-off-by: Karol Gugala --- projects/synlig.yml | 51 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 projects/synlig.yml diff --git a/projects/synlig.yml b/projects/synlig.yml new file mode 100644 index 0000000..9198943 --- /dev/null +++ b/projects/synlig.yml @@ -0,0 +1,51 @@ +# Project name +name: Systemverilog Netlist Generator (Synlig) +# Project status - sandbox, graduated or archived +status: graduated +# Links to project repos - may be one or list of several in YAML list format +repositories: https://github.com/chipsalliance/synlig +# A one-sentence summary of the project +brief_summary: Synlig is a SystemVerilog and UHDM front end for Yosys +# The project's open source license, normally Apache 2.0 unless special exception is granted +license: Apache-2.0 +# Link to issue tracker +issue_tracker_link: https://github.com/chipsalliance/synlig/issues +# Link to website +website_link: https://github.com/chipsalliance/synlig +# Links to social media, if present, can be a list, or N/A if none +social_media_links: N/A +# Brief summary of how widely the project is used e.g. list of companies +project_usage_and_scale: Google, Antmicro, numerous users in open source community +# Project's motivation to join CHIPS +why_join_chips: To help drive SystemVerilog support in open source ASIC/FPGA tooling +# The primary contact person for the project, will become TSC representative once admitted +primary_contact: + # Contact's full name + name: Karol Gugala + # Contact's work email + email: kgugala@antmicro.com + # Contact's GH handle, without the @ + github_handle: kgugala + # Contact's role in the project + project_role: Maintainer +### Data above this line is needed for Sandbox application, additional data below is needed for Graduated application +# Data about active project contributors +active_committers: https://github.com/chipsalliance/synlig/graphs/contributors +# Information about project's release methodology and mechanics +release_methodology: Rolling releases on GitHub for every commit passing tests on the main branch +# Link to project's mission statement +mission_statement_link: https://github.com/chipsalliance/synlig/blob/main/README.md +# Link to logo in .svg format, if present +svg_logo_link: https://raw.githubusercontent.com/chipsalliance/synlig/main/images/synlig-logo.svg +# Did the project accept the LF Code of Conduct? See https://lfprojects.org/policies/code-of-conduct/ +accepted_lf_code_of_conduct: yes +# Did the project adopt the CHIPS Alliance IP Policy? See https://technical-charter.chipsalliance.org +adopted_chips_alliance_ip_policy: yes +# Did the project put links to CHIPS in the header or footer of its website? If no website, still answer "yes" as declaration of will to do so. +chips_header_footer_text_on_website: yes +# Did the project transfer any registered trademarks and domains to CHIPS? If none are present, still answer "yes" as declaration of intent if that should change. +trademarks_and_domains_transferred_to_lf: yes +# Describe briefly the project's security vulnerability reporting process, or just defer to https://github.com/chipsalliance/tsc#reporting-security-vulnerabilities +security_vulnerabilities_reporting_process: The project will use [CHIPS Alliance's default security policy](https://github.com/chipsalliance/tsc#reporting-security-vulnerabilities) +# (For specifications only) link to reference implementation of the specification, N/A for non-spec projects +spec_public_reference_implementation: N/A