From fd71c866b7cca8aa2152d9c3887f2ee12636eaec Mon Sep 17 00:00:00 2001
From: chick <chick@qrhino.com>
Date: Fri, 20 Aug 2021 16:29:37 -0700
Subject: [PATCH] - asserts => assumes - printlns removed - change leq_assert
 to leq_cover where appropriate

---
 src/main/scala/treadle/TreadleTester.scala | 19 +++++++++++++++++--
 src/test/scala/treadle/ClockSpec.scala     | 21 +++++++++++++++++++++
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/treadle/TreadleTester.scala b/src/main/scala/treadle/TreadleTester.scala
index 112718a2..84e9643d 100644
--- a/src/main/scala/treadle/TreadleTester.scala
+++ b/src/main/scala/treadle/TreadleTester.scala
@@ -4,8 +4,8 @@ package treadle
 
 import java.io.PrintWriter
 import java.util.Calendar
-
 import firrtl.AnnotationSeq
+import firrtl.ir.ClockType
 import firrtl.options.StageOptions
 import firrtl.options.Viewer.view
 import firrtl.stage.OutputFileAnnotation
@@ -74,8 +74,23 @@ class TreadleTester(annotationSeq: AnnotationSeq) {
 
   val startTime: Long = System.nanoTime()
 
+  private def findTopLevelClocks() = {
+    engine.symbolTable.symbols.collect {
+      case symbol if symbol.firrtlType == ClockType && !(symbol.name.contains(".") || symbol.name.endsWith("/prev")) =>
+        symbol
+    }.toList
+  }
+
   val clockInfoList: Seq[ClockInfo] = if (clockInfo.isEmpty) {
-    if (engine.symbolTable.contains("clock")) {
+    val topClocks = findTopLevelClocks()
+
+    if (topClocks.length > 2) {
+      println(s"Warning: multiple top level clocks found without any ClockInfo information, is this intentional?")
+    }
+
+    if (topClocks.length == 1) {
+      Seq(ClockInfo(topClocks.head.name))
+    } else if (engine.symbolTable.contains("clock")) {
       Seq(ClockInfo())
     } else if (engine.symbolTable.contains("clk")) {
       Seq(ClockInfo("clk"))
diff --git a/src/test/scala/treadle/ClockSpec.scala b/src/test/scala/treadle/ClockSpec.scala
index 7109a419..4828b470 100644
--- a/src/test/scala/treadle/ClockSpec.scala
+++ b/src/test/scala/treadle/ClockSpec.scala
@@ -53,6 +53,27 @@ class ClockSpec extends AnyFreeSpec with Matchers with LazyLogging {
     }
   }
 
+  "clocks can have names other than clock" in {
+    val input =
+      """
+        |circuit OddClockName :
+        |  module OddClockName :
+        |    input tardigrade : Clock
+        |    input reset : UInt<1>
+        |    output out2 : UInt<8>
+        |
+        |    reg reg2 : UInt<8>, tardigrade with : (reset => (reset, UInt<8>("h0")))
+        |    reg2 <= add(reg2, UInt<8>("h01"))
+        |    out2 <= reg2
+        |
+      """.stripMargin
+
+    TreadleTestHarness(Seq(FirrtlSourceAnnotation(input))) { tester =>
+      tester.step(100)
+      tester.expect("out2", 100)
+    }
+  }
+
   "clocks must behave properly behind validif" in {
     val input =
       """