diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-07-30.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-07-30.log new file mode 100644 index 0000000..fd3e1b5 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-07-30.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 16.1623 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.5872 ( 7.2%) 2.5872 ( 16.0%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.1978 ( 6.1%) 2.1978 ( 13.6%) Parse modules + 0.3476 ( 1.0%) 0.3476 ( 2.2%) Verify circuit + 15.1713 ( 42.3%) 6.8238 ( 42.2%) 'firrtl.circuit' Pipeline + 0.3370 ( 0.9%) 0.3370 ( 2.1%) LowerFIRRTLAnnotations + 0.1043 ( 0.3%) 0.1043 ( 0.6%) LowerIntrinsics + 0.1042 ( 0.3%) 0.1042 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.8918 ( 8.1%) 0.7386 ( 4.6%) 'firrtl.module' Pipeline + 1.2516 ( 3.5%) 0.3276 ( 2.0%) DropName + 1.6370 ( 4.6%) 0.4195 ( 2.6%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1116 ( 0.3%) 0.0285 ( 0.2%) 'firrtl.module' Pipeline + 0.1094 ( 0.3%) 0.0279 ( 0.2%) LowerCHIRRTLPass + 0.0946 ( 0.3%) 0.0946 ( 0.6%) InferWidths + 0.2028 ( 0.6%) 0.2028 ( 1.3%) MemToRegOfVec + 0.3647 ( 1.0%) 0.3647 ( 2.3%) InferResets + 0.0502 ( 0.1%) 0.0502 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0684 ( 0.2%) 0.0684 ( 0.4%) WireDFT + 0.5957 ( 1.7%) 0.1511 ( 0.9%) 'firrtl.module' Pipeline + 0.5936 ( 1.7%) 0.1506 ( 0.9%) FlattenMemory + 0.3201 ( 0.9%) 0.3201 ( 2.0%) LowerFIRRTLTypes + 0.7128 ( 2.0%) 0.1840 ( 1.1%) 'firrtl.module' Pipeline + 0.6685 ( 1.9%) 0.1774 ( 1.1%) ExpandWhens + 0.0275 ( 0.1%) 0.0165 ( 0.1%) SFCCompat + 0.3140 ( 0.9%) 0.3140 ( 1.9%) Inliner + 0.5504 ( 1.5%) 0.1413 ( 0.9%) 'firrtl.module' Pipeline + 0.5482 ( 1.5%) 0.1408 ( 0.9%) RandomizeRegisterInit + 0.9457 ( 2.6%) 0.9457 ( 5.9%) CheckCombLoops + 0.0499 ( 0.1%) 0.0499 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.1654 ( 8.8%) 0.8070 ( 5.0%) 'firrtl.module' Pipeline + 2.8958 ( 8.1%) 0.7533 ( 4.7%) Canonicalizer + 0.2664 ( 0.7%) 0.0728 ( 0.5%) InferReadWrite + 0.1373 ( 0.4%) 0.1373 ( 0.8%) PrefixModules + 0.0529 ( 0.1%) 0.0529 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6151 ( 1.7%) 0.6151 ( 3.8%) IMConstProp + 0.0545 ( 0.2%) 0.0545 ( 0.3%) AddSeqMemPorts + 0.0543 ( 0.2%) 0.0543 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.1777 ( 0.5%) 0.1777 ( 1.1%) CreateSiFiveMetadata + 0.0382 ( 0.1%) 0.0382 ( 0.2%) ExtractInstances + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.0000 ( 0.0%) 0.0000 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3197 ( 0.9%) 0.0821 ( 0.5%) 'firrtl.module' Pipeline + 0.3176 ( 0.9%) 0.0817 ( 0.5%) DropName + 0.3080 ( 0.9%) 0.3080 ( 1.9%) SymbolDCE + 0.2242 ( 0.6%) 0.2242 ( 1.4%) InnerSymbolDCE + 1.9377 ( 5.4%) 1.0752 ( 6.7%) 'firrtl.circuit' Pipeline + 0.8625 ( 2.4%) 0.2203 ( 1.4%) 'firrtl.module' Pipeline + 0.8604 ( 2.4%) 0.2201 ( 1.4%) Canonicalizer + 0.5016 ( 1.4%) 0.5016 ( 3.1%) IMDeadCodeElim + 0.0521 ( 0.1%) 0.0521 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0244 ( 0.1%) 0.0244 ( 0.2%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2432 ( 0.7%) 0.2432 ( 1.5%) LowerXMR + 0.0473 ( 0.1%) 0.0473 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.6765 ( 1.9%) 0.6765 ( 4.2%) LowerFIRRTLToHW + 0.0497 ( 0.1%) 0.0497 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.0630 ( 14.1%) 1.3748 ( 8.5%) 'hw.module' Pipeline + 0.9299 ( 2.6%) 0.2429 ( 1.5%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 2.9344 ( 8.2%) 0.9604 ( 5.9%) Canonicalizer + 0.6098 ( 1.7%) 0.1736 ( 1.1%) CSE + 0.0007 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.5830 ( 1.6%) 0.1875 ( 1.2%) LowerSeqFIRRTLToSV + 0.1725 ( 0.5%) 0.1725 ( 1.1%) HWMemSimImpl + 3.3813 ( 9.4%) 0.9463 ( 5.9%) 'hw.module' Pipeline + 0.9226 ( 2.6%) 0.2737 ( 1.7%) CSE + 0.0012 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 1.6694 ( 4.7%) 0.6044 ( 3.7%) Canonicalizer + 0.5288 ( 1.5%) 0.1723 ( 1.1%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.2530 ( 0.7%) 0.0777 ( 0.5%) HWCleanup + 0.5731 ( 1.6%) 0.1435 ( 0.9%) 'hw.module' Pipeline + 0.0577 ( 0.2%) 0.0163 ( 0.1%) HWLegalizeModules + 0.5105 ( 1.4%) 0.1298 ( 0.8%) PrettifyVerilog + 0.2106 ( 0.6%) 0.2106 ( 1.3%) StripDebugInfoWithPred + 1.6500 ( 4.6%) 1.6500 ( 10.2%) ExportVerilog + 2.0209 ( 5.6%) 0.5267 ( 3.3%) 'builtin.module' Pipeline + 1.4943 ( 4.2%) 0.3767 ( 2.3%) 'hw.module' Pipeline + 1.4919 ( 4.2%) 0.3761 ( 2.3%) PrepareForEmission + -0.5218 ( -1.5%) -0.5218 ( -3.2%) Rest + 35.8839 (100.0%) 16.1623 (100.0%) Total + +{ + totalTime: 16.21, + maxMemory: 874467328 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-07-30.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-07-30.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-07-30.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I