diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-15.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-15.log new file mode 100644 index 0000000..af01d95 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-15.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 16.2496 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.5870 ( 7.1%) 2.5870 ( 15.9%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.1989 ( 6.0%) 2.1989 ( 13.5%) Parse modules + 0.3476 ( 1.0%) 0.3476 ( 2.1%) Verify circuit + 15.7439 ( 43.3%) 6.9105 ( 42.5%) 'firrtl.circuit' Pipeline + 0.3356 ( 0.9%) 0.3356 ( 2.1%) LowerFIRRTLAnnotations + 0.0930 ( 0.3%) 0.0930 ( 0.6%) LowerIntrinsics + 0.0929 ( 0.3%) 0.0929 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.8489 ( 7.8%) 0.7305 ( 4.5%) 'firrtl.module' Pipeline + 1.1932 ( 3.3%) 0.3129 ( 1.9%) DropName + 1.6527 ( 4.5%) 0.4167 ( 2.6%) CSE + 0.0008 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1131 ( 0.3%) 0.0290 ( 0.2%) 'firrtl.module' Pipeline + 0.1099 ( 0.3%) 0.0279 ( 0.2%) LowerCHIRRTLPass + 0.0946 ( 0.3%) 0.0946 ( 0.6%) InferWidths + 0.2010 ( 0.6%) 0.2010 ( 1.2%) MemToRegOfVec + 0.3681 ( 1.0%) 0.3681 ( 2.3%) InferResets + 0.0502 ( 0.1%) 0.0502 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0662 ( 0.2%) 0.0662 ( 0.4%) WireDFT + 0.5233 ( 1.4%) 0.1344 ( 0.8%) 'firrtl.module' Pipeline + 0.5212 ( 1.4%) 0.1339 ( 0.8%) FlattenMemory + 0.2590 ( 0.7%) 0.2590 ( 1.6%) LowerFIRRTLTypes + 0.6770 ( 1.9%) 0.1743 ( 1.1%) 'firrtl.module' Pipeline + 0.6567 ( 1.8%) 0.1689 ( 1.0%) ExpandWhens + 0.0172 ( 0.0%) 0.0056 ( 0.0%) SFCCompat + 0.3177 ( 0.9%) 0.3177 ( 2.0%) Inliner + 0.5457 ( 1.5%) 0.1404 ( 0.9%) 'firrtl.module' Pipeline + 0.5438 ( 1.5%) 0.1401 ( 0.9%) RandomizeRegisterInit + 0.9566 ( 2.6%) 0.9566 ( 5.9%) CheckCombLoops + 0.0516 ( 0.1%) 0.0516 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.8027 ( 10.5%) 0.9717 ( 6.0%) 'firrtl.module' Pipeline + 3.5074 ( 9.6%) 0.9124 ( 5.6%) Canonicalizer + 0.2809 ( 0.8%) 0.0845 ( 0.5%) InferReadWrite + 0.1388 ( 0.4%) 0.1388 ( 0.9%) PrefixModules + 0.0527 ( 0.1%) 0.0527 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6515 ( 1.8%) 0.6515 ( 4.0%) IMConstProp + 0.0522 ( 0.1%) 0.0522 ( 0.3%) AddSeqMemPorts + 0.0520 ( 0.1%) 0.0520 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.1594 ( 0.4%) 0.1594 ( 1.0%) CreateSiFiveMetadata + 0.0411 ( 0.1%) 0.0411 ( 0.3%) ExtractInstances + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.0000 ( 0.0%) 0.0000 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3227 ( 0.9%) 0.0824 ( 0.5%) 'firrtl.module' Pipeline + 0.3206 ( 0.9%) 0.0819 ( 0.5%) DropName + 0.3036 ( 0.8%) 0.3036 ( 1.9%) SymbolDCE + 0.2331 ( 0.6%) 0.2331 ( 1.4%) InnerSymbolDCE + 1.9526 ( 5.4%) 1.0908 ( 6.7%) 'firrtl.circuit' Pipeline + 0.8618 ( 2.4%) 0.2206 ( 1.4%) 'firrtl.module' Pipeline + 0.8599 ( 2.4%) 0.2202 ( 1.4%) Canonicalizer + 0.5056 ( 1.4%) 0.5056 ( 3.1%) IMDeadCodeElim + 0.0512 ( 0.1%) 0.0512 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0240 ( 0.1%) 0.0240 ( 0.1%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2500 ( 0.7%) 0.2500 ( 1.5%) LowerXMR + 0.0478 ( 0.1%) 0.0478 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.6791 ( 1.9%) 0.6791 ( 4.2%) LowerFIRRTLToHW + 0.0527 ( 0.1%) 0.0527 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.0523 ( 13.9%) 1.3734 ( 8.5%) 'hw.module' Pipeline + 0.9335 ( 2.6%) 0.2537 ( 1.6%) CSE + 0.0008 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 2.9354 ( 8.1%) 0.9455 ( 5.8%) Canonicalizer + 0.6083 ( 1.7%) 0.1732 ( 1.1%) CSE + 0.0007 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.5690 ( 1.6%) 0.2116 ( 1.3%) LowerSeqFIRRTLToSV + 0.1763 ( 0.5%) 0.1763 ( 1.1%) HWMemSimImpl + 3.3261 ( 9.1%) 0.9309 ( 5.7%) 'hw.module' Pipeline + 0.9156 ( 2.5%) 0.2606 ( 1.6%) CSE + 0.0012 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 1.6286 ( 4.5%) 0.5916 ( 3.6%) Canonicalizer + 0.5285 ( 1.5%) 0.1548 ( 1.0%) CSE + 0.0010 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.2460 ( 0.7%) 0.0755 ( 0.5%) HWCleanup + 0.5639 ( 1.6%) 0.1413 ( 0.9%) 'hw.module' Pipeline + 0.0570 ( 0.2%) 0.0159 ( 0.1%) HWLegalizeModules + 0.5020 ( 1.4%) 0.1276 ( 0.8%) PrettifyVerilog + 0.2138 ( 0.6%) 0.2138 ( 1.3%) StripDebugInfoWithPred + 1.6288 ( 4.5%) 1.6288 ( 10.0%) ExportVerilog + 1.9885 ( 5.5%) 0.5204 ( 3.2%) 'builtin.module' Pipeline + 1.4680 ( 4.0%) 0.3702 ( 2.3%) 'hw.module' Pipeline + 1.4649 ( 4.0%) 0.3695 ( 2.3%) PrepareForEmission + -0.5156 ( -1.4%) -0.5156 ( -3.2%) Rest + 36.3552 (100.0%) 16.2496 (100.0%) Total + +{ + totalTime: 16.294, + maxMemory: 876449792 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-15.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-15.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-15.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I