diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-14.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-14.log new file mode 100644 index 0000000..40a36c8 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-14.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 16.9967 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.7321 ( 7.3%) 2.7321 ( 16.1%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.3384 ( 6.2%) 2.3384 ( 13.8%) Parse modules + 0.3511 ( 0.9%) 0.3511 ( 2.1%) Verify circuit + 15.7928 ( 42.2%) 7.1579 ( 42.1%) 'firrtl.circuit' Pipeline + 0.3425 ( 0.9%) 0.3425 ( 2.0%) LowerFIRRTLAnnotations + 0.0979 ( 0.3%) 0.0979 ( 0.6%) LowerIntrinsics + 0.0978 ( 0.3%) 0.0978 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.9593 ( 7.9%) 0.7585 ( 4.5%) 'firrtl.module' Pipeline + 1.2505 ( 3.3%) 0.3255 ( 1.9%) DropName + 1.7055 ( 4.6%) 0.4323 ( 2.5%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1327 ( 0.4%) 0.0337 ( 0.2%) 'firrtl.module' Pipeline + 0.1247 ( 0.3%) 0.0329 ( 0.2%) LowerCHIRRTLPass + 0.1008 ( 0.3%) 0.1008 ( 0.6%) InferWidths + 0.2558 ( 0.7%) 0.2558 ( 1.5%) MemToRegOfVec + 0.3888 ( 1.0%) 0.3888 ( 2.3%) InferResets + 0.0541 ( 0.1%) 0.0541 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0719 ( 0.2%) 0.0719 ( 0.4%) WireDFT + 0.5324 ( 1.4%) 0.1367 ( 0.8%) 'firrtl.module' Pipeline + 0.5303 ( 1.4%) 0.1361 ( 0.8%) FlattenMemory + 0.2628 ( 0.7%) 0.2628 ( 1.5%) LowerFIRRTLTypes + 0.6895 ( 1.8%) 0.1775 ( 1.0%) 'firrtl.module' Pipeline + 0.6673 ( 1.8%) 0.1723 ( 1.0%) ExpandWhens + 0.0183 ( 0.0%) 0.0057 ( 0.0%) SFCCompat + 0.3346 ( 0.9%) 0.3346 ( 2.0%) Inliner + 0.5648 ( 1.5%) 0.1459 ( 0.9%) 'firrtl.module' Pipeline + 0.5628 ( 1.5%) 0.1454 ( 0.9%) RandomizeRegisterInit + 0.9900 ( 2.6%) 0.9900 ( 5.8%) CheckCombLoops + 0.0507 ( 0.1%) 0.0507 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.4242 ( 9.1%) 0.8872 ( 5.2%) 'firrtl.module' Pipeline + 3.1230 ( 8.3%) 0.8214 ( 4.8%) Canonicalizer + 0.2977 ( 0.8%) 0.0794 ( 0.5%) InferReadWrite + 0.1512 ( 0.4%) 0.1512 ( 0.9%) PrefixModules + 0.0597 ( 0.2%) 0.0597 ( 0.4%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6999 ( 1.9%) 0.6999 ( 4.1%) IMConstProp + 0.0629 ( 0.2%) 0.0629 ( 0.4%) AddSeqMemPorts + 0.0627 ( 0.2%) 0.0627 ( 0.4%) (A) circt::firrtl::InstanceGraph + 0.1666 ( 0.4%) 0.1666 ( 1.0%) CreateSiFiveMetadata + 0.0437 ( 0.1%) 0.0437 ( 0.3%) ExtractInstances + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.0001 ( 0.0%) 0.0001 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3320 ( 0.9%) 0.0849 ( 0.5%) 'firrtl.module' Pipeline + 0.3300 ( 0.9%) 0.0844 ( 0.5%) DropName + 0.3280 ( 0.9%) 0.3280 ( 1.9%) SymbolDCE + 0.2387 ( 0.6%) 0.2387 ( 1.4%) InnerSymbolDCE + 2.0336 ( 5.4%) 1.1501 ( 6.8%) 'firrtl.circuit' Pipeline + 0.8835 ( 2.4%) 0.2261 ( 1.3%) 'firrtl.module' Pipeline + 0.8815 ( 2.4%) 0.2258 ( 1.3%) Canonicalizer + 0.5429 ( 1.4%) 0.5429 ( 3.2%) IMDeadCodeElim + 0.0566 ( 0.2%) 0.0566 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0249 ( 0.1%) 0.0249 ( 0.1%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2649 ( 0.7%) 0.2649 ( 1.6%) LowerXMR + 0.0550 ( 0.1%) 0.0550 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.7052 ( 1.9%) 0.7052 ( 4.1%) LowerFIRRTLToHW + 0.0566 ( 0.2%) 0.0566 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.3322 ( 14.2%) 1.4892 ( 8.8%) 'hw.module' Pipeline + 0.9630 ( 2.6%) 0.2626 ( 1.5%) CSE + 0.0010 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 3.1011 ( 8.3%) 1.0386 ( 6.1%) Canonicalizer + 0.6450 ( 1.7%) 0.1819 ( 1.1%) CSE + 0.0008 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.6167 ( 1.6%) 0.2236 ( 1.3%) LowerSeqFIRRTLToSV + 0.1815 ( 0.5%) 0.1815 ( 1.1%) HWMemSimImpl + 3.5048 ( 9.4%) 1.0149 ( 6.0%) 'hw.module' Pipeline + 0.9539 ( 2.5%) 0.2744 ( 1.6%) CSE + 0.0011 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 1.7404 ( 4.6%) 0.6200 ( 3.6%) Canonicalizer + 0.5391 ( 1.4%) 0.1733 ( 1.0%) CSE + 0.0010 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.2640 ( 0.7%) 0.0785 ( 0.5%) HWCleanup + 0.5812 ( 1.6%) 0.1457 ( 0.9%) 'hw.module' Pipeline + 0.0610 ( 0.2%) 0.0162 ( 0.1%) HWLegalizeModules + 0.5153 ( 1.4%) 0.1308 ( 0.8%) PrettifyVerilog + 0.2179 ( 0.6%) 0.2179 ( 1.3%) StripDebugInfoWithPred + 1.6717 ( 4.5%) 1.6717 ( 9.8%) ExportVerilog + 2.0702 ( 5.5%) 0.5389 ( 3.2%) 'builtin.module' Pipeline + 1.5313 ( 4.1%) 0.3865 ( 2.3%) 'hw.module' Pipeline + 1.5289 ( 4.1%) 0.3859 ( 2.3%) PrepareForEmission + -0.5339 ( -1.4%) -0.5339 ( -3.1%) Rest + 37.4646 (100.0%) 16.9967 (100.0%) Total + +{ + totalTime: 17.039, + maxMemory: 875130880 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-14.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-14.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-14.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I