diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-10-23.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-10-23.log new file mode 100644 index 0000000..4105e6b --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-10-23.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 16.6526 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.6779 ( 7.2%) 2.6779 ( 16.1%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.2773 ( 6.2%) 2.2773 ( 13.7%) Parse modules + 0.3585 ( 1.0%) 0.3585 ( 2.2%) Verify circuit + 15.3340 ( 41.4%) 6.9137 ( 41.5%) 'firrtl.circuit' Pipeline + 0.3401 ( 0.9%) 0.3401 ( 2.0%) LowerFIRRTLAnnotations + 0.0923 ( 0.2%) 0.0923 ( 0.6%) LowerIntrinsics + 0.0921 ( 0.2%) 0.0921 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.9636 ( 8.0%) 0.7623 ( 4.6%) 'firrtl.module' Pipeline + 1.2677 ( 3.4%) 0.3327 ( 2.0%) DropName + 1.6928 ( 4.6%) 0.4396 ( 2.6%) CSE + 0.0010 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1510 ( 0.4%) 0.0381 ( 0.2%) 'firrtl.module' Pipeline + 0.1369 ( 0.4%) 0.0365 ( 0.2%) LowerCHIRRTLPass + 0.0995 ( 0.3%) 0.0995 ( 0.6%) InferWidths + 0.2219 ( 0.6%) 0.2219 ( 1.3%) MemToRegOfVec + 0.3737 ( 1.0%) 0.3737 ( 2.2%) InferResets + 0.0518 ( 0.1%) 0.0518 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0688 ( 0.2%) 0.0688 ( 0.4%) WireDFT + 0.5269 ( 1.4%) 0.1360 ( 0.8%) 'firrtl.module' Pipeline + 0.5249 ( 1.4%) 0.1355 ( 0.8%) FlattenMemory + 0.2629 ( 0.7%) 0.2629 ( 1.6%) LowerFIRRTLTypes + 0.6888 ( 1.9%) 0.1775 ( 1.1%) 'firrtl.module' Pipeline + 0.6677 ( 1.8%) 0.1716 ( 1.0%) ExpandWhens + 0.0177 ( 0.0%) 0.0058 ( 0.0%) SFCCompat + 0.3253 ( 0.9%) 0.3253 ( 2.0%) Inliner + 0.5511 ( 1.5%) 0.1416 ( 0.9%) 'firrtl.module' Pipeline + 0.5491 ( 1.5%) 0.1411 ( 0.8%) RandomizeRegisterInit + 0.9607 ( 2.6%) 0.9607 ( 5.8%) CheckCombLoops + 0.0521 ( 0.1%) 0.0521 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.2129 ( 8.7%) 0.8218 ( 4.9%) 'firrtl.module' Pipeline + 2.9335 ( 7.9%) 0.7643 ( 4.6%) Canonicalizer + 0.2761 ( 0.7%) 0.0754 ( 0.5%) InferReadWrite + 0.1414 ( 0.4%) 0.1414 ( 0.8%) PrefixModules + 0.0544 ( 0.1%) 0.0544 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6582 ( 1.8%) 0.6582 ( 4.0%) IMConstProp + 0.0523 ( 0.1%) 0.0523 ( 0.3%) AddSeqMemPorts + 0.0521 ( 0.1%) 0.0521 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.1628 ( 0.4%) 0.1628 ( 1.0%) CreateSiFiveMetadata + 0.0425 ( 0.1%) 0.0425 ( 0.3%) ExtractInstances + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.0000 ( 0.0%) 0.0000 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3259 ( 0.9%) 0.0836 ( 0.5%) 'firrtl.module' Pipeline + 0.3231 ( 0.9%) 0.0830 ( 0.5%) DropName + 0.3124 ( 0.8%) 0.3124 ( 1.9%) SymbolDCE + 0.2326 ( 0.6%) 0.2326 ( 1.4%) InnerSymbolDCE + 1.9787 ( 5.3%) 1.1063 ( 6.6%) 'firrtl.circuit' Pipeline + 0.8724 ( 2.4%) 0.2236 ( 1.3%) 'firrtl.module' Pipeline + 0.8701 ( 2.3%) 0.2228 ( 1.3%) Canonicalizer + 0.5186 ( 1.4%) 0.5186 ( 3.1%) IMDeadCodeElim + 0.0516 ( 0.1%) 0.0516 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0242 ( 0.1%) 0.0242 ( 0.1%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2511 ( 0.7%) 0.2511 ( 1.5%) LowerXMR + 0.0495 ( 0.1%) 0.0495 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.7116 ( 1.9%) 0.7116 ( 4.3%) LowerFIRRTLToHW + 0.0517 ( 0.1%) 0.0517 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.2617 ( 14.2%) 1.4616 ( 8.8%) 'hw.module' Pipeline + 0.9546 ( 2.6%) 0.2486 ( 1.5%) CSE + 0.0007 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 3.0687 ( 8.3%) 1.0062 ( 6.0%) Canonicalizer + 0.6292 ( 1.7%) 0.1727 ( 1.0%) CSE + 0.0006 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.6041 ( 1.6%) 0.2048 ( 1.2%) LowerSeqFIRRTLToSV + 0.1777 ( 0.5%) 0.1777 ( 1.1%) HWMemSimImpl + 3.6953 ( 10.0%) 1.0407 ( 6.2%) 'hw.module' Pipeline + 1.0210 ( 2.8%) 0.2911 ( 1.7%) CSE + 0.0013 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 1.8294 ( 4.9%) 0.6535 ( 3.9%) Canonicalizer + 0.5532 ( 1.5%) 0.1791 ( 1.1%) CSE + 0.0013 ( 0.0%) 0.0006 ( 0.0%) (A) DominanceInfo + 0.2839 ( 0.8%) 0.0988 ( 0.6%) HWCleanup + 0.5904 ( 1.6%) 0.1478 ( 0.9%) 'hw.module' Pipeline + 0.0596 ( 0.2%) 0.0155 ( 0.1%) HWLegalizeModules + 0.5257 ( 1.4%) 0.1332 ( 0.8%) PrettifyVerilog + 0.2162 ( 0.6%) 0.2162 ( 1.3%) StripDebugInfoWithPred + 1.6756 ( 4.5%) 1.6756 ( 10.1%) ExportVerilog + 2.0797 ( 5.6%) 0.5430 ( 3.3%) 'builtin.module' Pipeline + 1.5368 ( 4.2%) 0.3901 ( 2.3%) 'hw.module' Pipeline + 1.5344 ( 4.1%) 0.3895 ( 2.3%) PrepareForEmission + -0.5382 ( -1.5%) -0.5382 ( -3.2%) Rest + 37.0295 (100.0%) 16.6526 (100.0%) Total + +{ + totalTime: 16.701, + maxMemory: 866242560 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-10-23.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-10-23.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-10-23.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I