diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-05.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-05.log new file mode 100644 index 0000000..2bb4306 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-05.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 17.5497 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.7732 ( 7.1%) 2.7732 ( 15.8%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.3742 ( 6.1%) 2.3742 ( 13.5%) Parse modules + 0.3542 ( 0.9%) 0.3542 ( 2.0%) Verify circuit + 16.4387 ( 42.3%) 7.3045 ( 41.6%) 'firrtl.circuit' Pipeline + 0.3506 ( 0.9%) 0.3506 ( 2.0%) LowerFIRRTLAnnotations + 0.0947 ( 0.2%) 0.0947 ( 0.5%) LowerIntrinsics + 0.0946 ( 0.2%) 0.0946 ( 0.5%) (A) circt::firrtl::InstanceGraph + 3.5441 ( 9.1%) 0.9254 ( 5.3%) 'firrtl.module' Pipeline + 1.6391 ( 4.2%) 0.4605 ( 2.6%) DropName + 1.8994 ( 4.9%) 0.4895 ( 2.8%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1141 ( 0.3%) 0.0291 ( 0.2%) 'firrtl.module' Pipeline + 0.1116 ( 0.3%) 0.0285 ( 0.2%) LowerCHIRRTLPass + 0.1051 ( 0.3%) 0.1051 ( 0.6%) InferWidths + 0.2113 ( 0.5%) 0.2113 ( 1.2%) MemToRegOfVec + 0.4083 ( 1.1%) 0.4083 ( 2.3%) InferResets + 0.0568 ( 0.1%) 0.0568 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0732 ( 0.2%) 0.0732 ( 0.4%) WireDFT + 0.5431 ( 1.4%) 0.1403 ( 0.8%) 'firrtl.module' Pipeline + 0.5408 ( 1.4%) 0.1398 ( 0.8%) FlattenMemory + 0.2735 ( 0.7%) 0.2735 ( 1.6%) LowerFIRRTLTypes + 0.7114 ( 1.8%) 0.1837 ( 1.0%) 'firrtl.module' Pipeline + 0.6881 ( 1.8%) 0.1770 ( 1.0%) ExpandWhens + 0.0200 ( 0.1%) 0.0064 ( 0.0%) SFCCompat + 0.3375 ( 0.9%) 0.3375 ( 1.9%) Inliner + 0.5530 ( 1.4%) 0.1420 ( 0.8%) 'firrtl.module' Pipeline + 0.5510 ( 1.4%) 0.1415 ( 0.8%) RandomizeRegisterInit + 0.9834 ( 2.5%) 0.9834 ( 5.6%) CheckCombLoops + 0.0528 ( 0.1%) 0.0528 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.3322 ( 8.6%) 0.8550 ( 4.9%) 'firrtl.module' Pipeline + 3.0341 ( 7.8%) 0.7884 ( 4.5%) Canonicalizer + 0.2947 ( 0.8%) 0.0787 ( 0.4%) InferReadWrite + 0.1556 ( 0.4%) 0.1556 ( 0.9%) PrefixModules + 0.0618 ( 0.2%) 0.0618 ( 0.4%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6859 ( 1.8%) 0.6859 ( 3.9%) IMConstProp + 0.0628 ( 0.2%) 0.0628 ( 0.4%) AddSeqMemPorts + 0.0626 ( 0.2%) 0.0626 ( 0.4%) (A) circt::firrtl::InstanceGraph + 0.1702 ( 0.4%) 0.1702 ( 1.0%) CreateSiFiveMetadata + 0.0467 ( 0.1%) 0.0467 ( 0.3%) ExtractInstances + 0.0003 ( 0.0%) 0.0003 ( 0.0%) (A) circt::firrtl::NLATable + 0.0001 ( 0.0%) 0.0001 ( 0.0%) GrandCentral + 0.0004 ( 0.0%) 0.0004 ( 0.0%) BlackBoxReader + 0.3364 ( 0.9%) 0.0864 ( 0.5%) 'firrtl.module' Pipeline + 0.3340 ( 0.9%) 0.0859 ( 0.5%) DropName + 0.3409 ( 0.9%) 0.3409 ( 1.9%) SymbolDCE + 0.2541 ( 0.7%) 0.2541 ( 1.4%) InnerSymbolDCE + 2.0791 ( 5.3%) 1.1793 ( 6.7%) 'firrtl.circuit' Pipeline + 0.8999 ( 2.3%) 0.2307 ( 1.3%) 'firrtl.module' Pipeline + 0.8978 ( 2.3%) 0.2302 ( 1.3%) Canonicalizer + 0.5592 ( 1.4%) 0.5592 ( 3.2%) IMDeadCodeElim + 0.0614 ( 0.2%) 0.0614 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0273 ( 0.1%) 0.0273 ( 0.2%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2675 ( 0.7%) 0.2675 ( 1.5%) LowerXMR + 0.0563 ( 0.1%) 0.0563 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.7387 ( 1.9%) 0.7387 ( 4.2%) LowerFIRRTLToHW + 0.0636 ( 0.2%) 0.0636 ( 0.4%) (A) circt::firrtl::InstanceGraph + 0.0003 ( 0.0%) 0.0003 ( 0.0%) (A) circt::firrtl::NLATable + 5.3807 ( 13.8%) 1.5350 ( 8.7%) 'hw.module' Pipeline + 0.9859 ( 2.5%) 0.2565 ( 1.5%) CSE + 0.0009 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 3.0952 ( 8.0%) 1.0019 ( 5.7%) Canonicalizer + 0.6583 ( 1.7%) 0.1888 ( 1.1%) CSE + 0.0007 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.6351 ( 1.6%) 0.2019 ( 1.2%) LowerSeqFIRRTLToSV + 0.1961 ( 0.5%) 0.1961 ( 1.1%) HWMemSimImpl + 3.6694 ( 9.4%) 1.0829 ( 6.2%) 'hw.module' Pipeline + 0.9889 ( 2.5%) 0.2814 ( 1.6%) CSE + 0.0013 ( 0.0%) 0.0005 ( 0.0%) (A) DominanceInfo + 1.8384 ( 4.7%) 0.6828 ( 3.9%) Canonicalizer + 0.5501 ( 1.4%) 0.1737 ( 1.0%) CSE + 0.0011 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 0.2843 ( 0.7%) 0.0827 ( 0.5%) HWCleanup + 0.6352 ( 1.6%) 0.1599 ( 0.9%) 'hw.module' Pipeline + 0.0654 ( 0.2%) 0.0175 ( 0.1%) HWLegalizeModules + 0.5616 ( 1.4%) 0.1423 ( 0.8%) PrettifyVerilog + 0.2337 ( 0.6%) 0.2337 ( 1.3%) StripDebugInfoWithPred + 1.7795 ( 4.6%) 1.7795 ( 10.1%) ExportVerilog + 2.1882 ( 5.6%) 0.5775 ( 3.3%) 'builtin.module' Pipeline + 1.6107 ( 4.1%) 0.4086 ( 2.3%) 'hw.module' Pipeline + 1.6083 ( 4.1%) 0.4081 ( 2.3%) PrepareForEmission + -0.5724 ( -1.5%) -0.5724 ( -3.3%) Rest + 38.8799 (100.0%) 17.5497 (100.0%) Total + +{ + totalTime: 17.595, + maxMemory: 876728320 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-05.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-05.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-05.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I