diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-13.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-13.log new file mode 100644 index 0000000..b8dc6dc --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-11-13.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 16.0876 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.5400 ( 7.0%) 2.5400 ( 15.8%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.1394 ( 5.9%) 2.1394 ( 13.3%) Parse modules + 0.3584 ( 1.0%) 0.3584 ( 2.2%) Verify circuit + 15.2996 ( 42.4%) 6.7928 ( 42.2%) 'firrtl.circuit' Pipeline + 0.3701 ( 1.0%) 0.3701 ( 2.3%) LowerFIRRTLAnnotations + 0.0914 ( 0.3%) 0.0914 ( 0.6%) LowerIntrinsics + 0.0913 ( 0.3%) 0.0913 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.8892 ( 8.0%) 0.7456 ( 4.6%) 'firrtl.module' Pipeline + 1.2105 ( 3.4%) 0.3239 ( 2.0%) DropName + 1.6746 ( 4.6%) 0.4230 ( 2.6%) CSE + 0.0010 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1126 ( 0.3%) 0.0288 ( 0.2%) 'firrtl.module' Pipeline + 0.1099 ( 0.3%) 0.0281 ( 0.2%) LowerCHIRRTLPass + 0.0910 ( 0.3%) 0.0910 ( 0.6%) InferWidths + 0.1988 ( 0.6%) 0.1988 ( 1.2%) MemToRegOfVec + 0.3690 ( 1.0%) 0.3690 ( 2.3%) InferResets + 0.0496 ( 0.1%) 0.0496 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0651 ( 0.2%) 0.0651 ( 0.4%) WireDFT + 0.5108 ( 1.4%) 0.1315 ( 0.8%) 'firrtl.module' Pipeline + 0.5088 ( 1.4%) 0.1310 ( 0.8%) FlattenMemory + 0.2570 ( 0.7%) 0.2570 ( 1.6%) LowerFIRRTLTypes + 0.6762 ( 1.9%) 0.1744 ( 1.1%) 'firrtl.module' Pipeline + 0.6562 ( 1.8%) 0.1697 ( 1.1%) ExpandWhens + 0.0167 ( 0.0%) 0.0056 ( 0.0%) SFCCompat + 0.3173 ( 0.9%) 0.3173 ( 2.0%) Inliner + 0.5402 ( 1.5%) 0.1392 ( 0.9%) 'firrtl.module' Pipeline + 0.5379 ( 1.5%) 0.1387 ( 0.9%) RandomizeRegisterInit + 0.9488 ( 2.6%) 0.9488 ( 5.9%) CheckCombLoops + 0.0490 ( 0.1%) 0.0490 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.4620 ( 9.6%) 0.8926 ( 5.5%) 'firrtl.module' Pipeline + 3.1729 ( 8.8%) 0.8359 ( 5.2%) Canonicalizer + 0.2806 ( 0.8%) 0.0777 ( 0.5%) InferReadWrite + 0.1363 ( 0.4%) 0.1363 ( 0.8%) PrefixModules + 0.0518 ( 0.1%) 0.0518 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6140 ( 1.7%) 0.6140 ( 3.8%) IMConstProp + 0.0510 ( 0.1%) 0.0510 ( 0.3%) AddSeqMemPorts + 0.0508 ( 0.1%) 0.0508 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.1540 ( 0.4%) 0.1540 ( 1.0%) CreateSiFiveMetadata + 0.0380 ( 0.1%) 0.0380 ( 0.2%) ExtractInstances + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.0000 ( 0.0%) 0.0000 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3158 ( 0.9%) 0.0813 ( 0.5%) 'firrtl.module' Pipeline + 0.3136 ( 0.9%) 0.0809 ( 0.5%) DropName + 0.3018 ( 0.8%) 0.3018 ( 1.9%) SymbolDCE + 0.2234 ( 0.6%) 0.2234 ( 1.4%) InnerSymbolDCE + 1.9475 ( 5.4%) 1.0791 ( 6.7%) 'firrtl.circuit' Pipeline + 0.8684 ( 2.4%) 0.2207 ( 1.4%) 'firrtl.module' Pipeline + 0.8606 ( 2.4%) 0.2202 ( 1.4%) Canonicalizer + 0.5060 ( 1.4%) 0.5060 ( 3.1%) IMDeadCodeElim + 0.0512 ( 0.1%) 0.0512 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0234 ( 0.1%) 0.0234 ( 0.1%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2431 ( 0.7%) 0.2431 ( 1.5%) LowerXMR + 0.0451 ( 0.1%) 0.0451 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.6663 ( 1.8%) 0.6663 ( 4.1%) LowerFIRRTLToHW + 0.0485 ( 0.1%) 0.0485 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.1349 ( 14.2%) 1.4113 ( 8.8%) 'hw.module' Pipeline + 0.9325 ( 2.6%) 0.2505 ( 1.6%) CSE + 0.0008 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 2.9913 ( 8.3%) 0.9885 ( 6.1%) Canonicalizer + 0.6227 ( 1.7%) 0.1788 ( 1.1%) CSE + 0.0006 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.5823 ( 1.6%) 0.1934 ( 1.2%) LowerSeqFIRRTLToSV + 0.1708 ( 0.5%) 0.1708 ( 1.1%) HWMemSimImpl + 3.3825 ( 9.4%) 0.9499 ( 5.9%) 'hw.module' Pipeline + 0.9203 ( 2.6%) 0.2660 ( 1.7%) CSE + 0.0011 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 1.6707 ( 4.6%) 0.6047 ( 3.8%) Canonicalizer + 0.5322 ( 1.5%) 0.1748 ( 1.1%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.2522 ( 0.7%) 0.0742 ( 0.5%) HWCleanup + 0.5646 ( 1.6%) 0.1414 ( 0.9%) 'hw.module' Pipeline + 0.0552 ( 0.2%) 0.0157 ( 0.1%) HWLegalizeModules + 0.5042 ( 1.4%) 0.1278 ( 0.8%) PrettifyVerilog + 0.2056 ( 0.6%) 0.2056 ( 1.3%) StripDebugInfoWithPred + 1.6359 ( 4.5%) 1.6359 ( 10.2%) ExportVerilog + 2.0367 ( 5.6%) 0.5242 ( 3.3%) 'builtin.module' Pipeline + 1.5125 ( 4.2%) 0.3793 ( 2.4%) 'hw.module' Pipeline + 1.5101 ( 4.2%) 0.3788 ( 2.4%) PrepareForEmission + -0.5192 ( -1.4%) -0.5192 ( -3.2%) Rest + 36.0572 (100.0%) 16.0876 (100.0%) Total + +{ + totalTime: 16.129, + maxMemory: 880697344 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-13.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-13.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-11-13.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I