diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-19.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-19.log new file mode 100644 index 0000000..cbf9284 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-19.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 16.1691 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.5401 ( 7.1%) 2.5401 ( 15.7%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.1570 ( 6.0%) 2.1570 ( 13.3%) Parse modules + 0.3401 ( 0.9%) 0.3401 ( 2.1%) Verify circuit + 15.1099 ( 42.2%) 6.8123 ( 42.1%) 'firrtl.circuit' Pipeline + 0.3346 ( 0.9%) 0.3346 ( 2.1%) LowerFIRRTLAnnotations + 0.0915 ( 0.3%) 0.0915 ( 0.6%) LowerIntrinsics + 0.0914 ( 0.3%) 0.0914 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.8739 ( 8.0%) 0.7391 ( 4.6%) 'firrtl.module' Pipeline + 1.1899 ( 3.3%) 0.3139 ( 1.9%) DropName + 1.6800 ( 4.7%) 0.4245 ( 2.6%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1186 ( 0.3%) 0.0306 ( 0.2%) 'firrtl.module' Pipeline + 0.1161 ( 0.3%) 0.0301 ( 0.2%) LowerCHIRRTLPass + 0.0946 ( 0.3%) 0.0946 ( 0.6%) InferWidths + 0.2042 ( 0.6%) 0.2042 ( 1.3%) MemToRegOfVec + 0.4141 ( 1.2%) 0.4141 ( 2.6%) InferResets + 0.0499 ( 0.1%) 0.0499 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0656 ( 0.2%) 0.0656 ( 0.4%) WireDFT + 0.6183 ( 1.7%) 0.1572 ( 1.0%) 'firrtl.module' Pipeline + 0.5990 ( 1.7%) 0.1554 ( 1.0%) FlattenMemory + 0.2627 ( 0.7%) 0.2627 ( 1.6%) LowerFIRRTLTypes + 0.6762 ( 1.9%) 0.1742 ( 1.1%) 'firrtl.module' Pipeline + 0.6560 ( 1.8%) 0.1699 ( 1.1%) ExpandWhens + 0.0170 ( 0.0%) 0.0056 ( 0.0%) SFCCompat + 0.3157 ( 0.9%) 0.3157 ( 2.0%) Inliner + 0.5393 ( 1.5%) 0.1390 ( 0.9%) 'firrtl.module' Pipeline + 0.5373 ( 1.5%) 0.1386 ( 0.9%) RandomizeRegisterInit + 0.9399 ( 2.6%) 0.9399 ( 5.8%) CheckCombLoops + 0.0504 ( 0.1%) 0.0504 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.1518 ( 8.8%) 0.8103 ( 5.0%) 'firrtl.module' Pipeline + 2.8791 ( 8.0%) 0.7565 ( 4.7%) Canonicalizer + 0.2693 ( 0.8%) 0.0728 ( 0.5%) InferReadWrite + 0.1419 ( 0.4%) 0.1419 ( 0.9%) PrefixModules + 0.0564 ( 0.2%) 0.0564 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6282 ( 1.8%) 0.6282 ( 3.9%) IMConstProp + 0.0588 ( 0.2%) 0.0588 ( 0.4%) AddSeqMemPorts + 0.0586 ( 0.2%) 0.0586 ( 0.4%) (A) circt::firrtl::InstanceGraph + 0.1715 ( 0.5%) 0.1715 ( 1.1%) CreateSiFiveMetadata + 0.0420 ( 0.1%) 0.0420 ( 0.3%) ExtractInstances + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.0000 ( 0.0%) 0.0000 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3195 ( 0.9%) 0.0818 ( 0.5%) 'firrtl.module' Pipeline + 0.3173 ( 0.9%) 0.0814 ( 0.5%) DropName + 0.3099 ( 0.9%) 0.3099 ( 1.9%) SymbolDCE + 0.2266 ( 0.6%) 0.2266 ( 1.4%) InnerSymbolDCE + 1.9401 ( 5.4%) 1.0846 ( 6.7%) 'firrtl.circuit' Pipeline + 0.8555 ( 2.4%) 0.2186 ( 1.4%) 'firrtl.module' Pipeline + 0.8536 ( 2.4%) 0.2183 ( 1.4%) Canonicalizer + 0.5072 ( 1.4%) 0.5072 ( 3.1%) IMDeadCodeElim + 0.0512 ( 0.1%) 0.0512 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0234 ( 0.1%) 0.0234 ( 0.1%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2476 ( 0.7%) 0.2476 ( 1.5%) LowerXMR + 0.0477 ( 0.1%) 0.0477 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.6902 ( 1.9%) 0.6902 ( 4.3%) LowerFIRRTLToHW + 0.0507 ( 0.1%) 0.0507 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.0580 ( 14.1%) 1.3983 ( 8.6%) 'hw.module' Pipeline + 0.9350 ( 2.6%) 0.2565 ( 1.6%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 2.9303 ( 8.2%) 0.9610 ( 5.9%) Canonicalizer + 0.6138 ( 1.7%) 0.1774 ( 1.1%) CSE + 0.0007 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.5729 ( 1.6%) 0.2069 ( 1.3%) LowerSeqFIRRTLToSV + 0.1746 ( 0.5%) 0.1746 ( 1.1%) HWMemSimImpl + 3.3721 ( 9.4%) 0.9555 ( 5.9%) 'hw.module' Pipeline + 0.9218 ( 2.6%) 0.2689 ( 1.7%) CSE + 0.0011 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 1.6593 ( 4.6%) 0.6065 ( 3.8%) Canonicalizer + 0.5324 ( 1.5%) 0.1744 ( 1.1%) CSE + 0.0010 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.2510 ( 0.7%) 0.0764 ( 0.5%) HWCleanup + 0.5868 ( 1.6%) 0.1473 ( 0.9%) 'hw.module' Pipeline + 0.0588 ( 0.2%) 0.0158 ( 0.1%) HWLegalizeModules + 0.5232 ( 1.5%) 0.1325 ( 0.8%) PrettifyVerilog + 0.2113 ( 0.6%) 0.2113 ( 1.3%) StripDebugInfoWithPred + 1.6438 ( 4.6%) 1.6438 ( 10.2%) ExportVerilog + 2.0357 ( 5.7%) 0.5297 ( 3.3%) 'builtin.module' Pipeline + 1.5060 ( 4.2%) 0.3775 ( 2.3%) 'hw.module' Pipeline + 1.5034 ( 4.2%) 0.3768 ( 2.3%) PrepareForEmission + -0.5249 ( -1.5%) -0.5249 ( -3.2%) Rest + 35.8450 (100.0%) 16.1691 (100.0%) Total + +{ + totalTime: 16.211, + maxMemory: 880365568 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-19.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-19.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-19.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I