diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-13.log b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-13.log new file mode 100644 index 0000000..737c02d --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2024-08-13.log @@ -0,0 +1,99 @@ +===-------------------------------------------------------------------------=== + ... Execution time report ... +===-------------------------------------------------------------------------=== + Total Execution Time: 17.1043 seconds + + ----User Time---- ----Wall Time---- ----Name---- + 2.6500 ( 7.0%) 2.6500 ( 15.5%) FIR Parser + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse annotations + 0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR + 2.2627 ( 6.0%) 2.2627 ( 13.2%) Parse modules + 0.3455 ( 0.9%) 0.3455 ( 2.0%) Verify circuit + 15.6594 ( 41.4%) 7.0875 ( 41.4%) 'firrtl.circuit' Pipeline + 0.3388 ( 0.9%) 0.3388 ( 2.0%) LowerFIRRTLAnnotations + 0.0961 ( 0.3%) 0.0961 ( 0.6%) LowerIntrinsics + 0.0959 ( 0.3%) 0.0959 ( 0.6%) (A) circt::firrtl::InstanceGraph + 2.8833 ( 7.6%) 0.7394 ( 4.3%) 'firrtl.module' Pipeline + 1.2034 ( 3.2%) 0.3163 ( 1.8%) DropName + 1.6767 ( 4.4%) 0.4225 ( 2.5%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy + 0.1132 ( 0.3%) 0.0289 ( 0.2%) 'firrtl.module' Pipeline + 0.1107 ( 0.3%) 0.0284 ( 0.2%) LowerCHIRRTLPass + 0.0986 ( 0.3%) 0.0986 ( 0.6%) InferWidths + 0.2544 ( 0.7%) 0.2544 ( 1.5%) MemToRegOfVec + 0.3811 ( 1.0%) 0.3811 ( 2.2%) InferResets + 0.0568 ( 0.2%) 0.0568 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0700 ( 0.2%) 0.0700 ( 0.4%) WireDFT + 0.5270 ( 1.4%) 0.1361 ( 0.8%) 'firrtl.module' Pipeline + 0.5250 ( 1.4%) 0.1357 ( 0.8%) FlattenMemory + 0.2659 ( 0.7%) 0.2659 ( 1.6%) LowerFIRRTLTypes + 0.7020 ( 1.9%) 0.1814 ( 1.1%) 'firrtl.module' Pipeline + 0.6669 ( 1.8%) 0.1693 ( 1.0%) ExpandWhens + 0.0185 ( 0.0%) 0.0060 ( 0.0%) SFCCompat + 0.3378 ( 0.9%) 0.3378 ( 2.0%) Inliner + 0.5603 ( 1.5%) 0.1442 ( 0.8%) 'firrtl.module' Pipeline + 0.5582 ( 1.5%) 0.1435 ( 0.8%) RandomizeRegisterInit + 1.0068 ( 2.7%) 1.0068 ( 5.9%) CheckCombLoops + 0.0558 ( 0.1%) 0.0558 ( 0.3%) (A) circt::firrtl::InstanceGraph + 3.4489 ( 9.1%) 0.8999 ( 5.3%) 'firrtl.module' Pipeline + 3.1577 ( 8.3%) 0.8373 ( 4.9%) Canonicalizer + 0.2878 ( 0.8%) 0.0785 ( 0.5%) InferReadWrite + 0.1475 ( 0.4%) 0.1475 ( 0.9%) PrefixModules + 0.0564 ( 0.1%) 0.0564 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.6463 ( 1.7%) 0.6463 ( 3.8%) IMConstProp + 0.0566 ( 0.1%) 0.0566 ( 0.3%) AddSeqMemPorts + 0.0564 ( 0.1%) 0.0564 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.1626 ( 0.4%) 0.1626 ( 1.0%) CreateSiFiveMetadata + 0.0428 ( 0.1%) 0.0428 ( 0.3%) ExtractInstances + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 0.0000 ( 0.0%) 0.0000 ( 0.0%) GrandCentral + 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader + 0.3373 ( 0.9%) 0.0858 ( 0.5%) 'firrtl.module' Pipeline + 0.3352 ( 0.9%) 0.0854 ( 0.5%) DropName + 0.3234 ( 0.9%) 0.3234 ( 1.9%) SymbolDCE + 0.2429 ( 0.6%) 0.2429 ( 1.4%) InnerSymbolDCE + 2.0396 ( 5.4%) 1.1498 ( 6.7%) 'firrtl.circuit' Pipeline + 0.8897 ( 2.4%) 0.2262 ( 1.3%) 'firrtl.module' Pipeline + 0.8879 ( 2.3%) 0.2257 ( 1.3%) Canonicalizer + 0.5411 ( 1.4%) 0.5411 ( 3.2%) IMDeadCodeElim + 0.0546 ( 0.1%) 0.0546 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0000 ( 0.0%) 0.0000 ( 0.0%) EmitOMIR + 0.0262 ( 0.1%) 0.0262 ( 0.2%) ResolveTraces + 0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable + 0.2636 ( 0.7%) 0.2636 ( 1.5%) LowerXMR + 0.0530 ( 0.1%) 0.0530 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.7204 ( 1.9%) 0.7204 ( 4.2%) LowerFIRRTLToHW + 0.0563 ( 0.1%) 0.0563 ( 0.3%) (A) circt::firrtl::InstanceGraph + 0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable + 5.2509 ( 13.9%) 1.4457 ( 8.5%) 'hw.module' Pipeline + 0.9689 ( 2.6%) 0.2552 ( 1.5%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 3.0581 ( 8.1%) 0.9910 ( 5.8%) Canonicalizer + 0.6132 ( 1.6%) 0.1674 ( 1.0%) CSE + 0.0007 ( 0.0%) 0.0002 ( 0.0%) (A) DominanceInfo + 0.6048 ( 1.6%) 0.1986 ( 1.2%) LowerSeqFIRRTLToSV + 0.1878 ( 0.5%) 0.1878 ( 1.1%) HWMemSimImpl + 3.6324 ( 9.6%) 1.0622 ( 6.2%) 'hw.module' Pipeline + 0.9515 ( 2.5%) 0.2721 ( 1.6%) CSE + 0.0012 ( 0.0%) 0.0004 ( 0.0%) (A) DominanceInfo + 1.8264 ( 4.8%) 0.6561 ( 3.8%) Canonicalizer + 0.5588 ( 1.5%) 0.1572 ( 0.9%) CSE + 0.0009 ( 0.0%) 0.0003 ( 0.0%) (A) DominanceInfo + 0.2884 ( 0.8%) 0.0836 ( 0.5%) HWCleanup + 0.7190 ( 1.9%) 0.1908 ( 1.1%) 'hw.module' Pipeline + 0.0768 ( 0.2%) 0.0225 ( 0.1%) HWLegalizeModules + 0.6370 ( 1.7%) 0.1670 ( 1.0%) PrettifyVerilog + 0.2485 ( 0.7%) 0.2485 ( 1.5%) StripDebugInfoWithPred + 1.7896 ( 4.7%) 1.7896 ( 10.5%) ExportVerilog + 2.2492 ( 5.9%) 0.5933 ( 3.5%) 'builtin.module' Pipeline + 1.6559 ( 4.4%) 0.4177 ( 2.4%) 'hw.module' Pipeline + 1.6530 ( 4.4%) 0.4166 ( 2.4%) PrepareForEmission + -0.5884 ( -1.6%) -0.5884 ( -3.4%) Rest + 37.8242 (100.0%) 17.1043 (100.0%) Total + +{ + totalTime: 17.147, + maxMemory: 874217472 +} diff --git a/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-13.json b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-13.json new file mode 100644 index 0000000..7261973 --- /dev/null +++ b/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2024-08-13.json @@ -0,0 +1,49 @@ +{ + "errors": { + "'table_1_ext'": 1, + "This may be because there's no search path specified with -I