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Add debug outputs to sgmiiCdc
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jvnknvlgl committed Jul 1, 2024
1 parent 3606764 commit 0db48a9
Showing 1 changed file with 5 additions and 1 deletion.
6 changes: 5 additions & 1 deletion clash-cores/src/Clash/Cores/Sgmii.hs
Original file line number Diff line number Diff line change
Expand Up @@ -28,12 +28,16 @@ sgmiiCdc ::
Signal txDom Bool ->
Signal txDom (BitVector 8) ->
Signal rxDom (BitVector 10) ->
(Signal rxDom (Bool, Bool, BitVector 8), Signal txDom (BitVector 10))
( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10)
, Signal txDom (BitVector 10)
)
sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
( bundle
( exposeClockResetEnable regMaybe rxClk rxRst enableGen False rxDv
, exposeClockResetEnable regMaybe rxClk rxRst enableGen False rxEr
, exposeClockResetEnable regMaybe rxClk rxRst enableGen 0 dw4
, fromDw . head <$> dw2
, cg2
)
, cg4
)
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