From 0db48a94b6438ed2b24ab83e938a54769a4a01d6 Mon Sep 17 00:00:00 2001
From: Jasper Vinkenvleugel <j.t.vinkenvleugel@proton.me>
Date: Fri, 28 Jun 2024 14:13:10 +0200
Subject: [PATCH] Add debug outputs to sgmiiCdc

---
 clash-cores/src/Clash/Cores/Sgmii.hs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/clash-cores/src/Clash/Cores/Sgmii.hs b/clash-cores/src/Clash/Cores/Sgmii.hs
index 6f44896d93..2e0372eac2 100644
--- a/clash-cores/src/Clash/Cores/Sgmii.hs
+++ b/clash-cores/src/Clash/Cores/Sgmii.hs
@@ -28,12 +28,16 @@ sgmiiCdc ::
   Signal txDom Bool ->
   Signal txDom (BitVector 8) ->
   Signal rxDom (BitVector 10) ->
-  (Signal rxDom (Bool, Bool, BitVector 8), Signal txDom (BitVector 10))
+  ( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10)
+  , Signal txDom (BitVector 10)
+  )
 sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
   ( bundle
       ( exposeClockResetEnable regMaybe rxClk rxRst enableGen False rxDv
       , exposeClockResetEnable regMaybe rxClk rxRst enableGen False rxEr
       , exposeClockResetEnable regMaybe rxClk rxRst enableGen 0 dw4
+      , fromDw . head <$> dw2
+      , cg2
       )
   , cg4
   )