From 6c9781eca624904b7ed5a7919bdcd321f42253af Mon Sep 17 00:00:00 2001 From: Leon Schoorl Date: Mon, 30 Sep 2024 16:26:14 +0200 Subject: [PATCH] Fix (System)Verilog literal rendering of Index values There was confusion between the size in bits and the type level argument to Index. Fixes #2813 --- clash-lib/src/Clash/Backend/SystemVerilog.hs | 4 +++- clash-lib/src/Clash/Backend/Verilog.hs | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs index 88928dc138..f9af26948f 100644 --- a/clash-lib/src/Clash/Backend/SystemVerilog.hs +++ b/clash-lib/src/Clash/Backend/SystemVerilog.hs @@ -1228,7 +1228,9 @@ expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _) expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _) | pNm == "Clash.Sized.Internal.Index.fromInteger#" , [Literal _ (NumLit n), Literal _ i] <- extractLiterals bbCtx - = exprLitSV (Just (Index (fromInteger n),fromInteger n)) i + , Just k <- clogBase 2 n + , let k' = max 1 k + = exprLitSV (Just (Index (fromInteger n),k')) i expr_ b (BlackBoxE _ libs imps inc bs bbCtx b') = parenIf (b || b') (Ap (renderBlackBox libs imps inc bs bbCtx <*> pure 0)) diff --git a/clash-lib/src/Clash/Backend/Verilog.hs b/clash-lib/src/Clash/Backend/Verilog.hs index 1dd81118db..79884623f0 100644 --- a/clash-lib/src/Clash/Backend/Verilog.hs +++ b/clash-lib/src/Clash/Backend/Verilog.hs @@ -1151,7 +1151,9 @@ expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _) expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _) | pNm == "Clash.Sized.Internal.Index.fromInteger#" , [Literal _ (NumLit n), Literal _ i] <- extractLiterals bbCtx - = exprLit undefValue (Just (Index (fromInteger n),fromInteger n)) i + , Just k <- clogBase 2 n + , let k' = max 1 k + = exprLit undefValue (Just (Index (fromInteger n),k')) i expr_ b (BlackBoxE _ libs imps inc bs bbCtx b') = do parenIf (b || b') (Ap (renderBlackBox libs imps inc bs bbCtx <*> pure 0))