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Fixes for FPGA tests
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jvnknvlgl committed Jul 1, 2024
1 parent 4c506e3 commit 9fb6324
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Showing 5 changed files with 22 additions and 31 deletions.
6 changes: 2 additions & 4 deletions clash-cores/src/Clash/Cores/Sgmii.hs
Original file line number Diff line number Diff line change
Expand Up @@ -28,17 +28,15 @@ sgmiiCdc ::
Signal txDom Bool ->
Signal txDom (BitVector 8) ->
Signal rxDom (BitVector 10) ->
( Signal rxDom (Bool, Bool, BitVector 8, BitVector 8, BitVector 10, Bool)
( Signal rxDom (Bool, Bool, BitVector 8, BitVector 10)
, Signal txDom (BitVector 10)
)
sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
( bundle
( exposeClockResetEnable regMaybe rxClk rxRst enableGen False rxDv
, exposeClockResetEnable regMaybe rxClk rxRst enableGen False rxEr
, exposeClockResetEnable regMaybe rxClk rxRst enableGen 0 dw4
, fromDw . head <$> dw2
, cg2
, ok
)
, cg4
)
Expand Down Expand Up @@ -70,7 +68,7 @@ sgmiiCdc autoNegCdc rxClk txClk rxRst txRst txEn txEr dw1 cg1 =
where
sync' = exposeClockResetEnable sync

(cg2, ok) = unbundle $ bitSlip' rxClk rxRst enableGen cg1
(cg2, _) = unbundle $ bitSlip' rxClk rxRst enableGen cg1
where
bitSlip' = exposeClockResetEnable bitSlip

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26 changes: 13 additions & 13 deletions clash-cores/src/Clash/Cores/Sgmii/BitSlip.hs
Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@ import Clash.Prelude
import Data.Maybe (fromJust, isNothing)

-- | State variable for 'bitSlip'
data BitSlipState n
data BitSlipState
= BSFail
{ _s :: BitVector (2 * n)
, _ns :: Vec 8 (Index n)
, _hist :: Vec 10 (BitVector 7)
{ _s :: BitVector 20
, _ns :: Vec 8 (Index 14)
, _hist :: Vec 14 (BitVector 7)
}
| BSOk {_s :: BitVector (2 * n), _n :: Index n}
| BSOk {_s :: BitVector 20, _n :: Index 14}
deriving (Generic, NFDataX, Eq, Show)

-- | State transition function for 'bitSlip', where the initial state is the
Expand All @@ -22,11 +22,11 @@ data BitSlipState n
-- 'BitVector'
bitSlipT ::
-- | Current state
BitSlipState 10 ->
BitSlipState ->
-- | New input value
BitVector 10 ->
-- | New state
BitSlipState 10
BitSlipState
bitSlipT BSFail{..} cg = nextState
where
nextState
Expand All @@ -36,11 +36,11 @@ bitSlipT BSFail{..} cg = nextState

s = resize $ _s ++# cg
ns = maybe _ns (_ns <<+) n
hist = map pack $ take d10 $ windows1d d7 $ bv2v s
hist = map pack $ windows1d d7 $ bv2v s

n = elemIndex True $ map f _hist
where
f a = a == 0b0011111 || a == 0b1100000
f a = a == 0b1111100 || a == 0b0000011
bitSlipT BSOk{..} cg = nextState
where
nextState = BSOk s _n
Expand All @@ -51,15 +51,15 @@ bitSlipT BSOk{..} cg = nextState
-- rotates the state vector to create the new output value
bitSlipO ::
-- | Current state
BitSlipState 10 ->
BitSlipState ->
-- | New output value
(BitSlipState 10, BitVector 10, Bool)
(BitSlipState, BitVector 10, Bool)
bitSlipO self@BSFail{..} = out
where
out = (self, resize _s, False)
out = (self, resize $ rotateR _s 10, False)
bitSlipO self@BSOk{..} = out
where
out = (self, resize $ rotateR _s (10 - fromEnum _n), True)
out = (self, resize $ rotateR _s (13 - fromEnum _n), True)

-- | Function that takes a code word and returns the same code word, but if a
-- comma is detected the code words is shifted such that the comma is at the
Expand Down
4 changes: 2 additions & 2 deletions clash-cores/src/Clash/Cores/Sgmii/PcsReceive.hs
Original file line number Diff line number Diff line change
Expand Up @@ -95,8 +95,8 @@ carrierDetect cg rd rxEven
True
| otherwise = False
where
cgK28_5N = 0b0011111010
cgK28_5P = 0b1100000101
cgK28_5N = 0b0101111100
cgK28_5P = 0b1010000011
cgK28_5 = if rd then cgK28_5P else cgK28_5N

-- | Take the running disparity, the current and next two input data words and
Expand Down
15 changes: 4 additions & 11 deletions clash-cores/src/Clash/Cores/Sgmii/Sync.hs
Original file line number Diff line number Diff line change
Expand Up @@ -83,17 +83,10 @@ data SyncState
}
deriving (Generic, NFDataX, Eq, Show)

-- | Vector containing the 3 code groups that contain a comma (K28.1, K28.5 and
-- K28.7) and their alternative forms (with opposite running disparity)
commas :: Vec 6 (BitVector 10)
commas =
0b0011111001
:> 0b1100000110
:> 0b0011111010
:> 0b1100000101
:> 0b0011111000
:> 0b1100000111
:> Nil
-- | Vector containing the two alternative forms (with opposite running
-- disparity) of K28.5
commas :: Vec 2 (BitVector 10)
commas = 0b0101111100 :> 0b1010000011 :> Nil

-- | State transition function for 'sync'. Takes the state as defined in
-- 'SyncState', a the new incoming code group from the SerDes-block and
Expand Down
2 changes: 1 addition & 1 deletion clash-cores/test/Test/Cores/Sgmii/BitSlip.hs
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ import Prelude
bitSlipSim ::
(C.HiddenClockResetEnable dom) =>
C.Signal dom (C.BitVector 10) ->
C.Signal dom (BitSlipState 10, C.BitVector 10, Bool)
C.Signal dom (BitSlipState, C.BitVector 10, Bool)
bitSlipSim cg =
C.bundle $ C.mooreB bitSlipT bitSlipO (BSFail 0 (C.repeat 0) (C.repeat 0)) cg

Expand Down

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