Skip to content

Commit

Permalink
Fix the test for #1796
Browse files Browse the repository at this point in the history
Something probably changed since it was introduced.
It would prefer to read the source instead of the precompiled module and always succeed, even with the original fix reverted.
  • Loading branch information
leonschoorl committed Jun 20, 2024
1 parent 68f5f4c commit a40ff92
Show file tree
Hide file tree
Showing 3 changed files with 20 additions and 28 deletions.
6 changes: 3 additions & 3 deletions tests/clash-testsuite.cabal
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@ library
-- Behaviour when loading modules can differ if the module is loaded from
-- an external interface file. See
-- https://github.com/clash-lang/clash-compiler/issues/1796 for an example.
shouldwork/LoadModules
shouldwork/LoadModules/precompiled

exposed-modules:
Test.Tasty.Common
Expand All @@ -119,8 +119,8 @@ library
Test.Tasty.Vivado
Test.Tasty.Clash.CollectSimResults

-- From tests/shouldwork/LoadModules
T1796
-- From tests/shouldwork/LoadModules/precompiled
T1796a

other-modules:
Paths_clash_testsuite
Expand Down
27 changes: 2 additions & 25 deletions tests/shouldwork/LoadModules/T1796.hs
Original file line number Diff line number Diff line change
Expand Up @@ -4,29 +4,6 @@

module T1796 where

import Clash.Prelude
import T1796a

import Clash.Explicit.Testbench

topEntity
:: Signal System Bool
-> Signal System Bool
topEntity = id
-- See: https://github.com/clash-lang/clash-compiler/pull/2511
{-# CLASH_OPAQUE topEntity #-}

tb
:: Signal System Bool
tb = done
where
testInput = stimuliGenerator clk rst (singleton True)
expectOutput = outputVerifier' clk rst (singleton True)
done = expectOutput $ topEntity testInput
clk = tbClockGen @System (not <$> done)
rst = resetGen @System
{-# INLINE tb #-}

testBench :: Signal System Bool
testBench = tb
-- See: https://github.com/clash-lang/clash-compiler/pull/2511
{-# CLASH_OPAQUE testBench #-}
topEntity = tb
15 changes: 15 additions & 0 deletions tests/shouldwork/LoadModules/precompiled/T1796a.hs
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
{-# LANGUAGE CPP #-}
{-# LANGUAGE NoImplicitPrelude #-}
{-# LANGUAGE TypeApplications #-}

module T1796a where

import Clash.Explicit.Prelude
import Clash.Explicit.Testbench

tb :: Signal System Bool
tb = done
where
done = register clk rst enableGen False $ id (pure True)
clk = tbClockGen @System (not <$> done)
rst = resetGen @System

0 comments on commit a40ff92

Please sign in to comment.