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No inlining let-bound global vars with clock types
The global vars are usually backed by a clock generator that are not work-free. In addition, when these global vars are recursively defined, they can mess up the post-normalization flattening stage which then violates certain invariants of the netlist generation stage. This then causes the netlist generation stage to generate bad Verilog names. Fixes #2845
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FIXED: Clash generates illegal Verilog names [#2845](https://github.com/clash-lang/clash-compiler/issues/2845) |
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module T2845 where | ||
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import Clash.Explicit.Prelude | ||
import Clash.Explicit.Testbench | ||
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topEntity :: | ||
Signal System (Unsigned 8) | ||
topEntity = cntr + x | ||
where | ||
cntr = register clk noReset enableGen 0 0 | ||
x = register clk noReset enableGen 100 0 | ||
done = (== 100) <$> cntr | ||
clk = tbClockGen $ not <$> done |