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Render CompDecl in VHDL decl function #2819

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merged 1 commit into from
Oct 9, 2024
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christiaanb
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@christiaanb christiaanb commented Oct 4, 2024

Instead of rendering them in inst_. I noticed that while creating a primitive that when I used a combination of compInBlock and instDecl Empty that the entire block declaration and its declarative part were elided; leaving only the portmap.

So before this change, the following primitive declaration:

  = do
    plusFloatInstName <- Id.makeBasic "plusFloat_inst"

    let
      compInps =
        [ ("clk", N.Bit)
        , ("arg1", DSL.ety a)
        , ("arg2", DSL.ety b) ]
      compOuts =
        [ ("dout", DSL.ety result) ]

      plusFloatName = "plusFloat"

    DSL.declaration "plusFloat_inst_block" $ do
      DSL.compInBlock "plusFloat" compInps compOuts

      let
        inps =
          [ ("clk", clk )
          , ("arg1", a)
          , ("arg2", b)
          ]

        outs =
          [ ("dout", result)
          ]

      DSL.instDecl Empty (Id.unsafeMake plusFloatName) plusFloatInstName
        [] inps outs

would get translated to:

    plusFloat_inst : plusFloat
      port map
        ( clk  => clk
        , arg1 => y
        , arg2 => z
        , dout => \c$app_arg\ );

instead of the expected:

  plusFloat_inst_block : block
    component plusFloat port
      ( clk : in std_logic
      ; arg1 : in std_logic_vector(31 downto 0)
      ; arg2 : in std_logic_vector(31 downto 0)
      ; dout : out std_logic_vector(31 downto 0) );
    end component;
  begin
    plusFloat_inst : plusFloat
      port map
        ( clk  => clk
        , arg1 => y
        , arg2 => z
        , dout => \c$app_arg\ );


  end block;

Still TODO:

  • Check copyright notices are up to date in edited files

Instead of rendering them in `inst_`. I noticed that while creating
a primitive that when I used a combination of `compInBlock` and
`instDecl Empty` that the entire block declaration and its
declarative part were elided; leaving only the portmap.
@christiaanb
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christiaanb commented Oct 7, 2024

@DigitalBrains1 Could you review the change? I'm mostly asking you because you also reviewed #2255 which introduced component declarations.

@DigitalBrains1
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I am wildly unfamiliar with this part of our codebase :-D. I can't say anything pertinent about this PR.

(I notice in the PR you refer to I say "I've got something to say" and then Martijn requests my review but I never said anything else X-D. I suppose my point was already made by another reviewer.)

@christiaanb christiaanb merged commit 4cc4044 into master Oct 9, 2024
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@christiaanb christiaanb deleted the compdec_in_decs branch October 9, 2024 11:11
mergify bot pushed a commit that referenced this pull request Oct 9, 2024
Instead of rendering them in `inst_`. I noticed that while creating
a primitive that when I used a combination of `compInBlock` and
`instDecl Empty` that the entire block declaration and its
declarative part were elided; leaving only the portmap.

(cherry picked from commit 4cc4044)
christiaanb added a commit that referenced this pull request Nov 2, 2024
Render CompDecl in VHDL `decl` function (copy #2819)
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2 participants