Render CompDecl in VHDL decl
function
#2819
Merged
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Instead of rendering them in
inst_
. I noticed that while creating a primitive that when I used a combination ofcompInBlock
andinstDecl Empty
that the entire block declaration and its declarative part were elided; leaving only the portmap.So before this change, the following primitive declaration:
would get translated to:
instead of the expected:
Still TODO: