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Render CompDecl in VHDL decl function #2819

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Oct 9, 2024
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Render CompDecl in VHDL decl function #2819

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31 changes: 12 additions & 19 deletions clash-lib/src/Clash/Backend/VHDL.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ import qualified Data.HashMap.Strict as HashMapS
import Data.HashSet (HashSet)
import qualified Data.HashSet as HashSet
import Data.List
(mapAccumL, nub, nubBy, partition, intersperse, group, sort)
(mapAccumL, nub, nubBy, intersperse, group, sort)
import Data.List.Extra ((<:>), equalLength, zipEqual)
import Data.Maybe (catMaybes,mapMaybe)
import Data.Monoid (Ap(Ap))
Expand Down Expand Up @@ -254,24 +254,17 @@ instance Backend VHDLState where
| NetDecl' _ id_ hwtype _ <- ds
, attr <- hwTypeAttrs hwtype]
if isEmpty decs
then insts ids
then insts ds
else nest 2
(pretty nm <+> colon <+> "block" <> line <>
pure decs <>
(if null attrs
then emptyDoc
else line <> line <> renderAttrs (TextS.pack "signal") attrs) <>
if null cds
then emptyDoc
else line <> line <> insts cds) <> line <> "begin" <>
nest 2 (line <> insts ids)
else line <> line <> renderAttrs (TextS.pack "signal") attrs)) <> line <>
"begin" <>
nest 2 (line <> insts ds)
<> line <>
"end block" <> semi
where
(cds, ids) = partition isCompDecl ds

isCompDecl (CompDecl {}) = True
isCompDecl _ = False

addIncludes inc = includes %= (inc++)
addLibraries libs = libraries %= (libs ++)
Expand Down Expand Up @@ -1426,6 +1419,13 @@ decl _ (InstDecl Comp _ attrs nm _ gens (NamedPortMap pms)) = fmap (Just . (,0))
| null attrs = emptyDoc
| otherwise = renderAttrs (TextS.pack "component") [(nm, a) | a <- attrs]

decl _ (CompDecl nm ps0) =
fmap (Just . (,0)) $ "component" <+> pretty nm <+>
("port" <> line <> indent 2 (tupledSemi ps <> semi))
<> line <> "end component" <> semi
where ps = traverse (\(t,pd,ty) -> pretty t <+> ":" <+> ppd pd <+> sizedQualTyName ty) ps0
ppd = \case { In -> "in"; Out -> "out"}

decl _ _ = return Nothing

noEmptyInit :: VHDLM Doc -> VHDLM Doc
Expand Down Expand Up @@ -1522,13 +1522,6 @@ inst_ :: Declaration -> VHDLM (Maybe Doc)
inst_ (Assignment id_ Cont e) = fmap Just $
pretty id_ <+> larrow <+> align (expr_ False e) <> semi

inst_ (CompDecl nm ps0) =
fmap Just $ "component" <+> pretty nm <+>
("port" <> line <> indent 2 (tupledSemi ps <> semi))
<> line <> "end component" <> semi
where ps = traverse (\(t,pd,ty) -> pretty t <+> ":" <+> ppd pd <+> sizedQualTyName ty) ps0
ppd = \case { In -> "in"; Out -> "out"}

inst_ (CondAssignment id_ _ scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $
pretty id_ <+> larrow
<+> align (vsep (sequence [expr_ False t <+> "when" <+>
Expand Down