This repository contains a VexRiscv based CPU core and bindings for use in Clash.
For now this repository only contains one example CPU configuration, which implements a 32 bit IMC RISC-V core.
This package includes simulation via verilator as
well as a black-box for Verilog synthesis.
The core interfaces with other components via Wishbone
interfaces, using clash-protocols types.
For building the CPU, the following software needs to be installed and available in the PATH:
- a recent JDK installation
- SBT, the scala build tool
- a recent C compiler
verilator, at least version 5.001 (development version at time of writing)makefor building the verilated library and FFI code
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VexRiscv has a "reset vector" for the instruction bus. This is the initial PC that gets fetched. This address only gets presented to the IBUS after at least one cycle of RST being asserted.
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The contents of memories need to be stored in little endian. This means that for example the contents of an ELF file need to be endian-swapped before being used as the contents of the instruction storage. This applies to all storages.