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ADuCM350.h
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/*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file ADuCM350.h
* @brief CMSIS HeaderFile
* @version 1.0
* @date 08. November 2018
* @note Generated by SVDConv V3.3.21 on Thursday, 08.11.2018 10:36:11
* from File 'ADuCM350.svd',
* last modified on Wednesday, 07.11.2018 23:47:41
*/
/** @addtogroup Analog Devices
* @{
*/
/** @addtogroup ADuCM350
* @{
*/
#ifndef ADUCM350_H
#define ADUCM350_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum {
/* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== ADuCM350 Specific Interrupt Numbers ========================================== */
WUT_IRQn = 0, /*!< 0 Wake Up Timer interrupt */
EINT0_IRQn = 1, /*!< 1 External Interrupt 0 */
EINT1_IRQn = 2, /*!< 2 External Interrupt 1 */
EINT2_IRQn = 3, /*!< 3 External Interrupt 2 */
EINT3_IRQn = 4, /*!< 4 External Interrupt 3 */
EINT4_IRQn = 5, /*!< 5 External Interrupt 4 */
EINT5_IRQn = 6, /*!< 6 External Interrupt 5 */
EINT6_IRQn = 7, /*!< 7 External Interrupt 6 */
EINT7_IRQn = 8, /*!< 8 External Interrupt 7 */
EINT8_IRQn = 9, /*!< 9 External Interrupt 8 */
WDT_IRQn = 10, /*!< 10 WDT Interrupt */
TIMER0_IRQn = 11, /*!< 11 Timer interrupt */
TIMER1_IRQn = 12, /*!< 12 Timer 1 Interrupt */
FLASH0_IRQn = 13, /*!< 13 Flash Controller Interrupt */
UART_IRQn = 14, /*!< 14 interrupt */
SPI0_IRQn = 15, /*!< 15 SPI 0 interrupt */
SPIH_IRQn = 16, /*!< 16 interrupt */
I2CS_IRQn = 17, /*!< 17 I2C 0 slave interrupt */
I2CM_IRQn = 18, /*!< 18 I2C 0 master interrupt */
DMA_ERR_IRQn = 19, /*!< 19 DMA interrupt */
DMA_SPIH_TX_IRQn = 20, /*!< 20 DMA Ch 0 interrupt */
DMA_SPIH_RX_IRQn = 21, /*!< 21 DMA Ch 1 interrupt */
DMA_SPI0_TX_IRQn = 22, /*!< 22 DMA Ch 2 interrupt */
DMA_SPI0_RX_IRQn = 23, /*!< 23 DMA Ch 3 interrupt */
DMA_SPI1_TX_IRQn = 24, /*!< 24 DMA Ch 4 interrupt */
DMA_SPI1_RX_IRQn = 25, /*!< 25 DMA Ch 5 interrupt */
DMA_UART_TX_IRQn = 26, /*!< 26 DMA Ch 6 interrupt */
DMA_UART_RX_IRQn = 27, /*!< 27 DMA Ch 7 interrupt */
DMA_I2CS_TX_IRQn = 28, /*!< 28 DMA Ch 8 interrupt */
DMA_I2CS_RX_IRQn = 29, /*!< 29 DMA Ch 9 interrupt */
DMA_I2CM_IRQn = 30, /*!< 30 DMA Ch 10 interrupt */
DMA_AFE_TX_IRQn = 31, /*!< 31 DMA Ch 11 interrupt */
DMA_AFE_RX_IRQn = 32, /*!< 32 DMA Ch 12 interrupt */
DMA_CRC_IRQn = 33, /*!< 33 DMA Ch 13 interrupt */
DMA_PDI_IRQn = 34, /*!< 34 DMA Ch 14 interrupt */
DMA_I2S_IRQn = 35, /*!< 35 DMA Ch 15 interrupt */
USB_WAKEUP_IRQn = 36, /*!< 36 USB Wakeup interrupt */
USB_CNTL_IRQn = 37, /*!< 37 USB Controller interrupt */
USB_DMA_IRQn = 38, /*!< 38 USB DMA interrupt */
I2S_IRQn = 39, /*!< 39 I2S interrupt */
TIMER2_IRQn = 40, /*!< 40 TIMER 2 interrupt */
SPI1_IRQn = 42, /*!< 42 interrupt */
RTC_IRQn = 43, /*!< 43 Real Time Clock interrupt */
BEEP_IRQn = 45, /*!< 45 Beep interrupt */
LCD_IRQn = 46, /*!< 46 LCD Controller interrupt */
GPIOA_IRQn = 47, /*!< 47 interrupt */
GPIOB_IRQn = 48, /*!< 48 interrupt */
AFE_CAPTURE_IRQn = 50, /*!< 50 Analog Front End Capture interrupt */
AFE_GENERATE_IRQn = 51, /*!< 51 Analog Front End Generation interrupt */
AFE_CMD_FIFO_IRQn = 52, /*!< 52 Analog Front End FIFO CMD interrupt */
AFE_DATA_FIFO_IRQn = 53, /*!< 53 Analog Front End FIFO DATA interrupt */
GP_FLASH_IRQn = 55, /*!< 55 Flash EEPROM interrupt */
RAND_IRQn = 58, /*!< 58 Random Bit Generator interrupt */
PDI_IRQn = 59 /*!< 59 Paraller Display Interface interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the ARM Cortex-M3 Processor and Core Peripherals =========================== */
#define __CM3_REV 0x0201U /*!< CM3 Core Revision */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __FPU_PRESENT 0 /*!< FPU present or not */
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm3.h" /*!< ARM Cortex-M3 processor and core peripherals */
#include "system_ADuCM350.h" /*!< ADuCM350 System */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
#endif
#ifndef __OM /*!< Fallback for older CMSIS versions */
#define __OM __O
#endif
#ifndef __IOM /*!< Fallback for older CMSIS versions */
#define __IOM __IO
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ ADI_GPT0 ================ */
/* =========================================================================================================================== */
/**
* @brief General Purpose Timer 0 (ADI_GPT0)
*/
typedef struct { /*!< (@ 0x40000000) ADI_GPT0 Structure */
__IOM uint16_t LOAD; /*!< (@ 0x00000000) 16-bit load value */
__IM uint16_t RESERVED;
__IOM uint16_t CURCNT; /*!< (@ 0x00000004) 16-bit timer value. read only. */
__IM uint16_t RESERVED1;
__IOM uint16_t CTL; /*!< (@ 0x00000008) Control Register */
__IM uint16_t RESERVED2;
__IOM uint16_t CLRINT; /*!< (@ 0x0000000C) Clear interrupt register */
__IM uint16_t RESERVED3;
__IOM uint16_t CAPTURE; /*!< (@ 0x00000010) Capture Register */
__IM uint16_t RESERVED4;
__IOM uint16_t ALOAD; /*!< (@ 0x00000014) 16-bit load value, asynchronous */
__IM uint16_t RESERVED5;
__IOM uint16_t ACURCNT; /*!< (@ 0x00000018) 16-bit timer value, asynchronous */
__IM uint16_t RESERVED6;
__IOM uint16_t STATUS; /*!< (@ 0x0000001C) Status */
__IM uint16_t RESERVED7;
__IOM uint16_t PWMCTL; /*!< (@ 0x00000020) PWM Control Register */
__IM uint16_t RESERVED8;
__IOM uint16_t PWMMATCH; /*!< (@ 0x00000024) PWM Match Value */
} ADI_GPT0_Type; /*!< Size = 38 (0x26) */
/* =========================================================================================================================== */
/* ================ ADI_GPT1 ================ */
/* =========================================================================================================================== */
/**
* @brief General Purpose Timer1 (ADI_GPT1)
*/
typedef struct { /*!< (@ 0x40000400) ADI_GPT1 Structure */
__IOM uint16_t LOAD; /*!< (@ 0x00000000) 16-bit load value */
__IM uint16_t RESERVED;
__IOM uint16_t CURCNT; /*!< (@ 0x00000004) 16-bit timer value. read only. */
__IM uint16_t RESERVED1;
__IOM uint16_t CTL; /*!< (@ 0x00000008) Control Register */
__IM uint16_t RESERVED2;
__IOM uint16_t CLRINT; /*!< (@ 0x0000000C) Clear interrupt register */
__IM uint16_t RESERVED3;
__IOM uint16_t CAPTURE; /*!< (@ 0x00000010) Capture Register */
__IM uint16_t RESERVED4;
__IOM uint16_t ALOAD; /*!< (@ 0x00000014) 16-bit load value, asynchronous */
__IM uint16_t RESERVED5;
__IOM uint16_t ACURCNT; /*!< (@ 0x00000018) 16-bit timer value, asynchronous */
__IM uint16_t RESERVED6;
__IOM uint16_t STATUS; /*!< (@ 0x0000001C) Status */
__IM uint16_t RESERVED7;
__IOM uint16_t PWMCTL; /*!< (@ 0x00000020) PWM Control Register */
__IM uint16_t RESERVED8;
__IOM uint16_t PWMMATCH; /*!< (@ 0x00000024) PWM Match Value */
} ADI_GPT1_Type; /*!< Size = 38 (0x26) */
/* =========================================================================================================================== */
/* ================ ADI_GPT2 ================ */
/* =========================================================================================================================== */
/**
* @brief General Purpose Timer2 (ADI_GPT2)
*/
typedef struct { /*!< (@ 0x40000800) ADI_GPT2 Structure */
__IOM uint16_t LOAD; /*!< (@ 0x00000000) 16-bit load value */
__IM uint16_t RESERVED;
__IOM uint16_t CURCNT; /*!< (@ 0x00000004) 16-bit timer value. read only. */
__IM uint16_t RESERVED1;
__IOM uint16_t CTL; /*!< (@ 0x00000008) Control Register */
__IM uint16_t RESERVED2;
__IOM uint16_t CLRINT; /*!< (@ 0x0000000C) Clear interrupt register */
__IM uint16_t RESERVED3;
__IOM uint16_t CAPTURE; /*!< (@ 0x00000010) Capture Register */
__IM uint16_t RESERVED4;
__IOM uint16_t ALOAD; /*!< (@ 0x00000014) 16-bit load value, asynchronous */
__IM uint16_t RESERVED5;
__IOM uint16_t ACURCNT; /*!< (@ 0x00000018) 16-bit timer value, asynchronous */
__IM uint16_t RESERVED6;
__IOM uint16_t STATUS; /*!< (@ 0x0000001C) Status */
__IM uint16_t RESERVED7;
__IOM uint16_t PWMCTL; /*!< (@ 0x00000020) PWM Control Register */
__IM uint16_t RESERVED8;
__IOM uint16_t PWMMATCH; /*!< (@ 0x00000024) PWM Match Value */
} ADI_GPT2_Type; /*!< Size = 38 (0x26) */
/* =========================================================================================================================== */
/* ================ ADI_ID ================ */
/* =========================================================================================================================== */
/**
* @brief Power Control and ID (ADI_ID)
*/
typedef struct { /*!< (@ 0x40002020) ADI_ID Structure */
__IOM uint16_t ADIID; /*!< (@ 0x00000000) Analog Devices ID Register */
__IM uint16_t RESERVED;
__IOM uint16_t CHIPID; /*!< (@ 0x00000004) Chip ID Register */
} ADI_ID_Type; /*!< Size = 6 (0x6) */
/* =========================================================================================================================== */
/* ================ ADI_PWR ================ */
/* =========================================================================================================================== */
/**
* @brief Power Management Unit (ADI_PWR)
*/
typedef struct { /*!< (@ 0x40002400) ADI_PWR Structure */
__IOM uint16_t PWRMOD; /*!< (@ 0x00000000) PWR Power modes */
__IM uint16_t RESERVED;
__IOM uint16_t PWRKEY; /*!< (@ 0x00000004) PWR Key protection for PWRMOD */
__IM uint16_t RESERVED1;
__IOM uint16_t PSMCON; /*!< (@ 0x00000008) PWR PSM Configuration */
__IM uint16_t RESERVED2;
__IOM uint16_t OSCKEY; /*!< (@ 0x0000000C) PWR Key protection for OSCCTRL */
__IM uint16_t RESERVED3;
__IOM uint16_t OSCCTRL; /*!< (@ 0x00000010) PWR Oscillator control */
} ADI_PWR_Type; /*!< Size = 18 (0x12) */
/* =========================================================================================================================== */
/* ================ ADI_EI ================ */
/* =========================================================================================================================== */
/**
* @brief External Interrupts (ADI_EI)
*/
typedef struct { /*!< (@ 0x40002420) ADI_EI Structure */
__IOM uint16_t EI0CFG; /*!< (@ 0x00000000) PWR External Interrupt configuration 0 */
__IM uint16_t RESERVED;
__IOM uint16_t EI1CFG; /*!< (@ 0x00000004) PWR External Interrupt configuration 1 */
__IM uint16_t RESERVED1;
__IOM uint16_t EI2CFG; /*!< (@ 0x00000008) PWR External Interrupt configuration 2 */
__IM uint16_t RESERVED2[3];
__IOM uint16_t EICLR; /*!< (@ 0x00000010) PWR External Interrupt clear */
__IM uint16_t RESERVED3;
__IOM uint16_t NMICLR; /*!< (@ 0x00000014) PWR Non-maskable interrupt clear */
__IM uint16_t RESERVED4;
__IOM uint16_t USBWKSTAT; /*!< (@ 0x00000018) PWR USB Wakeup Status */
__IM uint16_t RESERVED5[3];
__IOM uint16_t RSTSTA; /*!< (@ 0x00000020) PWR Reset status */
} ADI_EI_Type; /*!< Size = 34 (0x22) */
/* =========================================================================================================================== */
/* ================ ADI_PWRVCC ================ */
/* =========================================================================================================================== */
/**
* @brief Power (ADI_PWRVCC)
*/
typedef struct { /*!< (@ 0x40002480) ADI_PWRVCC Structure */
__IM uint16_t RESERVED[4];
__IOM uint16_t VCCMCON; /*!< (@ 0x00000008) PWR VCCM Control and Status */
__IM uint16_t RESERVED1;
__IOM uint16_t VBACKCON; /*!< (@ 0x0000000C) PWR VBACK control and status */
} ADI_PWRVCC_Type; /*!< Size = 14 (0xe) */
/* =========================================================================================================================== */
/* ================ ADI_WUT ================ */
/* =========================================================================================================================== */
/**
* @brief Wake-up timer (ADI_WUT)
*/
typedef struct { /*!< (@ 0x40002500) ADI_WUT Structure */
__IOM uint16_t T2VAL0; /*!< (@ 0x00000000) WUT Current count value - LS halfword. */
__IM uint16_t RESERVED;
__IOM uint16_t T2VAL1; /*!< (@ 0x00000004) WUT Current count value - MS halfword */
__IM uint16_t RESERVED1;
__IOM uint16_t T2CON; /*!< (@ 0x00000008) WUT Control */
__IM uint16_t RESERVED2;
__IOM uint16_t T2INC; /*!< (@ 0x0000000C) WUT 12-bit interval for wakeup field A */
__IM uint16_t RESERVED3;
__IOM uint16_t T2WUFB0; /*!< (@ 0x00000010) WUT Wakeup field B - LS halfword */
__IM uint16_t RESERVED4;
__IOM uint16_t T2WUFB1; /*!< (@ 0x00000014) WUT Wakeup field B - MS halfword */
__IM uint16_t RESERVED5;
__IOM uint16_t T2WUFC0; /*!< (@ 0x00000018) WUT Wakeup field C - LS halfword */
__IM uint16_t RESERVED6;
__IOM uint16_t T2WUFC1; /*!< (@ 0x0000001C) WUT Wakeup field C - MS halfword */
__IM uint16_t RESERVED7;
__IOM uint16_t T2WUFD0; /*!< (@ 0x00000020) WUT Wakeup field D - LS halfword */
__IM uint16_t RESERVED8;
__IOM uint16_t T2WUFD1; /*!< (@ 0x00000024) WUT Wakeup field D - MS halfword */
__IM uint16_t RESERVED9;
__IOM uint16_t T2IEN; /*!< (@ 0x00000028) WUT Interrupt enable */
__IM uint16_t RESERVED10;
__IOM uint16_t T2STA; /*!< (@ 0x0000002C) WUT Status */
__IM uint16_t RESERVED11;
__IOM uint16_t T2CLRI; /*!< (@ 0x00000030) WUT Clear interrupt register */
__IM uint16_t RESERVED12;
__IOM uint16_t WUTVAL_LOW; /*!< (@ 0x00000034) WUT Unsynchronized lower 16 bits of WU Timer
counter value. */
__IM uint16_t RESERVED13;
__IOM uint16_t WUTVAL_HIGH; /*!< (@ 0x00000038) WUT Unsynchronized upper 16 bits of WU Timer
counter value. */
__IM uint16_t RESERVED14;
__IOM uint16_t T2WUFA0; /*!< (@ 0x0000003C) WUT Wakeup field A - LS halfword */
__IM uint16_t RESERVED15;
__IOM uint16_t T2WUFA1; /*!< (@ 0x00000040) WUT Wakeup field A - MS halfword */
} ADI_WUT_Type; /*!< Size = 66 (0x42) */
/* =========================================================================================================================== */
/* ================ ADI_WDT ================ */
/* =========================================================================================================================== */
/**
* @brief WatchDog Timer (ADI_WDT)
*/
typedef struct { /*!< (@ 0x40002580) ADI_WDT Structure */
__IOM uint16_t T3LD; /*!< (@ 0x00000000) WDT Load value */
__IM uint16_t RESERVED;
__IOM uint16_t T3VAL; /*!< (@ 0x00000004) WDT Current count value */
__IM uint16_t RESERVED1;
__IOM uint16_t T3CON; /*!< (@ 0x00000008) WDT Control */
__IM uint16_t RESERVED2;
__IOM uint16_t T3CLRI; /*!< (@ 0x0000000C) WDT Clear interrupt register */
__IM uint16_t RESERVED3[5];
__IOM uint16_t T3STA; /*!< (@ 0x00000018) WDT Status */
} ADI_WDT_Type; /*!< Size = 26 (0x1a) */
/* =========================================================================================================================== */
/* ================ ADI_RTC ================ */
/* =========================================================================================================================== */
/**
* @brief RealTimeClock (ADI_RTC)
*/
typedef struct { /*!< (@ 0x40002600) ADI_RTC Structure */
__IOM uint16_t RTCCR; /*!< (@ 0x00000000) RTC RTC Control */
__IM uint16_t RESERVED;
__IOM uint16_t RTCSR0; /*!< (@ 0x00000004) RTC RTC Status 0 */
__IM uint16_t RESERVED1;
__IOM uint16_t RTCSR1; /*!< (@ 0x00000008) RTC RTC Status 1 */
__IM uint16_t RESERVED2;
__IOM uint16_t RTCCNT0; /*!< (@ 0x0000000C) RTC RTC Count 0 */
__IM uint16_t RESERVED3;
__IOM uint16_t RTCCNT1; /*!< (@ 0x00000010) RTC RTC Count 1 */
__IM uint16_t RESERVED4;
__IOM uint16_t RTCALM0; /*!< (@ 0x00000014) RTC RTC Alarm 0 */
__IM uint16_t RESERVED5;
__IOM uint16_t RTCALM1; /*!< (@ 0x00000018) RTC RTC Alarm 1 */
__IM uint16_t RESERVED6;
__IOM uint16_t RTCTRM; /*!< (@ 0x0000001C) RTC RTC Trim */
__IM uint16_t RESERVED7;
__IOM uint16_t RTCGWY; /*!< (@ 0x00000020) RTC RTC Gateway */
} ADI_RTC_Type; /*!< Size = 34 (0x22) */
/* =========================================================================================================================== */
/* ================ ADI_I2C ================ */
/* =========================================================================================================================== */
/**
* @brief I2C Master/Slave (ADI_I2C)
*/
typedef struct { /*!< (@ 0x40003000) ADI_I2C Structure */
__IOM uint16_t I2CMCON; /*!< (@ 0x00000000) I2C Master control */
__IM uint16_t RESERVED;
__IOM uint16_t I2CMSTA; /*!< (@ 0x00000004) I2C Master status */
__IM uint16_t RESERVED1;
__IOM uint16_t I2CMRX; /*!< (@ 0x00000008) I2C Master receive data */
__IM uint16_t RESERVED2;
__IOM uint16_t I2CMTX; /*!< (@ 0x0000000C) I2C Master transmit data */
__IM uint16_t RESERVED3;
__IOM uint16_t I2CMRXCNT; /*!< (@ 0x00000010) I2C Master receive data count */
__IM uint16_t RESERVED4;
__IOM uint16_t I2CMCRXCNT; /*!< (@ 0x00000014) I2C Master current receive data count */
__IM uint16_t RESERVED5;
__IOM uint16_t I2CADR1; /*!< (@ 0x00000018) I2C 1st master address byte */
__IM uint16_t RESERVED6;
__IOM uint16_t I2CADR2; /*!< (@ 0x0000001C) I2C 2nd master address byte */
__IM uint16_t RESERVED7;
__IOM uint16_t I2CBYT; /*!< (@ 0x00000020) I2C Start byte */
__IM uint16_t RESERVED8;
__IOM uint16_t I2CDIV; /*!< (@ 0x00000024) I2C Serial clock period divisor */
__IM uint16_t RESERVED9;
__IOM uint16_t I2CSCON; /*!< (@ 0x00000028) I2C Slave control */
__IM uint16_t RESERVED10;
__IOM uint16_t I2CSSTA; /*!< (@ 0x0000002C) I2C Slave I2C Status/Error/IRQ */
__IM uint16_t RESERVED11;
__IOM uint16_t I2CSRX; /*!< (@ 0x00000030) I2C Slave receive */
__IM uint16_t RESERVED12;
__IOM uint16_t I2CSTX; /*!< (@ 0x00000034) I2C Slave transmit */
__IM uint16_t RESERVED13;
__IOM uint16_t I2CALT; /*!< (@ 0x00000038) I2C Hardware general call ID */
__IM uint16_t RESERVED14;
__IOM uint16_t I2CID0; /*!< (@ 0x0000003C) I2C 1st slave address device ID */
__IM uint16_t RESERVED15;
__IOM uint16_t I2CID1; /*!< (@ 0x00000040) I2C 2nd slave address device ID */
__IM uint16_t RESERVED16;
__IOM uint16_t I2CID2; /*!< (@ 0x00000044) I2C 3rd slave address device ID */
__IM uint16_t RESERVED17;
__IOM uint16_t I2CID3; /*!< (@ 0x00000048) I2C 4th slave address device ID */
__IM uint16_t RESERVED18;
__IOM uint16_t I2CFSTA; /*!< (@ 0x0000004C) I2C Master and slave FIFO status */
__IM uint16_t RESERVED19;
__IOM uint16_t I2CSHCON; /*!< (@ 0x00000050) I2C Shared control */
__IM uint16_t RESERVED20;
__IOM uint16_t I2CTCTL; /*!< (@ 0x00000054) I2C Timing Control Register */
} ADI_I2C_Type; /*!< Size = 86 (0x56) */
/* =========================================================================================================================== */
/* ================ ADI_SPI0 ================ */
/* =========================================================================================================================== */
/**
* @brief SPI0 Maste/Slave (ADI_SPI0)
*/
typedef struct { /*!< (@ 0x40004000) ADI_SPI0 Structure */
__IOM uint16_t SPISTA; /*!< (@ 0x00000000) SPI0 Status */
__IM uint16_t RESERVED;
__IOM uint16_t SPIRX; /*!< (@ 0x00000004) SPI0 Receive */
__IM uint16_t RESERVED1;
__IOM uint16_t SPITX; /*!< (@ 0x00000008) SPI0 Transmit */
__IM uint16_t RESERVED2;
__IOM uint16_t SPIDIV; /*!< (@ 0x0000000C) SPI0 Baud rate selection */
__IM uint16_t RESERVED3;
__IOM uint16_t SPICON; /*!< (@ 0x00000010) SPI0 SPI configuration */
__IM uint16_t RESERVED4;
__IOM uint16_t SPIDMA; /*!< (@ 0x00000014) SPI0 SPI DMA enable */
__IM uint16_t RESERVED5;
__IOM uint16_t SPICNT; /*!< (@ 0x00000018) SPI0 Transfer byte count */
} ADI_SPI0_Type; /*!< Size = 26 (0x1a) */
/* =========================================================================================================================== */
/* ================ ADI_SPI1 ================ */
/* =========================================================================================================================== */
/**
* @brief SPI1 Master/Slave (ADI_SPI1)
*/
typedef struct { /*!< (@ 0x40004400) ADI_SPI1 Structure */
__IOM uint16_t SPISTA; /*!< (@ 0x00000000) SPI1 Status */
__IM uint16_t RESERVED;
__IOM uint16_t SPIRX; /*!< (@ 0x00000004) SPI1 Receive */
__IM uint16_t RESERVED1;
__IOM uint16_t SPITX; /*!< (@ 0x00000008) SPI1 Transmit */
__IM uint16_t RESERVED2;
__IOM uint16_t SPIDIV; /*!< (@ 0x0000000C) SPI1 Baud rate selection */
__IM uint16_t RESERVED3;
__IOM uint16_t SPICON; /*!< (@ 0x00000010) SPI1 SPI configuration */
__IM uint16_t RESERVED4;
__IOM uint16_t SPIDMA; /*!< (@ 0x00000014) SPI1 SPI DMA enable */
__IM uint16_t RESERVED5;
__IOM uint16_t SPICNT; /*!< (@ 0x00000018) SPI1 Transfer byte count */
} ADI_SPI1_Type; /*!< Size = 26 (0x1a) */
/* =========================================================================================================================== */
/* ================ ADI_UART ================ */
/* =========================================================================================================================== */
/**
* @brief Uart (ADI_UART)
*/
typedef struct { /*!< (@ 0x40005000) ADI_UART Structure */
__IOM uint16_t COMRX; /*!< (@ 0x00000000) UART Receive Buffer Register */
__IM uint16_t RESERVED;
__IOM uint16_t COMIEN; /*!< (@ 0x00000004) UART Interrupt Enable */
__IM uint16_t RESERVED1;
__IOM uint16_t COMIIR; /*!< (@ 0x00000008) UART Interrupt ID */
__IM uint16_t RESERVED2;
__IOM uint16_t COMLCR; /*!< (@ 0x0000000C) UART Line Control */
__IM uint16_t RESERVED3;
__IOM uint16_t COMMCR; /*!< (@ 0x00000010) UART Modem Control */
__IM uint16_t RESERVED4;
__IOM uint16_t COMLSR; /*!< (@ 0x00000014) UART Line Status */
__IM uint16_t RESERVED5;
__IOM uint16_t COMMSR; /*!< (@ 0x00000018) UART Modem Status */
__IM uint16_t RESERVED6;
__IOM uint16_t COMSCR; /*!< (@ 0x0000001C) UART Scratch buffer */
__IM uint16_t RESERVED7[3];
__IOM uint16_t COMFBR; /*!< (@ 0x00000024) UART Fractional Baud Rate */
__IM uint16_t RESERVED8;
__IOM uint16_t COMDIV; /*!< (@ 0x00000028) UART Baudrate divider */
} ADI_UART_Type; /*!< Size = 42 (0x2a) */
/* =========================================================================================================================== */
/* ================ ADI_I2S ================ */
/* =========================================================================================================================== */
/**
* @brief I2S Master/Slave (ADI_I2S)
*/
typedef struct { /*!< (@ 0x40005800) ADI_I2S Structure */
__IOM uint16_t OUT1L; /*!< (@ 0x00000000) I2S Channel 1 LSBs */
__IM uint16_t RESERVED;
__IOM uint16_t OUT1H; /*!< (@ 0x00000004) I2S Channel 1 MSBs */
__IM uint16_t RESERVED1;
__IOM uint16_t OUT2L; /*!< (@ 0x00000008) I2S Channel 2 LSBs */
__IM uint16_t RESERVED2;
__IOM uint16_t OUT2H; /*!< (@ 0x0000000C) I2S Channel 2 MSBs */
__IM uint16_t RESERVED3;
__IOM uint16_t MODE1; /*!< (@ 0x00000010) I2S I2S format modes 1 */
__IM uint16_t RESERVED4;
__IOM uint16_t MODE2; /*!< (@ 0x00000014) I2S I2S format modes 2 */
__IM uint16_t RESERVED5;
__IOM uint16_t CFG1; /*!< (@ 0x00000018) I2S I2S configuration 1 */
__IM uint16_t RESERVED6;
__IOM uint16_t CFG2; /*!< (@ 0x0000001C) I2S I2S configuration 2 */
__IM uint16_t RESERVED7;
__IOM uint16_t STAT; /*!< (@ 0x00000020) I2S I2S status */
} ADI_I2S_Type; /*!< Size = 34 (0x22) */
/* =========================================================================================================================== */
/* ================ ADI_BEEP ================ */
/* =========================================================================================================================== */
/**
* @brief Beeper (ADI_BEEP)
*/
typedef struct { /*!< (@ 0x40005C00) ADI_BEEP Structure */
__IOM uint16_t BEEP_CFG; /*!< (@ 0x00000000) BEEP Beeper configuration */
__IM uint16_t RESERVED;
__IOM uint16_t STAT; /*!< (@ 0x00000004) BEEP Beeper status */
__IM uint16_t RESERVED1;
__IOM uint16_t TONE_A; /*!< (@ 0x00000008) BEEP Tone A Data */
__IM uint16_t RESERVED2;
__IOM uint16_t TONE_B; /*!< (@ 0x0000000C) BEEP Tone B Data */
} ADI_BEEP_Type; /*!< Size = 14 (0xe) */
/* =========================================================================================================================== */
/* ================ ADI_RNG ================ */
/* =========================================================================================================================== */
/**
* @brief Random Bit Generator (ADI_RNG)
*/
typedef struct { /*!< (@ 0x40006000) ADI_RNG Structure */
__IOM uint16_t RNGCTL; /*!< (@ 0x00000000) RNG Control Register */
__IM uint16_t RESERVED;
__IOM uint16_t RNGLEN; /*!< (@ 0x00000004) RNG Sample Length Register */
__IM uint16_t RESERVED1;
__IOM uint16_t RNGSTAT; /*!< (@ 0x00000008) RNG Status Register */
__IM uint16_t RESERVED2;
__IOM uint16_t RNGDATA; /*!< (@ 0x0000000C) RNG Data Register */
__IM uint16_t RESERVED3;
__IM uint16_t RNGCNTL; /*!< (@ 0x00000010) RNG Oscillator Count Low */
__IM uint16_t RESERVED4;
__IM uint16_t RNGCNTH; /*!< (@ 0x00000014) RNG Oscillator Count High */
} ADI_RNG_Type; /*!< Size = 22 (0x16) */
/* =========================================================================================================================== */
/* ================ ADI_LCD ================ */
/* =========================================================================================================================== */
/**
* @brief LCD Controller (ADI_LCD)
*/
typedef struct { /*!< (@ 0x40008000) ADI_LCD Structure */
__IOM uint16_t LCDCON; /*!< (@ 0x00000000) LCD LCD Configuration Register */
__IM uint16_t RESERVED;
__IOM uint16_t LCDSTAT; /*!< (@ 0x00000004) LCD LCD Status Register */
__IM uint16_t RESERVED1;
__IOM uint16_t LCDBLINK; /*!< (@ 0x00000008) LCD LCD Blink Control Register */
__IM uint16_t RESERVED2;
__IOM uint16_t LCDCONTRAST; /*!< (@ 0x0000000C) LCD LCD Contrast Control Register */
__IM uint16_t RESERVED3;
__IOM uint16_t LCDDATA0_S0; /*!< (@ 0x00000010) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED4;
__IOM uint16_t LCDDATA1_S0; /*!< (@ 0x00000014) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED5;
__IOM uint16_t LCDDATA2_S0; /*!< (@ 0x00000018) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED6;
__IOM uint16_t LCDDATA3_S0; /*!< (@ 0x0000001C) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED7;
__IOM uint16_t LCDDATA4_S0; /*!< (@ 0x00000020) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED8;
__IOM uint16_t LCDDATA5_S0; /*!< (@ 0x00000024) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED9;
__IOM uint16_t LCDDATA6_S0; /*!< (@ 0x00000028) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED10;
__IOM uint16_t LCDDATA7_S0; /*!< (@ 0x0000002C) LCD Screen 0 LCD Data Register n */
__IM uint16_t RESERVED11;
__IOM uint16_t LCDDATA0_S1; /*!< (@ 0x00000030) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED12;
__IOM uint16_t LCDDATA1_S1; /*!< (@ 0x00000034) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED13;
__IOM uint16_t LCDDATA2_S1; /*!< (@ 0x00000038) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED14;
__IOM uint16_t LCDDATA3_S1; /*!< (@ 0x0000003C) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED15;
__IOM uint16_t LCDDATA4_S1; /*!< (@ 0x00000040) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED16;
__IOM uint16_t LCDDATA5_S1; /*!< (@ 0x00000044) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED17;
__IOM uint16_t LCDDATA6_S1; /*!< (@ 0x00000048) LCD Screen 1 LCD Data Register n */
__IM uint16_t RESERVED18;
__IOM uint16_t LCDDATA7_S1; /*!< (@ 0x0000004C) LCD Screen 1 LCD Data Register n */
} ADI_LCD_Type; /*!< Size = 78 (0x4e) */
/* =========================================================================================================================== */
/* ================ ADI_DMA ================ */
/* =========================================================================================================================== */
/**
* @brief DMA (ADI_DMA)
*/
typedef struct { /*!< (@ 0x40010000) ADI_DMA Structure */
__IOM uint32_t DMASTA; /*!< (@ 0x00000000) DMA DMA Status */
__IOM uint32_t DMACFG; /*!< (@ 0x00000004) DMA DMA Configuration */
__IOM uint32_t DMAPDBPTR; /*!< (@ 0x00000008) DMA DMA channel primary control data base pointer */
__IOM uint32_t DMAADBPTR; /*!< (@ 0x0000000C) DMA DMA channel alternate control data base pointer */
__IM uint32_t RESERVED;
__IOM uint16_t DMASWREQ; /*!< (@ 0x00000014) DMA DMA channel software request */
__IM uint16_t RESERVED1;
__IM uint32_t RESERVED2[2];
__IOM uint16_t DMARMSKSET; /*!< (@ 0x00000020) DMA DMA channel request mask set */
__IM uint16_t RESERVED3;
__IOM uint16_t DMARMSKCLR; /*!< (@ 0x00000024) DMA DMA channel request mask clear */
__IM uint16_t RESERVED4;
__IOM uint16_t DMAENSET; /*!< (@ 0x00000028) DMA DMA channel enable set */
__IM uint16_t RESERVED5;
__IOM uint16_t DMAENCLR; /*!< (@ 0x0000002C) DMA DMA channel enable clear */
__IM uint16_t RESERVED6;
__IOM uint16_t DMAALTSET; /*!< (@ 0x00000030) DMA DMA channel primary-alternate set */
__IM uint16_t RESERVED7;
__IOM uint16_t DMAALTCLR; /*!< (@ 0x00000034) DMA DMA channel primary-alternate clear */
__IM uint16_t RESERVED8;
__IOM uint16_t DMAPRISET; /*!< (@ 0x00000038) DMA DMA channel priority set */
__IM uint16_t RESERVED9;
__IOM uint16_t DMAPRICLR; /*!< (@ 0x0000003C) DMA DMA channel priority clear */
__IM uint16_t RESERVED10;
__IM uint32_t RESERVED11[2];
__IOM uint16_t DMAERRCHNLCLR; /*!< (@ 0x00000048) DMA DMA Per Channel Error Clear */
__IM uint16_t RESERVED12;
__IOM uint16_t DMAERRCLR; /*!< (@ 0x0000004C) DMA DMA bus error clear */
__IM uint16_t RESERVED13;
__IOM uint16_t DMAINVALIDDESCCLR; /*!< (@ 0x00000050) DMA DMA Per Channel Invalid Descriptor Clear */
__IM uint16_t RESERVED14;
__IM uint32_t RESERVED15[491];
__IOM uint16_t DMABSSET; /*!< (@ 0x00000800) DMA DMA channel bytes swap enable set */
__IM uint16_t RESERVED16;
__IOM uint16_t DMABSCLR; /*!< (@ 0x00000804) DMA DMA channel bytes swap enable clear */
__IM uint16_t RESERVED17;
__IM uint32_t RESERVED18[2];
__IOM uint16_t DMASRCADSSET; /*!< (@ 0x00000810) DMA DMA channel source address decrement enable
set */
__IM uint16_t RESERVED19;
__IOM uint16_t DMASRCADCLR; /*!< (@ 0x00000814) DMA DMA channel source address decrement enable
clear */
__IM uint16_t RESERVED20;
__IOM uint16_t DMADSTADSET; /*!< (@ 0x00000818) DMA DMA channel destination address decrement
enable set */
__IM uint16_t RESERVED21;
__IOM uint16_t DMADSTADCLR; /*!< (@ 0x0000081C) DMA DMA channel destination address decrement
enable clear */
__IM uint16_t RESERVED22;
__IM uint32_t RESERVED23[496];
__IOM uint8_t DMAREVID; /*!< (@ 0x00000FE0) DMA DMA Controller Revision ID */
__IM uint8_t RESERVED24;
__IM uint16_t RESERVED25;
} ADI_DMA_Type; /*!< Size = 4068 (0xfe4) */
/* =========================================================================================================================== */
/* ================ ADI_FEE0 ================ */
/* =========================================================================================================================== */
/**
* @brief Instruction Flash Controller (ADI_FEE0)
*/
typedef struct { /*!< (@ 0x40018000) ADI_FEE0 Structure */
__IOM uint16_t FEESTA; /*!< (@ 0x00000000) FEE0 Status */
__IM uint16_t RESERVED;
__IOM uint16_t FEECON0; /*!< (@ 0x00000004) FEE0 Command Control */
__IM uint16_t RESERVED1;
__IOM uint16_t FEECMD; /*!< (@ 0x00000008) FEE0 Command */
__IM uint16_t RESERVED2[3];
__IOM uint16_t FEEADR0L; /*!< (@ 0x00000010) FEE0 Lower page address */
__IM uint16_t RESERVED3;
__IOM uint16_t FEEADR0H; /*!< (@ 0x00000014) FEE0 Upper page address */
__IM uint16_t RESERVED4;
__IOM uint16_t FEEADR1L; /*!< (@ 0x00000018) FEE0 Lower page address */
__IM uint16_t RESERVED5;
__IOM uint16_t FEEADR1H; /*!< (@ 0x0000001C) FEE0 Upper page address */
__IM uint16_t RESERVED6;
__IOM uint16_t FEEKEY; /*!< (@ 0x00000020) FEE0 Key */
__IM uint16_t RESERVED7[7];
__IOM uint16_t FEESIGL; /*!< (@ 0x00000030) FEE0 Lower halfword of signature */
__IM uint16_t RESERVED8;
__IOM uint16_t FEESIGH; /*!< (@ 0x00000034) FEE0 Upper halfword of signature */
__IM uint16_t RESERVED9[9];
__IOM uint16_t FEEADRAL; /*!< (@ 0x00000048) FEE0 Lower halfword of write abort address */
__IM uint16_t RESERVED10;
__IOM uint16_t FEEADRAH; /*!< (@ 0x0000004C) FEE0 Upper halfword of write abort address */
__IM uint16_t RESERVED11;
__IOM uint16_t FEEPARCTL; /*!< (@ 0x00000050) FEE0 Parity Control Register */
__IM uint16_t RESERVED12;
__IOM uint16_t FEEPARSTA; /*!< (@ 0x00000054) FEE0 Parity Status Register */
__IM uint16_t RESERVED13;
__IOM uint16_t FEEPARADRL; /*!< (@ 0x00000058) FEE0 Parity Error Address Low */
__IM uint16_t RESERVED14;
__IOM uint16_t FEEPARADRH; /*!< (@ 0x0000005C) FEE0 Parity Error Address High */
__IM uint16_t RESERVED15[13];
__IOM uint16_t FEEAEN0; /*!< (@ 0x00000078) FEE0 System IRQ abort enable for interrupts 15
to 0 */
__IM uint16_t RESERVED16;
__IOM uint16_t FEEAEN1; /*!< (@ 0x0000007C) FEE0 System IRQ abort enable for interrupts 31
to 16 */
__IM uint16_t RESERVED17;
__IOM uint16_t FEEAEN2; /*!< (@ 0x00000080) FEE0 System IRQ abort enable for interrupts 47
to 32 */
__IM uint16_t RESERVED18;
__IOM uint16_t FEEAEN3; /*!< (@ 0x00000084) FEE0 System IRQ abort enable for interrupts 60
to 48 */
} ADI_FEE0_Type; /*!< Size = 134 (0x86) */
/* =========================================================================================================================== */
/* ================ ADI_GPF ================ */
/* =========================================================================================================================== */
/**
* @brief General Purpose Flash Controller (ADI_GPF)
*/
typedef struct { /*!< (@ 0x4001C000) ADI_GPF Structure */
__IOM uint16_t GPFEESTA; /*!< (@ 0x00000000) GPF Status */
__IM uint16_t RESERVED;
__IOM uint16_t GPFEECON0; /*!< (@ 0x00000004) GPF Command Control */
__IM uint16_t RESERVED1;
__IOM uint16_t GPFEECMD; /*!< (@ 0x00000008) GPF Command */
__IM uint16_t RESERVED2[3];
__IOM uint16_t GPFEEADR0L; /*!< (@ 0x00000010) GPF Lower page address */
__IM uint16_t RESERVED3[3];
__IOM uint16_t GPFEEADR1L; /*!< (@ 0x00000018) GPF Lower page address */
__IM uint16_t RESERVED4[3];
__IOM uint16_t GPFEEKEY; /*!< (@ 0x00000020) GPF Key */
__IM uint16_t RESERVED5[7];
__IOM uint16_t GPFEESIGL; /*!< (@ 0x00000030) GPF Lower halfword of signature */
__IM uint16_t RESERVED6;
__IOM uint16_t GPFEESIGH; /*!< (@ 0x00000034) GPF Upper halfword of signature */
__IM uint16_t RESERVED7[9];
__IOM uint16_t GPFEEADRAL; /*!< (@ 0x00000048) GPF Lower halfword of write abort address */
__IM uint16_t RESERVED8;
__IOM uint16_t GPFEEADRAH; /*!< (@ 0x0000004C) GPF Upper halfword of write abort address */
__IM uint16_t RESERVED9[21];
__IOM uint16_t GPFEEAEN0; /*!< (@ 0x00000078) GPF System IRQ abort enable for interrupts 15
to 0 */
__IM uint16_t RESERVED10;
__IOM uint16_t GPFEEAEN1; /*!< (@ 0x0000007C) GPF System IRQ abort enable for interrupts 31
to 16 */
__IM uint16_t RESERVED11;
__IOM uint16_t GPFEEAEN2; /*!< (@ 0x00000080) GPF System IRQ abort enable for interrupts 47
to 32 */
__IM uint16_t RESERVED12;
__IOM uint16_t GPFEEAEN3; /*!< (@ 0x00000084) GPF System IRQ abort enable for interrupts 60
to 48 */
} ADI_GPF_Type; /*!< Size = 134 (0x86) */
/* =========================================================================================================================== */
/* ================ ADI_GPIO0 ================ */
/* =========================================================================================================================== */
/**
* @brief GPIO (ADI_GPIO0)
*/
typedef struct { /*!< (@ 0x40020000) ADI_GPIO0 Structure */
__IOM uint16_t GPCON; /*!< (@ 0x00000000) GPIO Configuration */
__IM uint16_t RESERVED;
__IOM uint16_t GPOEN; /*!< (@ 0x00000004) GPIO output enable */
__IM uint16_t RESERVED1;
__IOM uint16_t GPPE; /*!< (@ 0x00000008) GPIO output pullup/pulldown enable */
__IM uint16_t RESERVED2;
__IOM uint16_t GPIEN; /*!< (@ 0x0000000C) GPIO Input Path Enable */
__IM uint16_t RESERVED3;
__IOM uint16_t GPIN; /*!< (@ 0x00000010) GPIO registered data input */
__IM uint16_t RESERVED4;
__IOM uint16_t GPOUT; /*!< (@ 0x00000014) GPIO data output */
__IM uint16_t RESERVED5;
__IOM uint16_t GPSET; /*!< (@ 0x00000018) GPIO data out set */
__IM uint16_t RESERVED6;
__IOM uint16_t GPCLR; /*!< (@ 0x0000001C) GPIO data out clear */
__IM uint16_t RESERVED7;
__IOM uint16_t GPTGL; /*!< (@ 0x00000020) GPIO pin toggle */
__IM uint16_t RESERVED8;
__IOM uint16_t GPPOL; /*!< (@ 0x00000024) GPIO interrupt polarity */
__IM uint16_t RESERVED9;
__IOM uint16_t GPIENA; /*!< (@ 0x00000028) GPIO interrupt A enable */
__IM uint16_t RESERVED10;
__IOM uint16_t GPIENB; /*!< (@ 0x0000002C) GPIO interrupt B enable */
__IM uint16_t RESERVED11;
__IOM uint16_t GPINT; /*!< (@ 0x00000030) GPIO interrupt Status */
} ADI_GPIO0_Type; /*!< Size = 50 (0x32) */
/* =========================================================================================================================== */
/* ================ ADI_GPIO1 ================ */
/* =========================================================================================================================== */
/**
* @brief GPIO 1 (ADI_GPIO1)
*/
typedef struct { /*!< (@ 0x40020040) ADI_GPIO1 Structure */
__IOM uint16_t GPCON; /*!< (@ 0x00000000) GPIO Configuration */
__IM uint16_t RESERVED;
__IOM uint16_t GPOEN; /*!< (@ 0x00000004) GPIO output enable */
__IM uint16_t RESERVED1;
__IOM uint16_t GPPE; /*!< (@ 0x00000008) GPIO output pullup/pulldown enable */
__IM uint16_t RESERVED2;
__IOM uint16_t GPIEN; /*!< (@ 0x0000000C) GPIO Input Path Enable */
__IM uint16_t RESERVED3;
__IOM uint16_t GPIN; /*!< (@ 0x00000010) GPIO registered data input */
__IM uint16_t RESERVED4;
__IOM uint16_t GPOUT; /*!< (@ 0x00000014) GPIO data output */
__IM uint16_t RESERVED5;
__IOM uint16_t GPSET; /*!< (@ 0x00000018) GPIO data out set */
__IM uint16_t RESERVED6;
__IOM uint16_t GPCLR; /*!< (@ 0x0000001C) GPIO data out clear */
__IM uint16_t RESERVED7;
__IOM uint16_t GPTGL; /*!< (@ 0x00000020) GPIO pin toggle */
__IM uint16_t RESERVED8;
__IOM uint16_t GPPOL; /*!< (@ 0x00000024) GPIO interrupt polarity */
__IM uint16_t RESERVED9;
__IOM uint16_t GPIENA; /*!< (@ 0x00000028) GPIO interrupt A enable */
__IM uint16_t RESERVED10;
__IOM uint16_t GPIENB; /*!< (@ 0x0000002C) GPIO interrupt B enable */
__IM uint16_t RESERVED11;
__IOM uint16_t GPINT; /*!< (@ 0x00000030) GPIO interrupt Status */
} ADI_GPIO1_Type; /*!< Size = 50 (0x32) */
/* =========================================================================================================================== */
/* ================ ADI_GPIO2 ================ */
/* =========================================================================================================================== */
/**
* @brief GPIO 2 (ADI_GPIO2)
*/
typedef struct { /*!< (@ 0x40020080) ADI_GPIO2 Structure */
__IOM uint16_t GPCON; /*!< (@ 0x00000000) GPIO Configuration */
__IM uint16_t RESERVED;
__IOM uint16_t GPOEN; /*!< (@ 0x00000004) GPIO output enable */
__IM uint16_t RESERVED1;
__IOM uint16_t GPPE; /*!< (@ 0x00000008) GPIO output pullup/pulldown enable */
__IM uint16_t RESERVED2;
__IOM uint16_t GPIEN; /*!< (@ 0x0000000C) GPIO Input Path Enable */
__IM uint16_t RESERVED3;
__IOM uint16_t GPIN; /*!< (@ 0x00000010) GPIO registered data input */
__IM uint16_t RESERVED4;
__IOM uint16_t GPOUT; /*!< (@ 0x00000014) GPIO data output */
__IM uint16_t RESERVED5;
__IOM uint16_t GPSET; /*!< (@ 0x00000018) GPIO data out set */
__IM uint16_t RESERVED6;