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os9x_65c816_mac_op.h
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os9x_65c816_mac_op.h
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/*****************************************************************
FLAGS
*****************************************************************/
.macro UPDATE_C
// CC : ARM Carry Clear
BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
// CS : ARM Carry Set
ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
.endm
.macro UPDATE_Z
// NE : ARM Zero Clear
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
// EQ : ARM Zero Set
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
.endm
.macro UPDATE_ZN
// NE : ARM Zero Clear
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
// EQ : ARM Zero Set
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
// PL : ARM Neg Clear
BICPL rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
// MI : ARM Neg Set
ORRMI rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set N to one
.endm
/*****************************************************************
OPCODES_MAC
*****************************************************************/
.macro ADC8
TST rstatus, #MASK_DECIMAL
BEQ 1111f
S9xGetByte
STMFD R13!,{rscratch}
MOV rscratch4,#0x0F000000
//rscratch2=xxW1xxxxxxxxxxxx
AND rscratch2, rscratch, rscratch4
//rscratch=xxW2xxxxxxxxxxxx
AND rscratch, rscratch4, rscratch, LSR #4
//rscratch3=xxA2xxxxxxxxxxxx
AND rscratch3, rscratch4, regA, LSR #4
//rscratch4=xxA1xxxxxxxxxxxx
AND rscratch4,regA,rscratch4
//R1=A1+W1+CARRY
TST rstatus, #MASK_CARRY
ADDNE rscratch2, rscratch2, #0x01000000
ADD rscratch2,rscratch2,rscratch4
// if R1 > 9
CMP rscratch2, #0x09000000
// then R1 -= 10
SUBGT rscratch2, rscratch2, #0x0A000000
// then A2++
ADDGT rscratch3, rscratch3, #0x01000000
// R2 = A2+W2
ADD rscratch3, rscratch3, rscratch
// if R2 > 9
CMP rscratch3, #0x09000000
// then R2 -= 10//
SUBGT rscratch3, rscratch3, #0x0A000000
// then SetCarry()
ORRGT rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
// else ClearCarry()
BICLE rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
// gather rscratch3 and rscratch2 into ans8
// rscratch3 : 0R2000000
// rscratch2 : 0R1000000
// -> 0xR2R1000000
ORR rscratch2, rscratch2, rscratch3, LSL #4
LDMFD R13!,{rscratch}
//only last bit
AND rscratch,rscratch,#0x80000000
// (register.AL ^ Work8)
EORS rscratch3, regA, rscratch
BICNE rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
BNE 1112f
// (Work8 ^ Ans8)
EORS rscratch3, rscratch2, rscratch
// & 0x80
TSTNE rscratch3,#0x80000000
BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
1112:
MOVS regA, rscratch2
UPDATE_ZN
B 1113f
1111:
S9xGetByteLow
MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
SUBCS rscratch, rscratch, #0x100
ADCS regA, regA, rscratch, ROR #8
//OverFlow
ORRVS rstatus, rstatus, #MASK_OVERFLOW
BICVC rstatus, rstatus, #MASK_OVERFLOW
//Carry
UPDATE_C
//clear lower part
ANDS regA, regA, #0xFF000000
//Update flag
UPDATE_ZN
1113:
.endm
/* TO TEST */
.macro ADC16
TST rstatus, #MASK_DECIMAL
BEQ 1111f
S9xGetWord
//rscratch = W3W2W1W0........
LDR rscratch4, = 0x0F0F0000
// rscratch2 = xxW2xxW0xxxxxx
// rscratch3 = xxW3xxW1xxxxxx
AND rscratch2, rscratch4, rscratch
AND rscratch3, rscratch4, rscratch, LSR #4
// rscratch2 = xxW3xxW1xxW2xxW0
ORR rscratch2, rscratch3, rscratch2, LSR #16
// rscratch3 = xxA2xxA0xxxxxx
// rscratch4 = xxA3xxA1xxxxxx
// rscratch2 = xxA3xxA1xxA2xxA0
AND rscratch3, rscratch4, regA
AND rscratch4, rscratch4, regA, LSR #4
ORR rscratch3, rscratch4, rscratch3, LSR #16
ADD rscratch2, rscratch3, rscratch2
LDR rscratch4, = 0x0F0F0000
// rscratch2 = A + W
TST rstatus, #MASK_CARRY
ADDNE rscratch2, rscratch2, #0x1
// rscratch2 = A + W + C
//A0
AND rscratch3, rscratch2, #0x0000001F
CMP rscratch3, #0x00000009
ADDHI rscratch2, rscratch2, #0x00010000
SUBHI rscratch2, rscratch2, #0x0000000A
//A1
AND rscratch3, rscratch2, #0x001F0000
CMP rscratch3, #0x00090000
ADDHI rscratch2, rscratch2, #0x00000100
SUBHI rscratch2, rscratch2, #0x000A0000
//A2
AND rscratch3, rscratch2, #0x00001F00
CMP rscratch3, #0x00000900
SUBHI rscratch2, rscratch2, #0x00000A00
ADDHI rscratch2, rscratch2, #0x01000000
//A3
AND rscratch3, rscratch2, #0x1F000000
CMP rscratch3, #0x09000000
SUBHI rscratch2, rscratch2, #0x0A000000
//SetCarry
ORRHI rstatus, rstatus, #MASK_CARRY
//ClearCarry
BICLS rstatus, rstatus, #MASK_CARRY
//rscratch2 = xxR3xxR1xxR2xxR0
//Pack result
//rscratch3 = xxR3xxR1xxxxxxxx
AND rscratch3, rscratch4, rscratch2
//rscratch2 = xxR2xxR0xxxxxxxx
AND rscratch2, rscratch4, rscratch2,LSL #16
//rscratch2 = R3R2R1R0xxxxxxxx
ORR rscratch2, rscratch2,rscratch3,LSL #4
//only last bit
AND rscratch,rscratch,#0x80000000
// (register.AL ^ Work8)
EORS rscratch3, regA, rscratch
BICNE rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
BNE 1112f
// (Work8 ^ Ans8)
EORS rscratch3, rscratch2, rscratch
TSTNE rscratch3,#0x80000000
BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
1112:
MOVS regA, rscratch2
UPDATE_ZN
B 1113f
1111:
S9xGetWordLow
MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
SUBCS rscratch, rscratch, #0x10000
ADCS regA, regA,rscratch, ROR #16
//OverFlow
ORRVS rstatus, rstatus, #MASK_OVERFLOW
BICVC rstatus, rstatus, #MASK_OVERFLOW
MOV regA, regA, LSR #16
//Carry
UPDATE_C
//clear lower parts
MOVS regA, regA, LSL #16
//Update flag
UPDATE_ZN
1113:
.endm
.macro AND16
S9xGetWord
ANDS regA, regA, rscratch
UPDATE_ZN
.endm
.macro AND8
S9xGetByte
ANDS regA, regA, rscratch
UPDATE_ZN
.endm
.macro A_ASL8
// 7 instr
MOVS regA, regA, LSL #1
UPDATE_C
UPDATE_ZN
ADD1CYCLE
.endm
.macro A_ASL16
// 7 instr
MOVS regA, regA, LSL #1
UPDATE_C
UPDATE_ZN
ADD1CYCLE
.endm
.macro ASL16
S9xGetWordRegNS rscratch2 // do not destroy Opadress in rscratch
MOVS rscratch2, rscratch2, LSL #1
UPDATE_C
UPDATE_ZN
S9xSetWord rscratch2
ADD1CYCLE
.endm
.macro ASL8
S9xGetByteRegNS rscratch2 // do not destroy Opadress in rscratch
MOVS rscratch2, rscratch2, LSL #1
UPDATE_C
UPDATE_ZN
S9xSetByte rscratch2
ADD1CYCLE
.endm
.macro BIT8
S9xGetByte
MOVS rscratch2, rscratch, LSL #1
// Trick in ASM : shift one more bit : ARM C = Snes N
// ARM N = Snes V
// If Carry Set, then Set Neg in SNES
BICCC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set C to zero
ORRCS rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set C to one
// If Neg Set, then Set Overflow in SNES
BICPL rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set N to zero
ORRMI rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set N to one
// Now do a real AND with A register
// Set Zero Flag, bit test
ANDS rscratch2, regA, rscratch
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
.endm
.macro BIT16
S9xGetWord
MOVS rscratch2, rscratch, LSL #1
// Trick in ASM : shift one more bit : ARM C = Snes N
// ARM N = Snes V
// If Carry Set, then Set Neg in SNES
BICCC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
ORRCS rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set N to one
// If Neg Set, then Set Overflow in SNES
BICPL rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
ORRMI rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
// Now do a real AND with A register
// Set Zero Flag, bit test
ANDS rscratch2, regA, rscratch
// Bit set ->Z=0->xxxNE Clear flag
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
// Bit clear->Z=1->xxxEQ Set flag
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
.endm
.macro CMP8
S9xGetByte
SUBS rscratch2,regA,rscratch
BICCC rstatus, rstatus, #MASK_CARRY
ORRCS rstatus, rstatus, #MASK_CARRY
UPDATE_ZN
.endm
.macro CMP16
S9xGetWord
SUBS rscratch2,regA,rscratch
BICCC rstatus, rstatus, #MASK_CARRY
ORRCS rstatus, rstatus, #MASK_CARRY
UPDATE_ZN
.endm
.macro CMX16
S9xGetWord
SUBS rscratch2,regX,rscratch
BICCC rstatus, rstatus, #MASK_CARRY
ORRCS rstatus, rstatus, #MASK_CARRY
UPDATE_ZN
.endm
.macro CMX8
S9xGetByte
SUBS rscratch2,regX,rscratch
BICCC rstatus, rstatus, #MASK_CARRY
ORRCS rstatus, rstatus, #MASK_CARRY
UPDATE_ZN
.endm
.macro CMY16
S9xGetWord
SUBS rscratch2,regY,rscratch
BICCC rstatus, rstatus, #MASK_CARRY
ORRCS rstatus, rstatus, #MASK_CARRY
UPDATE_ZN
.endm
.macro CMY8
S9xGetByte
SUBS rscratch2,regY,rscratch
BICCC rstatus, rstatus, #MASK_CARRY
ORRCS rstatus, rstatus, #MASK_CARRY
UPDATE_ZN
.endm
.macro A_DEC8
MOV rscratch,#0
SUBS regA, regA, #0x01000000
STR rscratch,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro A_DEC16
MOV rscratch,#0
SUBS regA, regA, #0x00010000
STR rscratch,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro DEC16
S9xGetWordRegNS rscratch2 // do not destroy Opadress in rscratch
MOV rscratch3,#0
SUBS rscratch2, rscratch2, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
S9xSetWord rscratch2
ADD1CYCLE
.endm
.macro DEC8
S9xGetByteRegNS rscratch2 // do not destroy Opadress in rscratch
MOV rscratch3,#0
SUBS rscratch2, rscratch2, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
S9xSetByte rscratch2
ADD1CYCLE
.endm
.macro EOR16
S9xGetWord
EORS regA, regA, rscratch
UPDATE_ZN
.endm
.macro EOR8
S9xGetByte
EORS regA, regA, rscratch
UPDATE_ZN
.endm
.macro A_INC8
MOV rscratch3,#0
ADDS regA, regA, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro A_INC16
MOV rscratch3,#0
ADDS regA, regA, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro INC16
S9xGetWordRegNS rscratch2
MOV rscratch3,#0
ADDS rscratch2, rscratch2, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
S9xSetWord rscratch2
ADD1CYCLE
.endm
.macro INC8
S9xGetByteRegNS rscratch2
MOV rscratch3,#0
ADDS rscratch2, rscratch2, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
S9xSetByte rscratch2
ADD1CYCLE
.endm
.macro LDA16
S9xGetWordRegStatus regA
UPDATE_ZN
.endm
.macro LDA8
S9xGetByteRegStatus regA
UPDATE_ZN
.endm
.macro LDX16
S9xGetWordRegStatus regX
UPDATE_ZN
.endm
.macro LDX8
S9xGetByteRegStatus regX
UPDATE_ZN
.endm
.macro LDY16
S9xGetWordRegStatus regY
UPDATE_ZN
.endm
.macro LDY8
S9xGetByteRegStatus regY
UPDATE_ZN
.endm
.macro A_LSR16
BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
MOVS regA, regA, LSR #17 // hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
// Update Zero
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
MOV regA, regA, LSL #16 // -> 0lllllll 00000000 00000000 00000000
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
// Note : the two MOV are included between instruction, to optimize
// the pipeline.
UPDATE_C
ADD1CYCLE
.endm
.macro A_LSR8
BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
MOVS regA, regA, LSR #25 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
// Update Zero
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
MOV regA, regA, LSL #24 // -> 00000000 00000000 00000000 0lllllll
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
// Note : the two MOV are included between instruction, to optimize
// the pipeline.
UPDATE_C
ADD1CYCLE
.endm
.macro LSR16
S9xGetWordRegNS rscratch2
// N set to zero by >> 1 LSR
BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
MOVS rscratch2, rscratch2, LSR #17 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
// Update Carry
BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
// Update Zero
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
S9xSetWordLow rscratch2
ADD1CYCLE
.endm
.macro LSR8
S9xGetByteRegNS rscratch2
// N set to zero by >> 1 LSR
BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
MOVS rscratch2, rscratch2, LSR #25 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
// Update Carry
BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
// Update Zero
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
S9xSetByteLow rscratch2
ADD1CYCLE
.endm
.macro ORA8
S9xGetByte
ORRS regA, regA, rscratch
UPDATE_ZN
.endm
.macro ORA16
S9xGetWord
ORRS regA, regA, rscratch
UPDATE_ZN
.endm
.macro A_ROL16
TST rstatus, #MASK_CARRY
ORRNE regA, regA, #0x00008000
MOVS regA, regA, LSL #1
UPDATE_ZN
UPDATE_C
ADD1CYCLE
.endm
.macro A_ROL8
TST rstatus, #MASK_CARRY
ORRNE regA, regA, #0x00800000
MOVS regA, regA, LSL #1
UPDATE_ZN
UPDATE_C
ADD1CYCLE
.endm
.macro ROL16
S9xGetWordRegNS rscratch2
TST rstatus, #MASK_CARRY
ORRNE rscratch2, rscratch2, #0x00008000
MOVS rscratch2, rscratch2, LSL #1
UPDATE_ZN
UPDATE_C
S9xSetWord rscratch2
ADD1CYCLE
.endm
.macro ROL8
S9xGetByteRegNS rscratch2
TST rstatus, #MASK_CARRY
ORRNE rscratch2, rscratch2, #0x00800000
MOVS rscratch2, rscratch2, LSL #1
UPDATE_ZN
UPDATE_C
S9xSetByte rscratch2
ADD1CYCLE
.endm
.macro A_ROR16
MOV regA,regA, LSR #16
TST rstatus, #MASK_CARRY
ORRNE regA, regA, #0x00010000
ORRNE rstatus,rstatus,#MASK_NEG
BICEQ rstatus,rstatus,#MASK_NEG
MOVS regA,regA,LSR #1
UPDATE_C
UPDATE_Z
MOV regA,regA, LSL #16
ADD1CYCLE
.endm
.macro A_ROR8
MOV regA,regA, LSR #24
TST rstatus, #MASK_CARRY
ORRNE regA, regA, #0x00000100
ORRNE rstatus,rstatus,#MASK_NEG
BICEQ rstatus,rstatus,#MASK_NEG
MOVS regA,regA,LSR #1
UPDATE_C
UPDATE_Z
MOV regA,regA, LSL #24
ADD1CYCLE
.endm
.macro ROR16
S9xGetWordLowRegNS rscratch2
TST rstatus, #MASK_CARRY
ORRNE rscratch2, rscratch2, #0x00010000
ORRNE rstatus,rstatus,#MASK_NEG
BICEQ rstatus,rstatus,#MASK_NEG
MOVS rscratch2,rscratch2,LSR #1
UPDATE_C
UPDATE_Z
S9xSetWordLow rscratch2
ADD1CYCLE
.endm
.macro ROR8
S9xGetByteLowRegNS rscratch2
TST rstatus, #MASK_CARRY
ORRNE rscratch2, rscratch2, #0x00000100
ORRNE rstatus,rstatus,#MASK_NEG
BICEQ rstatus,rstatus,#MASK_NEG
MOVS rscratch2,rscratch2,LSR #1
UPDATE_C
UPDATE_Z
S9xSetByteLow rscratch2
ADD1CYCLE
.endm
.macro SBC16
TST rstatus, #MASK_DECIMAL
BEQ 1111f
//TODO
S9xGetWord
STMFD R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9}
MOV rscratch9,#0x000F0000
//rscratch2=xxxxxxW1xxxxxxxxxx + !Carry
//rscratch3=xxxxxxW2xxxxxxxxxx
//rscratch4=xxxxxxW3xxxxxxxxxx
//rscratch5=xxxxxxW4xxxxxxxxxx
AND rscratch2, rscratch9, rscratch
TST rstatus, #MASK_CARRY
ADDEQ rscratch2, rscratch2, #0x00010000 //W1=W1+!Carry
AND rscratch3, rscratch9, rscratch, LSR #4
AND rscratch4, rscratch9, rscratch, LSR #8
AND rscratch5, rscratch9, rscratch, LSR #12
//rscratch6=xxxxxxA1xxxxxxxxxx
//rscratch7=xxxxxxA2xxxxxxxxxx
//rscratch8=xxxxxxA3xxxxxxxxxx
//rscratch9=xxxxxxA4xxxxxxxxxx
AND rscratch6, rscratch9, regA
AND rscratch7, rscratch9, regA, LSR #4
AND rscratch8, rscratch9, regA, LSR #8
AND rscratch9, rscratch9, regA, LSR #12
SUB rscratch2,rscratch6,rscratch2 //R1=A1-W1-!Carry
CMP rscratch2, #0x00090000 // if R1 > 9
ADDHI rscratch2, rscratch2, #0x000A0000 // then R1 += 10
ADDHI rscratch3, rscratch3, #0x00010000 // then (W2++)
SUB rscratch3,rscratch7,rscratch3 //R2=A2-W2
CMP rscratch3, #0x00090000 // if R2 > 9
ADDHI rscratch3, rscratch3, #0x000A0000 // then R2 += 10
ADDHI rscratch4, rscratch4, #0x00010000 // then (W3++)
SUB rscratch4,rscratch8,rscratch4 //R3=A3-W3
CMP rscratch4, #0x00090000 // if R3 > 9
ADDHI rscratch4, rscratch4, #0x000A0000 // then R3 += 10
ADDHI rscratch5, rscratch5, #0x00010000 // then (W3++)
SUB rscratch5,rscratch9,rscratch5 //R4=A4-W4
CMP rscratch5, #0x00090000 // if R4 > 9
ADDHI rscratch5, rscratch5, #0x000A0000 // then R4 += 10
BICHI rstatus, rstatus, #MASK_CARRY // then ClearCarry
ORRLS rstatus, rstatus, #MASK_CARRY // else SetCarry
MOV rscratch9,#0x000F0000
AND rscratch2,rscratch9,rscratch2
AND rscratch3,rscratch9,rscratch3
AND rscratch4,rscratch9,rscratch4
AND rscratch5,rscratch9,rscratch5
ORR rscratch2,rscratch2,rscratch3,LSL #4
ORR rscratch2,rscratch2,rscratch4,LSL #8
ORR rscratch2,rscratch2,rscratch5,LSL #12
LDMFD R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9}
//only last bit
AND regA,regA,#0x80000000
// (register.A.W ^ Work8)
EORS rscratch3, regA, rscratch
BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
BEQ 1112f
// (register.A.W ^ Ans8)
EORS rscratch3, regA, rscratch2
// & 0x80
TSTNE rscratch3,#0x80000000
BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
1112:
MOVS regA, rscratch2
UPDATE_ZN
B 1113f
1111:
S9xGetWordLow
MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
SBCS regA, regA, rscratch, LSL #16
//OverFlow
ORRVS rstatus, rstatus, #MASK_OVERFLOW
BICVC rstatus, rstatus, #MASK_OVERFLOW
MOV regA, regA, LSR #16
//Carry
UPDATE_C
MOVS regA, regA, LSL #16
//Update flag
UPDATE_ZN
1113:
.endm
.macro SBC8
TST rstatus, #MASK_DECIMAL
BEQ 1111f
S9xGetByte
STMFD R13!,{rscratch}
MOV rscratch4,#0x0F000000
//rscratch2=xxW1xxxxxxxxxxxx
AND rscratch2, rscratch, rscratch4
//rscratch=xxW2xxxxxxxxxxxx
AND rscratch, rscratch4, rscratch, LSR #4
//rscratch3=xxA2xxxxxxxxxxxx
AND rscratch3, rscratch4, regA, LSR #4
//rscratch4=xxA1xxxxxxxxxxxx
AND rscratch4,regA,rscratch4
//R1=A1-W1-!CARRY
TST rstatus, #MASK_CARRY
ADDEQ rscratch2, rscratch2, #0x01000000
SUB rscratch2,rscratch4,rscratch2
// if R1 > 9
CMP rscratch2, #0x09000000
// then R1 += 10
ADDHI rscratch2, rscratch2, #0x0A000000
// then A2-- (W2++)
ADDHI rscratch, rscratch, #0x01000000
// R2=A2-W2
SUB rscratch3, rscratch3, rscratch
// if R2 > 9
CMP rscratch3, #0x09000000
// then R2 -= 10//
ADDHI rscratch3, rscratch3, #0x0A000000
// then SetCarry()
BICHI rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
// else ClearCarry()
ORRLS rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
// gather rscratch3 and rscratch2 into ans8
AND rscratch3,rscratch3,#0x0F000000
AND rscratch2,rscratch2,#0x0F000000
// rscratch3 : 0R2000000
// rscratch2 : 0R1000000
// -> 0xR2R1000000
ORR rscratch2, rscratch2, rscratch3, LSL #4
LDMFD R13!,{rscratch}
//only last bit
AND regA,regA,#0x80000000
// (register.AL ^ Work8)
EORS rscratch3, regA, rscratch
BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
BEQ 1112f
// (register.AL ^ Ans8)
EORS rscratch3, regA, rscratch2
// & 0x80
TSTNE rscratch3,#0x80000000
BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
1112:
MOVS regA, rscratch2
UPDATE_ZN
B 1113f
1111:
S9xGetByteLow
MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
SBCS regA, regA, rscratch, LSL #24
//OverFlow
ORRVS rstatus, rstatus, #MASK_OVERFLOW
BICVC rstatus, rstatus, #MASK_OVERFLOW
//Carry
UPDATE_C
//Update flag
ANDS regA, regA, #0xFF000000
UPDATE_ZN
1113:
.endm
.macro STA16
S9xSetWord regA
.endm
.macro STA8
S9xSetByte regA
.endm
.macro STX16
S9xSetWord regX
.endm
.macro STX8
S9xSetByte regX
.endm
.macro STY16
S9xSetWord regY
.endm
.macro STY8
S9xSetByte regY
.endm
.macro STZ16
S9xSetWordZero
.endm
.macro STZ8
S9xSetByteZero
.endm
.macro TSB16
S9xGetWordRegNS rscratch2
TST regA, rscratch2
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
ORR rscratch2, regA, rscratch2
S9xSetWord rscratch2
ADD1CYCLE
.endm
.macro TSB8
S9xGetByteRegNS rscratch2
TST regA, rscratch2
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
ORR rscratch2, regA, rscratch2
S9xSetByte rscratch2
ADD1CYCLE
.endm
.macro TRB16
S9xGetWordRegNS rscratch2
TST regA, rscratch2
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
MVN rscratch3, regA
AND rscratch2, rscratch3, rscratch2
S9xSetWord rscratch2
ADD1CYCLE
.endm
.macro TRB8
S9xGetByteRegNS rscratch2
TST regA, rscratch2
BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
MVN rscratch3, regA
AND rscratch2, rscratch3, rscratch2
S9xSetByte rscratch2
ADD1CYCLE
.endm
/**************************************************************************/
/**************************************************************************/
.macro Op09M0 /*ORA*/
LDRB rscratch2, [rpc,#1]
LDRB rscratch, [rpc], #2
ORR rscratch2,rscratch,rscratch2,LSL #8
ORRS regA,regA,rscratch2,LSL #16
UPDATE_ZN
ADD2MEM
.endm
.macro Op09M1 /*ORA*/
LDRB rscratch, [rpc], #1
ORRS regA,regA,rscratch,LSL #24
UPDATE_ZN
ADD1MEM
.endm
/***********************************************************************/
.macro Op90 /*BCC*/
asmRelative
BranchCheck0
TST rstatus, #MASK_CARRY
BNE 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro OpB0 /*BCS*/
asmRelative
BranchCheck0
TST rstatus, #MASK_CARRY
BEQ 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro OpF0 /*BEQ*/
asmRelative
BranchCheck2
TST rstatus, #MASK_ZERO
BEQ 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro OpD0 /*BNE*/
asmRelative
BranchCheck1
TST rstatus, #MASK_ZERO
BNE 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro Op30 /*BMI*/
asmRelative
BranchCheck0
TST rstatus, #MASK_NEG
BEQ 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro Op10 /*BPL*/
asmRelative
BranchCheck1
TST rstatus, #MASK_NEG // neg, z!=0, NE
BNE 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro Op50 /*BVC*/
asmRelative
BranchCheck0
TST rstatus, #MASK_OVERFLOW // neg, z!=0, NE
BNE 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro Op70 /*BVS*/
asmRelative
BranchCheck0
TST rstatus, #MASK_OVERFLOW // neg, z!=0, NE
BEQ 1111f
ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
.macro Op80 /*BRA*/
asmRelative
ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
ADD1CYCLE
CPUShutdown
1111:
.endm
/*******************************************************************************************/
/************************************************************/
/* SetFlag Instructions ********************************************************************** */
.macro Op38 /*SEC*/
ORR rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
ADD1CYCLE
.endm
.macro OpF8 /*SED*/
SetDecimal
ADD1CYCLE
.endm
.macro Op78 /*SEI*/
SetIRQ
ADD1CYCLE
.endm
/****************************************************************************************/
/* ClearFlag Instructions ******************************************************************** */
.macro Op18 /*CLC*/
BIC rstatus, rstatus, #MASK_CARRY
ADD1CYCLE
.endm
.macro OpD8 /*CLD*/
ClearDecimal
ADD1CYCLE
.endm
.macro Op58 /*CLI*/
ClearIRQ
ADD1CYCLE
//CHECK_FOR_IRQ
.endm
.macro OpB8 /*CLV*/
BIC rstatus, rstatus, #MASK_OVERFLOW
ADD1CYCLE
.endm
/******************************************************************************************/
/* DEX/DEY *********************************************************************************** */
.macro OpCAX1 /*DEX*/
MOV rscratch3,#0
SUBS regX, regX, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro OpCAX0 /*DEX*/
MOV rscratch3,#0
SUBS regX, regX, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro Op88X1 /*DEY*/
MOV rscratch3,#0
SUBS regY, regY, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro Op88X0 /*DEY*/
MOV rscratch3,#0
SUBS regY, regY, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
/******************************************************************************************/
/* INX/INY *********************************************************************************** */
.macro OpE8X1
MOV rscratch3,#0
ADDS regX, regX, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro OpE8X0
MOV rscratch3,#0
ADDS regX, regX, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro OpC8X1
MOV rscratch3,#0
ADDS regY, regY, #0x01000000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
.macro OpC8X0
MOV rscratch3,#0
ADDS regY, regY, #0x00010000
STR rscratch3,[regCPUvar,#WaitAddress_ofs]
UPDATE_ZN
ADD1CYCLE
.endm
/**********************************************************************************************/
/* NOP *************************************************************************************** */