diff --git a/doc/OH_modules.docx b/doc/OH_modules.docx index 02adf9f..471fd25 100644 Binary files a/doc/OH_modules.docx and b/doc/OH_modules.docx differ diff --git a/prj/OptoHybrid_v3.xise b/prj/OptoHybrid_v3.xise index c57b1f5..4360b52 100644 --- a/prj/OptoHybrid_v3.xise +++ b/prj/OptoHybrid_v3.xise @@ -296,18 +296,13 @@ - - - - - - - - + + + @@ -368,7 +363,7 @@ - + @@ -633,6 +628,7 @@ + @@ -657,6 +653,7 @@ + diff --git a/src/gbt/gbt.vhd b/src/gbt/gbt.vhd index 1e07ce4..5fb1819 100644 --- a/src/gbt/gbt.vhd +++ b/src/gbt/gbt.vhd @@ -58,8 +58,8 @@ end gbt; architecture Behavioral of gbt is - signal gbt_dout : std_logic_vector(15 downto 0) := (others => '0'); - signal gbt_din : std_logic_vector(15 downto 0) := (others => '0'); + signal gbt_tx_data : std_logic_vector(15 downto 0) := (others => '0'); + signal gbt_rx_data : std_logic_vector(15 downto 0) := (others => '0'); signal reset : std_logic; @@ -102,8 +102,8 @@ begin -- parallel data - data_o => gbt_din, -- Parallel data out - data_i => gbt_dout -- Parallel data in + data_o => gbt_rx_data, -- Parallel data out + data_i => gbt_tx_data -- Parallel data in ); -- decodes GBT frames to build packets @@ -118,8 +118,8 @@ begin clock => clock_i, -- 40 MHz ttc fabric clock -- parallel data - data_i => gbt_din, - data_o => gbt_dout, + data_i => gbt_rx_data, + data_o => gbt_tx_data, -- wishbone master wb_mst_req_o => wb_mst_req_o, diff --git a/src/gbt/gbt_link.vhd b/src/gbt/gbt_link.vhd index 859bc0a..f80f7bf 100644 --- a/src/gbt/gbt_link.vhd +++ b/src/gbt/gbt_link.vhd @@ -96,9 +96,8 @@ begin resync_o => resync_o, reset_vfats_o => reset_vfats_o, - -- 65 bit output packet to fifo - req_en_o => gbt_rx_req, - req_data_o => gbt_rx_data, + req_en_o => gbt_rx_req, -- 1 bit, wishbone request recevied from GBTx + req_data_o => gbt_rx_data, -- 49 bit packet (1 bit we + 16 bit addr + 32 bit data) -- status error_o => error_o @@ -140,9 +139,9 @@ begin reset_i => reset, -- rx parallel data (from GBT) - wb_mst_req_o => wb_mst_req_o, -- 32 bit adr + 32 bit data + we + wb_mst_req_o => wb_mst_req_o, -- 16 bit adr + 32 bit data + we rx_en_i => gbt_rx_req, - rx_data_i => gbt_rx_data, -- 32 bit adr + 32 bit data + rx_data_i => gbt_rx_data, -- 16 bit adr + 32 bit data -- tx parallel data (to GBT) diff --git a/src/gbt/gbt_serdes.vhd b/src/gbt/gbt_serdes.vhd index a35ec5e..babfa57 100644 --- a/src/gbt/gbt_serdes.vhd +++ b/src/gbt/gbt_serdes.vhd @@ -40,16 +40,16 @@ port( clock : in std_logic; - -- serial data + -- serial data to/from GBTx elink_o_p : out std_logic_vector(1 downto 0); elink_o_n : out std_logic_vector(1 downto 0); elink_i_p : in std_logic_vector(1 downto 0); elink_i_n : in std_logic_vector(1 downto 0); - -- parallel data - data_i : in std_logic_vector (15 downto 0); - data_o : out std_logic_vector(15 downto 0); + -- parallel data to/from FPGA logic + data_i : in std_logic_vector (15 downto 0); + data_o : out std_logic_vector (15 downto 0); valid_o : out std_logic ); end gbt_serdes; diff --git a/src/pkg/param_pkg.vhd b/src/pkg/param_pkg.vhd index d68f83f..6cf657d 100644 --- a/src/pkg/param_pkg.vhd +++ b/src/pkg/param_pkg.vhd @@ -8,11 +8,11 @@ package param_pkg is constant MAJOR_VERSION : std_logic_vector(7 downto 0) := x"03"; constant MINOR_VERSION : std_logic_vector(7 downto 0) := x"00"; - constant RELEASE_VERSION : std_logic_vector(7 downto 0) := x"00"; + constant RELEASE_VERSION : std_logic_vector(7 downto 0) := x"01"; constant RELEASE_YEAR : std_logic_vector(15 downto 0) := x"2017"; - constant RELEASE_MONTH : std_logic_vector(7 downto 0) := x"10"; - constant RELEASE_DAY : std_logic_vector(7 downto 0) := x"06"; + constant RELEASE_MONTH : std_logic_vector(7 downto 0) := x"11"; + constant RELEASE_DAY : std_logic_vector(7 downto 0) := x"01"; constant RELEASE_HARDWARE : std_logic_vector(7 downto 0) := x"0A"; diff --git a/src/ucf/gbt.ucf b/src/ucf/gbt.ucf index 5f762b5..8e23238 100644 --- a/src/ucf/gbt.ucf +++ b/src/ucf/gbt.ucf @@ -1,16 +1,25 @@ ######################################################################################################################## # E-links ######################################################################################################################## + # outputs + +# 80 MHZ e-link NET "elink_o_p<0>" LOC = AG16; # GBTx DOUT 28 NET "elink_o_n<0>" LOC = AF16; # + +# 320 MHz e-link # POLSWAPed, make sure to account in firmware NET "elink_o_p<1>" LOC = L19; NET "elink_o_n<1>" LOC = L18; # inputs + +# 80MHz e-link NET "elink_i_p<0>" LOC = AG15 |IOSTANDARD = LVDS_25 |DIFF_TERM = FALSE; # GBTx DIN 28 NET "elink_i_n<0>" LOC = AF15 |IOSTANDARD = LVDS_25 |DIFF_TERM = FALSE; # + +# 320 MHz e-link NET "elink_i_p<1>" LOC = AD24 |IOSTANDARD = LVDS_25 |DIFF_TERM = FALSE; # GBTx DIN 36 NET "elink_i_n<1>" LOC = AE24 |IOSTANDARD = LVDS_25 |DIFF_TERM = FALSE; # diff --git a/src/utils/led_control.v b/src/utils/led_control.v index f286c31..b91d7b4 100644 --- a/src/utils/led_control.v +++ b/src/utils/led_control.v @@ -45,7 +45,7 @@ module led_control ( // LED Blinkers //---------------------------------------------------------------------------------------------------------------------- - // count to 20 bits for 40 MHz clock to divide to 4 Hz + // count to 21 bits for 40 MHz clock to divide to 2 Hz wire clk = clock; @@ -58,7 +58,7 @@ module led_control ( clk_led <= ~ clk_led; end - // count to 20 bits for 40 MHz clock to divide to 4 Hz + // count to 21 bits for 40 MHz clock to divide to 2 Hz wire eclk = gbt_eclk; @@ -82,9 +82,9 @@ module led_control ( .g_CLK_FREQUENCY (32'd40079000), // 40MHz LHC frequency .g_COUNTER_WIDTH (32'd32), .g_INCREMENTER_WIDTH (32'd8), - .g_PROGRESS_BAR_WIDTH (32'd12), // we'll have 12 LEDs as a rate progress bar - .g_PROGRESS_BAR_STEP (32'd20000), // each bar is 20KHz - .g_SPEEDUP_FACTOR (32'd4) // update 16 times per second + .g_PROGRESS_BAR_WIDTH (32'd12), // we'll have 12 LEDs as a rate progress bar + .g_PROGRESS_BAR_STEP (32'd100), // each bar is 20KHz + .g_SPEEDUP_FACTOR (32'd4) // update 16 times per second ) u_rate_cnt ( .clk_i (clock), diff --git a/src/utils/sbits.vhd b/src/utils/sbits.vhd index 7f93c8f..a5145f0 100644 --- a/src/utils/sbits.vhd +++ b/src/utils/sbits.vhd @@ -1,17 +1,14 @@ ---------------------------------------------------------------------------------- --- Company: IIHE - ULB --- Engineer: Evaldas Juska --- --- Create Date: 13:13:21 05/13/2016 --- Design Name: OptoHybrid v2 --- Module Name: sbits - Behavioral --- Project Name: OptoHybrid v2 --- Target Devices: xc6vlx130t-1ff1156 --- Tool versions: ISE P.20131013 +-- CMS Muon Endcap +-- GEM Collaboration +-- Optohybrid v3 Firmware -- S-Bits +-- A. Peck +---------------------------------------------------------------------------------- -- Description: --- --- Sbits handling --- +-- This module wraps up all the functionality for deserializing 320 MHz S-bits +-- as well as the cluster packer +---------------------------------------------------------------------------------- +-- 2017/11/01 -- Add description / comments ---------------------------------------------------------------------------------- library ieee; @@ -29,7 +26,7 @@ port( clk40_i : in std_logic; delay_refclk_i : in std_logic; - cluster_clk : in std_logic; + cluster_clk : in std_logic; reset_i : in std_logic; @@ -83,6 +80,8 @@ begin -- don't need to do a 180 on the clock-- use local inverters for deserialization to save 1 global clock clk160_180 <= not clk160_i; + -- remap VFATs for input to cluster packer + sbits_p <= trigger_unit_i(23).trig_data_p & trigger_unit_i(22).trig_data_p & trigger_unit_i(21).trig_data_p @@ -184,6 +183,12 @@ begin & trigger_unit_i(0).start_of_frame_n; + --=======================-- + --== Trigger Alignment ==-- + --=======================-- + + -- deserializes and aligns the 192 320 MHz s-bits into 1536 40MHz s-bits + trig_alignment : entity work.trig_alignment port map ( @@ -208,7 +213,7 @@ begin sbits => sbits ); - -- combinatorial renaming for input to module + -- combinatorial renaming for input to cluster packing module vfat_sbits (0) <= sbits (63 downto 0); vfat_sbits (1) <= sbits (127 downto 64); @@ -235,6 +240,13 @@ begin vfat_sbits (22) <= sbits (1471 downto 1408); vfat_sbits (23) <= sbits (1535 downto 1472); + --========================-- + --== Active VFAT Flags ==-- + --========================-- + + -- want to generate 24 bits as active VFAT flags, indicating that at least one s-bit on that VFAT + -- was active in this 40MHz cycle + -- I don't want to do 64 bit reduction in 1 clock... split it over 2 to add slack to PAR and timing active_vfat_s1 : for I in 0 to (191) generate @@ -257,6 +269,10 @@ begin end process; end generate; + --======================-- + --== Cluster Packer ==-- + --======================-- + cluster_packer_inst : entity work.cluster_packer generic map (ONESHOT_EN => 1, TRUNCATE_CLUSTERS => 1)