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This repository has been archived by the owner on Jan 31, 2022. It is now read-only.
Right now GE1/1 uses a 320MHz clock that gets divided down to 40MHz... this will introduce some variable latency into the trigger path. Either a 40MHz clock should be used instead (which requires switching to the phase-shiftable clock output, which was seen to have worse jitter performance) or some mechanism to align the clocks in firmware.
The text was updated successfully, but these errors were encountered:
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Right now GE1/1 uses a 320MHz clock that gets divided down to 40MHz... this will introduce some variable latency into the trigger path. Either a 40MHz clock should be used instead (which requires switching to the phase-shiftable clock output, which was seen to have worse jitter performance) or some mechanism to align the clocks in firmware.
The text was updated successfully, but these errors were encountered: